the following patch was just integrated into master:
commit 5605f1b4ab7661f893bf0f10aea72cacdd51dc99
Author: Stefan Reinauer <reinauer(a)chromium.org>
Date: Thu Mar 21 18:43:51 2013 -0700
Fix compilation of Intel LynxPoint based boards
The haswell patches that verified correctly were not yet submitted,
but verified correctly. However they still used romcc_io.h which was
dropped in another patch earlier today.
With a lot of development happening in parallel, this is
unfortunately nothing that the gerrit 2.6 Rebase If Necessary submit
type could have fixed.
Change-Id: Ifef9ae05b22c408e78d6cff37defd68e4ed91ed9
Signed-off-by: Stefan Reinauer <reinauer(a)google.com>
Reviewed-on: http://review.coreboot.org/2876
Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org>
Tested-by: build bot (Jenkins)
Build-Tested: build bot (Jenkins) at Fri Mar 22 03:08:45 2013, giving +1
Reviewed-By: Stefan Reinauer <stefan.reinauer(a)coreboot.org> at Fri Mar 22 02:48:11 2013, giving +2
See http://review.coreboot.org/2876 for details.
-gerrit
the following patch was just integrated into master:
commit db6c5bfd8bdef4489e7fec533cb2ca8ae6c24cf3
Author: Jens Rottmann <JRottmann(a)LiPPERTembedded.de>
Date: Thu Mar 21 22:21:28 2013 +0100
Asrock E350M1: Use SPD read code from F14 wrapper
Changes:
- Get rid of the E350M1 mainboard specific code and use the
platform generic function wrapper that was added in change
http://review.coreboot.org/#/c/2497/
AMD f14: Add SPD read functions to wrapper code
- Move DIMM addresses into devicetree.cb
- Add the ASF init that used to be in the SPD read code into
mainboard_enable()
Notes:
- The DIMM reads only happen in romstage, so the function is not
available in ramstage. Point the read-SPD callback to a generic
function in ramstage.
Change-Id: I08c2aebc62facc14f94400ee1ad188901ba73f19
Signed-off-by: Jens Rottmann <JRottmann(a)LiPPERTembedded.de>
Reviewed-on: http://review.coreboot.org/2875
Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net>
Tested-by: build bot (Jenkins)
Build-Tested: build bot (Jenkins) at Thu Mar 21 23:04:42 2013, giving +1
See http://review.coreboot.org/2875 for details.
-gerrit
the following patch was just integrated into master:
commit 3db86ccfd7caaec5a1c494dfe3bfe9b092837f65
Author: Jens Rottmann <JRottmann(a)LiPPERTembedded.de>
Date: Thu Mar 21 22:31:19 2013 +0100
FrontRunner/Toucan-AF: Use SPD read code from F14 wrapper
Changes:
- Get rid of the LiPPERT FrontRunner-AF and Toucan-AF mainboard
specific code and use the platform generic function wrapper that
was added in change
http://review.coreboot.org/#/c/2497/
AMD f14: Add SPD read functions to wrapper code
- Move DIMM addresses into devicetree.cb
- Add the ASF init that used to be in the SPD read code into
mainboard_enable()
Notes:
- The DIMM reads only happen in romstage, so the function is not
available in ramstage. Point the read-SPD callback to a generic
function in ramstage.
Change-Id: I4ee5e1bc34f4caee20615c48248d4f7605c09377
Signed-off-by: Jens Rottmann <JRottmann(a)LiPPERTembedded.de>
Reviewed-on: http://review.coreboot.org/2874
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net>
Build-Tested: build bot (Jenkins) at Thu Mar 21 22:54:06 2013, giving +1
See http://review.coreboot.org/2874 for details.
-gerrit
the following patch was just integrated into master:
commit 36b6f367c064e9d5d64bc2246bf7cc85bb7c62d3
Author: Patrick Georgi <patrick(a)georgi-clan.de>
Date: Sat Mar 9 10:36:10 2013 +0100
libpayload: initial test case + tiny "framework"
This adds a test case for using CBFS images that reside in RAM
and a Makefile to run it (and maybe other tests in the future).
The test concerns an issue in libcbfs when using x86 style CBFS
images in non-canonical locations (eg. when loading CBFS images
for processing).
Use with "make run" inside the tests directory.
Change-Id: I1af3792a1451728ff9594ba7f0410027cdecb59d
Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de>
Reviewed-on: http://review.coreboot.org/2623
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org>
Build-Tested: build bot (Jenkins) at Sat Mar 9 11:08:31 2013, giving +1
Reviewed-By: Stefan Reinauer <stefan.reinauer(a)coreboot.org> at Mon Mar 11 18:24:58 2013, giving +2
See http://review.coreboot.org/2623 for details.
-gerrit
the following patch was just integrated into master:
commit b02c873190990698350a7c2a9bce52ce81c0f1b2
Author: Hung-Te Lin <hungte(a)chromium.org>
Date: Fri Mar 15 17:40:08 2013 +0800
cbfstool: Fix initial empty space in image creation.
When calculating initial CBFS empty entry space, the size of header itself must
be not included (with the reserved space for entry name). This is a regression
of the old cbfstool size bug.
Before this fix, in build process we see:
OBJCOPY cbfs/fallback/romstage_null.bin
W: CBFS image was created with old cbfstool with size bug.
Fixing size in last entry...
And checking the output binary:
cbfstool build/coreboot.pre1 print -v -v
DEBUG: read_cbfs_image: build/coreboot.pre1 (262144 bytes)
DEBUG: x86sig: 0xfffffd30, offset: 0x3fd30
W: CBFS image was created with old cbfstool with size bug.
Fixing size in last entry...
DEBUG: Last entry has been changed from 0x3fd40 to 0x3fd00.
coreboot.pre1: 256 kB, bootblksz 688, romsize 262144, offset 0x0 align: 64
Name Offset Type Size
(empty) 0x0 null 261296
DEBUG: cbfs_file=0x0, offset=0x28, content_address=0x28+0x3fcb0
After this fix, no more alerts in build process.
Verified to build successfully on x86/qemu and arm/snow configurations.
Change-Id: I35c96f4c10a41bae671148a0e08988fa3bf6b7d3
Signed-off-by: Hung-Te Lin <hungte(a)chromium.org>
Reviewed-on: http://review.coreboot.org/2731
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org>
Build-Tested: build bot (Jenkins) at Fri Mar 15 18:01:05 2013, giving +1
Reviewed-By: Stefan Reinauer <stefan.reinauer(a)coreboot.org> at Fri Mar 22 00:20:03 2013, giving +2
See http://review.coreboot.org/2731 for details.
-gerrit
the following patch was just integrated into master:
commit 3e4e3038584fb2055c482fd346bb821b3d6236fc
Author: Stefan Reinauer <reinauer(a)chromium.org>
Date: Wed Mar 20 14:08:04 2013 -0700
Unify coreboot table generation
coreboot tables are, unlike general system tables, a platform
independent concept. Hence, use the same code for coreboot table
generation on all platforms. lib/coreboot_tables.c is based
on the x86 version of the file, because some important fixes
were missed on the ARMv7 version lately.
Change-Id: Icc38baf609f10536a320d21ac64408bef44bb77d
Signed-off-by: Stefan Reinauer <reinauer(a)coreboot.org>
Reviewed-on: http://review.coreboot.org/2863
Reviewed-by: Ronald G. Minnich <rminnich(a)gmail.com>
Reviewed-by: Aaron Durbin <adurbin(a)google.com>
Tested-by: build bot (Jenkins)
Build-Tested: build bot (Jenkins) at Thu Mar 21 02:50:44 2013, giving +1
See http://review.coreboot.org/2863 for details.
-gerrit