the following patch was just integrated into master:
commit c0cbd6e8c2bad5453f7c3b6961bc12d03862497a
Author: Aaron Durbin <adurbin(a)chromium.org>
Date: Wed Mar 13 13:51:20 2013 -0500
haswell: use dynamic cbmem
Convert the existing haswell code to support reloctable ramstage
to use dynamic cbmem. This patch always selects DYNAMIC_CBMEM as
this option is a hard requirement for relocatable ramstage.
Aside from converting a few new API calls, a cbmem_top()
implementation is added which is defined to be at the begining of the
TSEG region. Also, use the dynamic cbmem library for allocating a
stack in ram for romstage after CAR is torn down.
Utilizing dynamic cbmem does mean that the cmem field in the gnvs
chromeos acpi table is now 0. Also, the memconsole driver in the kernel
won't be able to find the memconsole because the cbmem structure
changed.
Change-Id: I7cf98d15b97ad82abacfb36ec37b004ce4605c38
Signed-off-by: Aaron Durbin <adurbin(a)chromium.org>
Reviewed-on: http://review.coreboot.org/2850
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich(a)gmail.com>
Build-Tested: build bot (Jenkins) at Wed Mar 20 23:54:07 2013, giving +1
See http://review.coreboot.org/2850 for details.
-gerrit
the following patch was just integrated into master:
commit dd4a6d2357decf0cf505370234b378985c68f97f
Author: Aaron Durbin <adurbin(a)chromium.org>
Date: Wed Feb 27 22:50:12 2013 -0600
coreboot: dynamic cbmem requirement
Dynamic cbmem is now a requirement for relocatable ramstage.
This patch replaces the reserve_* fields in the romstage_handoff
structure by using the dynamic cbmem library.
The haswell code is not moved over in this commit, but it should be
safe because there is a hard requirement for DYNAMIC_CBMEM when using
a reloctable ramstage.
Change-Id: I59ab4552c3ae8c2c3982df458cd81a4a9b712cc2
Signed-off-by: Aaron Durbin <adurbin(a)chromium.org>
Reviewed-on: http://review.coreboot.org/2849
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org>
Build-Tested: build bot (Jenkins) at Fri Mar 22 00:08:59 2013, giving +1
Reviewed-By: Stefan Reinauer <stefan.reinauer(a)coreboot.org> at Fri Mar 22 00:13:42 2013, giving +2
See http://review.coreboot.org/2849 for details.
-gerrit
the following patch was just integrated into master:
commit 24d1d4b47274eb82893e6726472a991a36fce0aa
Author: Stefan Reinauer <reinauer(a)chromium.org>
Date: Thu Mar 21 11:51:41 2013 -0700
x86: Unify arch/io.h and arch/romcc_io.h
Here's the great news: From now on you don't have to worry about
hitting the right io.h include anymore. Just forget about romcc_io.h
and use io.h instead. This cleanup has a number of advantages, like
you don't have to guard device/ includes for SMM and pre RAM
anymore. This allows to get rid of a number of ifdefs and will
generally make the code more readable and understandable.
Potentially in the future some of the code in the io.h __PRE_RAM__
path should move to device.h or other device/ includes instead,
but that's another incremental change.
Change-Id: I356f06110e2e355e9a5b4b08c132591f36fec7d9
Signed-off-by: Stefan Reinauer <reinauer(a)google.com>
Reviewed-on: http://review.coreboot.org/2872
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich(a)gmail.com>
Build-Tested: build bot (Jenkins) at Thu Mar 21 21:29:53 2013, giving +1
See http://review.coreboot.org/2872 for details.
-gerrit
Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2849
-gerrit
commit e522d53e0d4b2daf9fbefe7cefb07fb66f45961e
Author: Aaron Durbin <adurbin(a)chromium.org>
Date: Wed Feb 27 22:50:12 2013 -0600
coreboot: dynamic cbmem requirement
Dynamic cbmem is now a requirement for relocatable ramstage.
This patch replaces the reserve_* fields in the romstage_handoff
structure by using the dynamic cbmem library.
The haswell code is not moved over in this commit, but it should be
safe because there is a hard requirement for DYNAMIC_CBMEM when using
a reloctable ramstage.
Change-Id: I59ab4552c3ae8c2c3982df458cd81a4a9b712cc2
Signed-off-by: Aaron Durbin <adurbin(a)chromium.org>
---
src/Kconfig | 9 +--
src/arch/x86/boot/coreboot_table.c | 20 -------
src/include/cbfs.h | 21 ++++---
src/include/cbmem.h | 5 --
src/include/rmodule.h | 16 ++---
src/include/romstage_handoff.h | 3 -
src/lib/cbfs.c | 91 ++++++++++++++++-------------
src/lib/hardwaremain.c | 9 ---
src/lib/rmodule.c | 38 ++++++------
src/northbridge/intel/haswell/northbridge.c | 15 -----
10 files changed, 94 insertions(+), 133 deletions(-)
diff --git a/src/Kconfig b/src/Kconfig
index 0297970..18b5bad 100644
--- a/src/Kconfig
+++ b/src/Kconfig
@@ -315,14 +315,7 @@ config HAVE_INIT_TIMER
config HIGH_SCRATCH_MEMORY_SIZE
hex
- default 0x5000 if RELOCATABLE_RAMSTAGE
default 0x0
- help
- The amount of extra memory to reserve from the OS. If
- RELOCATABLE_RAMSTAGE is enabled a size of 20KiB is reserved. This is
- for the use of a stack in romstage after memory has been initialized.
- The stack size required in romstage can be large when needing to
- decompress the ramstage.
config USE_OPTION_TABLE
bool
@@ -390,7 +383,7 @@ config RELOCATABLE_MODULES
loaded anywhere and all the relocations are handled automatically.
config RELOCATABLE_RAMSTAGE
- depends on RELOCATABLE_MODULES
+ depends on (RELOCATABLE_MODULES && DYNAMIC_CBMEM)
bool "Build the ramstage to be relocatable in 32-bit address space."
default n
help
diff --git a/src/arch/x86/boot/coreboot_table.c b/src/arch/x86/boot/coreboot_table.c
index 617fab2..530849f 100644
--- a/src/arch/x86/boot/coreboot_table.c
+++ b/src/arch/x86/boot/coreboot_table.c
@@ -31,7 +31,6 @@
#include <stdlib.h>
#include <cbfs.h>
#include <cbmem.h>
-#include <romstage_handoff.h>
#if CONFIG_USE_OPTION_TABLE
#include <option_table.h>
#endif
@@ -596,23 +595,6 @@ static void add_lb_reserved(struct lb_memory *mem)
lb_add_rsvd_range, mem);
}
-static void add_romstage_resources(struct lb_memory *mem)
-{
- struct romstage_handoff *handoff;
-
- /* Reserve memory requested to be reserved from romstage. */
- handoff = cbmem_find(CBMEM_ID_ROMSTAGE_INFO);
-
- if (handoff == NULL)
- return;
-
- if (handoff->reserve_size == 0)
- return;
-
- lb_add_memory_range(mem, LB_MEM_RESERVED, handoff->reserve_base,
- handoff->reserve_size);
-}
-
unsigned long write_coreboot_table(
unsigned long low_table_start, unsigned long low_table_end,
unsigned long rom_table_start, unsigned long rom_table_end)
@@ -686,8 +668,6 @@ unsigned long write_coreboot_table(
/* Add reserved regions */
add_lb_reserved(mem);
- add_romstage_resources(mem);
-
lb_dump_memory_ranges(mem);
/* Note:
diff --git a/src/include/cbfs.h b/src/include/cbfs.h
index 811df88..ac249aa 100644
--- a/src/include/cbfs.h
+++ b/src/include/cbfs.h
@@ -87,21 +87,24 @@ int init_default_cbfs_media(struct cbfs_media *media);
/* The cache_loaded_ramstage() and load_cached_ramstage() functions are defined
* to be weak so that board and chipset code may override them. Their job is to
* cache and load the ramstage for quick S3 resume. By default a copy of the
- * relocated ramstage is saved just below the running ramstage region. These
+ * relocated ramstage is saved using the cbmem infrastructure. These
* functions are only valid during romstage. */
struct romstage_handoff;
+struct cbmem_entry;
-/* The implementer of cache_loaded_ramstage() needs to ensure that the
- * reserve_* fields in in romstage_handoff reflect the memory footprint of the
- * ramstage (including cached region). Note that the handoff variable can be
- * NULL. */
+/* The implementer of cache_loaded_ramstage() may use the romstage_handoff
+ * structure to store information, but note that the handoff variable can be
+ * NULL. The ramstage cbmem_entry represents the region occupied by the loaded
+ * ramstage. */
void __attribute__((weak))
-cache_loaded_ramstage(struct romstage_handoff *handoff, void *ramstage_base,
- uint32_t ramstage_size, void *entry_point);
-/* Return NULL on error or entry point on success. */
+cache_loaded_ramstage(struct romstage_handoff *handoff,
+ const struct cbmem_entry *ramstage, void *entry_point);
+/* Return NULL on error or entry point on success. The ramstage cbmem_entry is
+ * the region where to load the cached contents to. */
void * __attribute__((weak))
-load_cached_ramstage(struct romstage_handoff *handoff);
+load_cached_ramstage(struct romstage_handoff *handoff,
+ const struct cbmem_entry *ramstage);
#endif /* CONFIG_RELOCATABLE_RAMSTAGE */
#endif
diff --git a/src/include/cbmem.h b/src/include/cbmem.h
index 41f5971..b3d9f86 100644
--- a/src/include/cbmem.h
+++ b/src/include/cbmem.h
@@ -131,11 +131,6 @@ void cbmem_add_lb_mem(struct lb_memory *mem);
#ifndef __PRE_RAM__
extern uint64_t high_tables_base, high_tables_size;
-#if CONFIG_EARLY_CBMEM_INIT
-/* Return 0 on success, < 0 on error. */
-int __attribute__((weak)) cbmem_get_table_location(uint64_t *tables_base,
- uint64_t *tables_size);
-#endif
void set_cbmem_toc(struct cbmem_entry *);
#endif
diff --git a/src/include/rmodule.h b/src/include/rmodule.h
index 2d8fc0f..631c63d 100644
--- a/src/include/rmodule.h
+++ b/src/include/rmodule.h
@@ -41,13 +41,15 @@ int rmodule_entry_offset(const struct rmodule *m);
int rmodule_memory_size(const struct rmodule *m);
int rmodule_load(void *loc, struct rmodule *m);
int rmodule_load_alignment(const struct rmodule *m);
-/* Returns the an aligned pointer that reflects a region used below addr
- * based on the rmodule_size. i.e. the returned pointer up to addr is memory
- * that may be utilized by the rmodule. program_start and rmodule_start
- * are pointers updated to reflect where the rmodule program starts and where
- * the rmodule (including header) should be placed respectively. */
-void *rmodule_find_region_below(void *addr, size_t rmodule_size,
- void **program_start, void **rmodule_start);
+/* rmodule_calc_region() calculates the region size, offset to place an
+ * rmodule in memory, and load address offset based off of a region allocator
+ * with an alignment of region_alignment. This function helps place an rmodule
+ * in the same location in ram it will run from. The offset to place the
+ * rmodule into the region allocated of size region_size is returned. The
+ * load_offset is the address to load and relocate the rmodule.
+ * region_alignment must be a power of 2. */
+int rmodule_calc_region(unsigned int region_alignment, size_t rmodule_size,
+ size_t *region_size, int *load_offset);
#define FIELD_ENTRY(x_) ((u32)&x_)
#define RMODULE_HEADER(entry_, type_) \
diff --git a/src/include/romstage_handoff.h b/src/include/romstage_handoff.h
index 4150e8e..3152fb2 100644
--- a/src/include/romstage_handoff.h
+++ b/src/include/romstage_handoff.h
@@ -28,9 +28,6 @@
* using the CBMEM_ID_ROMSTAGE_INFO id it needs to ensure it doesn't clobber
* fields it doesn't own. */
struct romstage_handoff {
- /* This indicates to the ramstage to reserve a chunk of memory. */
- uint32_t reserve_base;
- uint32_t reserve_size;
/* Inidicate if the current boot is an S3 resume. If
* CONFIG_RELOCTABLE_RAMSTAGE is enabled the chipset code is
* responsible for initializing this variable. Otherwise, ramstage
diff --git a/src/lib/cbfs.c b/src/lib/cbfs.c
index 7bd4309..45ae7c7 100644
--- a/src/lib/cbfs.c
+++ b/src/lib/cbfs.c
@@ -120,41 +120,48 @@ void *cbfs_load_optionrom(struct cbfs_media *media, uint16_t vendor,
#include <rmodule.h>
#include <romstage_handoff.h>
/* When CONFIG_RELOCATABLE_RAMSTAGE is enabled and this file is being compiled
- * for the romstage, the rmodule loader is used. The ramstage is placed just
- * below the cbmem location. */
-
+ * for the romstage, the rmodule loader is used. */
void __attribute__((weak))
-cache_loaded_ramstage(struct romstage_handoff *handoff, void *ramstage_base,
- uint32_t ramstage_size, void *entry_point)
+cache_loaded_ramstage(struct romstage_handoff *handoff,
+ const struct cbmem_entry *ramstage, void *entry_point)
{
+ uint32_t ramstage_size;
+ const struct cbmem_entry *entry;
+
if (handoff == NULL)
return;
- /* Cache the loaded ramstage just below the to-be-run ramstage. Then
- * save the base, size, and entry point in the handoff area. */
- handoff->reserve_base = (uint32_t)ramstage_base - ramstage_size;
- handoff->reserve_size = ramstage_size;
- handoff->ramstage_entry_point = (uint32_t)entry_point;
+ ramstage_size = cbmem_entry_size(ramstage);
+ /* cbmem_entry_add() does a find() before add(). */
+ entry = cbmem_entry_add(CBMEM_ID_RAMSTAGE_CACHE, ramstage_size);
- memcpy((void *)handoff->reserve_base, ramstage_base, ramstage_size);
+ if (entry == NULL)
+ return;
+
+ /* Keep track of the entry point in the handoff structure. */
+ handoff->ramstage_entry_point = (uint32_t)entry_point;
- /* Update the reserve region by 2x in order to store the cached copy. */
- handoff->reserve_size += handoff->reserve_size;
+ memcpy(cbmem_entry_start(entry), cbmem_entry_start(ramstage),
+ ramstage_size);
}
void * __attribute__((weak))
-load_cached_ramstage(struct romstage_handoff *handoff)
+load_cached_ramstage(struct romstage_handoff *handoff,
+ const struct cbmem_entry *ramstage)
{
- uint32_t ramstage_size;
+ const struct cbmem_entry *entry_cache;
if (handoff == NULL)
return NULL;
- /* Load the cached ramstage copy into the to-be-run region. It is just
- * above the cached copy. */
- ramstage_size = handoff->reserve_size / 2;
- memcpy((void *)(handoff->reserve_base + ramstage_size),
- (void *)handoff->reserve_base, ramstage_size);
+ entry_cache = cbmem_entry_find(CBMEM_ID_RAMSTAGE_CACHE);
+
+ if (entry_cache == NULL)
+ return NULL;
+
+ /* Load the cached ramstage copy into the to-be-run region. */
+ memcpy(cbmem_entry_start(ramstage), cbmem_entry_start(entry_cache),
+ cbmem_entry_size(ramstage));
return (void *)handoff->ramstage_entry_point;
}
@@ -164,12 +171,12 @@ static void *load_stage_from_cbfs(struct cbfs_media *media, const char *name,
{
struct cbfs_stage *stage;
struct rmodule ramstage;
- char *cbmem_base;
- char *ramstage_base;
- void *decompression_loc;
- void *ramstage_loc;
void *entry_point;
- uint32_t ramstage_size;
+ size_t region_size;
+ char *ramstage_region;
+ int rmodule_offset;
+ int load_offset;
+ const struct cbmem_entry *ramstage_entry;
stage = (struct cbfs_stage *)
cbfs_get_file_content(media, name, CBFS_TYPE_STAGE);
@@ -177,34 +184,34 @@ static void *load_stage_from_cbfs(struct cbfs_media *media, const char *name,
if (stage == NULL)
return (void *) -1;
- cbmem_base = (void *)get_cbmem_toc();
- if (cbmem_base == NULL)
+ rmodule_offset =
+ rmodule_calc_region(DYN_CBMEM_ALIGN_SIZE,
+ stage->memlen, ®ion_size, &load_offset);
+
+ ramstage_entry = cbmem_entry_add(CBMEM_ID_RAMSTAGE, region_size);
+
+ if (ramstage_entry == NULL)
return (void *) -1;
- ramstage_base =
- rmodule_find_region_below(cbmem_base, stage->memlen,
- &ramstage_loc,
- &decompression_loc);
+ ramstage_region = cbmem_entry_start(ramstage_entry);
LOG("Decompressing stage %s @ 0x%p (%d bytes)\n",
- name, decompression_loc, stage->memlen);
+ name, &ramstage_region[rmodule_offset], stage->memlen);
if (cbfs_decompress(stage->compression, &stage[1],
- decompression_loc, stage->len))
+ &ramstage_region[rmodule_offset], stage->len))
return (void *) -1;
- if (rmodule_parse(decompression_loc, &ramstage))
+ if (rmodule_parse(&ramstage_region[rmodule_offset], &ramstage))
return (void *) -1;
/* The ramstage is responsible for clearing its own bss. */
- if (rmodule_load(ramstage_loc, &ramstage))
+ if (rmodule_load(&ramstage_region[load_offset], &ramstage))
return (void *) -1;
entry_point = rmodule_entry(&ramstage);
- ramstage_size = cbmem_base - ramstage_base;
- cache_loaded_ramstage(handoff, ramstage_base, ramstage_size,
- entry_point);
+ cache_loaded_ramstage(handoff, ramstage_entry, entry_point);
return entry_point;
}
@@ -212,6 +219,7 @@ static void *load_stage_from_cbfs(struct cbfs_media *media, const char *name,
void * cbfs_load_stage(struct cbfs_media *media, const char *name)
{
struct romstage_handoff *handoff;
+ const struct cbmem_entry *ramstage;
void *entry;
handoff = romstage_handoff_find_or_add();
@@ -222,9 +230,14 @@ void * cbfs_load_stage(struct cbfs_media *media, const char *name)
} else if (!handoff->s3_resume)
return load_stage_from_cbfs(media, name, handoff);
+ ramstage = cbmem_entry_find(CBMEM_ID_RAMSTAGE);
+
+ if (ramstage == NULL)
+ return load_stage_from_cbfs(name, handoff);
+
/* S3 resume path. Load a cached copy of the loaded ramstage. If
* return value is NULL load from cbfs. */
- entry = load_cached_ramstage(handoff);
+ entry = load_cached_ramstage(handoff, ramstage);
if (entry == NULL)
return load_stage_from_cbfs(name, handoff);
diff --git a/src/lib/hardwaremain.c b/src/lib/hardwaremain.c
index bc18989..a3ee10b 100644
--- a/src/lib/hardwaremain.c
+++ b/src/lib/hardwaremain.c
@@ -85,15 +85,6 @@ void hardwaremain(int boot_complete)
/* FIXME: Is there a better way to handle this? */
init_timer();
- /* CONFIG_EARLY_CBMEM_INIT indicates that romstage initialized
- * the cbmem area. Therefore the table location can be initialized
- * early in ramstage if cbmem_get_table_location() is implemented.
- */
-#if CONFIG_EARLY_CBMEM_INIT
- if (cbmem_get_table_location != NULL &&
- !cbmem_get_table_location(&high_tables_base, &high_tables_size))
- cbmem_initialize();
-#endif
init_cbmem_pre_device();
timestamp_stash(TS_DEVICE_ENUMERATE);
diff --git a/src/lib/rmodule.c b/src/lib/rmodule.c
index 4276ed3..b56ec32 100644
--- a/src/lib/rmodule.c
+++ b/src/lib/rmodule.c
@@ -16,6 +16,7 @@
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
+#include <assert.h>
#include <stdint.h>
#include <stdlib.h>
#include <string.h>
@@ -254,16 +255,22 @@ int rmodule_load(void *base, struct rmodule *module)
return 0;
}
-void *rmodule_find_region_below(void *addr, size_t rmodule_size,
- void **program_start, void **rmodule_start)
+int rmodule_calc_region(unsigned int region_alignment, size_t rmodule_size,
+ size_t *region_size, int *load_offset)
{
- unsigned long ceiling;
- unsigned long program_base;
- unsigned long placement_loc;
- unsigned long program_begin;
+ /* region_alignment must be a power of 2. */
+ if (region_alignment & (region_alignment - 1))
+ BUG();
- ceiling = (unsigned long)addr;
- /* Place the rmodule just under the ceiling. The rmodule files
+ if (region_alignment < 4096)
+ region_alignment = 4096;
+
+ /* Sanity check rmodule_header size. The code below assumes it is less
+ * than the minimum alignment required. */
+ if (region_alignment < sizeof(struct rmodule_header))
+ BUG();
+
+ /* Place the rmodule according to alignment. The rmodule files
* themselves are packed as a header and a payload, however the rmodule
* itself is linked along with the header. The header starts at address
* 0. Immediately following the header in the file is the program,
@@ -273,13 +280,13 @@ void *rmodule_find_region_below(void *addr, size_t rmodule_size,
* to place the rmodule so that the program falls on the aligned
* address with the header just before it. Therefore, we need at least
* a page to account for the size of the header. */
- program_base = ALIGN((ceiling - (rmodule_size + 4096)), 4096);
+ *region_size = ALIGN(rmodule_size + region_alignment, 4096);
/* The program starts immediately after the header. However,
* it needs to be aligned to a 4KiB boundary. Therefore, adjust the
* program location so that the program lands on a page boundary. The
* layout looks like the following:
*
- * +--------------------------------+ ceiling
+ * +--------------------------------+ region_alignment + region_size
* | >= 0 bytes from alignment |
* +--------------------------------+ program end (4KiB aligned)
* | program size |
@@ -287,14 +294,9 @@ void *rmodule_find_region_below(void *addr, size_t rmodule_size,
* | sizeof(struct rmodule_header) |
* +--------------------------------+ rmodule header start
* | >= 0 bytes from alignment |
- * +--------------------------------+ program_base (4KiB aligned)
+ * +--------------------------------+ region_alignment
*/
- placement_loc = ALIGN(program_base + sizeof(struct rmodule_header),
- 4096) - sizeof(struct rmodule_header);
- program_begin = placement_loc + sizeof(struct rmodule_header);
-
- *program_start = (void *)program_begin;
- *rmodule_start = (void *)placement_loc;
+ *load_offset = region_alignment;
- return (void *)program_base;
+ return region_alignment - sizeof(struct rmodule_header);
}
diff --git a/src/northbridge/intel/haswell/northbridge.c b/src/northbridge/intel/haswell/northbridge.c
index 8708138..53c2f36 100644
--- a/src/northbridge/intel/haswell/northbridge.c
+++ b/src/northbridge/intel/haswell/northbridge.c
@@ -543,21 +543,6 @@ static void northbridge_init(struct device *dev)
MCHBAR32(0x5500) = 0x00100001;
}
-#if CONFIG_EARLY_CBMEM_INIT
-int cbmem_get_table_location(uint64_t *tables_base, uint64_t *tables_size)
-{
- uint32_t tseg;
-
- /* Put the CBMEM location just below TSEG. */
- *tables_size = HIGH_MEMORY_SIZE;
- tseg = (pci_read_config32(dev_find_slot(0, PCI_DEVFN(0, 0)),
- TSEG) & ~((1 << 20) - 1)) - HIGH_MEMORY_SIZE;
- *tables_base = tseg;
-
- return 0;
-}
-#endif
-
static void northbridge_enable(device_t dev)
{
#if CONFIG_HAVE_ACPI_RESUME
the following patch was just integrated into master:
commit 55ed3106556a9bcbe36d3389dc5230d4a4ee2a40
Author: Aaron Durbin <adurbin(a)chromium.org>
Date: Fri Mar 1 17:00:39 2013 -0600
rmodule: correct ordering of bss clearing
This patch fixes an issue for rmodules which are copied into memory
at the final load/link location. If the bss section is cleared for
that rmodule the relocation could not take place properly since the
relocation information was wiped by act of clearing the bss. The
reason is that the relocation information resides at the same
address as the bss section. Correct this issue by performing the
relocation before clearing the bss.
Change-Id: I01a124a8201321a9eaf6144c743fa818c0f004b4
Signed-off-by: Aaron Durbin <adurbin(a)chromium.org>
Reviewed-on: http://review.coreboot.org/2822
Reviewed-by: Ronald G. Minnich <rminnich(a)gmail.com>
Tested-by: build bot (Jenkins)
Build-Tested: build bot (Jenkins) at Thu Mar 21 23:38:16 2013, giving +1
See http://review.coreboot.org/2822 for details.
-gerrit
Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2822
-gerrit
commit d6dd8cfea3aaad0445d28caf67a92ce0deb2993a
Author: Aaron Durbin <adurbin(a)chromium.org>
Date: Fri Mar 1 17:00:39 2013 -0600
rmodule: correct ordering of bss clearing
This patch fixes an issue for rmodules which are copied into memory
at the final load/link location. If the bss section is cleared for
that rmodule the relocation could not take place properly since the
relocation information was wiped by act of clearing the bss. The
reason is that the relocation information resides at the same
address as the bss section. Correct this issue by performing the
relocation before clearing the bss.
Change-Id: I01a124a8201321a9eaf6144c743fa818c0f004b4
Signed-off-by: Aaron Durbin <adurbin(a)chromium.org>
---
src/lib/rmodule.c | 10 +++++++---
1 file changed, 7 insertions(+), 3 deletions(-)
diff --git a/src/lib/rmodule.c b/src/lib/rmodule.c
index 81e9ef1..4276ed3 100644
--- a/src/lib/rmodule.c
+++ b/src/lib/rmodule.c
@@ -241,13 +241,17 @@ int rmodule_load(void *base, struct rmodule *module)
* In order to load the module at a given address, the following steps
* take place:
* 1. Copy payload to base address.
- * 2. Clear the bss segment.
- * 3. Adjust relocations within the module to new base address.
+ * 2. Adjust relocations within the module to new base address.
+ * 3. Clear the bss segment last since the relocations live where
+ * the bss is. If an rmodule is being loaded from its load
+ * address the relocations need to be processed before the bss.
*/
module->location = base;
rmodule_copy_payload(module);
+ if (rmodule_relocate(module))
+ return -1;
rmodule_clear_bss(module);
- return rmodule_relocate(module);
+ return 0;
}
void *rmodule_find_region_below(void *addr, size_t rmodule_size,
the following patch was just integrated into master:
commit df3a109b72907419d503c81257ea241becdbb915
Author: Aaron Durbin <adurbin(a)chromium.org>
Date: Wed Mar 13 12:41:44 2013 -0500
cbmem: dynamic cbmem support
This patch adds a parallel implementation of cbmem that supports
dynamic sizing. The original implementation relied on reserving
a fixed-size block of memory for adding cbmem entries. In order to
allow for more flexibility for adding cbmem allocations the dynamic
cbmem infrastructure was developed as an alternative to the fixed block
approach. Also, the amount of memory to reserve for cbmem allocations
does not need to be known prior to the first allocation.
The dynamic cbmem code implements the same API as the existing cbmem
code except for cbmem_init() and cbmem_reinit(). The add and find
routines behave the same way. The dynamic cbmem infrastructure
uses a top down allocator that starts allocating from a board/chipset
defined function cbmem_top(). A root pointer lives just below
cbmem_top(). In turn that pointer points to the root block which
contains the entries for all the large alloctations. The corresponding
block for each large allocation falls just below the previous entry.
It should be noted that this implementation rounds all allocations
up to a 4096 byte granularity. Though a packing allocator could
be written for small allocations it was deemed OK to just fragment
the memory as there shouldn't be that many small allocations. The
result is less code with a tradeoff of some wasted memory.
+----------------------+ <- cbmem_top()
| +----| root pointer |
| | +----------------------+
| | | |--------+
| +--->| root block |-----+ |
| +----------------------+ | |
| | | | |
| | | | |
| | alloc N |<----+ |
| +----------------------+ |
| | | |
| | | |
\|/ | alloc N + 1 |<-------+
v +----------------------+
In addition to preserving the previous cbmem API, the dynamic
cbmem API allows for removing blocks from cbmem. This allows for
the boot process to allocate memory that can be discarded after
it's been used for performing more complex boot tasks in romstage.
In order to plumb this support in there were some issues to work
around regarding writing of coreboot tables. There were a few
assumptions to how cbmem was layed out which dictated some ifdef
guarding and other runtime checks so as not to incorrectly
tag the e820 and coreboot memory tables.
The example shown below is using dynamic cbmem infrastructure.
The reserved memory for cbmem is less than 512KiB.
coreboot memory table:
0. 0000000000000000-0000000000000fff: CONFIGURATION TABLES
1. 0000000000001000-000000000002ffff: RAM
2. 0000000000030000-000000000003ffff: RESERVED
3. 0000000000040000-000000000009ffff: RAM
4. 00000000000a0000-00000000000fffff: RESERVED
5. 0000000000100000-0000000000efffff: RAM
6. 0000000000f00000-0000000000ffffff: RESERVED
7. 0000000001000000-000000007bf80fff: RAM
8. 000000007bf81000-000000007bffffff: CONFIGURATION TABLES
9. 000000007c000000-000000007e9fffff: RESERVED
10. 00000000f0000000-00000000f3ffffff: RESERVED
11. 00000000fed10000-00000000fed19fff: RESERVED
12. 00000000fed84000-00000000fed84fff: RESERVED
13. 0000000100000000-00000001005fffff: RAM
Wrote coreboot table at: 7bf81000, 0x39c bytes, checksum f5bf
coreboot table: 948 bytes.
CBMEM ROOT 0. 7bfff000 00001000
MRC DATA 1. 7bffe000 00001000
ROMSTAGE 2. 7bffd000 00001000
TIME STAMP 3. 7bffc000 00001000
ROMSTG STCK 4. 7bff7000 00005000
CONSOLE 5. 7bfe7000 00010000
VBOOT 6. 7bfe6000 00001000
RAMSTAGE 7. 7bf98000 0004e000
GDT 8. 7bf97000 00001000
ACPI 9. 7bf8b000 0000c000
ACPI GNVS 10. 7bf8a000 00001000
SMBIOS 11. 7bf89000 00001000
COREBOOT 12. 7bf81000 00008000
And the corresponding e820 entries:
BIOS-e820: [mem 0x0000000000000000-0x0000000000000fff] type 16
BIOS-e820: [mem 0x0000000000001000-0x000000000002ffff] usable
BIOS-e820: [mem 0x0000000000030000-0x000000000003ffff] reserved
BIOS-e820: [mem 0x0000000000040000-0x000000000009ffff] usable
BIOS-e820: [mem 0x00000000000a0000-0x00000000000fffff] reserved
BIOS-e820: [mem 0x0000000000100000-0x0000000000efffff] usable
BIOS-e820: [mem 0x0000000000f00000-0x0000000000ffffff] reserved
BIOS-e820: [mem 0x0000000001000000-0x000000007bf80fff] usable
BIOS-e820: [mem 0x000000007bf81000-0x000000007bffffff] type 16
BIOS-e820: [mem 0x000000007c000000-0x000000007e9fffff] reserved
BIOS-e820: [mem 0x00000000f0000000-0x00000000f3ffffff] reserved
BIOS-e820: [mem 0x00000000fed10000-0x00000000fed19fff] reserved
BIOS-e820: [mem 0x00000000fed84000-0x00000000fed84fff] reserved
BIOS-e820: [mem 0x0000000100000000-0x00000001005fffff] usable
Change-Id: Ie3bca52211800a8652a77ca684140cfc9b3b9a6b
Signed-off-by: Aaron Durbin <adurbin(a)chromium.org>
Reviewed-on: http://review.coreboot.org/2848
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich(a)gmail.com>
Build-Tested: build bot (Jenkins) at Wed Mar 20 23:30:02 2013, giving +1
Reviewed-By: Ronald G. Minnich <rminnich(a)gmail.com> at Thu Mar 21 23:24:19 2013, giving +2
See http://review.coreboot.org/2848 for details.
-gerrit
the following patch was just integrated into master:
commit c3221183ee4c5280103238a0068086479cf31ded
Author: Shawn Nematbakhsh <shawnn(a)google.com>
Date: Mon Feb 25 12:12:05 2013 -0800
cbfs: Change false ERROR print to a WARNING.
Change "ERROR" to "WARNING" -- not finding the indicated file is usually
not a fatal error.
Change-Id: I0600964360ee27484c393125823e833f29aaa7e7
Signed-off-by: Shawn Nematbakhsh <shawnn(a)google.com>
Reviewed-on: http://review.coreboot.org/2833
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net>
Reviewed-by: Ronald G. Minnich <rminnich(a)gmail.com>
Build-Tested: build bot (Jenkins) at Tue Mar 19 22:22:26 2013, giving +1
Reviewed-By: Ronald G. Minnich <rminnich(a)gmail.com> at Thu Mar 21 23:23:31 2013, giving +2
See http://review.coreboot.org/2833 for details.
-gerrit
the following patch was just integrated into master:
commit 71c7cdc8f40d9dc10c8cf44f8114d45ea54c8fae
Author: Stefan Reinauer <reinauer(a)chromium.org>
Date: Tue Mar 19 13:38:12 2013 -0700
Intel: Update CPU microcode for 6fx CPUs
Using the CPU microcode update script and
Intel's Linux* Processor Microcode Data File
from 2013-02-22
Change-Id: I9bb60bdc46f69db85487ba923e62315f6e5352f9
Signed-off-by: Stefan Reinauer <reinauer(a)google.com>
Reviewed-on: http://review.coreboot.org/2845
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich(a)gmail.com>
Build-Tested: build bot (Jenkins) at Tue Mar 19 23:49:56 2013, giving +1
Reviewed-By: Ronald G. Minnich <rminnich(a)gmail.com> at Thu Mar 21 23:20:40 2013, giving +2
See http://review.coreboot.org/2845 for details.
-gerrit
the following patch was just integrated into master:
commit b70197bfcbba39ca0a0a801ccc50ccaf0f942fa2
Author: Stefan Reinauer <reinauer(a)chromium.org>
Date: Tue Mar 19 13:33:50 2013 -0700
Intel: Update CPU microcode for 106cx CPUs
Using the CPU microcode update script and
Intel's Linux* Processor Microcode Data File
from 2013-02-22
Change-Id: Icaf0e39978daa9308cc2f0c4856d99fb6b7fdffa
Signed-off-by: Stefan Reinauer <reinauer(a)google.com>
Reviewed-on: http://review.coreboot.org/2844
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich(a)gmail.com>
Build-Tested: build bot (Jenkins) at Tue Mar 19 23:39:19 2013, giving +1
Reviewed-By: Ronald G. Minnich <rminnich(a)gmail.com> at Thu Mar 21 23:20:05 2013, giving +2
See http://review.coreboot.org/2844 for details.
-gerrit