the following patch was just integrated into master:
commit 1ad5564dd675a246f5b0a05d03482836d49d44a9
Author: Duncan Laurie <dlaurie(a)chromium.org>
Date: Thu Mar 7 14:08:04 2013 -0800
lynxpoint: Add helper functions for reading PM and GPIO base
These base addresses are used in several places and it
is helpful to have one location that is reading it.
Change-Id: Ibf589247f37771f06c18e3e58f92aaf3f0d11271
Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org>
Reviewed-on: http://review.coreboot.org/2812
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich(a)gmail.com>
Build-Tested: build bot (Jenkins) at Tue Mar 19 08:27:00 2013, giving +1
Reviewed-By: Ronald G. Minnich <rminnich(a)gmail.com> at Thu Mar 21 23:06:55 2013, giving +2
See http://review.coreboot.org/2812 for details.
-gerrit
the following patch was just integrated into master:
commit 5cc51c08cd44e2749f4a27775cefffd4b91e0a50
Author: Duncan Laurie <dlaurie(a)chromium.org>
Date: Thu Mar 7 14:06:43 2013 -0800
lynxpoint: Add function for checking for LP chipset
Add a helper function pch_is_lp() that will return 1 if
the current chipset is of the new "low power" variant used
with Haswell ULT.
Additionally these functions are added to SMM so it can
be used there.
Change-Id: I9acdea2c56076cd8d9627aba66cf0844c56a38fb
Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org>
Reviewed-on: http://review.coreboot.org/2811
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich(a)gmail.com>
Build-Tested: build bot (Jenkins) at Tue Mar 19 08:16:09 2013, giving +1
Reviewed-By: Ronald G. Minnich <rminnich(a)gmail.com> at Thu Mar 21 23:05:44 2013, giving +2
See http://review.coreboot.org/2811 for details.
-gerrit
the following patch was just integrated into master:
commit 7a3fd4de053e055ce6854e7ec42fb00da532d3d3
Author: Duncan Laurie <dlaurie(a)chromium.org>
Date: Thu Mar 7 14:00:43 2013 -0800
lynxpoint: Enable EC IO ports 0x62/0x66
In order to be able to talk to an EC via standard path.
Change-Id: I3fe76882dec9a0596cbc1c844afa2ddb03ed771c
Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org>
Reviewed-on: http://review.coreboot.org/2810
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich(a)gmail.com>
Build-Tested: build bot (Jenkins) at Tue Mar 19 08:04:59 2013, giving +1
Reviewed-By: Ronald G. Minnich <rminnich(a)gmail.com> at Thu Mar 21 23:04:31 2013, giving +2
See http://review.coreboot.org/2810 for details.
-gerrit
the following patch was just integrated into master:
commit 969ac8db18214cd56cf7d928cc3962554152a2de
Author: Duncan Laurie <dlaurie(a)chromium.org>
Date: Thu Mar 7 13:59:39 2013 -0800
haswell: Drop the device ID check in graphics init path
Change-Id: I10c4264d317b5fac02a44f50ed10b457e1865e17
Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org>
Reviewed-on: http://review.coreboot.org/2809
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich(a)gmail.com>
Build-Tested: build bot (Jenkins) at Tue Mar 19 07:54:20 2013, giving +1
Reviewed-By: Ronald G. Minnich <rminnich(a)gmail.com> at Thu Mar 21 23:04:07 2013, giving +2
See http://review.coreboot.org/2809 for details.
-gerrit
the following patch was just integrated into master:
commit b37d1fb95ae810bf8f55cc30aa6a5ca921c1ca05
Author: Aaron Durbin <adurbin(a)chromium.org>
Date: Mon Feb 25 10:51:52 2013 -0600
lynxpoint: update MBP give up routine
I'm not sure if I screwed this up originally or the Intel docs changed
(I didn't bother to go back and check). According to ME BWG 1.1.0 the give
up bit is in the host general status #2 register.
Change-Id: Ieaaf524b93e9eb9806173121dda63d0133278c2d
Signed-off-by: Aaron Durbin <adurbin(a)chromium.org>
Reviewed-on: http://review.coreboot.org/2808
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich(a)gmail.com>
Build-Tested: build bot (Jenkins) at Tue Mar 19 07:43:33 2013, giving +1
Reviewed-By: Ronald G. Minnich <rminnich(a)gmail.com> at Thu Mar 21 23:03:27 2013, giving +2
See http://review.coreboot.org/2808 for details.
-gerrit
the following patch was just integrated into master:
commit b86113fd9ade587f7cb69b8c0c5d6407917fb185
Author: Aaron Durbin <adurbin(a)chromium.org>
Date: Tue Feb 19 08:59:16 2013 -0600
haswell: RESET_ON_INVALID_RAMSTAGE_CACHE option
The RESET_ON_INVALID_RAMSTAGE_CACHE option indicates what to do
when the ramstage cache is found to be invalid on a S3 wake. If
selected the system will perform a system reset on S3 wake when the
ramstage cache is invalid. Otherwise it will signal to load the
ramstage from cbfs.
Change-Id: I8f21fcfc7f95fb3377ed2932868aa49a68904803
Signed-off-by: Aaron Durbin <adurbin(a)chromium.org>
Reviewed-on: http://review.coreboot.org/2807
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich(a)gmail.com>
Build-Tested: build bot (Jenkins) at Tue Mar 19 07:33:10 2013, giving +1
Reviewed-By: Ronald G. Minnich <rminnich(a)gmail.com> at Thu Mar 21 23:02:27 2013, giving +2
See http://review.coreboot.org/2807 for details.
-gerrit
the following patch was just integrated into master:
commit f7cdfe5b328dbddeead9ff62d19e9bed37f0295f
Author: Aaron Durbin <adurbin(a)chromium.org>
Date: Sat Feb 16 00:05:52 2013 -0600
haswell: implement ramstage caching in SMM region
Cache the relocated ramstage into the SMM region. There is
a reserved region within the final SMM region (TSEG). Use that
space to cache the relocated ramstage program. That way, on S3 resume
there is a copy that can be loaded quickly instead of accessing the
flash. Caching the ramstage in the SMM space is also helpful in that
it prevents the OS from tampering with the ramstage program.
Change-Id: Ifa695ad1c350d5b504b14cc29d3e83c79b317a62
Signed-off-by: Aaron Durbin <adurbin(a)chromium.org>
Reviewed-on: http://review.coreboot.org/2806
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich(a)gmail.com>
Build-Tested: build bot (Jenkins) at Tue Mar 19 07:21:23 2013, giving +1
Reviewed-By: Ronald G. Minnich <rminnich(a)gmail.com> at Thu Mar 21 23:00:39 2013, giving +2
See http://review.coreboot.org/2806 for details.
-gerrit
the following patch was just integrated into master:
commit de1f890186ce84963eb3dd1638784473193909c3
Author: Aaron Durbin <adurbin(a)chromium.org>
Date: Fri Feb 15 23:26:52 2013 -0600
coreboot: add caching loaded ramstage interface
Instead of hard coding the policy for how a relocated ramstage
image is saved add an interface. The interface consists of two
functions. cache_loaded_ramstage() and load_cached_ramstage()
are the functions to cache and load the relocated ramstage,
respectively. There are default implementations which cache and
load the relocated ramstage just below where the ramstage runs.
Change-Id: I4346e873d8543e7eee4c1cd484847d846f297bb0
Signed-off-by: Aaron Durbin <adurbin(a)chromium.org>
Reviewed-on: http://review.coreboot.org/2805
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich(a)gmail.com>
Build-Tested: build bot (Jenkins) at Tue Mar 19 07:10:25 2013, giving +1
Reviewed-By: Ronald G. Minnich <rminnich(a)gmail.com> at Thu Mar 21 22:59:40 2013, giving +2
See http://review.coreboot.org/2805 for details.
-gerrit
the following patch was just integrated into master:
commit 8ce667e50684bea7c60db43c0ca7dd1b3ec3fde3
Author: Aaron Durbin <adurbin(a)chromium.org>
Date: Fri Feb 15 21:45:06 2013 -0600
haswell: add multipurpose SMM memory region
The SMM region is available for multipurpose use before the SMM
handler is relocated. Provide a configurable sized region in the
TSEG for use before the SMM handler is relocated. This feature is
implemented by making the reserved size a Kconfig option. Also
make the IED region a Kconfig option as well. Lastly add some sanity
checking on the Kconfig options.
Change-Id: Idd7fccf925a8787146906ac766b7878845c75935
Signed-off-by: Aaron Durbin <adurbin(a)chromium.org>
Reviewed-on: http://review.coreboot.org/2804
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich(a)gmail.com>
Build-Tested: build bot (Jenkins) at Tue Mar 19 06:47:00 2013, giving +1
Reviewed-By: Ronald G. Minnich <rminnich(a)gmail.com> at Thu Mar 21 22:59:03 2013, giving +2
See http://review.coreboot.org/2804 for details.
-gerrit
the following patch was just integrated into master:
commit 67481ddc2e53cd3420fa8c723edb4fe47dccc196
Author: Aaron Durbin <adurbin(a)chromium.org>
Date: Fri Feb 15 15:08:37 2013 -0600
haswell: set TSEG as WB cacheable in romstage
The TSEG region is accessible until the SMM handler is relocated
to that region. Set the region as cacheable in romstage so that it
can be used for other purposes with fast access.
Change-Id: I92b83896e40bc26a54c2930e05c02492918e0874
Signed-off-by: Aaron Durbin <adurbin(a)chromium.org>
Reviewed-on: http://review.coreboot.org/2803
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich(a)gmail.com>
Build-Tested: build bot (Jenkins) at Tue Mar 19 06:58:30 2013, giving +1
Reviewed-By: Ronald G. Minnich <rminnich(a)gmail.com> at Thu Mar 21 22:58:17 2013, giving +2
See http://review.coreboot.org/2803 for details.
-gerrit