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March 2013

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New patch to review for coreboot: b07dc66 FrontRunner/Toucan-AF: Use SPD read code from F14 wrapper
by Jens Rottmann March 21, 2013

March 21, 2013

Jens Rottmann (JRottmann(a)LiPPERTembedded.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2874 -gerrit commit b07dc662cc382dd3c551bd2dd6ecb1baf034cb3a Author: Jens Rottmann <JRottmann(a)LiPPERTembedded.de> Date: Thu Mar 21 22:31:19 2013 +0100 FrontRunner/Toucan-AF: Use SPD read code from F14 wrapper Changes: - Get rid of the LiPPERT FrontRunner-AF and Toucan-AF mainboard specific code and use the platform generic function wrapper that was added in change http://review.coreboot.org/#/c/2497/ AMD f14: Add SPD read functions to wrapper code - Move DIMM addresses into devicetree.cb - Add the ASF init that used to be in the SPD read code into mainboard_enable() Notes: - The DIMM reads only happen in romstage, so the function is not available in ramstage. Point the read-SPD callback to a generic function in ramstage. Change-Id: I4ee5e1bc34f4caee20615c48248d4f7605c09377 Signed-off-by: Jens Rottmann <JRottmann(a)LiPPERTembedded.de> --- .../lippert/frontrunner-af/BiosCallOuts.c | 8 +- src/mainboard/lippert/frontrunner-af/Makefile.inc | 2 - src/mainboard/lippert/frontrunner-af/devicetree.cb | 7 + src/mainboard/lippert/frontrunner-af/dimmSpd.c | 164 --------------------- src/mainboard/lippert/frontrunner-af/dimmSpd.h | 63 -------- src/mainboard/lippert/frontrunner-af/mainboard.c | 9 ++ src/mainboard/lippert/toucan-af/BiosCallOuts.c | 8 +- src/mainboard/lippert/toucan-af/Makefile.inc | 2 - src/mainboard/lippert/toucan-af/devicetree.cb | 7 + src/mainboard/lippert/toucan-af/dimmSpd.c | 164 --------------------- src/mainboard/lippert/toucan-af/dimmSpd.h | 63 -------- src/mainboard/lippert/toucan-af/mainboard.c | 9 ++ 12 files changed, 44 insertions(+), 462 deletions(-) diff --git a/src/mainboard/lippert/frontrunner-af/BiosCallOuts.c b/src/mainboard/lippert/frontrunner-af/BiosCallOuts.c index 89e2731..fdb228c 100644 --- a/src/mainboard/lippert/frontrunner-af/BiosCallOuts.c +++ b/src/mainboard/lippert/frontrunner-af/BiosCallOuts.c @@ -19,9 +19,9 @@ #include "agesawrapper.h" #include "amdlib.h" -#include "dimmSpd.h" #include "BiosCallOuts.h" #include "heapManager.h" +#include <northbridge/amd/agesa/family14/dimmSpd.h> STATIC BIOS_CALLOUT_STRUCT BiosCallouts[] = { @@ -427,7 +427,11 @@ AGESA_STATUS BiosReset (UINT32 Func, UINT32 Data, VOID *ConfigPtr) AGESA_STATUS BiosReadSpd (UINT32 Func, UINT32 Data, VOID *ConfigPtr) { AGESA_STATUS Status; - Status = AmdMemoryReadSPD (Func, Data, (AGESA_READ_SPD_PARAMS *)ConfigPtr); +#ifdef __PRE_RAM__ + Status = agesa_ReadSPD (Func, Data, ConfigPtr); +#else + Status = AGESA_UNSUPPORTED; +#endif return Status; } diff --git a/src/mainboard/lippert/frontrunner-af/Makefile.inc b/src/mainboard/lippert/frontrunner-af/Makefile.inc index b1a3014..17443bc 100644 --- a/src/mainboard/lippert/frontrunner-af/Makefile.inc +++ b/src/mainboard/lippert/frontrunner-af/Makefile.inc @@ -26,13 +26,11 @@ endif romstage-y += buildOpts.c romstage-y += agesawrapper.c -romstage-y += dimmSpd.c romstage-y += BiosCallOuts.c romstage-y += PlatformGnbPcie.c ramstage-y += buildOpts.c ramstage-y += agesawrapper.c -ramstage-y += dimmSpd.c ramstage-y += BiosCallOuts.c ramstage-y += PlatformGnbPcie.c diff --git a/src/mainboard/lippert/frontrunner-af/devicetree.cb b/src/mainboard/lippert/frontrunner-af/devicetree.cb index 3a051aa..6aef23c 100644 --- a/src/mainboard/lippert/frontrunner-af/devicetree.cb +++ b/src/mainboard/lippert/frontrunner-af/devicetree.cb @@ -98,6 +98,13 @@ chip northbridge/amd/agesa/family14/root_complex device pci 18.5 on end device pci 18.6 on end device pci 18.7 on end + + register "spdAddrLookup" = " + { + { {0xA0, 0xA2}, {0x00, 0x00}, }, // socket 0 - Channel 0 & 1 - 8-bit SPD addresses + { {0x00, 0x00}, {0x00, 0x00}, }, // socket 1 - Channel 0 & 1 - 8-bit SPD addresses + }" + end #chip northbridge/amd/agesa/family14 # CPU side of HT root complex end #domain end #northbridge/amd/agesa/family14/root_complex diff --git a/src/mainboard/lippert/frontrunner-af/dimmSpd.c b/src/mainboard/lippert/frontrunner-af/dimmSpd.c deleted file mode 100644 index a021cc2..0000000 --- a/src/mainboard/lippert/frontrunner-af/dimmSpd.c +++ /dev/null @@ -1,164 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include "Porting.h" -#include "AGESA.h" -#include "amdlib.h" -#include "OEM.h" /* SMBUS0_BASE_ADDRESS */ - -AGESA_STATUS AmdMemoryReadSPD (UINT32 unused1, UINT32 unused2, AGESA_READ_SPD_PARAMS *info); -#define DIMENSION(array)(sizeof (array)/ sizeof (array [0])) - -/*#pragma optimize ("", off) // for source level debug -*--------------------------------------------------------------------------- -* -* SPD address table - porting required -*/ - -static const UINT8 spdAddressLookup [2] [2] [4] = // socket, channel, dimm -{ - // socket 0 - { - {0xA0, 0xA2}, // channel 0 dimms - {0x00, 0x00}, // channel 1 dimms - }, - // socket 1 - { - {0x00, 0x00}, // channel 0 dimms - {0x00, 0x00}, // channel 1 dimms - }, -}; - -/*----------------------------------------------------------------------------- - * - * readSmbusByteData - read a single SPD byte from any offset - */ - -static int readSmbusByteData (int iobase, int address, char *buffer, int offset) -{ - unsigned int status; - UINT64 limit; - - address |= 1; // set read bit - - __outbyte (iobase + 0, 0xFF); // clear error status - __outbyte (iobase + 1, 0x1F); // clear error status - __outbyte (iobase + 3, offset); // offset in eeprom - __outbyte (iobase + 4, address); // slave address and read bit - __outbyte (iobase + 2, 0x48); // read byte command - - // time limit to avoid hanging for unexpected error status (should never happen) - limit = __rdtsc () + 2000000000 / 10; - for (;;) { - status = __inbyte (iobase); - if (__rdtsc () > limit) break; - if ((status & 2) == 0) continue; // SMBusInterrupt not set, keep waiting - if ((status & 1) == 1) continue; // HostBusy set, keep waiting - break; - } - - buffer [0] = __inbyte (iobase + 5); - if (status == 2) status = 0; // check for done with no errors - return status; -} - -/*----------------------------------------------------------------------------- - * - * readSmbusByte - read a single SPD byte from the default offset - * this function is faster function readSmbusByteData - */ - -static int readSmbusByte (int iobase, int address, char *buffer) -{ - unsigned int status; - UINT64 limit; - - __outbyte (iobase + 0, 0xFF); // clear error status - __outbyte (iobase + 2, 0x44); // read command - - // time limit to avoid hanging for unexpected error status - limit = __rdtsc () + 2000000000 / 10; - for (;;) { - status = __inbyte (iobase); - if (__rdtsc () > limit) break; - if ((status & 2) == 0) continue; // SMBusInterrupt not set, keep waiting - if ((status & 1) == 1) continue; // HostBusy set, keep waiting - break; - } - - buffer [0] = __inbyte (iobase + 5); - if (status == 2) status = 0; // check for done with no errors - return status; -} - -/*--------------------------------------------------------------------------- - * - * readspd - Read one or more SPD bytes from a DIMM. - * Start with offset zero and read sequentially. - * Optimization relies on autoincrement to avoid - * sending offset for every byte. - * Reads 128 bytes in 7-8 ms at 400 KHz. - */ - -static int readspd (int iobase, int SmbusSlaveAddress, char *buffer, int count) -{ - int index, error; - - /* read the first byte using offset zero */ - error = readSmbusByteData (iobase, SmbusSlaveAddress, buffer, 0); - if (error) return error; - - /* read the remaining bytes using auto-increment for speed */ - for (index = 1; index < count; index++) { - error = readSmbusByte (iobase, SmbusSlaveAddress, &buffer [index]); - if (error) return error; - } - - return 0; -} - -static void writePmReg (int reg, int data) - { - __outbyte (0xCD6, reg); - __outbyte (0xCD7, data); - } - -static void setupFch (int ioBase) -{ - writePmReg (0x2D, ioBase >> 8); - writePmReg (0x2C, ioBase | 1); - writePmReg (0x29, 0x80); - writePmReg (0x28, 0x61); - __outbyte (ioBase + 0x0E, 66000000 / 400000 / 4); // set SMBus clock to 400 KHz -} - -AGESA_STATUS AmdMemoryReadSPD (UINT32 unused1, UINT32 unused2, AGESA_READ_SPD_PARAMS *info) -{ - int spdAddress, ioBase; - - if (info->SocketId >= DIMENSION (spdAddressLookup )) return AGESA_ERROR; - if (info->MemChannelId >= DIMENSION (spdAddressLookup[0] )) return AGESA_ERROR; - if (info->DimmId >= DIMENSION (spdAddressLookup[0][0])) return AGESA_ERROR; - - spdAddress = spdAddressLookup [info->SocketId] [info->MemChannelId] [info->DimmId]; - if (spdAddress == 0) return AGESA_ERROR; - ioBase = SMBUS0_BASE_ADDRESS; - setupFch (ioBase); - return readspd (ioBase, spdAddress, (void *) info->Buffer, 128); -} diff --git a/src/mainboard/lippert/frontrunner-af/dimmSpd.h b/src/mainboard/lippert/frontrunner-af/dimmSpd.h deleted file mode 100644 index 9ff397d..0000000 --- a/src/mainboard/lippert/frontrunner-af/dimmSpd.h +++ /dev/null @@ -1,63 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ - -#ifndef _DIMMSPD_H_ -#define _DIMMSPD_H_ - -#include "Porting.h" -#include "AGESA.h" - -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * E X P O R T E D F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - -AGESA_STATUS -AmdMemoryReadSPD ( - IN UINT32 Func, - IN UINT32 Data, - IN OUT AGESA_READ_SPD_PARAMS *SpdData - ); - -/*--------------------------------------------------------------------------------------- - * L O C A L F U N C T I O N S - *--------------------------------------------------------------------------------------- - */ - -#endif diff --git a/src/mainboard/lippert/frontrunner-af/mainboard.c b/src/mainboard/lippert/frontrunner-af/mainboard.c index 72f2793..57543c2 100644 --- a/src/mainboard/lippert/frontrunner-af/mainboard.c +++ b/src/mainboard/lippert/frontrunner-af/mainboard.c @@ -183,6 +183,15 @@ static void mainboard_enable(device_t dev) *(misc_mem_clk_cntrl + 2) = 0x00; *(misc_mem_clk_cntrl + 3) = 0x00; *(misc_mem_clk_cntrl + 4) = 0x00; + + /* + * Initialize ASF registers to an arbitrary address because someone + * long ago set things up this way inside the SPD read code. The + * SPD read code has been made generic and moved out of the board + * directory, so the ASF init is being done here. + */ + pm_iowrite(0x29, 0x80); + pm_iowrite(0x28, 0x61); } struct chip_operations mainboard_ops = { diff --git a/src/mainboard/lippert/toucan-af/BiosCallOuts.c b/src/mainboard/lippert/toucan-af/BiosCallOuts.c index 936ce9b..6398e31 100644 --- a/src/mainboard/lippert/toucan-af/BiosCallOuts.c +++ b/src/mainboard/lippert/toucan-af/BiosCallOuts.c @@ -19,9 +19,9 @@ #include "agesawrapper.h" #include "amdlib.h" -#include "dimmSpd.h" #include "BiosCallOuts.h" #include "heapManager.h" +#include <northbridge/amd/agesa/family14/dimmSpd.h> STATIC BIOS_CALLOUT_STRUCT BiosCallouts[] = { @@ -427,7 +427,11 @@ AGESA_STATUS BiosReset (UINT32 Func, UINT32 Data, VOID *ConfigPtr) AGESA_STATUS BiosReadSpd (UINT32 Func, UINT32 Data, VOID *ConfigPtr) { AGESA_STATUS Status; - Status = AmdMemoryReadSPD (Func, Data, (AGESA_READ_SPD_PARAMS *)ConfigPtr); +#ifdef __PRE_RAM__ + Status = agesa_ReadSPD (Func, Data, ConfigPtr); +#else + Status = AGESA_UNSUPPORTED; +#endif return Status; } diff --git a/src/mainboard/lippert/toucan-af/Makefile.inc b/src/mainboard/lippert/toucan-af/Makefile.inc index b1a3014..17443bc 100644 --- a/src/mainboard/lippert/toucan-af/Makefile.inc +++ b/src/mainboard/lippert/toucan-af/Makefile.inc @@ -26,13 +26,11 @@ endif romstage-y += buildOpts.c romstage-y += agesawrapper.c -romstage-y += dimmSpd.c romstage-y += BiosCallOuts.c romstage-y += PlatformGnbPcie.c ramstage-y += buildOpts.c ramstage-y += agesawrapper.c -ramstage-y += dimmSpd.c ramstage-y += BiosCallOuts.c ramstage-y += PlatformGnbPcie.c diff --git a/src/mainboard/lippert/toucan-af/devicetree.cb b/src/mainboard/lippert/toucan-af/devicetree.cb index fbe2a2c..d110c3a 100644 --- a/src/mainboard/lippert/toucan-af/devicetree.cb +++ b/src/mainboard/lippert/toucan-af/devicetree.cb @@ -104,6 +104,13 @@ chip northbridge/amd/agesa/family14/root_complex device pci 18.5 on end device pci 18.6 on end device pci 18.7 on end + + register "spdAddrLookup" = " + { + { {0xA0, 0xA2}, {0x00, 0x00}, }, // socket 0 - Channel 0 & 1 - 8-bit SPD addresses + { {0x00, 0x00}, {0x00, 0x00}, }, // socket 1 - Channel 0 & 1 - 8-bit SPD addresses + }" + end #chip northbridge/amd/agesa/family14 # CPU side of HT root complex end #domain end #northbridge/amd/agesa/family14/root_complex diff --git a/src/mainboard/lippert/toucan-af/dimmSpd.c b/src/mainboard/lippert/toucan-af/dimmSpd.c deleted file mode 100644 index a021cc2..0000000 --- a/src/mainboard/lippert/toucan-af/dimmSpd.c +++ /dev/null @@ -1,164 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include "Porting.h" -#include "AGESA.h" -#include "amdlib.h" -#include "OEM.h" /* SMBUS0_BASE_ADDRESS */ - -AGESA_STATUS AmdMemoryReadSPD (UINT32 unused1, UINT32 unused2, AGESA_READ_SPD_PARAMS *info); -#define DIMENSION(array)(sizeof (array)/ sizeof (array [0])) - -/*#pragma optimize ("", off) // for source level debug -*--------------------------------------------------------------------------- -* -* SPD address table - porting required -*/ - -static const UINT8 spdAddressLookup [2] [2] [4] = // socket, channel, dimm -{ - // socket 0 - { - {0xA0, 0xA2}, // channel 0 dimms - {0x00, 0x00}, // channel 1 dimms - }, - // socket 1 - { - {0x00, 0x00}, // channel 0 dimms - {0x00, 0x00}, // channel 1 dimms - }, -}; - -/*----------------------------------------------------------------------------- - * - * readSmbusByteData - read a single SPD byte from any offset - */ - -static int readSmbusByteData (int iobase, int address, char *buffer, int offset) -{ - unsigned int status; - UINT64 limit; - - address |= 1; // set read bit - - __outbyte (iobase + 0, 0xFF); // clear error status - __outbyte (iobase + 1, 0x1F); // clear error status - __outbyte (iobase + 3, offset); // offset in eeprom - __outbyte (iobase + 4, address); // slave address and read bit - __outbyte (iobase + 2, 0x48); // read byte command - - // time limit to avoid hanging for unexpected error status (should never happen) - limit = __rdtsc () + 2000000000 / 10; - for (;;) { - status = __inbyte (iobase); - if (__rdtsc () > limit) break; - if ((status & 2) == 0) continue; // SMBusInterrupt not set, keep waiting - if ((status & 1) == 1) continue; // HostBusy set, keep waiting - break; - } - - buffer [0] = __inbyte (iobase + 5); - if (status == 2) status = 0; // check for done with no errors - return status; -} - -/*----------------------------------------------------------------------------- - * - * readSmbusByte - read a single SPD byte from the default offset - * this function is faster function readSmbusByteData - */ - -static int readSmbusByte (int iobase, int address, char *buffer) -{ - unsigned int status; - UINT64 limit; - - __outbyte (iobase + 0, 0xFF); // clear error status - __outbyte (iobase + 2, 0x44); // read command - - // time limit to avoid hanging for unexpected error status - limit = __rdtsc () + 2000000000 / 10; - for (;;) { - status = __inbyte (iobase); - if (__rdtsc () > limit) break; - if ((status & 2) == 0) continue; // SMBusInterrupt not set, keep waiting - if ((status & 1) == 1) continue; // HostBusy set, keep waiting - break; - } - - buffer [0] = __inbyte (iobase + 5); - if (status == 2) status = 0; // check for done with no errors - return status; -} - -/*--------------------------------------------------------------------------- - * - * readspd - Read one or more SPD bytes from a DIMM. - * Start with offset zero and read sequentially. - * Optimization relies on autoincrement to avoid - * sending offset for every byte. - * Reads 128 bytes in 7-8 ms at 400 KHz. - */ - -static int readspd (int iobase, int SmbusSlaveAddress, char *buffer, int count) -{ - int index, error; - - /* read the first byte using offset zero */ - error = readSmbusByteData (iobase, SmbusSlaveAddress, buffer, 0); - if (error) return error; - - /* read the remaining bytes using auto-increment for speed */ - for (index = 1; index < count; index++) { - error = readSmbusByte (iobase, SmbusSlaveAddress, &buffer [index]); - if (error) return error; - } - - return 0; -} - -static void writePmReg (int reg, int data) - { - __outbyte (0xCD6, reg); - __outbyte (0xCD7, data); - } - -static void setupFch (int ioBase) -{ - writePmReg (0x2D, ioBase >> 8); - writePmReg (0x2C, ioBase | 1); - writePmReg (0x29, 0x80); - writePmReg (0x28, 0x61); - __outbyte (ioBase + 0x0E, 66000000 / 400000 / 4); // set SMBus clock to 400 KHz -} - -AGESA_STATUS AmdMemoryReadSPD (UINT32 unused1, UINT32 unused2, AGESA_READ_SPD_PARAMS *info) -{ - int spdAddress, ioBase; - - if (info->SocketId >= DIMENSION (spdAddressLookup )) return AGESA_ERROR; - if (info->MemChannelId >= DIMENSION (spdAddressLookup[0] )) return AGESA_ERROR; - if (info->DimmId >= DIMENSION (spdAddressLookup[0][0])) return AGESA_ERROR; - - spdAddress = spdAddressLookup [info->SocketId] [info->MemChannelId] [info->DimmId]; - if (spdAddress == 0) return AGESA_ERROR; - ioBase = SMBUS0_BASE_ADDRESS; - setupFch (ioBase); - return readspd (ioBase, spdAddress, (void *) info->Buffer, 128); -} diff --git a/src/mainboard/lippert/toucan-af/dimmSpd.h b/src/mainboard/lippert/toucan-af/dimmSpd.h deleted file mode 100644 index 9ff397d..0000000 --- a/src/mainboard/lippert/toucan-af/dimmSpd.h +++ /dev/null @@ -1,63 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ - -#ifndef _DIMMSPD_H_ -#define _DIMMSPD_H_ - -#include "Porting.h" -#include "AGESA.h" - -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * E X P O R T E D F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - -AGESA_STATUS -AmdMemoryReadSPD ( - IN UINT32 Func, - IN UINT32 Data, - IN OUT AGESA_READ_SPD_PARAMS *SpdData - ); - -/*--------------------------------------------------------------------------------------- - * L O C A L F U N C T I O N S - *--------------------------------------------------------------------------------------- - */ - -#endif diff --git a/src/mainboard/lippert/toucan-af/mainboard.c b/src/mainboard/lippert/toucan-af/mainboard.c index 367397e..f6cf09c 100644 --- a/src/mainboard/lippert/toucan-af/mainboard.c +++ b/src/mainboard/lippert/toucan-af/mainboard.c @@ -150,6 +150,15 @@ static void mainboard_enable(device_t dev) *(misc_mem_clk_cntrl + 2) = 0x00; *(misc_mem_clk_cntrl + 3) = 0x00; *(misc_mem_clk_cntrl + 4) = 0x00; + + /* + * Initialize ASF registers to an arbitrary address because someone + * long ago set things up this way inside the SPD read code. The + * SPD read code has been made generic and moved out of the board + * directory, so the ASF init is being done here. + */ + pm_iowrite(0x29, 0x80); + pm_iowrite(0x28, 0x61); } struct chip_operations mainboard_ops = {

1 0

Patch merged into coreboot/master: e2d9e5b haswell: support for CONFIG_RELOCATABLE_RAMSTAGE
by gerrit＠coreboot.org March 21, 2013

March 21, 2013

the following patch was just integrated into master: commit e2d9e5bfa99e56eff56ab9b0f3389cfccd9670d6 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Fri Feb 8 17:38:35 2013 -0600 haswell: support for CONFIG_RELOCATABLE_RAMSTAGE Now that CONFIG_RELOCTABLE_RAMSTAGE is available support it on Haswell-based systems. This patch is comprised of the following changes: 1. Ensure that memory is not preserved when a relocatable ramstage is enabled. There is no need. 2. Pick the proper stack to use after cache-as-ram is torn down. When the ramstage is relocatable, finding a stack to use before vectoring into ramstage is impossible since the ramstage is a black box with an unknown layout. Change-Id: I2a07a497f52375569bae9c994432a8e7e7a40224 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: http://review.coreboot.org/2793 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich(a)gmail.com> Build-Tested: build bot (Jenkins) at Tue Mar 19 04:57:08 2013, giving +1 Reviewed-By: Ronald G. Minnich <rminnich(a)gmail.com> at Thu Mar 21 22:38:18 2013, giving +2 See http://review.coreboot.org/2793 for details. -gerrit

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Patch merged into coreboot/master: 8e4a355 coreboot: introduce CONFIG_RELOCATABLE_RAMSTAGE
by gerrit＠coreboot.org March 21, 2013

March 21, 2013

the following patch was just integrated into master: commit 8e4a355773cc64a89b3fc4d79981cfb02bda7e66 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Fri Feb 8 17:28:04 2013 -0600 coreboot: introduce CONFIG_RELOCATABLE_RAMSTAGE This patch adds an option to build the ramstage as a reloctable binary. It uses the rmodule library for the relocation. The main changes consist of the following: 1. The ramstage is loaded just under the cmbem space. 2. Payloads cannot be loaded over where ramstage is loaded. If a payload is attempted to load where the relocatable ramstage resides the load is aborted. 3. The memory occupied by the ramstage is reserved from the OS's usage using the romstage_handoff structure stored in cbmem. This region is communicated to ramstage by an CBMEM_ID_ROMSTAGE_INFO entry in cbmem. 4. There is no need to reserve cbmem space for the OS controlled memory for the resume path because the ramsage region has been reserved in #3. 5. Since no memory needs to be preserved in the wake path, the loading and begin of execution of a elf payload is straight forward. Change-Id: Ia66cf1be65c29fa25ca7bd9ea6c8f11d7eee05f5 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: http://review.coreboot.org/2792 Reviewed-by: Ronald G. Minnich <rminnich(a)gmail.com> Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin(a)google.com> Build-Tested: build bot (Jenkins) at Thu Mar 21 22:13:27 2013, giving +1 See http://review.coreboot.org/2792 for details. -gerrit

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Patch merged into coreboot/master: 43e4a80 Fix race condition building console code
by gerrit＠coreboot.org March 21, 2013

March 21, 2013

the following patch was just integrated into master: commit 43e4a80a92bf00540e4d9b0734eb53f32044226f Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Thu Mar 21 13:15:45 2013 -0700 Fix race condition building console code On ARMv7 the console code can also be built into the bootblock. Currently building the ARM targets on a reasonably fast machine can fail, because console.bootblock.o is attempted to build before build.h is created. This patch adds a specific rule for the bootblock variant of console.c, to match the other variants so that the race condition goes away. Change-Id: I52e4242c66a02f011ef26b854aa50c2606a1f81f Signed-off-by: Stefan Reinauer <reinauer(a)google.com> Reviewed-on: http://review.coreboot.org/2873 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick(a)georgi-clan.de> Reviewed-By: Patrick Georgi <patrick(a)georgi-clan.de> at Thu Mar 21 22:08:05 2013, giving +2 See http://review.coreboot.org/2873 for details. -gerrit

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Patch set updated for coreboot: 93e5a88 coreboot: introduce CONFIG_RELOCATABLE_RAMSTAGE
by Stefan Reinauer March 21, 2013

March 21, 2013

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2792 -gerrit commit 93e5a88dd895e4e64f4a19eb2687d8ff355c13cf Author: Aaron Durbin <adurbin(a)chromium.org> Date: Fri Feb 8 17:28:04 2013 -0600 coreboot: introduce CONFIG_RELOCATABLE_RAMSTAGE This patch adds an option to build the ramstage as a reloctable binary. It uses the rmodule library for the relocation. The main changes consist of the following: 1. The ramstage is loaded just under the cmbem space. 2. Payloads cannot be loaded over where ramstage is loaded. If a payload is attempted to load where the relocatable ramstage resides the load is aborted. 3. The memory occupied by the ramstage is reserved from the OS's usage using the romstage_handoff structure stored in cbmem. This region is communicated to ramstage by an CBMEM_ID_ROMSTAGE_INFO entry in cbmem. 4. There is no need to reserve cbmem space for the OS controlled memory for the resume path because the ramsage region has been reserved in #3. 5. Since no memory needs to be preserved in the wake path, the loading and begin of execution of a elf payload is straight forward. Change-Id: Ia66cf1be65c29fa25ca7bd9ea6c8f11d7eee05f5 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/Kconfig | 18 +++++++++ src/arch/x86/Makefile.inc | 8 ++++ src/arch/x86/boot/Makefile.inc | 1 + src/arch/x86/boot/acpi.c | 4 ++ src/arch/x86/boot/boot.c | 29 ++++++++++++++ src/arch/x86/boot/ramstage_module_header.c | 24 ++++++++++++ src/arch/x86/boot/tables.c | 3 ++ src/include/cbmem.h | 5 +++ src/lib/Makefile.inc | 1 + src/lib/cbfs.c | 61 ++++++++++++++++++++++++++++++ src/lib/selfboot.c | 16 ++++++++ 11 files changed, 170 insertions(+) diff --git a/src/Kconfig b/src/Kconfig index f6a83e8..7a8985c 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -307,7 +307,14 @@ config HAVE_INIT_TIMER config HIGH_SCRATCH_MEMORY_SIZE hex + default 0x5000 if RELOCATABLE_RAMSTAGE default 0x0 + help + The amount of extra memory to reserve from the OS. If + RELOCATABLE_RAMSTAGE is enabled a size of 20KiB is reserved. This is + for the use of a stack in romstage after memory has been initialized. + The stack size required in romstage can be large when needing to + decompress the ramstage. config USE_OPTION_TABLE bool @@ -374,6 +381,17 @@ config RELOCATABLE_MODULES building relocatable modules in the ram stage. Those modules can be loaded anywhere and all the relocations are handled automatically. +config RELOCATABLE_RAMSTAGE + depends on RELOCATABLE_MODULES + bool "Build the ramstage to be relocatable in 32-bit address space." + default n + help + The reloctable ramstage support allows for the ramstage to be built + as a relocatable module. The stage loader can identify a place + out of the OS way so that copying memory is unnecessary during an S3 + wake. When selecting this option the romstage is responsible for + determing a stack location to use for loading the ramstage. + config HAVE_ACPI_TABLES bool help diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc index 433b434..7cda5b6 100644 --- a/src/arch/x86/Makefile.inc +++ b/src/arch/x86/Makefile.inc @@ -157,6 +157,12 @@ $(objcbfs)/%.elf: $(objcbfs)/%.debug ################################################################################ # Build the coreboot_ram (stage 2) +ifeq ($(CONFIG_RELOCATABLE_RAMSTAGE),y) + +$(eval $(call rmodule_link,$(objcbfs)/coreboot_ram.debug, $(obj)/arch/x86/boot/ramstage_module_header.ramstage.o $(objgenerated)/coreboot_ram.o, $(CONFIG_HEAP_SIZE))) + +else + $(objcbfs)/coreboot_ram.debug: $(objgenerated)/coreboot_ram.o $(src)/arch/x86/coreboot_ram.ld @printf " CC $(subst $(obj)/,,$(@))\n" ifeq ($(CONFIG_COMPILER_LLVM_CLANG),y) @@ -165,6 +171,8 @@ else $(CC) -nostdlib -nostartfiles -static -o $@ -L$(obj) -T $(src)/arch/x86/coreboot_ram.ld $< endif +endif + $(objgenerated)/coreboot_ram.o: $$(ramstage-objs) $(LIBGCC_FILE_NAME) @printf " CC $(subst $(obj)/,,$(@))\n" ifeq ($(CONFIG_COMPILER_LLVM_CLANG),y) diff --git a/src/arch/x86/boot/Makefile.inc b/src/arch/x86/boot/Makefile.inc index 3f11c01..9c18043 100644 --- a/src/arch/x86/boot/Makefile.inc +++ b/src/arch/x86/boot/Makefile.inc @@ -9,6 +9,7 @@ ramstage-$(CONFIG_GENERATE_ACPI_TABLES) += acpi.c ramstage-$(CONFIG_GENERATE_SMBIOS_TABLES) += smbios.c ramstage-$(CONFIG_GENERATE_ACPI_TABLES) += acpigen.c ramstage-$(CONFIG_HAVE_ACPI_RESUME) += wakeup.S +ramstage-$(CONFIG_RELOCATABLE_RAMSTAGE) += ramstage_module_header.c $(obj)/arch/x86/boot/coreboot_table.ramstage.o : $(OPTION_TABLE_H) $(obj)/arch/x86/boot/smbios.ramstage.o: $(obj)/build.h diff --git a/src/arch/x86/boot/acpi.c b/src/arch/x86/boot/acpi.c index 327d175..b04cbe5 100644 --- a/src/arch/x86/boot/acpi.c +++ b/src/arch/x86/boot/acpi.c @@ -759,6 +759,9 @@ extern unsigned int __wakeup_size; void acpi_jump_to_wakeup(void *vector) { +#if CONFIG_RELOCATABLE_RAMSTAGE + u32 acpi_backup_memory = 0; +#else u32 acpi_backup_memory = (u32)cbmem_find(CBMEM_ID_RESUME); if (!acpi_backup_memory) { @@ -766,6 +769,7 @@ void acpi_jump_to_wakeup(void *vector) "No S3 resume.\n"); return; } +#endif #if CONFIG_SMP // FIXME: This should go into the ACPI backup memory, too. No pork saussages. diff --git a/src/arch/x86/boot/boot.c b/src/arch/x86/boot/boot.c index d9cb02e..4892c5e 100644 --- a/src/arch/x86/boot/boot.c +++ b/src/arch/x86/boot/boot.c @@ -68,6 +68,34 @@ int elf_check_arch(Elf_ehdr *ehdr) } +#if CONFIG_RELOCATABLE_RAMSTAGE +/* When the ramstage is relocatable the elf loading ensures an elf image cannot + * be loaded over the ramstage code. */ +void jmp_to_elf_entry(void *entry, unsigned long unused1, unsigned long unused2) +{ + elf_boot_notes.hdr.b_checksum = + compute_ip_checksum(&elf_boot_notes, sizeof(elf_boot_notes)); + + /* Jump to kernel */ + __asm__ __volatile__( + " cld \n\t" + /* Now jump to the loaded image */ + " call *%0\n\t" + + /* The loaded image returned? */ + " cli \n\t" + " cld \n\t" + + :: + "r" (entry), +#if CONFIG_MULTIBOOT + "b"(mbi), "a" (MB_MAGIC2) +#else + "b"(&elf_boot_notes), "a" (0x0E1FB007) +#endif + ); +} +#else void jmp_to_elf_entry(void *entry, unsigned long buffer, unsigned long size) { extern unsigned char _ram_seg, _eram_seg; @@ -182,5 +210,6 @@ void jmp_to_elf_entry(void *entry, unsigned long buffer, unsigned long size) #endif ); } +#endif /* CONFIG_RELOCATABLE_RAMSTAGE */ diff --git a/src/arch/x86/boot/ramstage_module_header.c b/src/arch/x86/boot/ramstage_module_header.c new file mode 100644 index 0000000..b958c16 --- /dev/null +++ b/src/arch/x86/boot/ramstage_module_header.c @@ -0,0 +1,24 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 ChromeOS Authors + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <rmodule.h> + +extern char _start[]; + +DEFINE_RMODULE_HEADER(ramstage_module, _start, RMODULE_TYPE_STAGE); diff --git a/src/arch/x86/boot/tables.c b/src/arch/x86/boot/tables.c index 7f28861..294a10c 100644 --- a/src/arch/x86/boot/tables.c +++ b/src/arch/x86/boot/tables.c @@ -232,11 +232,14 @@ struct lb_memory *write_tables(void) post_code(0x9e); #if CONFIG_HAVE_ACPI_RESUME +/* Only add CBMEM_ID_RESUME when the ramstage isn't relocatable. */ +#if !CONFIG_RELOCATABLE_RAMSTAGE /* Let's prepare the ACPI S3 Resume area now already, so we can rely on * it begin there during reboot time. We don't need the pointer, nor * the result right now. If it fails, ACPI resume will be disabled. */ cbmem_add(CBMEM_ID_RESUME, HIGH_MEMORY_SAVE); +#endif #if CONFIG_NORTHBRIDGE_AMD_AGESA_FAMILY14 || CONFIG_NORTHBRIDGE_AMD_AGESA_FAMILY15_TN cbmem_add(CBMEM_ID_RESUME_SCRATCH, CONFIG_HIGH_SCRATCH_MEMORY_SIZE); #endif diff --git a/src/include/cbmem.h b/src/include/cbmem.h index 0aa9b30..d0f0c9a 100644 --- a/src/include/cbmem.h +++ b/src/include/cbmem.h @@ -28,7 +28,12 @@ #endif #if CONFIG_HAVE_ACPI_RESUME +#if CONFIG_RELOCATABLE_RAMSTAGE +#define HIGH_MEMORY_SAVE 0 +#else #define HIGH_MEMORY_SAVE (CONFIG_RAMTOP - CONFIG_RAMBASE) +#endif + #define HIGH_MEMORY_SIZE (HIGH_MEMORY_SAVE + CONFIG_HIGH_SCRATCH_MEMORY_SIZE + HIGH_MEMORY_DEF_SIZE) /* Delegation of resume backup memory so we don't have to diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc index d08ee7a..97baaa2 100644 --- a/src/lib/Makefile.inc +++ b/src/lib/Makefile.inc @@ -110,6 +110,7 @@ $(obj)/lib/uart8250.smm.o : $(OPTION_TABLE_H) ifeq ($(CONFIG_RELOCATABLE_MODULES),y) ramstage-y += rmodule.c +romstage-$(CONFIG_RELOCATABLE_RAMSTAGE) += rmodule.c RMODULE_LDSCRIPT := $(src)/lib/rmodule.ld RMODULE_LDFLAGS := -nostartfiles -shared -z defs -nostdlib -Bsymbolic -T $(RMODULE_LDSCRIPT) diff --git a/src/lib/cbfs.c b/src/lib/cbfs.c index c56f550..4dac4bb 100644 --- a/src/lib/cbfs.c +++ b/src/lib/cbfs.c @@ -36,6 +36,7 @@ #include <cbfs.h> #include <string.h> +#include <cbmem.h> #ifdef LIBPAYLOAD # include <stdio.h> @@ -114,6 +115,65 @@ void *cbfs_load_optionrom(struct cbfs_media *media, uint16_t vendor, return dest; } +#if CONFIG_RELOCATABLE_RAMSTAGE && defined(__PRE_RAM__) + +#include <rmodule.h> +#include <romstage_handoff.h> +/* When CONFIG_RELOCATABLE_RAMSTAGE is enabled and this file is being compiled + * for the romstage the rmodule loader is used. The ramstage is placed just + * below the cbemem location. */ + +void * cbfs_load_stage(struct cbfs_media *media, const char *name) +{ + struct cbfs_stage *stage; + struct rmodule ramstage; + void *cbmem_base; + void *ramstage_base; + void *decompression_loc; + void *ramstage_loc; + struct romstage_handoff *handoff; + + stage = (struct cbfs_stage *) + cbfs_get_file_content(media, name, CBFS_TYPE_STAGE); + + if (stage == NULL) + return (void *) -1; + + cbmem_base = get_cbmem_toc(); + if (cbmem_base == NULL) + return (void *) -1; + + ramstage_base = rmodule_find_region_below(cbmem_base, stage->memlen, + &ramstage_loc, + &decompression_loc); + + LOG("Decompressing stage %s @ 0x%p (%d bytes)\n", + name, decompression_loc, stage->memlen); + + if (cbfs_decompress(stage->compression, &stage[1], + decompression_loc, stage->len)) + return (void *) -1; + + if (rmodule_parse(decompression_loc, &ramstage)) + return (void *) -1; + + /* The ramstage is responsible for clearing its own bss. */ + if (rmodule_load(ramstage_loc, &ramstage)) + return (void *) -1; + + handoff = cbmem_add(CBMEM_ID_ROMSTAGE_INFO, sizeof(*handoff)); + if (handoff) { + handoff->reserve_base = (uint32_t)ramstage_base; + handoff->reserve_size = (uint32_t)cbmem_base - + (uint32_t)ramstage_base; + } else + LOG("Couldn't allocate romstage handoff.\n"); + + return rmodule_entry(&ramstage); +} + +#else + void * cbfs_load_stage(struct cbfs_media *media, const char *name) { struct cbfs_stage *stage = (struct cbfs_stage *) @@ -146,6 +206,7 @@ void * cbfs_load_stage(struct cbfs_media *media, const char *name) return (void *) entry; } +#endif /* CONFIG_RELOCATABLE_RAMSTAGE */ int cbfs_execute_stage(struct cbfs_media *media, const char *name) { diff --git a/src/lib/selfboot.c b/src/lib/selfboot.c index f32bb81..f933142 100644 --- a/src/lib/selfboot.c +++ b/src/lib/selfboot.c @@ -78,6 +78,16 @@ struct segment { static unsigned long bounce_size, bounce_buffer; +#if CONFIG_RELOCATABLE_RAMSTAGE +static void get_bounce_buffer(struct lb_memory *mem, unsigned long req_size) +{ + /* When the ramstage is relocatable there is no need for a bounce + * buffer. All payloads should not overlap the ramstage. + */ + bounce_buffer = ~0UL; + bounce_size = 0; +} +#else static void get_bounce_buffer(struct lb_memory *mem, unsigned long req_size) { unsigned long lb_size; @@ -114,6 +124,7 @@ static void get_bounce_buffer(struct lb_memory *mem, unsigned long req_size) bounce_buffer = buffer; bounce_size = req_size; } +#endif /* CONFIG_RELOCATABLE_RAMSTAGE */ static int valid_area(struct lb_memory *mem, unsigned long buffer, unsigned long start, unsigned long len) @@ -394,8 +405,13 @@ static int load_self_segments( for(ptr = head->next; ptr != head; ptr = ptr->next) { if (!overlaps_coreboot(ptr)) continue; +#if CONFIG_RELOCATABLE_RAMSTAGE + /* payloads are required to not overlap ramstage. */ + return 0; +#else if (ptr->s_dstaddr + ptr->s_memsz > bounce_high) bounce_high = ptr->s_dstaddr + ptr->s_memsz; +#endif } get_bounce_buffer(mem, bounce_high - lb_start); if (!bounce_buffer) {

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Patch set updated for coreboot: d518cc4 Add support for ASUS F2A85-M board
by Rudolf Marek March 21, 2013

March 21, 2013

Rudolf Marek (r.marek(a)assembler.cz) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2038 -gerrit commit d518cc41956fc1780ff2cd390be3fcb92f7684be Author: Rudolf Marek <r.marek(a)assembler.cz> Date: Wed Mar 20 21:43:50 2013 +0100 Add support for ASUS F2A85-M board The patch is based on Thatcher board. So far it boots Linux (3.2/3.7), internal network adapter works, AHCI works. External PCI/PCIe slots works too. Power management/ACPI seems to work. Internal VGA works with dumped ROM (VGA/DVI), but lacks GART. PCI pref devices are being relocated by Linux, reason unknown. This is a good start. USB and XHCI untested but visible. Change-Id: I1869aecb2634d548b00b3c9139517d6a0e0c9817 Signed-off-by: Rudolf Marek <r.marek(a)assembler.cz> --- src/mainboard/asus/Kconfig | 3 + src/mainboard/asus/f2a85-m/BiosCallOuts.c | 126 ++ src/mainboard/asus/f2a85-m/BiosCallOuts.h | 31 + src/mainboard/asus/f2a85-m/Kconfig | 133 ++ src/mainboard/asus/f2a85-m/Makefile.inc | 28 + src/mainboard/asus/f2a85-m/OptionsIds.h | 67 + src/mainboard/asus/f2a85-m/PlatformGnbPcie.c | 206 +++ .../asus/f2a85-m/PlatformGnbPcieComplex.h | 72 + src/mainboard/asus/f2a85-m/acpi/AmdImc.asl | 97 ++ src/mainboard/asus/f2a85-m/acpi/cpstate.asl | 115 ++ src/mainboard/asus/f2a85-m/acpi/ide.asl | 244 ++++ src/mainboard/asus/f2a85-m/acpi/routing.asl | 207 +++ src/mainboard/asus/f2a85-m/acpi/sata.asl | 148 ++ src/mainboard/asus/f2a85-m/acpi/usb.asl | 114 ++ src/mainboard/asus/f2a85-m/acpi_tables.c | 329 +++++ src/mainboard/asus/f2a85-m/agesawrapper.c | 775 +++++++++++ src/mainboard/asus/f2a85-m/agesawrapper.h | 97 ++ src/mainboard/asus/f2a85-m/buildOpts.c | 517 +++++++ src/mainboard/asus/f2a85-m/cmos.layout | 114 ++ src/mainboard/asus/f2a85-m/devicetree.cb | 130 ++ src/mainboard/asus/f2a85-m/dsdt.asl | 1411 ++++++++++++++++++++ src/mainboard/asus/f2a85-m/get_bus_conf.c | 139 ++ src/mainboard/asus/f2a85-m/irq_tables.c | 112 ++ src/mainboard/asus/f2a85-m/mainboard.c | 68 + src/mainboard/asus/f2a85-m/mptable.c | 195 +++ src/mainboard/asus/f2a85-m/pmio.h | 33 + src/mainboard/asus/f2a85-m/romstage.c | 206 +++ 27 files changed, 5717 insertions(+) diff --git a/src/mainboard/asus/Kconfig b/src/mainboard/asus/Kconfig index 6e6b420..66057df 100644 --- a/src/mainboard/asus/Kconfig +++ b/src/mainboard/asus/Kconfig @@ -27,6 +27,8 @@ config BOARD_ASUS_A8V_E_SE bool "A8V-E SE" config BOARD_ASUS_A8V_E_DELUXE bool "A8V-E Deluxe" +config BOARD_ASUS_F2A85_M + bool "F2A85-M" config BOARD_ASUS_K8V_X bool "K8V-X" config BOARD_ASUS_M2N_E @@ -66,6 +68,7 @@ endchoice source "src/mainboard/asus/a8n_e/Kconfig" source "src/mainboard/asus/a8v-e_se/Kconfig" source "src/mainboard/asus/a8v-e_deluxe/Kconfig" +source "src/mainboard/asus/f2a85-m/Kconfig" source "src/mainboard/asus/k8v-x/Kconfig" source "src/mainboard/asus/m2n-e/Kconfig" source "src/mainboard/asus/m2v/Kconfig" diff --git a/src/mainboard/asus/f2a85-m/BiosCallOuts.c b/src/mainboard/asus/f2a85-m/BiosCallOuts.c new file mode 100644 index 0000000..f976001 --- /dev/null +++ b/src/mainboard/asus/f2a85-m/BiosCallOuts.c @@ -0,0 +1,126 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include "agesawrapper.h" +#include "amdlib.h" +#include "BiosCallOuts.h" +#include "Ids.h" +#include "OptionsIds.h" +#include "heapManager.h" +#include "FchPlatform.h" +#include "cbfs.h" + +STATIC CONST BIOS_CALLOUT_STRUCT BiosCallouts[] = +{ + {AGESA_ALLOCATE_BUFFER, fam15tn_AllocateBuffer }, + {AGESA_DEALLOCATE_BUFFER, fam15tn_DeallocateBuffer }, + {AGESA_DO_RESET, fam15tn_Reset }, + {AGESA_LOCATE_BUFFER, fam15tn_LocateBuffer }, + {AGESA_READ_SPD, fam15tn_ReadSpd }, + {AGESA_READ_SPD_RECOVERY, fam15tn_DefaultRet }, + {AGESA_RUNFUNC_ONAP, fam15tn_RunFuncOnAp }, + {AGESA_GET_IDS_INIT_DATA, fam15tn_GetIdsInitData }, + {AGESA_HOOKBEFORE_DQS_TRAINING, fam15tn_HookBeforeDQSTraining }, + {AGESA_HOOKBEFORE_EXIT_SELF_REF, fam15tn_HookBeforeExitSelfRefresh }, + {AGESA_FCH_OEM_CALLOUT, Fch_Oem_config }, + {AGESA_GNB_GFX_GET_VBIOS_IMAGE, fam15tn_HookGfxGetVbiosImage } +}; + +AGESA_STATUS GetBiosCallout (UINT32 Func, UINT32 Data, VOID *ConfigPtr) +{ + UINTN i; + AGESA_STATUS CalloutStatus; + UINTN CallOutCount = sizeof (BiosCallouts) / sizeof (BiosCallouts [0]); + + for (i = 0; i < CallOutCount; i++) + { + if (BiosCallouts[i].CalloutName == Func) + break; + } + + if(i >= CallOutCount) + return AGESA_UNSUPPORTED; + + CalloutStatus = BiosCallouts[i].CalloutPtr (Func, Data, ConfigPtr); + + return CalloutStatus; +} + +/** + * AMD Thatcher Platform ALC272 Verb Table + */ +const CODEC_ENTRY Thatcher_Alc272_VerbTbl[] = { + {0x11, 0x411111F0}, + {0x12, 0x411111F0}, + {0x13, 0x411111F0}, + {0x14, 0x411111F0}, + {0x15, 0x411111F0}, + {0x16, 0x411111F0}, + {0x17, 0x411111F0}, + {0x18, 0x01a19840}, + {0x19, 0x411111F0}, + {0x1a, 0x01813030}, + {0x1b, 0x411111F0}, + {0x1d, 0x40130605}, + {0x1e, 0x01441120}, + {0x21, 0x01211010}, + {0xff, 0xffffffff} +}; + +const CODEC_TBL_LIST ThatcherCodecTableList[] = +{ + {0x10ec0272, (CODEC_ENTRY*)&Thatcher_Alc272_VerbTbl[0]}, + {(UINT32)0x0FFFFFFFF, (CODEC_ENTRY*)0x0FFFFFFFFUL} +}; + +/** + * Fch Oem setting callback + * + * Configure platform specific Hudson device, + * such Azalia, SATA, GEC, IMC etc. + */ +AGESA_STATUS Fch_Oem_config(UINT32 Func, UINT32 FchData, VOID *ConfigPtr) +{ + FCH_RESET_DATA_BLOCK *FchParams = (FCH_RESET_DATA_BLOCK *)FchData; + + if (FchParams->StdHeader->Func == AMD_INIT_RESET) { +#if CONFIG_HUDSON_LEGACY_FREE + FCH_RESET_DATA_BLOCK *FchParams_reset = (FCH_RESET_DATA_BLOCK *) FchData; + FchParams_reset->LegacyFree = 1; +#endif + printk(BIOS_DEBUG, "Fch OEM config in INIT RESET "); + } else if (FchParams->StdHeader->Func == AMD_INIT_ENV) { + FCH_DATA_BLOCK *FchParams_env = (FCH_DATA_BLOCK *)FchData; + printk(BIOS_DEBUG, "Fch OEM config in INIT ENV "); + + /* Azalia Controller OEM Codec Table Pointer */ + FchParams_env->Azalia.AzaliaOemCodecTablePtr = (CODEC_TBL_LIST *)(&ThatcherCodecTableList[0]); + /* Azalia Controller Front Panel OEM Table Pointer */ + FchParams_env->Imc.ImcEnable = FALSE; + FchParams_env->Hwm.HwMonitorEnable = FALSE; + FchParams_env->Hwm.HwmFchtsiAutoPoll = FALSE;/* 1 enable, 0 disable TSI Auto Polling */ + + /* XHCI configuration */ + FchParams_env->Usb.Xhci0Enable = TRUE; + FchParams_env->Usb.Xhci1Enable = TRUE; + } + printk(BIOS_DEBUG, "Done\n"); + + return AGESA_SUCCESS; +} diff --git a/src/mainboard/asus/f2a85-m/BiosCallOuts.h b/src/mainboard/asus/f2a85-m/BiosCallOuts.h new file mode 100644 index 0000000..9132fac --- /dev/null +++ b/src/mainboard/asus/f2a85-m/BiosCallOuts.h @@ -0,0 +1,31 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef _BIOS_CALLOUT_H_ +#define _BIOS_CALLOUT_H_ + +#include <northbridge/amd/agesa/family15tn/fam15tn_callouts.h> + +/* CALLOUT Initialization */ +AGESA_STATUS GetBiosCallout (UINT32 Func, UINT32 Data, VOID *ConfigPtr); + +/* FCH OEM Config*/ +AGESA_STATUS Fch_Oem_config(UINT32 Func, UINT32 FchData, VOID *ConfigPtr); + +#endif //_BIOS_CALLOUT_H_ diff --git a/src/mainboard/asus/f2a85-m/Kconfig b/src/mainboard/asus/f2a85-m/Kconfig new file mode 100644 index 0000000..e8f573e --- /dev/null +++ b/src/mainboard/asus/f2a85-m/Kconfig @@ -0,0 +1,133 @@ +# +# This file is part of the coreboot project. +# +# Copyright (C) 2012 Advanced Micro Devices, Inc. +# Copyright (C) 2012 Rudolf Marek <r.marek(a)assembler.cz> +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +# + +if BOARD_ASUS_F2A85_M + +config BOARD_SPECIFIC_OPTIONS # dummy + def_bool y + select ARCH_X86 + select CPU_AMD_AGESA_FAMILY15_TN + select NORTHBRIDGE_AMD_AGESA_FAMILY15_TN_ROOT_COMPLEX + select NORTHBRIDGE_AMD_AGESA_FAMILY15_TN + select SOUTHBRIDGE_AMD_AGESA_HUDSON + select HAVE_OPTION_TABLE + select HAVE_PIRQ_TABLE + select HAVE_MP_TABLE + select HAVE_ACPI_RESUME + select HAVE_HARD_RESET + select SB_HT_CHAIN_UNITID_OFFSET_ONLY + select LIFT_BSP_APIC_ID + select SERIAL_CPU_INIT + select AMDMCT + select HAVE_ACPI_TABLES + select SUPERIO_ITE_IT8712F + select BOARD_ROMSIZE_KB_8192 + select GFXUMA + select UDELAY_LAPIC + +choice + prompt "DDR3 memory voltage" + default BOARD_ASUS_F2A85_M_DDR3_VOLT_150 + +config BOARD_ASUS_F2A85_M_DDR3_VOLT_135 + bool "1.35V" + help + Set DRR3 memory voltage to 1.35V +config BOARD_ASUS_F2A85_M_DDR3_VOLT_150 + bool "1.50V" + help + Set DRR3 memory voltage to 1.50V +config BOARD_ASUS_F2A85_M_DDR3_VOLT_165 + bool "1.65V" + help + Set DRR3 memory voltage to 1.65V +endchoice + +config BOARD_ASUS_F2A85_M_DDR3_VOLT_VAL + hex + default 0x9e if BOARD_ASUS_F2A85_M_DDR3_VOLT_135 + default 0x0 if BOARD_ASUS_F2A85_M_DDR3_VOLT_150 + default 0x1e if BOARD_ASUS_F2A85_M_DDR3_VOLT_165 + +config MAINBOARD_DIR + string + default asus/f2a85-m + +config APIC_ID_OFFSET + hex + default 0x0 + +config MAINBOARD_PART_NUMBER + string + default "F2A85-M" + +config HW_MEM_HOLE_SIZEK + hex + default 0x200000 + +config MAX_CPUS + int + default 4 + +config MAX_PHYSICAL_CPUS + int + default 1 + +config HW_MEM_HOLE_SIZE_AUTO_INC + bool + default n + +config MEM_TRAIN_SEQ + int + default 2 + +config IRQ_SLOT_COUNT + int + default 11 + +config RAMTOP + hex + default 0x1000000 + +config HEAP_SIZE + hex + default 0xc0000 + +config STACK_SIZE + hex + default 0x10000 + +config RAMBASE + hex + default 0x200000 + +config ONBOARD_VGA_IS_PRIMARY + bool + default y + +config VGA_BIOS_ID + string + default "1002,9993" + +config HUDSON_LEGACY_FREE + bool + default y + +endif # BOARD_ASUS_F2A85_M diff --git a/src/mainboard/asus/f2a85-m/Makefile.inc b/src/mainboard/asus/f2a85-m/Makefile.inc new file mode 100644 index 0000000..3103f70 --- /dev/null +++ b/src/mainboard/asus/f2a85-m/Makefile.inc @@ -0,0 +1,28 @@ +# +# This file is part of the coreboot project. +# +# Copyright (C) 2012 Advanced Micro Devices, Inc. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +# + +romstage-y += buildOpts.c +romstage-y += agesawrapper.c +romstage-y += BiosCallOuts.c +romstage-y += PlatformGnbPcie.c + +ramstage-y += buildOpts.c +ramstage-y += agesawrapper.c +ramstage-y += BiosCallOuts.c +ramstage-y += PlatformGnbPcie.c diff --git a/src/mainboard/asus/f2a85-m/OptionsIds.h b/src/mainboard/asus/f2a85-m/OptionsIds.h new file mode 100644 index 0000000..bf7eedc --- /dev/null +++ b/src/mainboard/asus/f2a85-m/OptionsIds.h @@ -0,0 +1,67 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/** + * @file + * + * IDS Option File + * + * This file is used to switch on/off IDS features. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: Core + * @e \$Revision: 12067 $ @e \$Date: 2009-04-11 04:34:13 +0800 (Sat, 11 Apr 2009) $ + */ +#ifndef _OPTION_IDS_H_ +#define _OPTION_IDS_H_ + +/** + * + * This file generates the defaults tables for the Integrated Debug Support + * Module. The documented build options are imported from a user controlled + * file for processing. The build options for the Integrated Debug Support + * Module are listed below: + * + * IDSOPT_IDS_ENABLED + * IDSOPT_ERROR_TRAP_ENABLED + * IDSOPT_CONTROL_ENABLED + * IDSOPT_TRACING_ENABLED + * IDSOPT_PERF_ANALYSIS + * IDSOPT_ASSERT_ENABLED + * IDS_DEBUG_PORT + * IDSOPT_CAR_CORRUPTION_CHECK_ENABLED + * + **/ + +//#define IDSOPT_IDS_ENABLED TRUE +//#define IDSOPT_CONTROL_ENABLED TRUE +#define IDSOPT_TRACING_ENABLED TRUE +#define IDSOPT_TRACING_CONSOLE_SERIALPORT TRUE +//#define IDSOPT_PERF_ANALYSIS TRUE +#define IDSOPT_ASSERT_ENABLED TRUE +//#undef IDSOPT_DEBUG_ENABLED +//#define IDSOPT_DEBUG_ENABLED FALSE +//#undef IDSOPT_HOST_SIMNOW +//#define IDSOPT_HOST_SIMNOW FALSE +//#undef IDSOPT_HOST_HDT +//#define IDSOPT_HOST_HDT FALSE +//#define IDS_DEBUG_PORT 0x80 + +#endif diff --git a/src/mainboard/asus/f2a85-m/PlatformGnbPcie.c b/src/mainboard/asus/f2a85-m/PlatformGnbPcie.c new file mode 100644 index 0000000..8ee6707 --- /dev/null +++ b/src/mainboard/asus/f2a85-m/PlatformGnbPcie.c @@ -0,0 +1,206 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include "AGESA.h" +#include "amdlib.h" +#include "Ids.h" +#include "heapManager.h" +#include "PlatformGnbPcieComplex.h" +#include "Filecode.h" + +#define FILECODE PROC_GNB_PCIE_FAMILY_0X15_F15PCIECOMPLEXCONFIG_FILECODE + +PCIe_PORT_DESCRIPTOR PortList [] = { + /* PCIe port, Lanes 8:23, PCI Device Number 2 */ + { + 0, /* Descriptor flags */ + PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 8, 23), + PCIE_PORT_DATA_INITIALIZER (PortEnabled, ChannelTypeExt6db, 2, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 1) + }, + /* PCIe port, Lanes 16:23, PCI Device Number 3 */ + { + 0, /* Descriptor flags */ + PCIE_ENGINE_DATA_INITIALIZER (PcieUnusedEngine, 16, 23), + PCIE_PORT_DATA_INITIALIZER (PortDisabled, ChannelTypeExt6db, 3, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 1) + }, + + /* PCIe port, Lanes 4, PCI Device Number 4, PCIE MINI0 */ + { + 0, /* Descriptor flags */ + PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 4, 4), + PCIE_PORT_DATA_INITIALIZER (PortEnabled, ChannelTypeExt6db, 4, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 1) + }, + + /* PCIe port, Lanes 5, PCI Device Number 5, PCIE MINI1 */ + { + 0, /* Descriptor flags */ + PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 5, 5), + PCIE_PORT_DATA_INITIALIZER (PortEnabled, ChannelTypeExt6db, 5, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 1) + }, + + /* PCIe port, Lanes 6, PCI Device Number 6, PCIE SLOT1, TODO: Disabled. */ + { + 0, /* Descriptor flags */ + PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 6, 6), + PCIE_PORT_DATA_INITIALIZER (PortEnabled, ChannelTypeExt6db, 6, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 1) + }, + + /* PCIe port, Lanes 7, PCI Device Number 7, LAN , TODO: not the last entry.*/ + { + 0, /* Descriptor flags !!!IMPORTANT!!! Terminate last element of array */ + PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 7, 7), + PCIE_PORT_DATA_INITIALIZER (PortEnabled, ChannelTypeExt6db, 7, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 1) + }, + +#if 1 + /* Initialize Port descriptor (PCIe port, Lanes ?, PCI Device Number 8, ...) */ + { + DESCRIPTOR_TERMINATE_LIST, /* Descriptor flags !!!IMPORTANT!!! Terminate last element of array */ + PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 0, 3), + PCIE_PORT_DATA_INITIALIZER (PortEnabled, ChannelTypeExt6db, 8, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 0) + }, +#endif +}; + +PCIe_DDI_DESCRIPTOR DdiList [] = { + // DP0 to HDMI0/DP + { + 0, + PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 24, 27), + PCIE_DDI_DATA_INITIALIZER (ConnectorTypeHDMI, Aux1, Hdp1) + }, + // DP1 to FCH + { + 0, + PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 28, 31), + PCIE_DDI_DATA_INITIALIZER (ConnectorTypeNutmegDpToVga, Aux2, Hdp2) + }, + // DP2 to HDMI1/DP + { + 0, +// PCIE_ENGINE_DATA_INITIALIZER (PcieUnusedEngine, 32, 38), + PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 32, 35), + //PCIE_DDI_DATA_INITIALIZER (ConnectorTypeEDP, Aux3, Hdp3) + PCIE_DDI_DATA_INITIALIZER (ConnectorTypeHDMI, Aux3, Hdp3) + }, + // GFX Lane 15-12 + { + 0, + PCIE_ENGINE_DATA_INITIALIZER (PcieUnusedEngine, 12, 15), + PCIE_DDI_DATA_INITIALIZER (ConnectorTypeHDMI, Aux4, Hdp4) + }, + // GFX Lane 11-8 + { + 0, + PCIE_ENGINE_DATA_INITIALIZER (PcieUnusedEngine, 16, 19), + PCIE_DDI_DATA_INITIALIZER (ConnectorTypeHDMI, Aux5, Hdp5) + }, + // GFX Lane 7-4 + { + DESCRIPTOR_TERMINATE_LIST, + PCIE_ENGINE_DATA_INITIALIZER (PcieUnusedEngine, 20, 23), + PCIE_DDI_DATA_INITIALIZER (ConnectorTypeHDMI, Aux6, Hdp6) + } +}; + +PCIe_COMPLEX_DESCRIPTOR Trinity = { + DESCRIPTOR_TERMINATE_LIST, + 0, + &PortList[0], + &DdiList[0] +}; + +/*---------------------------------------------------------------------------------------*/ +/** + * OemCustomizeInitEarly + * + * Description: + * This stub function will call the host environment through the binary block + * interface (call-out port) to provide a user hook opportunity + * + * Parameters: + * @param[in] **PeiServices + * @param[in] *InitEarly + * + * @retval VOID + * + **/ +/*---------------------------------------------------------------------------------------*/ +VOID +OemCustomizeInitEarly ( + IN OUT AMD_EARLY_PARAMS *InitEarly + ) +{ + AGESA_STATUS Status; + VOID *TrinityPcieComplexListPtr; + VOID *TrinityPciePortPtr; + VOID *TrinityPcieDdiPtr; + + ALLOCATE_HEAP_PARAMS AllocHeapParams; + + // GNB PCIe topology Porting + + // + // Allocate buffer for PCIe_COMPLEX_DESCRIPTOR , PCIe_PORT_DESCRIPTOR and PCIe_DDI_DESCRIPTOR + // + AllocHeapParams.RequestedBufferSize = (sizeof (PCIe_COMPLEX_DESCRIPTOR) + + sizeof (PCIe_PORT_DESCRIPTOR) * 7 + + sizeof (PCIe_DDI_DESCRIPTOR)) * 6; + + AllocHeapParams.BufferHandle = AMD_MEM_MISC_HANDLES_START; + AllocHeapParams.Persist = HEAP_LOCAL_CACHE; + Status = HeapAllocateBuffer (&AllocHeapParams, &InitEarly->StdHeader); + if ( Status!= AGESA_SUCCESS) { + // Could not allocate buffer for PCIe_COMPLEX_DESCRIPTOR , PCIe_PORT_DESCRIPTOR and PCIe_DDI_DESCRIPTOR + ASSERT(FALSE); + return; + } + + TrinityPcieComplexListPtr = (PCIe_COMPLEX_DESCRIPTOR *) AllocHeapParams.BufferPtr; + + AllocHeapParams.BufferPtr += sizeof (PCIe_COMPLEX_DESCRIPTOR); + TrinityPciePortPtr = (PCIe_PORT_DESCRIPTOR *)AllocHeapParams.BufferPtr; + + AllocHeapParams.BufferPtr += sizeof (PCIe_PORT_DESCRIPTOR) * 7; + TrinityPcieDdiPtr = (PCIe_DDI_DESCRIPTOR *) AllocHeapParams.BufferPtr; + + LibAmdMemFill (TrinityPcieComplexListPtr, + 0, + sizeof (PCIe_COMPLEX_DESCRIPTOR), + &InitEarly->StdHeader); + + LibAmdMemFill (TrinityPciePortPtr, + 0, + sizeof (PCIe_PORT_DESCRIPTOR) * 7, + &InitEarly->StdHeader); + + LibAmdMemFill (TrinityPcieDdiPtr, + 0, + sizeof (PCIe_DDI_DESCRIPTOR) * 6, + &InitEarly->StdHeader); + + LibAmdMemCopy (TrinityPcieComplexListPtr, &Trinity, sizeof (PCIe_COMPLEX_DESCRIPTOR), &InitEarly->StdHeader); + LibAmdMemCopy (TrinityPciePortPtr, &PortList[0], sizeof (PCIe_PORT_DESCRIPTOR) * 7, &InitEarly->StdHeader); + LibAmdMemCopy (TrinityPcieDdiPtr, &DdiList[0], sizeof (PCIe_DDI_DESCRIPTOR) * 6, &InitEarly->StdHeader); + + ((PCIe_COMPLEX_DESCRIPTOR*)TrinityPcieComplexListPtr)->PciePortList = (PCIe_PORT_DESCRIPTOR*)TrinityPciePortPtr; + ((PCIe_COMPLEX_DESCRIPTOR*)TrinityPcieComplexListPtr)->DdiLinkList = (PCIe_DDI_DESCRIPTOR*)TrinityPcieDdiPtr; + + InitEarly->GnbConfig.PcieComplexList = TrinityPcieComplexListPtr; +} diff --git a/src/mainboard/asus/f2a85-m/PlatformGnbPcieComplex.h b/src/mainboard/asus/f2a85-m/PlatformGnbPcieComplex.h new file mode 100644 index 0000000..3f14805 --- /dev/null +++ b/src/mainboard/asus/f2a85-m/PlatformGnbPcieComplex.h @@ -0,0 +1,72 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef _PLATFORM_GNB_PCIE_COMPLEX_H +#define _PLATFORM_GNB_PCIE_COMPLEX_H + +#include "Porting.h" +#include "AGESA.h" +#include "amdlib.h" + +//GNB GPP Port4 +#define GNB_GPP_PORT4_PORT_PRESENT 1 //0:Disable 1:Enable +#define GNB_GPP_PORT4_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2 +#define GNB_GPP_PORT4_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1 +#define GNB_GPP_PORT4_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) + //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) +#define GNB_GPP_PORT4_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced + +//GNB GPP Port5 +#define GNB_GPP_PORT5_PORT_PRESENT 1 //0:Disable 1:Enable +#define GNB_GPP_PORT5_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2 +#define GNB_GPP_PORT5_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1 +#define GNB_GPP_PORT5_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) + //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) +#define GNB_GPP_PORT5_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced + +//GNB GPP Port6 +#define GNB_GPP_PORT6_PORT_PRESENT 1 //0:Disable 1:Enable +#define GNB_GPP_PORT6_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2 +#define GNB_GPP_PORT6_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1 +#define GNB_GPP_PORT6_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) + //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) +#define GNB_GPP_PORT6_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced + +//GNB GPP Port7 +#define GNB_GPP_PORT7_PORT_PRESENT 1 //0:Disable 1:Enable +#define GNB_GPP_PORT7_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2 +#define GNB_GPP_PORT7_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1 +#define GNB_GPP_PORT7_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) + //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) +#define GNB_GPP_PORT7_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced + +//GNB GPP Port8 +#define GNB_GPP_PORT8_PORT_PRESENT 1 //0:Disable 1:Enable +#define GNB_GPP_PORT8_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2 +#define GNB_GPP_PORT8_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1 +#define GNB_GPP_PORT8_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) + //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) +#define GNB_GPP_PORT8_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced + +VOID +OemCustomizeInitEarly ( + IN OUT AMD_EARLY_PARAMS *InitEarly + ); + +#endif //_PLATFORM_GNB_PCIE_COMPLEX_H diff --git a/src/mainboard/asus/f2a85-m/acpi/AmdImc.asl b/src/mainboard/asus/f2a85-m/acpi/AmdImc.asl new file mode 100644 index 0000000..f55a12a --- /dev/null +++ b/src/mainboard/asus/f2a85-m/acpi/AmdImc.asl @@ -0,0 +1,97 @@ +//BTDC Due to IMC Fan, ACPI control codes +OperationRegion(IMIO, SystemIO, 0x3E, 0x02) +Field(IMIO , ByteAcc, NoLock, Preserve) { + IMCX,8, + IMCA,8 +} + +IndexField(IMCX, IMCA, ByteAcc, NoLock, Preserve) { + Offset(0x80), + MSTI, 8, + MITS, 8, + MRG0, 8, + MRG1, 8, + MRG2, 8, + MRG3, 8, +} + +Method(WACK, 0) +{ + Store(0, Local0) + Store(50, Local1) + While (LAnd (LNotEqual(Local0, 0xFA), LGreater(Local1,0))) { + Store(MRG0, Local0) + Sleep(10) + Decrement(Local1) + } +} + +//Init +Method (ITZE, 0) +{ + Store(0, MRG0) + Store(0xB5, MRG1) + Store(0, MRG2) + Store(0x96, MSTI) + WACK() + + Store(0, MRG0) + Store(0, MRG1) + Store(0, MRG2) + Store(0x80, MSTI) + WACK() + + Or(MRG2, 0x01, Local0) + + Store(0, MRG0) + Store(0, MRG1) + Store(Local0, MRG2) + Store(0x81, MSTI) + WACK() +} + +//Sleep +Method (IMSP, 0) +{ + Store(0, MRG0) + Store(0xB5, MRG1) + Store(0, MRG2) + Store(0x96, MSTI) + WACK() + + Store(0, MRG0) + Store(1, MRG1) + Store(0, MRG2) + Store(0x98, MSTI) + WACK() + + Store(0, MRG0) + Store(0xB4, MRG1) + Store(0, MRG2) + Store(0x96, MSTI) + WACK() +} + +//Wake +Method (IMWK, 0) +{ + Store(0, MRG0) + Store(0xB5, MRG1) + Store(0, MRG2) + Store(0x96, MSTI) + WACK() + + Store(0, MRG0) + Store(0, MRG1) + Store(0, MRG2) + Store(0x80, MSTI) + WACK() + + Or(MRG2, 0x01, Local0) + + Store(0, MRG0) + Store(0, MRG1) + Store(Local0, MRG2) + Store(0x81, MSTI) + WACK() +} diff --git a/src/mainboard/asus/f2a85-m/acpi/cpstate.asl b/src/mainboard/asus/f2a85-m/acpi/cpstate.asl new file mode 100644 index 0000000..2240fd6 --- /dev/null +++ b/src/mainboard/asus/f2a85-m/acpi/cpstate.asl @@ -0,0 +1,115 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* This file defines the processor and performance state capability + * for each core in the system. It is included into the DSDT for each + * core. It assumes that each core of the system has the same performance + * characteristics. +*/ +/* +DefinitionBlock ("DSDT.AML","DSDT",0x01,"XXXXXX","XXXXXXXX",0x00010001) + { + Scope (\_PR) { + Processor(CPU0,0,0x808,0x06) { + #include "cpstate.asl" + } + Processor(CPU1,1,0x0,0x0) { + #include "cpstate.asl" + } + Processor(CPU2,2,0x0,0x0) { + #include "cpstate.asl" + } + Processor(CPU3,3,0x0,0x0) { + #include "cpstate.asl" + } + } +*/ + /* P-state support: The maximum number of P-states supported by the */ + /* CPUs we'll use is 6. */ + /* Get from AMI BIOS. */ + Name(_PSS, Package(){ + Package() + { + 0x00000D48, + 0x00011170, + 0x00000004, + 0x00000004, + 0x00000000, + 0x00000000 + }, + + Package() + { + 0x00000AF0, + 0x0000C544, + 0x00000004, + 0x00000004, + 0x00000001, + 0x00000001 + }, + + Package() + { + 0x000009C4, + 0x0000B3B0, + 0x00000004, + 0x00000004, + 0x00000002, + 0x00000002 + }, + + Package() + { + 0x00000898, + 0x0000ABE0, + 0x00000004, + 0x00000004, + 0x00000003, + 0x00000003 + }, + + Package() + { + 0x00000708, + 0x0000A410, + 0x00000004, + 0x00000004, + 0x00000004, + 0x00000004 + }, + + Package() + { + 0x00000578, + 0x00006F54, + 0x00000004, + 0x00000004, + 0x00000005, + 0x00000005 + } + }) + + Name(_PCT, Package(){ + ResourceTemplate(){Register(FFixedHW, 0, 0, 0)}, + ResourceTemplate(){Register(FFixedHW, 0, 0, 0)} + }) + + Method(_PPC, 0){ + Return(0) + } diff --git a/src/mainboard/asus/f2a85-m/acpi/ide.asl b/src/mainboard/asus/f2a85-m/acpi/ide.asl new file mode 100644 index 0000000..1ff2e79 --- /dev/null +++ b/src/mainboard/asus/f2a85-m/acpi/ide.asl @@ -0,0 +1,244 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* +Scope (_SB) { + Device(PCI0) { + Device(IDEC) { + Name(_ADR, 0x00140001) + #include "ide.asl" + } + } +} +*/ + +/* Some timing tables */ +Name(UDTT, Package(){ /* Udma timing table */ + 120, 90, 60, 45, 30, 20, 15, 0 /* UDMA modes 0 -> 6 */ +}) + +Name(MDTT, Package(){ /* MWDma timing table */ + 480, 150, 120, 0 /* Legacy DMA modes 0 -> 2 */ +}) + +Name(POTT, Package(){ /* Pio timing table */ + 600, 390, 270, 180, 120, 0 /* PIO modes 0 -> 4 */ +}) + +/* Some timing register value tables */ +Name(MDRT, Package(){ /* MWDma timing register table */ + 0x77, 0x21, 0x20, 0xFF /* Legacy DMA modes 0 -> 2 */ +}) + +Name(PORT, Package(){ + 0x99, 0x47, 0x34, 0x22, 0x20, 0x99 /* PIO modes 0 -> 4 */ +}) + +OperationRegion(ICRG, PCI_Config, 0x40, 0x20) /* ide control registers */ + Field(ICRG, AnyAcc, NoLock, Preserve) +{ + PPTS, 8, /* Primary PIO Slave Timing */ + PPTM, 8, /* Primary PIO Master Timing */ + OFFSET(0x04), PMTS, 8, /* Primary MWDMA Slave Timing */ + PMTM, 8, /* Primary MWDMA Master Timing */ + OFFSET(0x08), PPCR, 8, /* Primary PIO Control */ + OFFSET(0x0A), PPMM, 4, /* Primary PIO master Mode */ + PPSM, 4, /* Primary PIO slave Mode */ + OFFSET(0x14), PDCR, 2, /* Primary UDMA Control */ + OFFSET(0x16), PDMM, 4, /* Primary UltraDMA Mode */ + PDSM, 4, /* Primary UltraDMA Mode */ +} + +Method(GTTM, 1) /* get total time*/ +{ + Store(And(Arg0, 0x0F), Local0) /* Recovery Width */ + Increment(Local0) + Store(ShiftRight(Arg0, 4), Local1) /* Command Width */ + Increment(Local1) + Return(Multiply(30, Add(Local0, Local1))) +} + +Device(PRID) +{ + Name (_ADR, Zero) + Method(_GTM, 0) + { + NAME(OTBF, Buffer(20) { /* out buffer */ + 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00 + }) + + CreateDwordField(OTBF, 0, PSD0) /* PIO spd0 */ + CreateDwordField(OTBF, 4, DSD0) /* DMA spd0 */ + CreateDwordField(OTBF, 8, PSD1) /* PIO spd1 */ + CreateDwordField(OTBF, 12, DSD1) /* DMA spd1 */ + CreateDwordField(OTBF, 16, BFFG) /* buffer flags */ + + /* Just return if the channel is disabled */ + If(And(PPCR, 0x01)) { /* primary PIO control */ + Return(OTBF) + } + + /* Always tell them independent timing available and IOChannelReady used on both drives */ + Or(BFFG, 0x1A, BFFG) + + Store(GTTM(PPTM), PSD0) /* save total time of primary PIO master timming to PIO spd0 */ + Store(GTTM(PPTS), PSD1) /* save total time of primary PIO slave Timing to PIO spd1 */ + + If(And(PDCR, 0x01)) { /* It's under UDMA mode */ + Or(BFFG, 0x01, BFFG) + Store(DerefOf(Index(UDTT, PDMM)), DSD0) + } + Else { + Store(GTTM(PMTM), DSD0) /* Primary MWDMA Master Timing, DmaSpd0 */ + } + + If(And(PDCR, 0x02)) { /* It's under UDMA mode */ + Or(BFFG, 0x04, BFFG) + Store(DerefOf(Index(UDTT, PDSM)), DSD1) + } + Else { + Store(GTTM(PMTS), DSD1) /* Primary MWDMA Slave Timing, DmaSpd0 */ + } + + Return(OTBF) /* out buffer */ + } /* End Method(_GTM) */ + + Method(_STM, 3, NotSerialized) + { + NAME(INBF, Buffer(20) { /* in buffer */ + 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00 + }) + + CreateDwordField(INBF, 0, PSD0) /* PIO spd0 */ + CreateDwordField(INBF, 4, DSD0) /* PIO spd0 */ + CreateDwordField(INBF, 8, PSD1) /* PIO spd1 */ + CreateDwordField(INBF, 12, DSD1) /* DMA spd1 */ + CreateDwordField(INBF, 16, BFFG) /*buffer flag */ + + Store(Match(POTT, MLE, PSD0, MTR, 0, 0), Local0) + Divide(Local0, 5, PPMM,) /* Primary PIO master Mode */ + Store(Match(POTT, MLE, PSD1, MTR, 0, 0), Local1) + Divide(Local1, 5, PPSM,) /* Primary PIO slave Mode */ + + Store(DerefOf(Index(PORT, Local0)), PPTM) /* Primary PIO Master Timing */ + Store(DerefOf(Index(PORT, Local1)), PPTS) /* Primary PIO Slave Timing */ + + If(And(BFFG, 0x01)) { /* Drive 0 is under UDMA mode */ + Store(Match(UDTT, MLE, DSD0, MTR, 0, 0), Local0) + Divide(Local0, 7, PDMM,) + Or(PDCR, 0x01, PDCR) + } + Else { + If(LNotEqual(DSD0, 0xFFFFFFFF)) { + Store(Match(MDTT, MLE, DSD0, MTR, 0, 0), Local0) + Store(DerefOf(Index(MDRT, Local0)), PMTM) + } + } + + If(And(BFFG, 0x04)) { /* Drive 1 is under UDMA mode */ + Store(Match(UDTT, MLE, DSD1, MTR, 0, 0), Local0) + Divide(Local0, 7, PDSM,) + Or(PDCR, 0x02, PDCR) + } + Else { + If(LNotEqual(DSD1, 0xFFFFFFFF)) { + Store(Match(MDTT, MLE, DSD1, MTR, 0, 0), Local0) + Store(DerefOf(Index(MDRT, Local0)), PMTS) + } + } + /* Return(INBF) */ + } /*End Method(_STM) */ + Device(MST) + { + Name(_ADR, 0) + Method(_GTF) { + Name(CMBF, Buffer(21) { + 0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF, + 0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF5 + }) + CreateByteField(CMBF, 1, POMD) + CreateByteField(CMBF, 8, DMMD) + CreateByteField(CMBF, 5, CMDA) + CreateByteField(CMBF, 12, CMDB) + CreateByteField(CMBF, 19, CMDC) + + Store(0xA0, CMDA) + Store(0xA0, CMDB) + Store(0xA0, CMDC) + + Or(PPMM, 0x08, POMD) + + If(And(PDCR, 0x01)) { + Or(PDMM, 0x40, DMMD) + } + Else { + Store(Match + (MDTT, MLE, GTTM(PMTM), + MTR, 0, 0), Local0) + If(LLess(Local0, 3)) { + Or(0x20, Local0, DMMD) + } + } + Return(CMBF) + } + } /* End Device(MST) */ + + Device(SLAV) + { + Name(_ADR, 1) + Method(_GTF) { + Name(CMBF, Buffer(21) { + 0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF, + 0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF5 + }) + CreateByteField(CMBF, 1, POMD) + CreateByteField(CMBF, 8, DMMD) + CreateByteField(CMBF, 5, CMDA) + CreateByteField(CMBF, 12, CMDB) + CreateByteField(CMBF, 19, CMDC) + + Store(0xB0, CMDA) + Store(0xB0, CMDB) + Store(0xB0, CMDC) + + Or(PPSM, 0x08, POMD) + + If(And(PDCR, 0x02)) { + Or(PDSM, 0x40, DMMD) + } + Else { + Store(Match + (MDTT, MLE, GTTM(PMTS), + MTR, 0, 0), Local0) + If(LLess(Local0, 3)) { + Or(0x20, Local0, DMMD) + } + } + Return(CMBF) + } + } /* End Device(SLAV) */ +} diff --git a/src/mainboard/asus/f2a85-m/acpi/routing.asl b/src/mainboard/asus/f2a85-m/acpi/routing.asl new file mode 100644 index 0000000..03027c3 --- /dev/null +++ b/src/mainboard/asus/f2a85-m/acpi/routing.asl @@ -0,0 +1,207 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* +DefinitionBlock ("DSDT.AML","DSDT",0x01,"XXXXXX","XXXXXXXX",0x00010001 + ) + { + #include "routing.asl" + } +*/ + +/* Routing is in System Bus scope */ +Scope(\_SB) { + Name(PR0, Package(){ + /* NB devices */ + /* Bus 0, Dev 0 - F15 Host Controller */ + /* Bus 0, Dev 1 - PCI Bridge for Internal Graphics(IGP) */ + Package(){0x0001FFFF, 0, INTB, 0 }, + Package(){0x0001FFFF, 1, INTC, 0 }, + + /* Bus 0, Dev 2 - PCIe Bridge for x16 slot */ + Package(){0x0002FFFF, 0, INTC, 0 }, + Package(){0x0002FFFF, 1, INTD, 0 }, + Package(){0x0002FFFF, 2, INTA, 0 }, + Package(){0x0002FFFF, 3, INTB, 0 }, + + /* Bus 0, Dev 4 - PCIe Bridge for 4x slot */ + Package(){0x0004FFFF, 0, INTA, 0 }, + Package(){0x0004FFFF, 1, INTB, 0 }, + Package(){0x0004FFFF, 2, INTC, 0 }, + Package(){0x0004FFFF, 3, INTD, 0 }, + + + /* Bus 0, Funct 8 - Southbridge port (normally hidden) */ + + /* SB devices */ + /* Bus 0, Dev 20 - F0:SMBus/ACPI,F1:IDE;F2:HDAudio;F3:LPC;F4:PCIBridge;F5:USB */ + Package(){0x0014FFFF, 0, INTA, 0 }, + Package(){0x0014FFFF, 1, INTB, 0 }, + Package(){0x0014FFFF, 2, INTC, 0 }, + Package(){0x0014FFFF, 3, INTD, 0 }, + + /* Bus 0, Dev 19 - USB: OHCI, dev 18,19 func 0-2, dev 20 func 5; + * EHCI, dev 18, 19 func 2 */ + Package(){0x0012FFFF, 0, INTC, 0 }, + Package(){0x0012FFFF, 1, INTB, 0 }, + + Package(){0x0013FFFF, 0, INTC, 0 }, + Package(){0x0013FFFF, 1, INTB, 0 }, + + Package(){0x0016FFFF, 0, INTC, 0 }, + Package(){0x0016FFFF, 1, INTB, 0 }, + + /* Bus 0, Dev 10 - USB: XHCI func 0, 1 */ + Package(){0x0010FFFF, 0, INTC, 0 }, + Package(){0x0010FFFF, 1, INTB, 0 }, + + /* Bus 0, Dev 17 - SATA controller */ + Package(){0x0011FFFF, 0, INTD, 0 }, + + /* Bus 0, Dev 21 Pcie Bridge */ + Package(){0x0015FFFF, 0, INTA, 0 }, + Package(){0x0015FFFF, 1, INTB, 0 }, + Package(){0x0015FFFF, 2, INTC, 0 }, + Package(){0x0015FFFF, 3, INTD, 0 }, + }) + + Name(APR0, Package(){ + /* NB devices in APIC mode */ + /* Bus 0, Dev 0 - F15 Host Controller */ + + /* Bus 0, Dev 1 - PCI Bridge for Internal Graphics(IGP) */ + Package(){0x0001FFFF, 0, 0, 17 }, + package(){0x0001FFFF, 1, 0, 18 }, + + /* Bus 0, Dev 2 - PCIe Bridge for x16 PCIe Slot */ + Package(){0x0002FFFF, 0, 0, 18 }, + Package(){0x0002FFFF, 1, 0, 19 }, + Package(){0x0002FFFF, 2, 0, 16 }, + Package(){0x0002FFFF, 3, 0, 17 }, + + /* Bus 0, Dev 4 - PCIe Bridge for x4 PCIe Slot black */ + Package(){0x0004FFFF, 0, 0, 16 }, + Package(){0x0004FFFF, 1, 0, 17 }, + Package(){0x0004FFFF, 2, 0, 18 }, + Package(){0x0004FFFF, 3, 0, 19 }, + + /* Bus 0, Funct 8 - Southbridge port (normally hidden) */ + + /* SB devices in APIC mode */ + /* Bus 0, Dev 20 - F0:SMBus/ACPI, F1:IDE; F2:HDAudio; F3:LPC; F4:PCIBridge; F5:USB */ + Package(){0x0014FFFF, 0, 0, 16 }, + Package(){0x0014FFFF, 1, 0, 17 }, + Package(){0x0014FFFF, 2, 0, 18 }, + Package(){0x0014FFFF, 3, 0, 19 }, + + /* Bus 0, Dev 19 - USB: OHCI, dev 18,19 func 0-2, dev 20 func 5; + * EHCI, dev 18, 19 func 2 */ + Package(){0x0012FFFF, 0, 0, 18 }, + Package(){0x0012FFFF, 1, 0, 17 }, + + Package(){0x0013FFFF, 0, 0, 18 }, + Package(){0x0013FFFF, 1, 0, 17 }, + + Package(){0x0016FFFF, 0, 0, 18 }, + Package(){0x0016FFFF, 1, 0, 17 }, + + /* Bus 0, Dev 10 - USB: XHCI func 0, 1 */ + Package(){0x0010FFFF, 0, 0, 0x12}, + Package(){0x0010FFFF, 1, 0, 0x11}, + + /* Bus 0, Dev 17 - SATA controller */ + Package(){0x0011FFFF, 0, 0, 19 }, + + /* Bus0, Dev 21 PCIE Bridge */ + Package(){0x0015FFFF, 0, 0, 16 }, + Package(){0x0015FFFF, 1, 0, 17 }, + Package(){0x0015FFFF, 2, 0, 18 }, + Package(){0x0015FFFF, 3, 0, 19 }, + }) + + Name(PS2, Package(){ + /* The external GFX - Hooked to PCIe slot 2 */ + Package(){0x0000FFFF, 0, INTD, 0 }, + Package(){0x0000FFFF, 1, INTA, 0 }, + Package(){0x0000FFFF, 2, INTB, 0 }, + Package(){0x0000FFFF, 3, INTC, 0 }, + }) + Name(APS2, Package(){ + /* The external GFX - Hooked to PCIe slot 2 */ + Package(){0x0000FFFF, 0, 0, 0x12 }, + Package(){0x0000FFFF, 1, 0, 0x13 }, + Package(){0x0000FFFF, 2, 0, 0x10 }, + Package(){0x0000FFFF, 3, 0, 0x11 }, + }) + + /* black slot */ + Name(PS4, Package(){ + /* PCIe slot - Hooked to PCIe slot x4 */ + Package(){0x0000FFFF, 0, INTA, 0 }, + Package(){0x0000FFFF, 1, INTB, 0 }, + Package(){0x0000FFFF, 2, INTC, 0 }, + Package(){0x0000FFFF, 3, INTD, 0 }, + }) + Name(APS4, Package(){ + /* PCIe slot - Hooked to PCIe slot x4 */ + Package(){0x0000FFFF, 0, 0, 0x10 }, + Package(){0x0000FFFF, 1, 0, 0x11 }, + Package(){0x0000FFFF, 2, 0, 0x12 }, + Package(){0x0000FFFF, 3, 0, 0x13 }, + }) + + Name(PBR0, Package(){ + /* PCIx1 on SB */ + Package(){0x0000FFFF, 0, INTA, 0 }, + Package(){0x0000FFFF, 1, INTB, 0 }, + Package(){0x0000FFFF, 2, INTC, 0 }, + Package(){0x0000FFFF, 3, INTD, 0 }, + }) + Name(ABR0, Package(){ + /* PCIx1 on SB */ + Package(){0x0000FFFF, 0, 0, 0x10 }, + Package(){0x0000FFFF, 1, 0, 0x11 }, + Package(){0x0000FFFF, 2, 0, 0x12 }, + Package(){0x0000FFFF, 3, 0, 0x13 }, + }) + + Name(PBR1, Package(){ + /* Onboard network */ + Package(){0x0000FFFF, 0, INTB, 0 }, + Package(){0x0000FFFF, 1, INTC, 0 }, + Package(){0x0000FFFF, 2, INTD, 0 }, + Package(){0x0000FFFF, 3, INTA, 0 }, + }) + Name(ABR1, Package(){ + /* Onboard network */ + Package(){0x0000FFFF, 0, 0, 0x11 }, + Package(){0x0000FFFF, 1, 0, 0x12 }, + Package(){0x0000FFFF, 2, 0, 0x13 }, + Package(){0x0000FFFF, 3, 0, 0x10 }, + }) + + /* SB PCI Bridge */ + Name(PCIB, Package(){ + /* PCI slots: slot 0 behind Dev14, Fun4. */ + Package(){0x0005FFFF, 0, 0, 0x14 }, + Package(){0x0005FFFF, 1, 0, 0x15 }, + Package(){0x0005FFFF, 2, 0, 0x16 }, + Package(){0x0005FFFF, 3, 0, 0x17 }, + }) +} diff --git a/src/mainboard/asus/f2a85-m/acpi/sata.asl b/src/mainboard/asus/f2a85-m/acpi/sata.asl new file mode 100644 index 0000000..c817b6e --- /dev/null +++ b/src/mainboard/asus/f2a85-m/acpi/sata.asl @@ -0,0 +1,148 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* simple name description */ + +/* +Scope (_SB) { + Device(PCI0) { + Device(SATA) { + Name(_ADR, 0x00110000) + #include "sata.asl" + } + } +} +*/ + +Name(STTM, Buffer(20) { + 0x78, 0x00, 0x00, 0x00, 0x0f, 0x00, 0x00, 0x00, + 0x78, 0x00, 0x00, 0x00, 0x0f, 0x00, 0x00, 0x00, + 0x1f, 0x00, 0x00, 0x00 +}) + +/* Start by clearing the PhyRdyChg bits */ +Method(_INI) { + \_GPE._L1F() +} + +Device(PMRY) +{ + Name(_ADR, 0) + Method(_GTM, 0x0, NotSerialized) { + Return(STTM) + } + Method(_STM, 0x3, NotSerialized) {} + + Device(PMST) { + Name(_ADR, 0) + Method(_STA,0) { + if (LGreater(P0IS,0)) { + return (0x0F) /* sata is visible */ + } + else { + return (0x00) /* sata is missing */ + } + } + }/* end of PMST */ + + Device(PSLA) + { + Name(_ADR, 1) + Method(_STA,0) { + if (LGreater(P1IS,0)) { + return (0x0F) /* sata is visible */ + } + else { + return (0x00) /* sata is missing */ + } + } + } /* end of PSLA */ +} /* end of PMRY */ + +Device(SEDY) +{ + Name(_ADR, 1) /* IDE Scondary Channel */ + Method(_GTM, 0x0, NotSerialized) { + Return(STTM) + } + Method(_STM, 0x3, NotSerialized) {} + + Device(SMST) + { + Name(_ADR, 0) + Method(_STA,0) { + if (LGreater(P2IS,0)) { + return (0x0F) /* sata is visible */ + } + else { + return (0x00) /* sata is missing */ + } + } + } /* end of SMST */ + + Device(SSLA) + { + Name(_ADR, 1) + Method(_STA,0) { + if (LGreater(P3IS,0)) { + return (0x0F) /* sata is visible */ + } + else { + return (0x00) /* sata is missing */ + } + } + } /* end of SSLA */ +} /* end of SEDY */ + +/* SATA Hot Plug Support */ +Scope(\_GPE) { + Method(_L1F,0x0,NotSerialized) { + if (\_SB.P0PR) { + if (LGreater(\_SB.P0IS,0)) { + sleep(32) + } + Notify(\_SB.PCI0.STCR.PMRY.PMST, 0x01) /* NOTIFY_DEVICE_CHECK */ + store(one, \_SB.P0PR) + } + + if (\_SB.P1PR) { + if (LGreater(\_SB.P1IS,0)) { + sleep(32) + } + Notify(\_SB.PCI0.STCR.PMRY.PSLA, 0x01) /* NOTIFY_DEVICE_CHECK */ + store(one, \_SB.P1PR) + } + + if (\_SB.P2PR) { + if (LGreater(\_SB.P2IS,0)) { + sleep(32) + } + Notify(\_SB.PCI0.STCR.SEDY.SMST, 0x01) /* NOTIFY_DEVICE_CHECK */ + store(one, \_SB.P2PR) + } + + if (\_SB.P3PR) { + if (LGreater(\_SB.P3IS,0)) { + sleep(32) + } + Notify(\_SB.PCI0.STCR.SEDY.SSLA, 0x01) /* NOTIFY_DEVICE_CHECK */ + store(one, \_SB.P3PR) + } + } +} diff --git a/src/mainboard/asus/f2a85-m/acpi/usb.asl b/src/mainboard/asus/f2a85-m/acpi/usb.asl new file mode 100644 index 0000000..857c78f --- /dev/null +++ b/src/mainboard/asus/f2a85-m/acpi/usb.asl @@ -0,0 +1,114 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* simple name description */ +/* +DefinitionBlock ("DSDT.AML","DSDT",0x01,"XXXXXX","XXXXXXXX",0x00010001 + ) + { + #include "usb.asl" + } +*/ +Method(UCOC, 0) { + Sleep(20) + Store(0x13,CMTI) + Store(0,GPSL) +} + +/* USB Port 0 overcurrent uses Gpm 0 */ +If(LLessEqual(UOM0,9)) { + Scope (\_GPE) { + Method (_L13) { + } + } +} + +/* USB Port 1 overcurrent uses Gpm 1 */ +If (LLessEqual(UOM1,9)) { + Scope (\_GPE) { + Method (_L14) { + } + } +} + +/* USB Port 2 overcurrent uses Gpm 2 */ +If (LLessEqual(UOM2,9)) { + Scope (\_GPE) { + Method (_L15) { + } + } +} + +/* USB Port 3 overcurrent uses Gpm 3 */ +If (LLessEqual(UOM3,9)) { + Scope (\_GPE) { + Method (_L16) { + } + } +} + +/* USB Port 4 overcurrent uses Gpm 4 */ +If (LLessEqual(UOM4,9)) { + Scope (\_GPE) { + Method (_L19) { + } + } +} + +/* USB Port 5 overcurrent uses Gpm 5 */ +If (LLessEqual(UOM5,9)) { + Scope (\_GPE) { + Method (_L1A) { + } + } +} + +/* USB Port 6 overcurrent uses Gpm 6 */ +If (LLessEqual(UOM6,9)) { + Scope (\_GPE) { + /* Method (_L1C) { */ + Method (_L06) { + } + } +} + +/* USB Port 7 overcurrent uses Gpm 7 */ +If (LLessEqual(UOM7,9)) { + Scope (\_GPE) { + /* Method (_L1D) { */ + Method (_L07) { + } + } +} + +/* USB Port 8 overcurrent uses Gpm 8 */ +If (LLessEqual(UOM8,9)) { + Scope (\_GPE) { + Method (_L17) { + } + } +} + +/* USB Port 9 overcurrent uses Gpm 9 */ +If (LLessEqual(UOM9,9)) { + Scope (\_GPE) { + Method (_L0E) { + } + } +} diff --git a/src/mainboard/asus/f2a85-m/acpi_tables.c b/src/mainboard/asus/f2a85-m/acpi_tables.c new file mode 100644 index 0000000..d93fecc --- /dev/null +++ b/src/mainboard/asus/f2a85-m/acpi_tables.c @@ -0,0 +1,329 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <console/console.h> +#include <string.h> +#include <arch/acpi.h> +#include <arch/acpigen.h> +#include <arch/ioapic.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include <cpu/x86/msr.h> +#include "agesawrapper.h" +#include <cpu/amd/mtrr.h> +#include <cpu/amd/amdfam15.h> + +#include "agesawrapper.h" + +#define DUMP_ACPI_TABLES 0 + +#if DUMP_ACPI_TABLES == 1 + +static void dump_mem(u32 start, u32 end) +{ + u32 i; + print_debug("dump_mem:"); + for (i = start; i < end; i++) { + if ((i & 0xf) == 0) { + printk(BIOS_DEBUG, "\n%08x:", i); + } + printk(BIOS_DEBUG, " %02x", (u8)*((u8 *)i)); + } + print_debug("\n"); +} +#endif + +extern const unsigned char AmlCode[]; + +unsigned long acpi_fill_mcfg(unsigned long current) +{ + /* Just a dummy */ + return current; +} + +unsigned long acpi_fill_madt(unsigned long current) +{ + /* create all subtables for processors */ + current = acpi_create_madt_lapics(current); + + /* Write Hudson IOAPIC, only one */ + current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, CONFIG_MAX_CPUS, + IO_APIC_ADDR, 0); + + current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) + current, 0, 0, 2, 0); + current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) + current, 0, 9, 9, 0xF); + /* 0: mean bus 0--->ISA */ + /* 0: PIC 0 */ + /* 2: APIC 2 */ + /* 5 mean: 0101 --> Edige-triggered, Active high */ + + /* create all subtables for processors */ + current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *)current, 0xff, 5, 1); + /* 1: LINT1 connect to NMI */ + + return current; +} + +unsigned long acpi_fill_hest(acpi_hest_t *hest) +{ + void *addr, *current; + + /* Skip the HEST header. */ + current = (void *)(hest + 1); + + addr = agesawrapper_getlateinitptr(PICK_WHEA_MCE); + if (addr != NULL) + current += acpi_create_hest_error_source(hest, current, 0, (void *)((u32)addr + 2), *(UINT16 *)addr - 2); + + addr = agesawrapper_getlateinitptr(PICK_WHEA_CMC); + if (addr != NULL) + current += acpi_create_hest_error_source(hest, current, 1, (void *)((u32)addr + 2), *(UINT16 *)addr - 2); + + return (unsigned long)current; +} + +unsigned long acpi_fill_slit(unsigned long current) +{ + /* Not implemented */ + return current; +} + +unsigned long acpi_fill_srat(unsigned long current) +{ + /* No NUMA, no SRAT */ + return current; +} + +unsigned long acpi_fill_ssdt_generator(unsigned long current, const char *oem_table_id) +{ + int lens; + msr_t msr; + char pscope[] = "\\_SB.PCI0"; + + lens = acpigen_write_scope(pscope); + msr = rdmsr(TOP_MEM); + lens += acpigen_write_name_dword("TOM1", msr.lo); + msr = rdmsr(TOP_MEM2); + /* + * Since XP only implements parts of ACPI 2.0, we can't use a qword + * here. + * See http://www.acpi.info/presentations/S01USMOBS169_OS%2520new.ppt + * slide 22ff. + * Shift value right by 20 bit to make it fit into 32bit, + * giving us 1MB granularity and a limit of almost 4Exabyte of memory. + */ + lens += acpigen_write_name_dword("TOM2", (msr.hi << 12) | msr.lo >> 20); + acpigen_patch_len(lens - 1); + return (unsigned long) (acpigen_get_current()); +} + +unsigned long write_acpi_tables(unsigned long start) +{ + unsigned long current; + acpi_rsdp_t *rsdp; + acpi_rsdt_t *rsdt; + acpi_hpet_t *hpet; + acpi_madt_t *madt; + acpi_srat_t *srat; + acpi_slit_t *slit; + acpi_fadt_t *fadt; + acpi_facs_t *facs; + acpi_header_t *dsdt; + acpi_header_t *ssdt; + acpi_header_t *alib; + acpi_header_t *ivrs; + acpi_hest_t *hest; + + get_bus_conf(); /* it will get sblk, pci1234, hcdn, and sbdn */ + + /* Align ACPI tables to 16 bytes */ + start = ALIGN(start, 16); + current = start; + + printk(BIOS_INFO, "ACPI: Writing ACPI tables at %lx...\n", start); + + /* We need at least an RSDP and an RSDT Table */ + rsdp = (acpi_rsdp_t *) current; + current += sizeof(acpi_rsdp_t); + rsdt = (acpi_rsdt_t *) current; + current += sizeof(acpi_rsdt_t); + + /* clear all table memory */ + memset((void *)start, 0, current - start); + + acpi_write_rsdp(rsdp, rsdt, NULL); + acpi_write_rsdt(rsdt); + + /* DSDT */ + current = ALIGN(current, 8); + printk(BIOS_DEBUG, "ACPI: * DSDT at %lx\n", current); + dsdt = (acpi_header_t *)current; /* it will used by fadt */ + memcpy(dsdt, &AmlCode, sizeof(acpi_header_t)); + current += dsdt->length; + memcpy(dsdt, &AmlCode, dsdt->length); + printk(BIOS_DEBUG, "ACPI: * DSDT @ %p Length %x\n",dsdt,dsdt->length); + + /* FACS */ /* it needs 64 bit alignment */ + current = ALIGN(current, 8); + printk(BIOS_DEBUG, "ACPI: * FACS at %lx\n", current); + facs = (acpi_facs_t *) current; /* it will be used by fadt */ + current += sizeof(acpi_facs_t); + acpi_create_facs(facs); + + /* FADT */ + current = ALIGN(current, 8); + printk(BIOS_DEBUG, "ACPI: * FADT at %lx\n", current); + fadt = (acpi_fadt_t *) current; + current += sizeof(acpi_fadt_t); + + acpi_create_fadt(fadt, facs, dsdt); + acpi_add_table(rsdp, fadt); + + /* + * We explicitly add these tables later on: + */ + current = ALIGN(current, 8); + printk(BIOS_DEBUG, "ACPI: * HPET at %lx\n", current); + hpet = (acpi_hpet_t *) current; + current += sizeof(acpi_hpet_t); + acpi_create_hpet(hpet); + acpi_add_table(rsdp, hpet); + + /* If we want to use HPET Timers Linux wants an MADT */ + current = ALIGN(current, 8); + printk(BIOS_DEBUG, "ACPI: * MADT at %lx\n",current); + madt = (acpi_madt_t *) current; + acpi_create_madt(madt); + current += madt->header.length; + acpi_add_table(rsdp, madt); + + /* HEST */ + current = ALIGN(current, 8); + hest = (acpi_hest_t *)current; + acpi_write_hest((void *)current); + acpi_add_table(rsdp, (void *)current); + current += ((acpi_header_t *)current)->length; + + current = ALIGN(current, 8); + printk(BIOS_DEBUG, "ACPI: * IVRS at %lx\n", current); + ivrs = agesawrapper_getlateinitptr(PICK_IVRS); + if (ivrs != NULL) { + memcpy((void *)current, ivrs, ivrs->length); + ivrs = (acpi_header_t *) current; + current += ivrs->length; + acpi_add_table(rsdp, ivrs); + } else { + printk(BIOS_DEBUG, " AGESA IVRS table NULL. Skipping.\n"); + } + + /* SRAT */ + current = ALIGN(current, 8); + printk(BIOS_DEBUG, "ACPI: * SRAT at %lx\n", current); + srat = (acpi_srat_t *) agesawrapper_getlateinitptr (PICK_SRAT); + if (srat != NULL) { + memcpy((void *)current, srat, srat->header.length); + srat = (acpi_srat_t *) current; + current += srat->header.length; + acpi_add_table(rsdp, srat); + } else { + printk(BIOS_DEBUG, " AGESA SRAT table NULL. Skipping.\n"); + } + + /* SLIT */ + current = ALIGN(current, 8); + printk(BIOS_DEBUG, "ACPI: * SLIT at %lx\n", current); + slit = (acpi_slit_t *) agesawrapper_getlateinitptr (PICK_SLIT); + if (slit != NULL) { + memcpy((void *)current, slit, slit->header.length); + slit = (acpi_slit_t *) current; + current += slit->header.length; + acpi_add_table(rsdp, slit); + } else { + printk(BIOS_DEBUG, " AGESA SLIT table NULL. Skipping.\n"); + } + + /* ALIB */ + current = ALIGN(current, 16); + printk(BIOS_DEBUG, "ACPI: * AGESA ALIB SSDT at %lx\n", current); + alib = (acpi_header_t *)agesawrapper_getlateinitptr (PICK_ALIB); + if (alib != NULL) { + memcpy((void *)current, alib, alib->length); + alib = (acpi_header_t *) current; + current += alib->length; + acpi_add_table(rsdp, (void *)alib); + } + else { + printk(BIOS_DEBUG, " AGESA ALIB SSDT table NULL. Skipping.\n"); + } + + /* this pstate ssdt may cause Blue Screen: Fixed: Keep this comment for a while. */ + /* SSDT */ + current = ALIGN(current, 16); + printk(BIOS_DEBUG, "ACPI: * SSDT at %lx\n", current); + ssdt = (acpi_header_t *)agesawrapper_getlateinitptr (PICK_PSTATE); + if (ssdt != NULL) { + memcpy((void *)current, ssdt, ssdt->length); + ssdt = (acpi_header_t *) current; + current += ssdt->length; + } + else { + printk(BIOS_DEBUG, " AGESA PState table NULL. Skipping.\n"); + } + acpi_add_table(rsdp,ssdt); + + printk(BIOS_DEBUG, "ACPI: * SSDT for PState at %lx\n", current); + + printk(BIOS_DEBUG, "ACPI: * SSDT\n"); + ssdt = (acpi_header_t *)current; + + acpi_create_ssdt_generator(ssdt, ACPI_TABLE_CREATOR); + current += ssdt->length; + acpi_add_table(rsdp, ssdt); + +#if DUMP_ACPI_TABLES == 1 + printk(BIOS_DEBUG, "rsdp\n"); + dump_mem(rsdp, ((void *)rsdp) + sizeof(acpi_rsdp_t)); + + printk(BIOS_DEBUG, "rsdt\n"); + dump_mem(rsdt, ((void *)rsdt) + sizeof(acpi_rsdt_t)); + + printk(BIOS_DEBUG, "madt\n"); + dump_mem(madt, ((void *)madt) + madt->header.length); + + printk(BIOS_DEBUG, "srat\n"); + dump_mem(srat, ((void *)srat) + srat->header.length); + + printk(BIOS_DEBUG, "slit\n"); + dump_mem(slit, ((void *)slit) + slit->header.length); + + printk(BIOS_DEBUG, "ssdt\n"); + dump_mem(ssdt, ((void *)ssdt) + ssdt->length); + + printk(BIOS_DEBUG, "fadt\n"); + dump_mem(fadt, ((void *)fadt) + fadt->header.length); + + printk(BIOS_DEBUG, "hest\n"); + dump_mem(hest, ((void *)hest) + hest->header.length); +#endif + + printk(BIOS_INFO, "ACPI: done.\n"); + return current; +} diff --git a/src/mainboard/asus/f2a85-m/agesawrapper.c b/src/mainboard/asus/f2a85-m/agesawrapper.c new file mode 100644 index 0000000..df45148 --- /dev/null +++ b/src/mainboard/asus/f2a85-m/agesawrapper.c @@ -0,0 +1,775 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ + +#include <stdint.h> +#include <string.h> +#include "agesawrapper.h" +#include "BiosCallOuts.h" +#include "cpuRegisters.h" +#include "cpuCacheInit.h" +#include "cpuApicUtilities.h" +#include "cpuEarlyInit.h" +#include "cpuLateInit.h" +#include "Dispatcher.h" +#include "cpuCacheInit.h" +#include "amdlib.h" +#include "PlatformGnbPcieComplex.h" +#include "Filecode.h" +#include "heapManager.h" +#include "FchPlatform.h" +#include "Fch.h" +#include <cpu/amd/agesa/s3_resume.h> +#include <cbmem.h> +#include <arch/acpi.h> +#include <arch/io.h> + +VOID FchInitS3LateRestore (IN FCH_DATA_BLOCK *FchDataPtr); +VOID FchInitS3EarlyRestore (IN FCH_DATA_BLOCK *FchDataPtr); + +#define FILECODE UNASSIGNED_FILE_FILECODE + +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + +/* ACPI table pointers returned by AmdInitLate */ +VOID *DmiTable = NULL; +VOID *AcpiPstate = NULL; +VOID *AcpiSrat = NULL; +VOID *AcpiSlit = NULL; + +VOID *AcpiWheaMce = NULL; +VOID *AcpiWheaCmc = NULL; +VOID *AcpiAlib = NULL; +VOID *AcpiIvrs = NULL; + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * E X P O R T E D F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + +/*--------------------------------------------------------------------------------------- + * L O C A L F U N C T I O N S + *--------------------------------------------------------------------------------------- + */ +UINT32 +agesawrapper_amdinitcpuio ( + VOID + ) +{ + AGESA_STATUS Status; + UINT64 MsrReg; + UINT32 PciData; + PCI_ADDR PciAddress; + AMD_CONFIG_PARAMS StdHeader; + + /* Enable legacy video routing: D18F1xF4 VGA Enable */ + PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0xF4); + PciData = 1; + LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); + + /* The platform BIOS needs to ensure the memory ranges of Hudson legacy + * devices (TPM, HPET, BIOS RAM, Watchdog Timer, I/O APIC and ACPI) are + * set to non-posted regions. + */ + PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x84); + PciData = 0x00FEDF00; /* last address before processor local APIC at FEE00000 */ + PciData |= 1 << 7; /* set NP (non-posted) bit */ + LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); + PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x80); + PciData = (0xFED00000 >> 8) | 3; /* lowest NP address is HPET at FED00000 */ + LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); + + /* Map the remaining PCI hole as posted MMIO */ + PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x8C); + PciData = 0x00FECF00; /* last address before non-posted range */ + LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); + LibAmdMsrRead (0xC001001A, &MsrReg, &StdHeader); + MsrReg = (MsrReg >> 8) | 3; + PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x88); + PciData = (UINT32)MsrReg; + LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); + + /* Send all IO (0000-FFFF) to southbridge. */ + PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0xC4); + PciData = 0x0000F000; + LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); + PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0xC0); + PciData = 0x00000003; + LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); + Status = AGESA_SUCCESS; + return (UINT32)Status; +} + +UINT32 +agesawrapper_amdinitmmio ( + VOID + ) +{ + AGESA_STATUS Status; + UINT64 MsrReg; + UINT32 PciData; + PCI_ADDR PciAddress; + AMD_CONFIG_PARAMS StdHeader; + + /* + Set the MMIO Configuration Base Address and Bus Range onto MMIO configuration base + Address MSR register. + */ + MsrReg = CONFIG_MMCONF_BASE_ADDRESS | (LibAmdBitScanReverse (CONFIG_MMCONF_BUS_NUMBER) << 2) | 1; + LibAmdMsrWrite (0xC0010058, &MsrReg, &StdHeader); + + /* + Set the NB_CFG MSR register. Enable CF8 extended configuration cycles. + */ + LibAmdMsrRead (0xC001001F, &MsrReg, &StdHeader); + MsrReg = MsrReg | 0x0000400000000000; + LibAmdMsrWrite (0xC001001F, &MsrReg, &StdHeader); + + /* For serial port */ + PciData = 0xFF03FFD5; + PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x14, 0x3, 0x44); + LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); + + /* Set ROM cache onto WP to decrease post time */ + MsrReg = (0x0100000000ull - CONFIG_ROM_SIZE) | 5ull; + LibAmdMsrWrite (0x20C, &MsrReg, &StdHeader); + MsrReg = ((1ULL << CONFIG_CPU_ADDR_BITS) - CONFIG_ROM_SIZE) | 0x800ull; + LibAmdMsrWrite (0x20D, &MsrReg, &StdHeader); + + Status = AGESA_SUCCESS; + return (UINT32)Status; +} + +UINT32 +agesawrapper_amdinitreset ( + VOID + ) +{ + AGESA_STATUS status; + AMD_INTERFACE_PARAMS AmdParamStruct; + AMD_RESET_PARAMS AmdResetParams; + + LibAmdMemFill (&AmdParamStruct, + 0, + sizeof (AMD_INTERFACE_PARAMS), + &(AmdParamStruct.StdHeader)); + + LibAmdMemFill (&AmdResetParams, + 0, + sizeof (AMD_RESET_PARAMS), + &(AmdResetParams.StdHeader)); + + AmdParamStruct.AgesaFunctionName = AMD_INIT_RESET; + AmdParamStruct.AllocationMethod = ByHost; + AmdParamStruct.NewStructSize = sizeof(AMD_RESET_PARAMS); + AmdParamStruct.NewStructPtr = &AmdResetParams; + AmdParamStruct.StdHeader.AltImageBasePtr = 0; + AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; + AmdParamStruct.StdHeader.Func = 0; + AmdParamStruct.StdHeader.ImageBasePtr = 0; + AmdCreateStruct (&AmdParamStruct); + AmdResetParams.HtConfig.Depth = 0; + + status = AmdInitReset ((AMD_RESET_PARAMS *)AmdParamStruct.NewStructPtr); + if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog(AmdParamStruct.StdHeader.HeapStatus); + AmdReleaseStruct (&AmdParamStruct); + return (UINT32)status; +} + +UINT32 +agesawrapper_amdinitearly ( + VOID + ) +{ + AGESA_STATUS status; + AMD_INTERFACE_PARAMS AmdParamStruct; + AMD_EARLY_PARAMS *AmdEarlyParamsPtr; + + LibAmdMemFill (&AmdParamStruct, + 0, + sizeof (AMD_INTERFACE_PARAMS), + &(AmdParamStruct.StdHeader)); + + AmdParamStruct.AgesaFunctionName = AMD_INIT_EARLY; + AmdParamStruct.AllocationMethod = PreMemHeap; + AmdParamStruct.StdHeader.AltImageBasePtr = 0; + AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; + AmdParamStruct.StdHeader.Func = 0; + AmdParamStruct.StdHeader.ImageBasePtr = 0; + AmdCreateStruct (&AmdParamStruct); + + AmdEarlyParamsPtr = (AMD_EARLY_PARAMS *)AmdParamStruct.NewStructPtr; + OemCustomizeInitEarly (AmdEarlyParamsPtr); + + status = AmdInitEarly ((AMD_EARLY_PARAMS *)AmdParamStruct.NewStructPtr); + if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog(AmdParamStruct.StdHeader.HeapStatus); + AmdReleaseStruct (&AmdParamStruct); + + return (UINT32)status; +} + +UINT32 GetHeapBase( + AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT32 heap; + +#if CONFIG_HAVE_ACPI_RESUME + /* Both romstage and ramstage has this S3 detect. */ + if (acpi_get_sleep_type() == 3) + heap = (UINT32)cbmem_find(CBMEM_ID_RESUME_SCRATCH) + (CONFIG_HIGH_SCRATCH_MEMORY_SIZE - BIOS_HEAP_SIZE); /* base + high_stack_size */ + else +#endif + heap = BIOS_HEAP_START_ADDRESS; /* Low mem */ + + return heap; +} + +UINT32 +agesawrapper_amdinitpost ( + VOID + ) +{ + AGESA_STATUS status; + UINT16 i; + UINT32 *HeadPtr; + AMD_INTERFACE_PARAMS AmdParamStruct; + AMD_POST_PARAMS *PostParams; + BIOS_HEAP_MANAGER *BiosManagerPtr; + + LibAmdMemFill (&AmdParamStruct, + 0, + sizeof (AMD_INTERFACE_PARAMS), + &(AmdParamStruct.StdHeader)); + + AmdParamStruct.AgesaFunctionName = AMD_INIT_POST; + AmdParamStruct.AllocationMethod = PreMemHeap; + AmdParamStruct.StdHeader.AltImageBasePtr = 0; + AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; + AmdParamStruct.StdHeader.Func = 0; + AmdParamStruct.StdHeader.ImageBasePtr = 0; + + AmdCreateStruct (&AmdParamStruct); + PostParams = (AMD_POST_PARAMS *)AmdParamStruct.NewStructPtr; + status = AmdInitPost (PostParams); + if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog(PostParams->StdHeader.HeapStatus); + AmdReleaseStruct (&AmdParamStruct); + /* Initialize heap space */ + BiosManagerPtr = (BIOS_HEAP_MANAGER *)GetHeapBase(&AmdParamStruct.StdHeader); + + HeadPtr = (UINT32 *) ((UINT8 *) BiosManagerPtr + sizeof (BIOS_HEAP_MANAGER)); + for (i = 0; i < ((BIOS_HEAP_SIZE/4) - (sizeof (BIOS_HEAP_MANAGER)/4)); i++) + { + *HeadPtr = 0x00000000; + HeadPtr++; + } + BiosManagerPtr->StartOfAllocatedNodes = 0; + BiosManagerPtr->StartOfFreedNodes = 0; + + return (UINT32)status; +} + +UINT32 +agesawrapper_amdinitenv ( + VOID + ) +{ + AGESA_STATUS status; + AMD_INTERFACE_PARAMS AmdParamStruct; + AMD_ENV_PARAMS *EnvParam; + + LibAmdMemFill (&AmdParamStruct, + 0, + sizeof (AMD_INTERFACE_PARAMS), + &(AmdParamStruct.StdHeader)); + + AmdParamStruct.AgesaFunctionName = AMD_INIT_ENV; + AmdParamStruct.AllocationMethod = PostMemDram; + AmdParamStruct.StdHeader.AltImageBasePtr = 0; + AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; + AmdParamStruct.StdHeader.Func = 0; + AmdParamStruct.StdHeader.ImageBasePtr = 0; + status = AmdCreateStruct (&AmdParamStruct); + EnvParam = (AMD_ENV_PARAMS *)AmdParamStruct.NewStructPtr; + + status = AmdInitEnv (EnvParam); + if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog(EnvParam->StdHeader.HeapStatus); + /* Initialize Subordinate Bus Number and Secondary Bus Number + * In platform BIOS this address is allocated by PCI enumeration code + Modify D1F0x18 + */ + + return (UINT32)status; +} + +VOID * +agesawrapper_getlateinitptr ( + int pick + ) +{ + switch (pick) { + case PICK_DMI: + return DmiTable; + case PICK_PSTATE: + return AcpiPstate; + case PICK_SRAT: + return AcpiSrat; + case PICK_SLIT: + return AcpiSlit; + case PICK_WHEA_MCE: + return AcpiWheaMce; + case PICK_WHEA_CMC: + return AcpiWheaCmc; + case PICK_ALIB: + return AcpiAlib; + case PICK_IVRS: + return AcpiIvrs; + default: + return NULL; + } +} + +UINT32 +agesawrapper_amdinitmid ( + VOID + ) +{ + AGESA_STATUS status; + AMD_INTERFACE_PARAMS AmdParamStruct; + + /* Enable MMIO on AMD CPU Address Map Controller */ + agesawrapper_amdinitcpuio (); + + LibAmdMemFill (&AmdParamStruct, + 0, + sizeof (AMD_INTERFACE_PARAMS), + &(AmdParamStruct.StdHeader)); + + AmdParamStruct.AgesaFunctionName = AMD_INIT_MID; + AmdParamStruct.AllocationMethod = PostMemDram; + AmdParamStruct.StdHeader.AltImageBasePtr = 0; + AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; + AmdParamStruct.StdHeader.Func = 0; + AmdParamStruct.StdHeader.ImageBasePtr = 0; + + AmdCreateStruct (&AmdParamStruct); + + ((AMD_MID_PARAMS *)AmdParamStruct.NewStructPtr)->GnbMidConfiguration.iGpuVgaMode = 0;/* 0 iGpuVgaAdapter, 1 iGpuVgaNonAdapter; */ + status = AmdInitMid ((AMD_MID_PARAMS *)AmdParamStruct.NewStructPtr); + if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog(AmdParamStruct.StdHeader.HeapStatus); + AmdReleaseStruct (&AmdParamStruct); + + return (UINT32)status; +} + +UINT32 +agesawrapper_amdinitlate ( + VOID + ) +{ + AGESA_STATUS Status; + AMD_INTERFACE_PARAMS AmdParamStruct; + AMD_LATE_PARAMS *AmdLateParams; + + LibAmdMemFill (&AmdParamStruct, + 0, + sizeof (AMD_INTERFACE_PARAMS), + &(AmdParamStruct.StdHeader)); + + AmdParamStruct.AgesaFunctionName = AMD_INIT_LATE; + AmdParamStruct.AllocationMethod = PostMemDram; + AmdParamStruct.StdHeader.AltImageBasePtr = 0; + AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; + AmdParamStruct.StdHeader.HeapStatus = HEAP_SYSTEM_MEM; + AmdParamStruct.StdHeader.Func = 0; + AmdParamStruct.StdHeader.ImageBasePtr = 0; + + /* NOTE: if not call amdcreatestruct, the initializer(AmdInitLateInitializer) would not be called */ + AmdCreateStruct(&AmdParamStruct); + AmdLateParams = (AMD_LATE_PARAMS *)AmdParamStruct.NewStructPtr; + Status = AmdInitLate(AmdLateParams); + /* CDIT table is not created. */ + if (Status != AGESA_SUCCESS) { + agesawrapper_amdreadeventlog(AmdLateParams->StdHeader.HeapStatus); + ASSERT(Status == AGESA_SUCCESS); + } + + DmiTable = AmdLateParams->DmiTable; + AcpiPstate = AmdLateParams->AcpiPState; + AcpiSrat = AmdLateParams->AcpiSrat; + AcpiSlit = AmdLateParams->AcpiSlit; + + AcpiWheaMce = AmdLateParams->AcpiWheaMce; + AcpiWheaCmc = AmdLateParams->AcpiWheaCmc; + AcpiAlib = AmdLateParams->AcpiAlib; + AcpiIvrs = AmdLateParams->AcpiIvrs; + + printk(BIOS_DEBUG, "DmiTable:%x, AcpiPstatein: %x, AcpiSrat:%x," + "AcpiSlit:%x, Mce:%x, Cmc:%x," + "Alib:%x, AcpiIvrs:%x in %s\n", + (unsigned int)DmiTable, (unsigned int)AcpiPstate, (unsigned int)AcpiSrat, + (unsigned int)AcpiSlit, (unsigned int)AcpiWheaMce, (unsigned int)AcpiWheaCmc, + (unsigned int)AcpiAlib, (unsigned int)AcpiIvrs, __func__); + + /* AmdReleaseStruct (&AmdParamStruct); */ + return (UINT32)Status; +} + +UINT32 +agesawrapper_amdlaterunaptask ( + UINT32 Func, + UINT32 Data, + VOID *ConfigPtr + ) +{ + AGESA_STATUS Status; + AP_EXE_PARAMS ApExeParams; + + LibAmdMemFill (&ApExeParams, + 0, + sizeof (AP_EXE_PARAMS), + &(ApExeParams.StdHeader)); + + ApExeParams.StdHeader.AltImageBasePtr = 0; + ApExeParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; + ApExeParams.StdHeader.Func = 0; + ApExeParams.StdHeader.ImageBasePtr = 0; + ApExeParams.FunctionNumber = Func; + ApExeParams.RelatedDataBlock = ConfigPtr; + + Status = AmdLateRunApTask (&ApExeParams); + if (Status != AGESA_SUCCESS) { + /* agesawrapper_amdreadeventlog(); */ + ASSERT(Status == AGESA_SUCCESS); + } + + return (UINT32)Status; +} + +#if CONFIG_HAVE_ACPI_RESUME + +UINT32 agesawrapper_amdinitresume(VOID) +{ + AGESA_STATUS status; + AMD_INTERFACE_PARAMS AmdParamStruct; + AMD_RESUME_PARAMS *AmdResumeParamsPtr; + S3_DATA_TYPE S3DataType; + + LibAmdMemFill (&AmdParamStruct, + 0, + sizeof (AMD_INTERFACE_PARAMS), + &(AmdParamStruct.StdHeader)); + + AmdParamStruct.AgesaFunctionName = AMD_INIT_RESUME; + AmdParamStruct.AllocationMethod = PreMemHeap; + AmdParamStruct.StdHeader.AltImageBasePtr = 0; + AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; + AmdParamStruct.StdHeader.Func = 0; + AmdParamStruct.StdHeader.ImageBasePtr = 0; + AmdCreateStruct (&AmdParamStruct); + + AmdResumeParamsPtr = (AMD_RESUME_PARAMS *)AmdParamStruct.NewStructPtr; + + AmdResumeParamsPtr->S3DataBlock.NvStorageSize = 0; + AmdResumeParamsPtr->S3DataBlock.VolatileStorageSize = 0; + S3DataType = S3DataTypeNonVolatile; +#if 1 /* TODO: Get the param from Nv storage. */ + OemAgesaGetS3Info (S3DataType, + (u32 *) &AmdResumeParamsPtr->S3DataBlock.NvStorageSize, + (void **) &AmdResumeParamsPtr->S3DataBlock.NvStorage); +#endif + + status = AmdInitResume ((AMD_RESUME_PARAMS *)AmdParamStruct.NewStructPtr); + + if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog(AmdParamStruct.StdHeader.HeapStatus); + AmdReleaseStruct (&AmdParamStruct); + + return (UINT32)status; +} + +#ifndef __PRE_RAM__ + +extern FCH_DATA_BLOCK InitEnvCfgDefault; +STATIC VOID s3_resume_init_data(FCH_DATA_BLOCK *FchParams) +{ + FchParams->Gpp.GppLinkConfig = UserOptions.FchBldCfg->CfgFchGppLinkConfig; + FchParams->Gpp.PortCfg[0].PortPresent = UserOptions.FchBldCfg->CfgFchGppPort0Present; + FchParams->Gpp.PortCfg[1].PortPresent = UserOptions.FchBldCfg->CfgFchGppPort1Present; + FchParams->Gpp.PortCfg[2].PortPresent = UserOptions.FchBldCfg->CfgFchGppPort2Present; + FchParams->Gpp.PortCfg[3].PortPresent = UserOptions.FchBldCfg->CfgFchGppPort3Present; + FchParams->Gpp.PortCfg[0].PortHotPlug = UserOptions.FchBldCfg->CfgFchGppPort0HotPlug; + FchParams->Gpp.PortCfg[1].PortHotPlug = UserOptions.FchBldCfg->CfgFchGppPort1HotPlug; + FchParams->Gpp.PortCfg[2].PortHotPlug = UserOptions.FchBldCfg->CfgFchGppPort2HotPlug; + FchParams->Gpp.PortCfg[3].PortHotPlug = UserOptions.FchBldCfg->CfgFchGppPort3HotPlug; + FchParams->Gpp.GppFunctionEnable = TRUE; /* GppEnable */ + FchParams->Gpp.GppPhyPllPowerDown = TRUE; + FchParams->Gpp.GppDynamicPowerSaving = TRUE; + FchParams->Gpp.UmiPhyPllPowerDown = TRUE; + FchParams->Gpp.NewGppAlgorithm = TRUE; + FchParams->Gpp.GppPortMinPollingTime = 40; + + FchParams->Spi.SpiSpeed = 2; + FchParams->Ir.IrConfig = 3; + + FchParams->HwAcpi.Smbus0BaseAddress = UserOptions.FchBldCfg->CfgSmbus0BaseAddress; + FchParams->HwAcpi.Smbus1BaseAddress = UserOptions.FchBldCfg->CfgSmbus1BaseAddress; + FchParams->HwAcpi.SioPmeBaseAddress = UserOptions.FchBldCfg->CfgSioPmeBaseAddress; + FchParams->HwAcpi.AcpiPm1EvtBlkAddr = UserOptions.FchBldCfg->CfgAcpiPm1EvtBlkAddr; + FchParams->HwAcpi.AcpiPm1CntBlkAddr = UserOptions.FchBldCfg->CfgAcpiPm1CntBlkAddr; + FchParams->HwAcpi.AcpiPmTmrBlkAddr = UserOptions.FchBldCfg->CfgAcpiPmTmrBlkAddr; + FchParams->HwAcpi.CpuControlBlkAddr = UserOptions.FchBldCfg->CfgCpuControlBlkAddr; + FchParams->HwAcpi.AcpiGpe0BlkAddr = UserOptions.FchBldCfg->CfgAcpiGpe0BlkAddr; + FchParams->HwAcpi.SmiCmdPortAddr = UserOptions.FchBldCfg->CfgSmiCmdPortAddr; + FchParams->HwAcpi.AcpiPmaCntBlkAddr = UserOptions.FchBldCfg->CfgAcpiPmaCntBlkAddr; + FchParams->HwAcpi.WatchDogTimerBase = UserOptions.FchBldCfg->CfgWatchDogTimerBase; + FchParams->Sata.SataRaid5Ssid = UserOptions.FchBldCfg->CfgSataRaid5Ssid; + FchParams->Sata.SataRaidSsid = UserOptions.FchBldCfg->CfgSataRaidSsid; + FchParams->Sata.SataAhciSsid = UserOptions.FchBldCfg->CfgSataAhciSsid; + FchParams->Sata.SataIdeSsid = UserOptions.FchBldCfg->CfgSataIdeSsid; + FchParams->Gec.GecShadowRomBase = UserOptions.FchBldCfg->CfgGecShadowRomBase; + FchParams->Spi.RomBaseAddress = UserOptions.FchBldCfg->CfgSpiRomBaseAddress; + FchParams->Sd.SdSsid = UserOptions.FchBldCfg->CfgSdSsid; + FchParams->Spi.LpcSsid = UserOptions.FchBldCfg->CfgLpcSsid; + FchParams->Hpet.HpetBase = UserOptions.FchBldCfg->CfgHpetBaseAddress; + FchParams->Azalia.AzaliaSsid = UserOptions.FchBldCfg->CfgAzaliaSsid; + FchParams->Smbus.SmbusSsid = UserOptions.FchBldCfg->CfgSmbusSsid; + FchParams->Ide.IdeSsid = UserOptions.FchBldCfg->CfgIdeSsid; + FchParams->Usb.EhciSsid = UserOptions.FchBldCfg->CfgEhciSsid; + FchParams->Usb.OhciSsid = UserOptions.FchBldCfg->CfgOhciSsid; + FchParams->Usb.XhciSsid = UserOptions.FchBldCfg->CfgXhciSsid; + FchParams->Ir.IrPinControl = UserOptions.FchBldCfg->CfgFchIrPinControl; + FchParams->Sd.SdClockControl = UserOptions.FchBldCfg->CfgFchSdClockControl; +} + +UINT32 agesawrapper_fchs3earlyrestore (VOID) +{ + AGESA_STATUS status = AGESA_SUCCESS; + + FCH_DATA_BLOCK FchParams; + AMD_CONFIG_PARAMS StdHeader; + + StdHeader.HeapStatus = HEAP_SYSTEM_MEM; + StdHeader.HeapBasePtr = GetHeapBase(&StdHeader) + 0x10; + StdHeader.AltImageBasePtr = 0; + StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; + StdHeader.Func = 0; + StdHeader.ImageBasePtr = 0; + + FchParams = InitEnvCfgDefault; + FchParams.StdHeader = &StdHeader; + s3_resume_init_data(&FchParams); + + FchInitS3EarlyRestore(&FchParams); + + return status; +} +#endif + +UINT32 agesawrapper_amds3laterestore (VOID) +{ + AGESA_STATUS Status; + AMD_INTERFACE_PARAMS AmdInterfaceParams; + AMD_S3LATE_PARAMS AmdS3LateParams; + AMD_S3LATE_PARAMS *AmdS3LateParamsPtr; + S3_DATA_TYPE S3DataType; + + agesawrapper_amdinitcpuio(); + LibAmdMemFill (&AmdS3LateParams, + 0, + sizeof (AMD_S3LATE_PARAMS), + &(AmdS3LateParams.StdHeader)); + AmdInterfaceParams.StdHeader.ImageBasePtr = 0; + AmdInterfaceParams.AllocationMethod = ByHost; + AmdInterfaceParams.AgesaFunctionName = AMD_S3LATE_RESTORE; + AmdInterfaceParams.NewStructPtr = &AmdS3LateParams; + AmdInterfaceParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; + AmdS3LateParamsPtr = &AmdS3LateParams; + AmdInterfaceParams.NewStructSize = sizeof (AMD_S3LATE_PARAMS); + + AmdCreateStruct (&AmdInterfaceParams); + + AmdS3LateParamsPtr->S3DataBlock.VolatileStorageSize = 0; + S3DataType = S3DataTypeVolatile; + +#if 1 /* TODO:Get params from Volatile storage. */ + OemAgesaGetS3Info (S3DataType, + (u32 *) &AmdS3LateParamsPtr->S3DataBlock.VolatileStorageSize, + (void **) &AmdS3LateParamsPtr->S3DataBlock.VolatileStorage); +#endif + + Status = AmdS3LateRestore (AmdS3LateParamsPtr); + if (Status != AGESA_SUCCESS) { + agesawrapper_amdreadeventlog(AmdInterfaceParams.StdHeader.HeapStatus); + ASSERT(Status == AGESA_SUCCESS); + } + + return (UINT32)Status; +} + +#ifndef __PRE_RAM__ + +extern UINT8 picr_data[0x54], intr_data[0x54]; + +UINT32 agesawrapper_fchs3laterestore (VOID) +{ + AGESA_STATUS status = AGESA_SUCCESS; + + FCH_DATA_BLOCK FchParams; + AMD_CONFIG_PARAMS StdHeader; + UINT8 byte; + + StdHeader.HeapStatus = HEAP_SYSTEM_MEM; + StdHeader.HeapBasePtr = GetHeapBase(&StdHeader) + 0x10; + StdHeader.AltImageBasePtr = 0; + StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; + StdHeader.Func = 0; + StdHeader.ImageBasePtr = 0; + + FchParams = InitEnvCfgDefault; + FchParams.StdHeader = &StdHeader; + s3_resume_init_data(&FchParams); + FchInitS3LateRestore(&FchParams); + /* PIC IRQ routine */ + for (byte = 0x0; byte < sizeof(picr_data); byte ++) { + outb(byte, 0xC00); + outb(picr_data[byte], 0xC01); + } + + /* APIC IRQ routine */ + for (byte = 0x0; byte < sizeof(intr_data); byte ++) { + outb(byte | 0x80, 0xC00); + outb(intr_data[byte], 0xC01); + } + + return status; +} +#endif + +#ifndef __PRE_RAM__ + +UINT32 agesawrapper_amdS3Save(VOID) +{ + AGESA_STATUS Status; + AMD_S3SAVE_PARAMS *AmdS3SaveParamsPtr; + AMD_INTERFACE_PARAMS AmdInterfaceParams; + S3_DATA_TYPE S3DataType; + + LibAmdMemFill (&AmdInterfaceParams, + 0, + sizeof (AMD_INTERFACE_PARAMS), + &(AmdInterfaceParams.StdHeader)); + + AmdInterfaceParams.StdHeader.ImageBasePtr = 0; + AmdInterfaceParams.StdHeader.HeapStatus = HEAP_SYSTEM_MEM; + AmdInterfaceParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; + AmdInterfaceParams.AllocationMethod = PostMemDram; + AmdInterfaceParams.AgesaFunctionName = AMD_S3_SAVE; + AmdInterfaceParams.StdHeader.AltImageBasePtr = 0; + AmdInterfaceParams.StdHeader.Func = 0; + + AmdCreateStruct(&AmdInterfaceParams); + AmdS3SaveParamsPtr = (AMD_S3SAVE_PARAMS *)AmdInterfaceParams.NewStructPtr; + AmdS3SaveParamsPtr->StdHeader = AmdInterfaceParams.StdHeader; + + Status = AmdS3Save(AmdS3SaveParamsPtr); + if (Status != AGESA_SUCCESS) { + agesawrapper_amdreadeventlog(AmdInterfaceParams.StdHeader.HeapStatus); + ASSERT(Status == AGESA_SUCCESS); + } + + S3DataType = S3DataTypeNonVolatile; + printk(BIOS_DEBUG, "NvStorageSize=%x, NvStorage=%x\n", + (unsigned int)AmdS3SaveParamsPtr->S3DataBlock.NvStorageSize, + (unsigned int)AmdS3SaveParamsPtr->S3DataBlock.NvStorage); +#if 1 /* TODO: Save the params to NvStorage */ + Status = OemAgesaSaveS3Info ( + S3DataType, + AmdS3SaveParamsPtr->S3DataBlock.NvStorageSize, + AmdS3SaveParamsPtr->S3DataBlock.NvStorage); +#endif + printk(BIOS_DEBUG, "VolatileStorageSize=%x, VolatileStorage=%x\n", + (unsigned int)AmdS3SaveParamsPtr->S3DataBlock.VolatileStorageSize, + (unsigned int)AmdS3SaveParamsPtr->S3DataBlock.VolatileStorage); + + if (AmdS3SaveParamsPtr->S3DataBlock.VolatileStorageSize != 0) { + S3DataType = S3DataTypeVolatile; + +#if 1 /* TODO: Save the params to VolatileStorage */ + Status = OemAgesaSaveS3Info ( + S3DataType, + AmdS3SaveParamsPtr->S3DataBlock.VolatileStorageSize, + AmdS3SaveParamsPtr->S3DataBlock.VolatileStorage + ); +#endif + } + OemAgesaSaveMtrr(); + + AmdReleaseStruct (&AmdInterfaceParams); + + return (UINT32)Status; +} + +#endif /* #ifndef __PRE_RAM__ */ +#endif /* CONFIG_HAVE_ACPI_RESUME */ + +UINT32 +agesawrapper_amdreadeventlog ( + UINT8 HeapStatus + ) +{ + AGESA_STATUS Status; + EVENT_PARAMS AmdEventParams; + + LibAmdMemFill (&AmdEventParams, + 0, + sizeof (EVENT_PARAMS), + &(AmdEventParams.StdHeader)); + + AmdEventParams.StdHeader.AltImageBasePtr = 0; + AmdEventParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; + AmdEventParams.StdHeader.Func = 0; + AmdEventParams.StdHeader.ImageBasePtr = 0; + AmdEventParams.StdHeader.HeapStatus = HeapStatus; + Status = AmdReadEventLog (&AmdEventParams); + while (AmdEventParams.EventClass != 0) { + printk(BIOS_DEBUG,"\nEventLog: EventClass = %x, EventInfo = %x.\n", (unsigned int)AmdEventParams.EventClass,(unsigned int)AmdEventParams.EventInfo); + printk(BIOS_DEBUG," Param1 = %x, Param2 = %x.\n",(unsigned int)AmdEventParams.DataParam1, (unsigned int)AmdEventParams.DataParam2); + printk(BIOS_DEBUG," Param3 = %x, Param4 = %x.\n",(unsigned int)AmdEventParams.DataParam3, (unsigned int)AmdEventParams.DataParam4); + Status = AmdReadEventLog (&AmdEventParams); + } + + return (UINT32)Status; +} diff --git a/src/mainboard/asus/f2a85-m/agesawrapper.h b/src/mainboard/asus/f2a85-m/agesawrapper.h new file mode 100644 index 0000000..5007510 --- /dev/null +++ b/src/mainboard/asus/f2a85-m/agesawrapper.h @@ -0,0 +1,97 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ + +#ifndef _AGESAWRAPPER_H_ +#define _AGESAWRAPPER_H_ + +#include <stdint.h> +#include "Porting.h" +#include "AGESA.h" + +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ +/* Define AMD Ontario APPU SSID/SVID */ +#define AMD_APU_SVID 0x1022 +#define AMD_APU_SSID 0x1234 +#define PCIE_BASE_ADDRESS CONFIG_MMCONF_BASE_ADDRESS + +enum { + PICK_DMI, /* DMI Interface */ + PICK_PSTATE, /* Acpi Pstate SSDT Table */ + PICK_SRAT, /* SRAT Table */ + PICK_SLIT, /* SLIT Table */ + PICK_WHEA_MCE, /* WHEA MCE table */ + PICK_WHEA_CMC, /* WHEA CMV table */ + PICK_ALIB, /* SACPI SSDT table with ALIB implementation */ + PICK_IVRS, /* IOMMU ACPI IVRS(I/O Virtualization Reporting Structure) table */ +}; + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + +typedef struct { + UINT32 CalloutName; + AGESA_STATUS (*CalloutPtr) (UINT32 Func, UINT32 Data, VOID* ConfigPtr); +} BIOS_CALLOUT_STRUCT; + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * E X P O R T E D F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + +/*--------------------------------------------------------------------------------------- + * L O C A L F U N C T I O N S + *--------------------------------------------------------------------------------------- + */ + +UINT32 agesawrapper_amdinitreset (void); +UINT32 agesawrapper_amdinitearly (void); +UINT32 agesawrapper_amdinitenv (void); +UINT32 agesawrapper_amdinitlate (void); +UINT32 agesawrapper_amdinitpost (void); +UINT32 agesawrapper_amdinitmid (void); +UINT32 agesawrapper_amdreadeventlog (UINT8 HeapStatus); +UINT32 agesawrapper_amdinitmmio (void); +UINT32 agesawrapper_amdinitcpuio (void); +void *agesawrapper_getlateinitptr (int pick); +UINT32 agesawrapper_amdlaterunaptask (UINT32 Func, UINT32 Data, void *ConfigPtr); +UINT32 agesawrapper_amdS3Save(VOID); +UINT32 agesawrapper_amdinitresume(VOID); +UINT32 agesawrapper_amds3laterestore (VOID); + +UINT32 agesawrapper_fchs3earlyrestore (VOID); +UINT32 agesawrapper_fchs3laterestore (VOID); + +UINT32 GetHeapBase(AMD_CONFIG_PARAMS *StdHeader); + +#endif diff --git a/src/mainboard/asus/f2a85-m/buildOpts.c b/src/mainboard/asus/f2a85-m/buildOpts.c new file mode 100644 index 0000000..7f893f9 --- /dev/null +++ b/src/mainboard/asus/f2a85-m/buildOpts.c @@ -0,0 +1,517 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/** + * @file + * + * AMD User options selection for a Brazos platform solution system + * + * This file is placed in the user's platform directory and contains the + * build option selections desired for that platform. + * + * For Information about this file, see @ref platforminstall. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: Core + * @e \$Revision: 23714 $ @e \$Date: 2009-12-09 17:28:37 -0600 (Wed, 09 Dec 2009) $ + */ + +#include "AGESA.h" +//#include "CommonReturns.h" +#include "Filecode.h" +#define FILECODE PLATFORM_SPECIFIC_OPTIONS_FILECODE + +/* Select the cpu family. */ +#define INSTALL_FAMILY_10_SUPPORT FALSE +#define INSTALL_FAMILY_12_SUPPORT FALSE +#define INSTALL_FAMILY_14_SUPPORT FALSE +#define INSTALL_FAMILY_15_MODEL_1x_SUPPORT TRUE + +/* Select the cpu socket type. */ +#define INSTALL_G34_SOCKET_SUPPORT FALSE +#define INSTALL_C32_SOCKET_SUPPORT FALSE +#define INSTALL_S1G3_SOCKET_SUPPORT FALSE +#define INSTALL_S1G4_SOCKET_SUPPORT FALSE +#define INSTALL_ASB2_SOCKET_SUPPORT FALSE +#define INSTALL_FS1_SOCKET_SUPPORT FALSE +#define INSTALL_FM1_SOCKET_SUPPORT FALSE +#define INSTALL_FP2_SOCKET_SUPPORT FALSE +#define INSTALL_FT1_SOCKET_SUPPORT FALSE +#define INSTALL_AM3_SOCKET_SUPPORT FALSE + +#define INSTALL_FM2_SOCKET_SUPPORT TRUE + +//#define BLDOPT_REMOVE_UDIMMS_SUPPORT TRUE +#define BLDOPT_REMOVE_SODIMMS_SUPPORT TRUE +#define BLDOPT_REMOVE_RDIMMS_SUPPORT TRUE +#define BLDOPT_REMOVE_LRDIMMS_SUPPORT TRUE +#define BLDOPT_REMOVE_ECC_SUPPORT TRUE +//#define BLDOPT_REMOVE_BANK_INTERLEAVE TRUE +//#define BLDOPT_REMOVE_DCT_INTERLEAVE TRUE +#define BLDOPT_REMOVE_NODE_INTERLEAVE TRUE +#define BLDOPT_REMOVE_PARALLEL_TRAINING TRUE +#define BLDOPT_REMOVE_ONLINE_SPARE_SUPPORT TRUE +//#define BLDOPT_REMOVE_MEM_RESTORE_SUPPORT TRUE +#define BLDOPT_REMOVE_MULTISOCKET_SUPPORT TRUE +//#define BLDOPT_REMOVE_ACPI_PSTATES FALSE +#define BLDOPT_REMOVE_SRAT FALSE //TRUE +#define BLDOPT_REMOVE_SLIT FALSE //TRUE +#define BLDOPT_REMOVE_WHEA FALSE //TRUE +#define BLDOPT_REMOVE_CRAT TRUE +//#define BLDOPT_REMOVE_DMI FALSE //TRUE +//#define BLDOPT_REMOVE_EARLY_SAMPLES FALSE +//#define BLDCFG_REMOVE_ACPI_PSTATES_PPC TRUE +//#define BLDCFG_REMOVE_ACPI_PSTATES_PCT TRUE +//#define BLDCFG_REMOVE_ACPI_PSTATES_PSD TRUE +//#define BLDCFG_REMOVE_ACPI_PSTATES_PSS TRUE +//#define BLDCFG_REMOVE_ACPI_PSTATES_XPSS TRUE + +//This element selects whether P-States should be forced to be independent, +// as reported by the ACPI _PSD object. For single-link processors, +// setting TRUE for OS to support this feature. + +//#define BLDCFG_FORCE_INDEPENDENT_PSD_OBJECT TRUE + +#define BLDCFG_PCI_MMIO_BASE CONFIG_MMCONF_BASE_ADDRESS +#define BLDCFG_PCI_MMIO_SIZE CONFIG_MMCONF_BUS_NUMBER +/* Build configuration values here. + */ +#define BLDCFG_VRM_CURRENT_LIMIT 90000 +#define BLDCFG_VRM_LOW_POWER_THRESHOLD 0 +#define BLDCFG_VRM_MAXIMUM_CURRENT_LIMIT 0 +#define BLDCFG_PLAT_NUM_IO_APICS 3 +#define BLDCFG_CORE_LEVELING_MODE CORE_LEVEL_LOWEST +#define BLDCFG_MEM_INIT_PSTATE 0 + +#define BLDCFG_AMD_PLATFORM_TYPE AMD_PLATFORM_MOBILE + +#define BLDCFG_MEMORY_BUS_FREQUENCY_LIMIT DDR1866_FREQUENCY +#define BLDCFG_MEMORY_MODE_UNGANGED TRUE +#define BLDCFG_MEMORY_QUAD_RANK_CAPABLE TRUE +#define BLDCFG_MEMORY_QUADRANK_TYPE QUADRANK_UNBUFFERED +#define BLDCFG_MEMORY_RDIMM_CAPABLE FALSE +#define BLDCFG_MEMORY_UDIMM_CAPABLE TRUE +#define BLDCFG_MEMORY_SODIMM_CAPABLE FALSE +#define BLDCFG_MEMORY_ENABLE_BANK_INTERLEAVING TRUE +#define BLDCFG_MEMORY_ENABLE_NODE_INTERLEAVING FALSE +#define BLDCFG_MEMORY_CHANNEL_INTERLEAVING TRUE +#define BLDCFG_MEMORY_POWER_DOWN TRUE +#define BLDCFG_POWER_DOWN_MODE POWER_DOWN_BY_CHIP_SELECT +#define BLDCFG_ONLINE_SPARE FALSE +#define BLDCFG_BANK_SWIZZLE TRUE +#define BLDCFG_TIMING_MODE_SELECT TIMING_MODE_AUTO +#define BLDCFG_MEMORY_CLOCK_SELECT DDR1600_FREQUENCY +#define BLDCFG_DQS_TRAINING_CONTROL TRUE +#define BLDCFG_IGNORE_SPD_CHECKSUM FALSE +#define BLDCFG_USE_BURST_MODE FALSE +#define BLDCFG_MEMORY_ALL_CLOCKS_ON FALSE +#define BLDCFG_ENABLE_ECC_FEATURE FALSE +#define BLDCFG_ECC_REDIRECTION FALSE +#define BLDCFG_SCRUB_DRAM_RATE 0 +#define BLDCFG_SCRUB_L2_RATE 0 +#define BLDCFG_SCRUB_L3_RATE 0 +#define BLDCFG_SCRUB_IC_RATE 0 +#define BLDCFG_SCRUB_DC_RATE 0 +#define BLDCFG_ECC_SYMBOL_SIZE 4 +#define BLDCFG_HEAP_DRAM_ADDRESS 0xB0000 +#define BLDCFG_ECC_SYNC_FLOOD FALSE +#define BLDCFG_VRM_HIGH_SPEED_ENABLE TRUE +#define BLDCFG_1GB_ALIGN FALSE +#define BLDCFG_VRM_HIGH_SPEED_ENABLE TRUE +#define BLDCFG_PCIE_REFCLK_SPREAD_SPECTRUM 36 // PCIE Spread Spectrum default value 0.36% +#define BLDCFG_PLATFORM_CSTATE_IO_BASE_ADDRESS 0x1770 + +#define BLDOPT_REMOVE_ALIB FALSE +#define BLDCFG_PLATFORM_CPB_MODE CpbModeDisabled +#define BLDCFG_PROCESSOR_SCOPE_NAME0 'P' +#define BLDCFG_PROCESSOR_SCOPE_NAME1 '0' +#define BLDCFG_PLATFORM_CSTATE_MODE CStateModeC6 + +#define BLDCFG_CFG_LCD_BACK_LIGHT_CONTROL 200 +#define BLDCFG_CFG_ABM_SUPPORT 0 + +//#define BLDCFG_PLATFORM_CSTATE_OPDATA 0x1770 + +// Specify the default values for the VRM controlling the VDDNB plane. +// If not specified, the values used for the core VRM will be applied +//#define BLDCFG_VRM_NB_CURRENT_LIMIT 0 // Not currently used on Trinity +//#define BLDCFG_VRM_NB_LOW_POWER_THRESHOLD 1 // Zero - disable NBPSI_L, Non-zero - enable NBPSI_L +//#define BLDCFG_VRM_NB_SLEW_RATE 5000 // Used in calculating the VSRampSlamTime +//#define BLDCFG_VRM_NB_ADDITIONAL_DELAY 0 // Not currently used on Trinity +//#define BLDCFG_VRM_NB_HIGH_SPEED_ENABLE 0 // Not currently used on Trinity +//#define BLDCFG_VRM_NB_INRUSH_CURRENT_LIMIT 0 // Not currently used on Trinity + +#define BLDCFG_VRM_NB_CURRENT_LIMIT 60000 + +#define BLDCFG_LVDS_POWER_ON_SEQ_VARY_BL_TO_BLON 3 +#define BLDCFG_LVDS_POWER_ON_SEQ_BLON_TO_VARY_BL 3 + +#if CONFIG_GFXUMA +#define BLDCFG_UMA_ALIGNMENT UMA_4MB_ALIGNED +#define BLDCFG_UMA_ALLOCATION_MODE UMA_SPECIFIED +//#define BLDCFG_UMA_ALLOCATION_SIZE 0x1000//0x1800//0x1000 /* (1000 << 16) = 256M*/ +#define BLDCFG_UMA_ALLOCATION_SIZE 0x2000//512M +#define BLDCFG_UMA_ABOVE4G_SUPPORT FALSE +#endif + +#define BLDCFG_IOMMU_SUPPORT FALSE + +#define BLDCFG_CFG_GNB_HD_AUDIO TRUE +//#define BLDCFG_IGPU_SUBSYSTEM_ID OEM_IGPU_SSID +//#define BLDCFG_IGPU_HD_AUDIO_SUBSYSTEM_ID OEM_IGPU_HD_AUDIO_SSID +//#define BLFCFG_APU_PCIE_PORTS_SUBSYSTEM_ID OEM_APU_PCIE_PORTS_SSID + +/* Process the options... + * This file include MUST occur AFTER the user option selection settings + */ +#define AGESA_ENTRY_INIT_RESET TRUE +#define AGESA_ENTRY_INIT_RECOVERY FALSE +#define AGESA_ENTRY_INIT_EARLY TRUE +#define AGESA_ENTRY_INIT_POST TRUE +#define AGESA_ENTRY_INIT_ENV TRUE +#define AGESA_ENTRY_INIT_MID TRUE +#define AGESA_ENTRY_INIT_LATE TRUE +#define AGESA_ENTRY_INIT_S3SAVE TRUE +#define AGESA_ENTRY_INIT_RESUME TRUE //TRUE +#define AGESA_ENTRY_INIT_LATE_RESTORE TRUE +#define AGESA_ENTRY_INIT_GENERAL_SERVICES TRUE +/* + * Customized OEM build configurations for FCH component + */ +// #define BLDCFG_SMBUS0_BASE_ADDRESS 0xB00 +// #define BLDCFG_SMBUS1_BASE_ADDRESS 0xB20 +// #define BLDCFG_SIO_PME_BASE_ADDRESS 0xE00 +// #define BLDCFG_ACPI_PM1_EVT_BLOCK_ADDRESS 0x400 +// #define BLDCFG_ACPI_PM1_CNT_BLOCK_ADDRESS 0x404 +// #define BLDCFG_ACPI_PM_TMR_BLOCK_ADDRESS 0x408 +// #define BLDCFG_ACPI_CPU_CNT_BLOCK_ADDRESS 0x410 +// #define BLDCFG_ACPI_GPE0_BLOCK_ADDRESS 0x420 +// #define BLDCFG_SPI_BASE_ADDRESS 0xFEC10000 +// #define BLDCFG_WATCHDOG_TIMER_BASE 0xFEC00000 +// #define BLDCFG_HPET_BASE_ADDRESS 0xFED00000 +// #define BLDCFG_SMI_CMD_PORT_ADDRESS 0xB0 +// #define BLDCFG_ACPI_PMA_BLK_ADDRESS 0xFE00 +// #define BLDCFG_ROM_BASE_ADDRESS 0xFED61000 +// #define BLDCFG_AZALIA_SSID 0x780D1022 +// #define BLDCFG_SMBUS_SSID 0x780B1022 +// #define BLDCFG_IDE_SSID 0x780C1022 +// #define BLDCFG_SATA_AHCI_SSID 0x78011022 +// #define BLDCFG_SATA_IDE_SSID 0x78001022 +// #define BLDCFG_SATA_RAID5_SSID 0x78031022 +// #define BLDCFG_SATA_RAID_SSID 0x78021022 +// #define BLDCFG_EHCI_SSID 0x78081022 +// #define BLDCFG_OHCI_SSID 0x78071022 +// #define BLDCFG_LPC_SSID 0x780E1022 +// #define BLDCFG_SD_SSID 0x78061022 +// #define BLDCFG_XHCI_SSID 0x78121022 +// #define BLDCFG_FCH_PORT80_BEHIND_PCIB FALSE +// #define BLDCFG_FCH_ENABLE_ACPI_SLEEP_TRAP TRUE +// #define BLDCFG_FCH_GPP_LINK_CONFIG PortA4 +// #define BLDCFG_FCH_GPP_PORT0_PRESENT FALSE +// #define BLDCFG_FCH_GPP_PORT1_PRESENT FALSE +// #define BLDCFG_FCH_GPP_PORT2_PRESENT FALSE +// #define BLDCFG_FCH_GPP_PORT3_PRESENT FALSE +// #define BLDCFG_FCH_GPP_PORT0_HOTPLUG FALSE +// #define BLDCFG_FCH_GPP_PORT1_HOTPLUG FALSE +// #define BLDCFG_FCH_GPP_PORT2_HOTPLUG FALSE +// #define BLDCFG_FCH_GPP_PORT3_HOTPLUG FALSE + +CONST AP_MTRR_SETTINGS ROMDATA TrinityApMtrrSettingsList[] = +{ + { AMD_AP_MTRR_FIX64k_00000, 0x1E1E1E1E1E1E1E1E }, + { AMD_AP_MTRR_FIX16k_80000, 0x1E1E1E1E1E1E1E1E }, + { AMD_AP_MTRR_FIX16k_A0000, 0x0000000000000000 }, + { AMD_AP_MTRR_FIX4k_C0000, 0x0000000000000000 }, + { AMD_AP_MTRR_FIX4k_C8000, 0x0000000000000000 }, + { AMD_AP_MTRR_FIX4k_D0000, 0x0000000000000000 }, + { AMD_AP_MTRR_FIX4k_D8000, 0x0000000000000000 }, + { AMD_AP_MTRR_FIX4k_E0000, 0x1818181818181818 }, + { AMD_AP_MTRR_FIX4k_E8000, 0x1818181818181818 }, + { AMD_AP_MTRR_FIX4k_F0000, 0x1818181818181818 }, + { AMD_AP_MTRR_FIX4k_F8000, 0x1818181818181818 }, + { CPU_LIST_TERMINAL } +}; + +#define BLDCFG_AP_MTRR_SETTINGS_LIST &TrinityApMtrrSettingsList + +//#include "VirgoInstall.h" + +/* Include the files that instantiate the configuration definitions. */ +#include "cpuRegisters.h" +#include "cpuFamRegisters.h" +#include "cpuFamilyTranslation.h" +#include "AdvancedApi.h" +#include "heapManager.h" +#include "CreateStruct.h" +#include "cpuFeatures.h" +#include "Table.h" +#include "CommonReturns.h" +#include "cpuEarlyInit.h" +#include "cpuLateInit.h" +#include "GnbInterface.h" + + // This is the delivery package title, "BrazosPI" + // This string MUST be exactly 8 characters long +#define AGESA_PACKAGE_STRING {'c', 'b', '_', 'A', 'g', 'e', 's', 'a'} + + // This is the release version number of the AGESA component + // This string MUST be exactly 12 characters long +#define AGESA_VERSION_STRING {'V', '0', '.', '0', '.', '0', '.', '1', ' ', ' ', ' ', ' '} + +/* MEMORY_BUS_SPEED */ +#define DDR400_FREQUENCY 200 ///< DDR 400 +#define DDR533_FREQUENCY 266 ///< DDR 533 +#define DDR667_FREQUENCY 333 ///< DDR 667 +#define DDR800_FREQUENCY 400 ///< DDR 800 +#define DDR1066_FREQUENCY 533 ///< DDR 1066 +#define DDR1333_FREQUENCY 667 ///< DDR 1333 +#define DDR1600_FREQUENCY 800 ///< DDR 1600 +#define DDR1866_FREQUENCY 933 ///< DDR 1866 +#define DDR2100_FREQUENCY 1050 ///< DDR 2100 +#define DDR2133_FREQUENCY 1066 ///< DDR 2133 +#define DDR2400_FREQUENCY 1200 ///< DDR 2400 +#define UNSUPPORTED_DDR_FREQUENCY 1201 ///< Highest limit of DDR frequency + +/* QUANDRANK_TYPE*/ +#define QUADRANK_REGISTERED 0 ///< Quadrank registered DIMM +#define QUADRANK_UNBUFFERED 1 ///< Quadrank unbuffered DIMM + +/* USER_MEMORY_TIMING_MODE */ +#define TIMING_MODE_AUTO 0 ///< Use best rate possible +#define TIMING_MODE_LIMITED 1 ///< Set user top limit +#define TIMING_MODE_SPECIFIC 2 ///< Set user specified speed + +/* POWER_DOWN_MODE */ +#define POWER_DOWN_BY_CHANNEL 0 ///< Channel power down mode +#define POWER_DOWN_BY_CHIP_SELECT 1 ///< Chip select power down mode + +/* + * Agesa optional capabilities selection. + * Uncomment and mark FALSE those features you wish to include in the build. + * Comment out or mark TRUE those features you want to REMOVE from the build. + */ + +#define DFLT_SMBUS0_BASE_ADDRESS 0xB00 +#define DFLT_SMBUS1_BASE_ADDRESS 0xB20 +#define DFLT_SIO_PME_BASE_ADDRESS 0xE00 +#define DFLT_ACPI_PM1_EVT_BLOCK_ADDRESS 0x800 +#define DFLT_ACPI_PM1_CNT_BLOCK_ADDRESS 0x804 +#define DFLT_ACPI_PM_TMR_BLOCK_ADDRESS 0x808 +#define DFLT_ACPI_CPU_CNT_BLOCK_ADDRESS 0x810 +#define DFLT_ACPI_GPE0_BLOCK_ADDRESS 0x820 +#define DFLT_SPI_BASE_ADDRESS 0xFEC10000 +#define DFLT_WATCHDOG_TIMER_BASE_ADDRESS 0xFEC000F0 +#define DFLT_HPET_BASE_ADDRESS 0xFED00000 +#define DFLT_SMI_CMD_PORT 0xB0 +#define DFLT_ACPI_PMA_CNT_BLK_ADDRESS 0xFE00 +#define DFLT_GEC_BASE_ADDRESS 0xFED61000 +#define DFLT_AZALIA_SSID 0x780D1022 +#define DFLT_SMBUS_SSID 0x780B1022 +#define DFLT_IDE_SSID 0x780C1022 +#define DFLT_SATA_AHCI_SSID 0x78011022 +#define DFLT_SATA_IDE_SSID 0x78001022 +#define DFLT_SATA_RAID5_SSID 0x78031022 +#define DFLT_SATA_RAID_SSID 0x78021022 +#define DFLT_EHCI_SSID 0x78081022 +#define DFLT_OHCI_SSID 0x78071022 +#define DFLT_LPC_SSID 0x780E1022 +#define DFLT_SD_SSID 0x78061022 +#define DFLT_XHCI_SSID 0x78121022 +#define DFLT_FCH_PORT80_BEHIND_PCIB FALSE +#define DFLT_FCH_ENABLE_ACPI_SLEEP_TRAP TRUE +#define DFLT_FCH_GPP_LINK_CONFIG PortA1B1C1D1 +#define DFLT_FCH_GPP_PORT0_PRESENT TRUE +#define DFLT_FCH_GPP_PORT1_PRESENT TRUE +#define DFLT_FCH_GPP_PORT2_PRESENT FALSE +#define DFLT_FCH_GPP_PORT3_PRESENT FALSE +#define DFLT_FCH_GPP_PORT0_HOTPLUG FALSE +#define DFLT_FCH_GPP_PORT1_HOTPLUG FALSE +#define DFLT_FCH_GPP_PORT2_HOTPLUG FALSE +#define DFLT_FCH_GPP_PORT3_HOTPLUG FALSE +//#define BLDCFG_IR_PIN_CONTROL 0x33 +//#define FCH_NO_XHCI_SUPPORT FALSE +GPIO_CONTROL f2a85_m_gpio[] = { +// {183, Function1, PullUpB}, + {-1} +}; +#define BLDCFG_FCH_GPIO_CONTROL_LIST (&f2a85_m_gpio[0]) + +// The following definitions specify the default values for various parameters in which there are +// no clearly defined defaults to be used in the common file. The values below are based on product +// and BKDG content, please consult the AGESA Memory team for consultation. +#define DFLT_SCRUB_DRAM_RATE (0) +#define DFLT_SCRUB_L2_RATE (0) +#define DFLT_SCRUB_L3_RATE (0) +#define DFLT_SCRUB_IC_RATE (0) +#define DFLT_SCRUB_DC_RATE (0) +#define DFLT_MEMORY_QUADRANK_TYPE QUADRANK_UNBUFFERED +#define DFLT_VRM_SLEW_RATE (5000) + +#include "PlatformInstall.h" + +/*---------------------------------------------------------------------------------------- + * CUSTOMER OVERIDES MEMORY TABLE + *---------------------------------------------------------------------------------------- + */ + +/* + * Platform Specific Overriding Table allows IBV/OEM to pass in platform information to AGESA + * (e.g. MemClk routing, the number of DIMM slots per channel,...). If PlatformSpecificTable + * is populated, AGESA will base its settings on the data from the table. Otherwise, it will + * use its default conservative settings. + */ +CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = { + // + // The following macros are supported (use comma to separate macros): + // + // MEMCLK_DIS_MAP(SocketID, ChannelID, MemClkDisBit0CSMap,..., MemClkDisBit7CSMap) + // The MemClk pins are identified based on BKDG definition of Fn2x88[MemClkDis] bitmap. + // AGESA will base on this value to disable unused MemClk to save power. + // Example: + // BKDG definition of Fn2x88[MemClkDis] bitmap for AM3 package is like below: + // Bit AM3/S1g3 pin name + // 0 M[B,A]_CLK_H/L[0] + // 1 M[B,A]_CLK_H/L[1] + // 2 M[B,A]_CLK_H/L[2] + // 3 M[B,A]_CLK_H/L[3] + // 4 M[B,A]_CLK_H/L[4] + // 5 M[B,A]_CLK_H/L[5] + // 6 M[B,A]_CLK_H/L[6] + // 7 M[B,A]_CLK_H/L[7] + // And platform has the following routing: + // CS0 M[B,A]_CLK_H/L[4] + // CS1 M[B,A]_CLK_H/L[2] + // CS2 M[B,A]_CLK_H/L[3] + // CS3 M[B,A]_CLK_H/L[5] + // Then platform can specify the following macro: + // MEMCLK_DIS_MAP(ANY_SOCKET, ANY_CHANNEL, 0x00, 0x00, 0x02, 0x04, 0x01, 0x08, 0x00, 0x00) + // + // CKE_TRI_MAP(SocketID, ChannelID, CKETriBit0CSMap, CKETriBit1CSMap) + // The CKE pins are identified based on BKDG definition of Fn2x9C_0C[CKETri] bitmap. + // AGESA will base on this value to tristate unused CKE to save power. + // + // ODT_TRI_MAP(SocketID, ChannelID, ODTTriBit0CSMap,..., ODTTriBit3CSMap) + // The ODT pins are identified based on BKDG definition of Fn2x9C_0C[ODTTri] bitmap. + // AGESA will base on this value to tristate unused ODT pins to save power. + // + // CS_TRI_MAP(SocketID, ChannelID, CSTriBit0CSMap,..., CSTriBit7CSMap) + // The Chip select pins are identified based on BKDG definition of Fn2x9C_0C[ChipSelTri] bitmap. + // AGESA will base on this value to tristate unused Chip select to save power. + // + // NUMBER_OF_DIMMS_SUPPORTED(SocketID, ChannelID, NumberOfDimmSlotsPerChannel) + // Specifies the number of DIMM slots per channel. + // + // NUMBER_OF_CHIP_SELECTS_SUPPORTED(SocketID, ChannelID, NumberOfChipSelectsPerChannel) + // Specifies the number of Chip selects per channel. + // + // NUMBER_OF_CHANNELS_SUPPORTED(SocketID, NumberOfChannelsPerSocket) + // Specifies the number of channels per socket. + // + // OVERRIDE_DDR_BUS_SPEED(SocketID, ChannelID, USER_MEMORY_TIMING_MODE, MEMORY_BUS_SPEED) + // Specifies DDR bus speed of channel ChannelID on socket SocketID. + // + // DRAM_TECHNOLOGY(SocketID, TECHNOLOGY_TYPE) + // Specifies the DRAM technology type of socket SocketID (DDR2, DDR3,...) + // + // WRITE_LEVELING_SEED(SocketID, ChannelID, DimmID, Byte0Seed, Byte1Seed, Byte2Seed, Byte3Seed, Byte4Seed, Byte5Seed, + // Byte6Seed, Byte7Seed, ByteEccSeed) + // Specifies the write leveling seed for a channel of a socket. + // + // HW_RXEN_SEED(SocketID, ChannelID, DimmID, Byte0Seed, Byte1Seed, Byte2Seed, Byte3Seed, Byte4Seed, Byte5Seed, + // Byte6Seed, Byte7Seed, ByteEccSeed) + // Speicifes the HW RXEN training seed for a channel of a socket + // + + NUMBER_OF_DIMMS_SUPPORTED (ANY_SOCKET, ANY_CHANNEL, 2), + NUMBER_OF_CHANNELS_SUPPORTED (ANY_SOCKET, 2), +/* + TODO: is this OK for DDR3 socket FM2? + MEMCLK_DIS_MAP (ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00), + CKE_TRI_MAP (ANY_SOCKET, ANY_CHANNEL, 0x05, 0x0A), + ODT_TRI_MAP (ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x00, 0x00), + CS_TRI_MAP (ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00), + */ + PSO_END +}; + +/* + * These tables are optional and may be used to adjust memory timing settings + */ +#include "mm.h" +#include "mn.h" + +// Customer table +UINT8 AGESA_MEM_TABLE_TN[][sizeof (MEM_TABLE_ALIAS)] = +{ + // Hardcoded Memory Training Values + + // The following macro should be used to override training values for your platform + // + // DQSACCESS(MTAfterDqsRwPosTrn, MTNodes, MTDcts, MTDIMMs, BFRdDqsDly, MTOverride, 0x00, 0x04, 0x08, 0x0c, 0x10, 0x14, 0x18, 0x1c, 0x20), + // + // NOTE: + // The following training hardcode values are example values that were taken from a tilapia motherboard + // with a particular DIMM configuration. To hardcode your own values, uncomment the appropriate line in + // the table and replace the byte lane values with your own. + // + // ------------------ BYTE LANES ---------------------- + // BL0 BL1 BL2 BL3 BL4 BL5 BL6 Bl7 ECC + // Write Data Timing + // DQSACCESS(MTAfterHwWLTrnP2, MTNode0, MTDct0, MTDIMM0, BFWrDatDly, MTOverride, 0x1D, 0x20, 0x26, 0x2B, 0x37, 0x3A, 0x3e, 0x3F, 0x30),// DCT0, DIMM0 + // DQSACCESS(MTAfterHwWLTrnP2, MTNode0, MTDct0, MTDIMM1, BFWrDatDly, MTOverride, 0x1D, 0x00, 0x06, 0x0B, 0x17, 0x1A, 0x1E, 0x1F, 0x10),// DCT0, DIMM1 + // DQSACCESS(MTAfterHwWLTrnP2, MTNode0, MTDct1, MTDIMM0, BFWrDatDly, MTOverride, 0x18, 0x1D, 0x27, 0x2B, 0x3B, 0x3B, 0x3E, 0x3E, 0x30),// DCT1, DIMM0 + // DQSACCESS(MTAfterHwWLTrnP2, MTNode0, MTDct1, MTDIMM1, BFWrDatDly, MTOverride, 0x18, 0x1D, 0x1C, 0x0B, 0x17, 0x1A, 0x1D, 0x1C, 0x10),// DCT1, DIMM1 + + // DQS Receiver Enable + // DQSACCESS(MTAfterSwRxEnTrn, MTNode0, MTDct0, MTDIMM0, BFRcvEnDly, MTOverride, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00),// DCT0, DIMM0 + // DQSACCESS(MTAfterSwRxEnTrn, MTNode0, MTDct0, MTDIMM1, BFRcvEnDly, MTOverride, 0x7C, 0x7D, 0x7E, 0x81, 0x88, 0x8F, 0x96, 0x9F, 0x84),// DCT0, DIMM1 + // DQSACCESS(MTAfterSwRxEnTrn, MTNode0, MTDct1, MTDIMM0, BFRcvEnDly, MTOverride, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00),// DCT1, DIMM0 + // DQSACCESS(MTAfterSwRxEnTrn, MTNode0, MTDct1, MTDIMM1, BFRcvEnDly, MTOverride, 0x1C, 0x1D, 0x1E, 0x01, 0x08, 0x0F, 0x16, 0x1F, 0x04),// DCT1, DIMM1 + + // Write DQS Delays + // DQSACCESS(MTAfterDqsRwPosTrn, MTNode0, MTDct0, MTDIMM0, BFWrDqsDly, MTOverride, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00),// DCT0, DIMM0 + // DQSACCESS(MTAfterDqsRwPosTrn, MTNode0, MTDct0, MTDIMM1, BFWrDqsDly, MTOverride, 0x06, 0x0D, 0x12, 0x1A, 0x25, 0x28, 0x2C, 0x2C, 0x44),// DCT0, DIMM1 + // DQSACCESS(MTAfterDqsRwPosTrn, MTNode0, MTDct1, MTDIMM0, BFWrDqsDly, MTOverride, 0x07, 0x0E, 0x14, 0x1B, 0x24, 0x29, 0x2B, 0x2C, 0x1F),// DCT1, DIMM0 + // DQSACCESS(MTAfterDqsRwPosTrn, MTNode0, MTDct1, MTDIMM1, BFWrDqsDly, MTOverride, 0x07, 0x0C, 0x14, 0x19, 0x25, 0x28, 0x2B, 0x2B, 0x1A),// DCT1, DIMM1 + + // Read DQS Delays + // DQSACCESS(MTAfterDqsRwPosTrn, MTNode0, MTDct0, MTDIMM0, BFRdDqsDly, MTOverride, 0x10, 0x10, 0x0E, 0x10, 0x10, 0x10, 0x10, 0x0E, 0x10),// DCT0, DIMM0 + // DQSACCESS(MTAfterDqsRwPosTrn, MTNode0, MTDct0, MTDIMM1, BFRdDqsDly, MTOverride, 0x10, 0x10, 0x0E, 0x10, 0x10, 0x10, 0x10, 0x1E, 0x10),// DCT0, DIMM1 + // DQSACCESS(MTAfterDqsRwPosTrn, MTNode0, MTDct1, MTDIMM0, BFRdDqsDly, MTOverride, 0x10, 0x10, 0x0E, 0x10, 0x10, 0x10, 0x10, 0x1E, 0x10),// DCT1, DIMM0 + // DQSACCESS(MTAfterDqsRwPosTrn, MTNode0, MTDct1, MTDIMM1, BFRdDqsDly, MTOverride, 0x10, 0x10, 0x0E, 0x10, 0x10, 0x10, 0x10, 0x1E, 0x10),// DCT1, DIMM1 + //-------------------------------------------------------------------------------------------------------------------------------------------------- + // TABLE END + NBACCESS (MTEnd, 0, 0, 0, 0, 0), // End of Table +}; +UINT8 SizeOfTableTN = sizeof (AGESA_MEM_TABLE_TN) / sizeof (AGESA_MEM_TABLE_TN[0]); + +/* *************************************************************************** + * Optional User code to be included into the AGESA build + * These may be 32-bit call-out routines... + */ +//AGESA_STATUS +//AgesaReadSpd ( +// IN UINTN FcnData, +// IN OUT AGESA_READ_SPD_PARAMS *ReadSpd +// ) +//{ +// /* platform code to read an SPD... */ +// return Status; +//} diff --git a/src/mainboard/asus/f2a85-m/cmos.layout b/src/mainboard/asus/f2a85-m/cmos.layout new file mode 100644 index 0000000..5520564 --- /dev/null +++ b/src/mainboard/asus/f2a85-m/cmos.layout @@ -0,0 +1,114 @@ +#***************************************************************************** +# +# This file is part of the coreboot project. +# +# Copyright (C) 2012 Advanced Micro Devices, Inc. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +#***************************************************************************** + +entries + +#start-bit length config config-ID name +#0 8 r 0 seconds +#8 8 r 0 alarm_seconds +#16 8 r 0 minutes +#24 8 r 0 alarm_minutes +#32 8 r 0 hours +#40 8 r 0 alarm_hours +#48 8 r 0 day_of_week +#56 8 r 0 day_of_month +#64 8 r 0 month +#72 8 r 0 year +#80 4 r 0 rate_select +#84 3 r 0 REF_Clock +#87 1 r 0 UIP +#88 1 r 0 auto_switch_DST +#89 1 r 0 24_hour_mode +#90 1 r 0 binary_values_enable +#91 1 r 0 square-wave_out_enable +#92 1 r 0 update_finished_enable +#93 1 r 0 alarm_interrupt_enable +#94 1 r 0 periodic_interrupt_enable +#95 1 r 0 disable_clock_updates +#96 288 r 0 temporary_filler +0 384 r 0 reserved_memory +384 1 e 4 boot_option +385 1 e 4 last_boot +386 1 e 1 ECC_memory +388 4 r 0 reboot_bits +392 3 e 5 baud_rate +395 1 e 1 hw_scrubber +396 1 e 1 interleave_chip_selects +397 2 e 8 max_mem_clock +399 1 e 2 multi_core +400 1 e 1 power_on_after_fail +412 4 e 6 debug_level +416 4 e 7 boot_first +420 4 e 7 boot_second +424 4 e 7 boot_third +428 4 h 0 boot_index +432 8 h 0 boot_countdown +440 4 e 9 slow_cpu +444 1 e 1 nmi +445 1 e 1 iommu +728 256 h 0 user_data +984 16 h 0 check_sum +# Reserve the extended AMD configuration registers +1000 24 r 0 amd_reserved + +enumerations + +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +5 0 115200 +5 1 57600 +5 2 38400 +5 3 19200 +5 4 9600 +5 5 4800 +5 6 2400 +5 7 1200 +6 6 Notice +6 7 Info +6 8 Debug +6 9 Spew +7 0 Network +7 1 HDD +7 2 Floppy +7 8 Fallback_Network +7 9 Fallback_HDD +7 10 Fallback_Floppy +#7 3 ROM +8 0 400Mhz +8 1 333Mhz +8 2 266Mhz +8 3 200Mhz +9 0 off +9 1 87.5% +9 2 75.0% +9 3 62.5% +9 4 50.0% +9 5 37.5% +9 6 25.0% +9 7 12.5% + +checksums + +checksum 392 983 984 diff --git a/src/mainboard/asus/f2a85-m/devicetree.cb b/src/mainboard/asus/f2a85-m/devicetree.cb new file mode 100644 index 0000000..8272964 --- /dev/null +++ b/src/mainboard/asus/f2a85-m/devicetree.cb @@ -0,0 +1,130 @@ +# +# This file is part of the coreboot project. +# +# Copyright (C) 2012 Advanced Micro Devices, Inc. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +# +chip northbridge/amd/agesa/family15tn/root_complex + + device cpu_cluster 0 on + chip cpu/amd/agesa/family15tn + device lapic 10 on end + end + end + + device domain 0 on + subsystemid 0x1022 0x1410 inherit + chip northbridge/amd/agesa/family15tn # CPU side of HT root complex + + chip northbridge/amd/agesa/family15tn # PCI side of HT root complex + device pci 0.0 on end # Root Complex + device pci 1.0 on end # Internal Graphics P2P bridge 0x99XX + device pci 1.1 on end # Internal Multimedia + device pci 2.0 on end # PCIE SLOT0 x16 blue + device pci 3.0 off end # unused? + device pci 4.0 on end # PCIE 4x black + device pci 5.0 off end # unused? + device pci 6.0 off end # unused? + device pci 7.0 off end # LAN + device pci 8.0 off end # NB/SB Link P2P bridge + end #chip northbridge/amd/agesa/family15tn # PCI side of HT root complex + + chip southbridge/amd/agesa/hudson # it is under NB/SB Link, but on the same pci bus + device pci 10.0 on end # XHCI HC0 + device pci 10.1 on end # XHCI HC1 + device pci 11.0 on end # SATA + device pci 12.0 on end # USB + device pci 12.2 on end # USB + device pci 13.0 on end # USB + device pci 13.2 on end # USB + device pci 14.0 on # SMBUS + chip drivers/generic/generic #dimm 0 + device i2c 50 on end # 7-bit SPD address + end + chip drivers/generic/generic #dimm 1 + device i2c 51 on end # 7-bit SPD address + end + end # SM + device pci 14.1 off end # IDE 0x439c + device pci 14.2 on end # HDA 0x4383 + device pci 14.3 on # LPC 0x439d + chip superio/ite/it8712f + device pnp 2e.0 off # Floppy + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 + end + device pnp 2e.1 on # Com1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.2 off # Com2 + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 2e.3 off # Parallel Port + io 0x60 = 0x378 + irq 0x70 = 7 + end + device pnp 2e.4 off end # EC + device pnp 2e.5 on # Keyboard + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 + end + device pnp 2e.6 off # Mouse + irq 0x70 = 12 + end + device pnp 2e.7 off # GPIO, must be closed for unresolved reason. + end + device pnp 2e.8 off # MIDI + io 0x60 = 0x300 + irq 0x70 = 9 + end + device pnp 2e.9 off # GAME + io 0x60 = 0x220 + end + device pnp 2e.a off end # CIR + end #superio/ite/it8712f + end #device pci 14.3 # LPC + device pci 14.4 on end # PCI 0x4384 # PCI-b conflict with GPIO. + device pci 14.5 on end # USB 2 + device pci 14.6 off end # Gec + device pci 14.7 off end + device pci 15.0 on end # PCIe 0 - onboard PCIe 1x + device pci 15.1 on end # PCIe 1 onboard gigabit + device pci 15.2 off end # unused + device pci 15.3 off end # unused + + register "boot_switch_sata_ide" = "0" # 0: boot from SATA. 1: IDE + register "gpp_configuration" = "4" + end #chip southbridge/amd/hudson + + device pci 18.0 on end + device pci 18.1 on end + device pci 18.2 on end + device pci 18.3 on end + device pci 18.4 on end + device pci 18.5 on end + + register "spdAddrLookup" = " + { + { {0xA0, 0xA4}, {0xA2, 0xA6}, }, // socket 0 - Channel 0 & 1 - 8-bit SPD addresses + { {0x00, 0x00}, {0x00, 0x00}, }, // socket 1 - Channel 0 & 1 - 8-bit SPD addresses + }" + + end #chip northbridge/amd/agesa/family15tn # CPU side of HT root complex + end #domain +end #chip northbridge/amd/agesa/family15tn/root_complex diff --git a/src/mainboard/asus/f2a85-m/dsdt.asl b/src/mainboard/asus/f2a85-m/dsdt.asl new file mode 100644 index 0000000..d9f8fa4 --- /dev/null +++ b/src/mainboard/asus/f2a85-m/dsdt.asl @@ -0,0 +1,1411 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* DefinitionBlock Statement */ +DefinitionBlock ( + "DSDT.AML", /* Output filename */ + "DSDT", /* Signature */ + 0x02, /* DSDT Revision, needs to be 2 for 64bit */ + "ASUS ", /* OEMID */ + "COREBOOT", /* TABLE ID */ + 0x00010001 /* OEM Revision */ + ) +{ /* Start of ASL file */ + /* #include "../../../arch/x86/acpi/debug.asl" */ /* Include global debug methods if needed */ + + /* Data to be patched by the BIOS during POST */ + /* FIXME the patching is not done yet! */ + /* Memory related values */ + Name(LOMH, 0x0) /* Start of unused memory in C0000-E0000 range */ + Name(PBAD, 0x0) /* Address of BIOS area (If TOM2 != 0, Addr >> 16) */ + Name(PBLN, 0x0) /* Length of BIOS area */ + + Name(PCBA, CONFIG_MMCONF_BASE_ADDRESS) /* Base address of PCIe config space */ + Name(PCLN, Multiply(0x100000, CONFIG_MMCONF_BUS_NUMBER)) /* Length of PCIe config space, 1MB each bus */ + Name(HPBA, 0xFED00000) /* Base address of HPET table */ + + Name(SSFG, 0x0D) /* S1 support: bit 0, S2 Support: bit 1, etc. S0 & S5 assumed */ + + /* USB overcurrent mapping pins. */ + Name(UOM0, 0) + Name(UOM1, 2) + Name(UOM2, 0) + Name(UOM3, 7) + Name(UOM4, 2) + Name(UOM5, 2) + Name(UOM6, 6) + Name(UOM7, 2) + Name(UOM8, 6) + Name(UOM9, 6) + + /* Some global data */ + Name(OSTP, 3) /* Assume nothing. WinXp = 1, Vista = 2, Linux = 3, WinCE = 4 */ + Name(OSV, Ones) /* Assume nothing */ + Name(PMOD, One) /* Assume APIC */ + + /* + * Processor Object + * + */ + Scope (\_PR) { /* define processor scope */ + Processor( + P000, /* name space name */ + 0, /* Unique number for this processor */ + 0x810, /* PBLK system I/O address !hardcoded! */ + 0x06 /* PBLKLEN for boot processor */ + ) { + } + + Processor( + P001, /* name space name */ + 1, /* Unique number for this processor */ + 0x0810, /* PBLK system I/O address !hardcoded! */ + 0x06 /* PBLKLEN for boot processor */ + ) { + } + Processor( + P002, /* name space name */ + 2, /* Unique number for this processor */ + 0x0810, /* PBLK system I/O address !hardcoded! */ + 0x06 /* PBLKLEN for boot processor */ + ) { + } + Processor( + P003, /* name space name */ + 3, /* Unique number for this processor */ + 0x0810, /* PBLK system I/O address !hardcoded! */ + 0x06 /* PBLKLEN for boot processor */ + ) { + } + Processor( + P004, /* name space name */ + 4, /* Unique number for this processor */ + 0x0810, /* PBLK system I/O address !hardcoded! */ + 0x06 /* PBLKLEN for boot processor */ + ) { + } + Processor( + P005, /* name space name */ + 5, /* Unique number for this processor */ + 0x0810, /* PBLK system I/O address !hardcoded! */ + 0x06 /* PBLKLEN for boot processor */ + ) { + } + Processor( + P006, /* name space name */ + 6, /* Unique number for this processor */ + 0x0810, /* PBLK system I/O address !hardcoded! */ + 0x06 /* PBLKLEN for boot processor */ + ) { + } + Processor( + P007, /* name space name */ + 7, /* Unique number for this processor */ + 0x0810, /* PBLK system I/O address !hardcoded! */ + 0x06 /* PBLKLEN for boot processor */ + ) { + } + } /* End _PR scope */ + + /* PIC IRQ mapping registers, C00h-C01h. */ + OperationRegion(PRQM, SystemIO, 0x00000C00, 0x00000002) + Field(PRQM, ByteAcc, NoLock, Preserve) { + PRQI, 0x00000008, + PRQD, 0x00000008, /* Offset: 1h */ + } + IndexField(PRQI, PRQD, ByteAcc, NoLock, Preserve) { + PIRA, 0x00000008, /* Index 0 */ + PIRB, 0x00000008, /* Index 1 */ + PIRC, 0x00000008, /* Index 2 */ + PIRD, 0x00000008, /* Index 3 */ + PIRE, 0x00000008, /* Index 4 */ + PIRF, 0x00000008, /* Index 5 */ + PIRG, 0x00000008, /* Index 6 */ + PIRH, 0x00000008, /* Index 7 */ + } + + /* PCI Error control register */ + OperationRegion(PERC, SystemIO, 0x00000C14, 0x00000001) + Field(PERC, ByteAcc, NoLock, Preserve) { + SENS, 0x00000001, + PENS, 0x00000001, + SENE, 0x00000001, + PENE, 0x00000001, + } + + /* Client Management index/data registers */ + OperationRegion(CMT, SystemIO, 0x00000C50, 0x00000002) + Field(CMT, ByteAcc, NoLock, Preserve) { + CMTI, 8, + /* Client Management Data register */ + G64E, 1, + G64O, 1, + G32O, 2, + , 2, + GPSL, 2, + } + + /* GPM Port register */ + OperationRegion(GPT, SystemIO, 0x00000C52, 0x00000001) + Field(GPT, ByteAcc, NoLock, Preserve) { + GPB0,1, + GPB1,1, + GPB2,1, + GPB3,1, + GPB4,1, + GPB5,1, + GPB6,1, + GPB7,1, + } + + /* Flash ROM program enable register */ + OperationRegion(FRE, SystemIO, 0x00000C6F, 0x00000001) + Field(FRE, ByteAcc, NoLock, Preserve) { + , 0x00000006, + FLRE, 0x00000001, + } + + /* PM2 index/data registers */ + OperationRegion(PM2R, SystemIO, 0x00000CD0, 0x00000002) + Field(PM2R, ByteAcc, NoLock, Preserve) { + PM2I, 0x00000008, + PM2D, 0x00000008, + } + + /* Power Management I/O registers. */ + OperationRegion(PIOR, SystemIO, 0x00000CD6, 0x00000002) + Field(PIOR, ByteAcc, NoLock, Preserve) { + PIOI, 0x00000008, + PIOD, 0x00000008, + } + IndexField (PIOI, PIOD, ByteAcc, NoLock, Preserve) { + Offset(0xEE), + UPWS, 3, + } + + /* PM1 Event Block + * First word is PM1_Status, Second word is PM1_Enable + */ + Scope(\_SB) { + /* PCIe Configuration Space for CONFIG_MMCONF_BUS_NUMBER busses */ + OperationRegion(PCFG, SystemMemory, PCBA, PCLN) + Field(PCFG, ByteAcc, NoLock, Preserve) { + /* Byte offsets are computed using the following technique: + * ((bus number + 1) * ((device number * 8) * 4096)) + register offset + * The 8 comes from 8 functions per device, and 4096 bytes per function config space + */ + Offset(0x00088024), /* Byte offset to SATA register 24h - Bus 0, Device 17, Function 0 */ + STB5, 32, + Offset(0x00098042), /* Byte offset to OHCI0 register 42h - Bus 0, Device 19, Function 0 */ + PT0D, 1, + PT1D, 1, + PT2D, 1, + PT3D, 1, + PT4D, 1, + PT5D, 1, + PT6D, 1, + PT7D, 1, + PT8D, 1, + PT9D, 1, + Offset(0x000A0004), /* Byte offset to SMBUS register 4h - Bus 0, Device 20, Function 0 */ + SBIE, 1, + SBME, 1, + Offset(0x000A0008), /* Byte offset to SMBUS register 8h - Bus 0, Device 20, Function 0 */ + SBRI, 8, + Offset(0x000A0014), /* Byte offset to SMBUS register 14h - Bus 0, Device 20, Function 0 */ + SBB1, 32, + Offset(0x000A0078), /* Byte offset to SMBUS register 78h - Bus 0, Device 20, Function 0 */ + ,14, + P92E, 1, /* Port92 decode enable */ + } + + OperationRegion(SB5, SystemMemory, STB5, 0x1000) + Field(SB5, AnyAcc, NoLock, Preserve){ + /* Port 0 */ + Offset(0x120), /* Port 0 Task file status */ + P0ER, 1, + , 2, + P0DQ, 1, + , 3, + P0BY, 1, + Offset(0x128), /* Port 0 Serial ATA status */ + P0DD, 4, + , 4, + P0IS, 4, + Offset(0x12C), /* Port 0 Serial ATA control */ + P0DI, 4, + Offset(0x130), /* Port 0 Serial ATA error */ + , 16, + P0PR, 1, + + /* Port 1 */ + offset(0x1A0), /* Port 1 Task file status */ + P1ER, 1, + , 2, + P1DQ, 1, + , 3, + P1BY, 1, + Offset(0x1A8), /* Port 1 Serial ATA status */ + P1DD, 4, + , 4, + P1IS, 4, + Offset(0x1AC), /* Port 1 Serial ATA control */ + P1DI, 4, + Offset(0x1B0), /* Port 1 Serial ATA error */ + , 16, + P1PR, 1, + + /* Port 2 */ + Offset(0x220), /* Port 2 Task file status */ + P2ER, 1, + , 2, + P2DQ, 1, + , 3, + P2BY, 1, + Offset(0x228), /* Port 2 Serial ATA status */ + P2DD, 4, + , 4, + P2IS, 4, + Offset(0x22C), /* Port 2 Serial ATA control */ + P2DI, 4, + Offset(0x230), /* Port 2 Serial ATA error */ + , 16, + P2PR, 1, + + /* Port 3 */ + Offset(0x2A0), /* Port 3 Task file status */ + P3ER, 1, + , 2, + P3DQ, 1, + , 3, + P3BY, 1, + Offset(0x2A8), /* Port 3 Serial ATA status */ + P3DD, 4, + , 4, + P3IS, 4, + Offset(0x2AC), /* Port 3 Serial ATA control */ + P3DI, 4, + Offset(0x2B0), /* Port 3 Serial ATA error */ + , 16, + P3PR, 1, + } + } + + #include "acpi/routing.asl" + + Scope(\_SB) { + + Method(CkOT, 0){ + + if(LNotEqual(OSTP, Ones)) {Return(OSTP)} /* OS version was already detected */ + + if(CondRefOf(\_OSI,Local1)) + { + Store(1, OSTP) /* Assume some form of XP */ + if (\_OSI("Windows 2006")) /* Vista */ + { + Store(2, OSTP) + } + } else { + If(WCMP(\_OS,"Linux")) { + Store(3, OSTP) /* Linux */ + } Else { + Store(4, OSTP) /* Gotta be WinCE */ + } + } + Return(OSTP) + } + + Method(_PIC, 0x01, NotSerialized) + { + If (Arg0) + { + \_SB.CIRQ() + } + Store(Arg0, PMOD) + } + Method(CIRQ, 0x00, NotSerialized){ + //Store(0, PIRA) + //Store(0, PIRB) + //Store(0, PIRC) + //Store(0, PIRD) + //Store(0, PIRE) + //Store(0, PIRF) + //Store(0, PIRG) + //Store(0, PIRH) + } + + Name(IRQB, ResourceTemplate(){ + IRQ(Level,ActiveLow,Shared){15} + }) + + Name(IRQP, ResourceTemplate(){ + IRQ(Level,ActiveLow,Exclusive){3, 4, 5, 7, 10, 11, 12, 15} + }) + + Name(PITF, ResourceTemplate(){ + IRQ(Level,ActiveLow,Exclusive){9} + }) + + Device(INTA) { + Name(_HID, EISAID("PNP0C0F")) + Name(_UID, 1) + + Method(_STA, 0) { + if (PIRA) { + Return(0x0B) /* sata is invisible */ + } else { + Return(0x09) /* sata is disabled */ + } + } /* End Method(_SB.INTA._STA) */ + + Method(_DIS ,0) { + /* DBGO("\\_SB\\LNKA\\_DIS\n") */ + //Store(0x1F, PIRA) + } /* End Method(_SB.INTA._DIS) */ + + Method(_PRS ,0) { + /* DBGO("\\_SB\\LNKA\\_PRS\n") */ + Return(IRQP) + } /* Method(_SB.INTA._PRS) */ + + Method(_CRS ,0) { + /* DBGO("\\_SB\\LNKA\\_CRS\n") */ + CreateWordField(IRQB, 0x1, IRQN) + ShiftLeft(1, PIRA, IRQN) + Return(IRQB) + } /* Method(_SB.INTA._CRS) */ + + Method(_SRS, 1) { + /* DBGO("\\_SB\\LNKA\\_CRS\n") */ + CreateWordField(ARG0, 1, IRQM) + + /* Use lowest available IRQ */ + FindSetRightBit(IRQM, Local0) + if (Local0) { + Decrement(Local0) + } + //Store(Local0, PIRA) + } /* End Method(_SB.INTA._SRS) */ + } /* End Device(INTA) */ + + Device(INTB) { + Name(_HID, EISAID("PNP0C0F")) + Name(_UID, 2) + + Method(_STA, 0) { + if (PIRB) { + Return(0x0B) /* sata is invisible */ + } else { + Return(0x09) /* sata is disabled */ + } + } /* End Method(_SB.INTB._STA) */ + + Method(_DIS ,0) { + /* DBGO("\\_SB\\LNKB\\_DIS\n") */ + //Store(0, PIRB) + } /* End Method(_SB.INTB._DIS) */ + + Method(_PRS ,0) { + /* DBGO("\\_SB\\LNKB\\_PRS\n") */ + Return(IRQP) + } /* Method(_SB.INTB._PRS) */ + + Method(_CRS ,0) { + /* DBGO("\\_SB\\LNKB\\_CRS\n") */ + CreateWordField(IRQB, 0x1, IRQN) + ShiftLeft(1, PIRB, IRQN) + Return(IRQB) + } /* Method(_SB.INTB._CRS) */ + + Method(_SRS, 1) { + /* DBGO("\\_SB\\LNKB\\_CRS\n") */ + CreateWordField(ARG0, 1, IRQM) + + /* Use lowest available IRQ */ + FindSetRightBit(IRQM, Local0) + if (Local0) { + Decrement(Local0) + } + Store(Local0, PIRB) + } /* End Method(_SB.INTB._SRS) */ + } /* End Device(INTB) */ + + Device(INTC) { + Name(_HID, EISAID("PNP0C0F")) + Name(_UID, 3) + + Method(_STA, 0) { + if (PIRC) { + Return(0x0B) /* sata is invisible */ + } else { + Return(0x09) /* sata is disabled */ + } + } /* End Method(_SB.INTC._STA) */ + + Method(_DIS ,0) { + /* DBGO("\\_SB\\LNKC\\_DIS\n") */ + //Store(0, PIRC) + } /* End Method(_SB.INTC._DIS) */ + + Method(_PRS ,0) { + /* DBGO("\\_SB\\LNKC\\_PRS\n") */ + Return(IRQP) + } /* Method(_SB.INTC._PRS) */ + + Method(_CRS ,0) { + /* DBGO("\\_SB\\LNKC\\_CRS\n") */ + CreateWordField(IRQB, 0x1, IRQN) + ShiftLeft(1, PIRC, IRQN) + Return(IRQB) + } /* Method(_SB.INTC._CRS) */ + + Method(_SRS, 1) { + /* DBGO("\\_SB\\LNKC\\_CRS\n") */ + CreateWordField(ARG0, 1, IRQM) + + /* Use lowest available IRQ */ + FindSetRightBit(IRQM, Local0) + if (Local0) { + Decrement(Local0) + } + Store(Local0, PIRC) + } /* End Method(_SB.INTC._SRS) */ + } /* End Device(INTC) */ + + Device(INTD) { + Name(_HID, EISAID("PNP0C0F")) + Name(_UID, 4) + + Method(_STA, 0) { + if (PIRD) { + Return(0x0B) /* sata is invisible */ + } else { + Return(0x09) /* sata is disabled */ + } + } /* End Method(_SB.INTD._STA) */ + + Method(_DIS ,0) { + /* DBGO("\\_SB\\LNKD\\_DIS\n") */ + //Store(0, PIRD) + } /* End Method(_SB.INTD._DIS) */ + + Method(_PRS ,0) { + /* DBGO("\\_SB\\LNKD\\_PRS\n") */ + Return(IRQP) + } /* Method(_SB.INTD._PRS) */ + + Method(_CRS ,0) { + /* DBGO("\\_SB\\LNKD\\_CRS\n") */ + CreateWordField(IRQB, 0x1, IRQN) + ShiftLeft(1, PIRD, IRQN) + Return(IRQB) + } /* Method(_SB.INTD._CRS) */ + + Method(_SRS, 1) { + /* DBGO("\\_SB\\LNKD\\_CRS\n") */ + CreateWordField(ARG0, 1, IRQM) + + /* Use lowest available IRQ */ + FindSetRightBit(IRQM, Local0) + if (Local0) { + Decrement(Local0) + } + Store(Local0, PIRD) + } /* End Method(_SB.INTD._SRS) */ + } /* End Device(INTD) */ + + Device(INTE) { + Name(_HID, EISAID("PNP0C0F")) + Name(_UID, 5) + + Method(_STA, 0) { + if (PIRE) { + Return(0x0B) /* sata is invisible */ + } else { + Return(0x09) /* sata is disabled */ + } + } /* End Method(_SB.INTE._STA) */ + + Method(_DIS ,0) { + /* DBGO("\\_SB\\LNKE\\_DIS\n") */ + //Store(0, PIRE) + } /* End Method(_SB.INTE._DIS) */ + + Method(_PRS ,0) { + /* DBGO("\\_SB\\LNKE\\_PRS\n") */ + Return(IRQP) + } /* Method(_SB.INTE._PRS) */ + + Method(_CRS ,0) { + /* DBGO("\\_SB\\LNKE\\_CRS\n") */ + CreateWordField(IRQB, 0x1, IRQN) + ShiftLeft(1, PIRE, IRQN) + Return(IRQB) + } /* Method(_SB.INTE._CRS) */ + + Method(_SRS, 1) { + /* DBGO("\\_SB\\LNKE\\_CRS\n") */ + CreateWordField(ARG0, 1, IRQM) + + /* Use lowest available IRQ */ + FindSetRightBit(IRQM, Local0) + if (Local0) { + Decrement(Local0) + } + Store(Local0, PIRE) + } /* End Method(_SB.INTE._SRS) */ + } /* End Device(INTE) */ + + Device(INTF) { + Name(_HID, EISAID("PNP0C0F")) + Name(_UID, 6) + + Method(_STA, 0) { + if (PIRF) { + Return(0x0B) /* sata is invisible */ + } else { + Return(0x09) /* sata is disabled */ + } + } /* End Method(_SB.INTF._STA) */ + + Method(_DIS ,0) { + /* DBGO("\\_SB\\LNKF\\_DIS\n") */ + //Store(0, PIRF) + } /* End Method(_SB.INTF._DIS) */ + + Method(_PRS ,0) { + /* DBGO("\\_SB\\LNKF\\_PRS\n") */ + Return(PITF) + } /* Method(_SB.INTF._PRS) */ + + Method(_CRS ,0) { + /* DBGO("\\_SB\\LNKF\\_CRS\n") */ + CreateWordField(IRQB, 0x1, IRQN) + ShiftLeft(1, PIRF, IRQN) + Return(IRQB) + } /* Method(_SB.INTF._CRS) */ + + Method(_SRS, 1) { + /* DBGO("\\_SB\\LNKF\\_CRS\n") */ + CreateWordField(ARG0, 1, IRQM) + + /* Use lowest available IRQ */ + FindSetRightBit(IRQM, Local0) + if (Local0) { + Decrement(Local0) + } + Store(Local0, PIRF) + } /* End Method(_SB.INTF._SRS) */ + } /* End Device(INTF) */ + + Device(INTG) { + Name(_HID, EISAID("PNP0C0F")) + Name(_UID, 7) + + Method(_STA, 0) { + if (PIRG) { + Return(0x0B) /* sata is invisible */ + } else { + Return(0x09) /* sata is disabled */ + } + } /* End Method(_SB.INTG._STA) */ + + Method(_DIS ,0) { + /* DBGO("\\_SB\\LNKG\\_DIS\n") */ + //Store(0, PIRG) + } /* End Method(_SB.INTG._DIS) */ + + Method(_PRS ,0) { + /* DBGO("\\_SB\\LNKG\\_PRS\n") */ + Return(IRQP) + } /* Method(_SB.INTG._CRS) */ + + Method(_CRS ,0) { + /* DBGO("\\_SB\\LNKG\\_CRS\n") */ + CreateWordField(IRQB, 0x1, IRQN) + ShiftLeft(1, PIRG, IRQN) + Return(IRQB) + } /* Method(_SB.INTG._CRS) */ + + Method(_SRS, 1) { + /* DBGO("\\_SB\\LNKG\\_CRS\n") */ + CreateWordField(ARG0, 1, IRQM) + + /* Use lowest available IRQ */ + FindSetRightBit(IRQM, Local0) + if (Local0) { + Decrement(Local0) + } + Store(Local0, PIRG) + } /* End Method(_SB.INTG._SRS) */ + } /* End Device(INTG) */ + + Device(INTH) { + Name(_HID, EISAID("PNP0C0F")) + Name(_UID, 8) + + Method(_STA, 0) { + if (PIRH) { + Return(0x0B) /* sata is invisible */ + } else { + Return(0x09) /* sata is disabled */ + } + } /* End Method(_SB.INTH._STA) */ + + Method(_DIS ,0) { + /* DBGO("\\_SB\\LNKH\\_DIS\n") */ + //Store(0, PIRH) + } /* End Method(_SB.INTH._DIS) */ + + Method(_PRS ,0) { + /* DBGO("\\_SB\\LNKH\\_PRS\n") */ + Return(IRQP) + } /* Method(_SB.INTH._CRS) */ + + Method(_CRS ,0) { + /* DBGO("\\_SB\\LNKH\\_CRS\n") */ + CreateWordField(IRQB, 0x1, IRQN) + ShiftLeft(1, PIRH, IRQN) + Return(IRQB) + } /* Method(_SB.INTH._CRS) */ + + Method(_SRS, 1) { + /* DBGO("\\_SB\\LNKH\\_CRS\n") */ + CreateWordField(ARG0, 1, IRQM) + + /* Use lowest available IRQ */ + FindSetRightBit(IRQM, Local0) + if (Local0) { + Decrement(Local0) + } + //Store(Local0, PIRH) + } /* End Method(_SB.INTH._SRS) */ + } /* End Device(INTH) */ + + } /* End Scope(_SB) */ + + /* Supported sleep states: */ + Name(\_S0, Package () {0x00, 0x00, 0x00, 0x00} ) /* (S0) - working state */ + + If (LAnd(SSFG, 0x01)) { + Name(\_S1, Package () {0x01, 0x01, 0x00, 0x00} ) /* (S1) - sleeping w/CPU context */ + } + If (LAnd(SSFG, 0x02)) { + Name(\_S2, Package () {0x02, 0x02, 0x00, 0x00} ) /* (S2) - "light" Suspend to RAM */ + } + If (LAnd(SSFG, 0x04)) { + Name(\_S3, Package () {0x03, 0x03, 0x00, 0x00} ) /* (S3) - Suspend to RAM */ + } + If (LAnd(SSFG, 0x08)) { + Name(\_S4, Package () {0x04, 0x04, 0x00, 0x00} ) /* (S4) - Suspend to Disk */ + } + + Name(\_S5, Package () {0x05, 0x05, 0x00, 0x00} ) /* (S5) - Soft Off */ + + Name(\_SB.CSPS ,0) /* Current Sleep State (S0, S1, S2, S3, S4, S5) */ + Name(CSMS, 0) /* Current System State */ + + /* Wake status package */ + Name(WKST,Package(){Zero, Zero}) + + /* + * \_PTS - Prepare to Sleep method + * + * Entry: + * Arg0=The value of the sleeping state S1=1, S2=2, etc + * + * Exit: + * -none- + * + * The _PTS control method is executed at the beginning of the sleep process + * for S1-S5. The sleeping value is passed to the _PTS control method. This + * control method may be executed a relatively long time before entering the + * sleep state and the OS may abort the operation without notification to + * the ACPI driver. This method cannot modify the configuration or power + * state of any device in the system. + */ + Method(_PTS, 1) { + /* DBGO("\\_PTS\n") */ + /* DBGO("From S0 to S") */ + /* DBGO(Arg0) */ + /* DBGO("\n") */ + + /* Don't allow PCIRST# to reset USB */ + //if (LEqual(Arg0,3)){ + // Store(0,URRE) + //} + + /* Clear sleep SMI status flag and enable sleep SMI trap. */ + /*Store(One, CSSM) + Store(One, SSEN)*/ + + /* On older chips, clear PciExpWakeDisEn */ + /*if (LLessEqual(\_SB.SBRI, 0x13)) { + * Store(0,\_SB.PWDE) + *} + */ + + /* Clear wake status structure. */ + Store(0, Index(WKST,0)) + Store(0, Index(WKST,1)) + Store(7, UPWS) + } /* End Method(\_PTS) */ + + /* + * The following method results in a "not a valid reserved NameSeg" + * warning so I have commented it out for the duration. It isn't + * used, so it could be removed. + * + * + * \_GTS OEM Going To Sleep method + * + * Entry: + * Arg0=The value of the sleeping state S1=1, S2=2 + * + * Exit: + * -none- + * + * Method(\_GTS, 1) { + * DBGO("\\_GTS\n") + * DBGO("From S0 to S") + * DBGO(Arg0) + * DBGO("\n") + * } + */ + + /* + * \_BFS OEM Back From Sleep method + * + * Entry: + * Arg0=The value of the sleeping state S1=1, S2=2 + * + * Exit: + * -none- + */ + Method(\_BFS, 1) { + /* DBGO("\\_BFS\n") */ + /* DBGO("From S") */ + /* DBGO(Arg0) */ + /* DBGO(" to S0\n") */ + } + + /* + * \_WAK System Wake method + * + * Entry: + * Arg0=The value of the sleeping state S1=1, S2=2 + * + * Exit: + * Return package of 2 DWords + * Dword 1 - Status + * 0x00000000 wake succeeded + * 0x00000001 Wake was signaled but failed due to lack of power + * 0x00000002 Wake was signaled but failed due to thermal condition + * Dword 2 - Power Supply state + * if non-zero the effective S-state the power supply entered + */ + Method(\_WAK, 1) { + /* DBGO("\\_WAK\n") */ + /* DBGO("From S") */ + /* DBGO(Arg0) */ + /* DBGO(" to S0\n") */ + + /* Re-enable HPET */ + //Store(1,HPDE) + + /* Restore PCIRST# so it resets USB */ + //if (LEqual(Arg0,3)){ + // Store(1,URRE) + //} + + /* Arbitrarily clear PciExpWakeStatus */ + //Store(PWST, PWST) + + /* if(DeRefOf(Index(WKST,0))) { + * Store(0, Index(WKST,1)) + * } else { + * Store(Arg0, Index(WKST,1)) + * } + */ + Return(WKST) + } /* End Method(\_WAK) */ + + Scope(\_GPE) { /* Start Scope GPE */ + /* General event 0 */ + /* Method(_L00) { + * DBGO("\\_GPE\\_L00\n") + * } + */ + + /* General event 1 */ + /* Method(_L01) { + * DBGO("\\_GPE\\_L00\n") + * } + */ + + /* General event 2 */ + /* Method(_L02) { + * DBGO("\\_GPE\\_L00\n") + * } + */ + + /* General event 3 */ + Method(_L03) { + /* DBGO("\\_GPE\\_L00\n") */ + Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ + } + + /* General event 4 */ + /* Method(_L04) { + * DBGO("\\_GPE\\_L00\n") + * } + */ + + /* General event 5 */ + /* Method(_L05) { + * DBGO("\\_GPE\\_L00\n") + * } + */ + + /* General event 6 - Used for GPM6, moved to USB.asl */ + /* Method(_L06) { + * DBGO("\\_GPE\\_L00\n") + * } + */ + + /* General event 7 - Used for GPM7, moved to USB.asl */ + /* Method(_L07) { + * DBGO("\\_GPE\\_L07\n") + * } + */ + + /* Legacy PM event */ + Method(_L08) { + /* DBGO("\\_GPE\\_L08\n") */ + } + + /* Temp warning (TWarn) event */ + Method(_L09) { + /* DBGO("\\_GPE\\_L09\n") */ + /* Notify (\_TZ.TZ00, 0x80) */ + } + + /* Reserved */ + /* Method(_L0A) { + * DBGO("\\_GPE\\_L0A\n") + * } + */ + + /* USB controller PME# */ + Method(_L0B) { + /* DBGO("\\_GPE\\_L0B\n") */ + Notify(\_SB.PCI0.UOH1, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PCI0.UOH2, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PCI0.UOH3, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PCI0.UOH4, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PCI0.UOH5, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PCI0.UOH6, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PCI0.UEH1, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ + } + + /* AC97 controller PME# */ + /* Method(_L0C) { + * DBGO("\\_GPE\\_L0C\n") + * } + */ + + /* OtherTherm PME# */ + /* Method(_L0D) { + * DBGO("\\_GPE\\_L0D\n") + * } + */ + + /* GPM9 SCI event - Moved to USB.asl */ + /* Method(_L0E) { + * DBGO("\\_GPE\\_L0E\n") + * } + */ + + /* PCIe HotPlug event */ + /* Method(_L0F) { + * DBGO("\\_GPE\\_L0F\n") + * } + */ + + /* ExtEvent0 SCI event */ + Method(_L10) { + /* DBGO("\\_GPE\\_L10\n") */ + } + + /* ExtEvent1 SCI event */ + Method(_L11) { + /* DBGO("\\_GPE\\_L11\n") */ + } + + /* PCIe PME# event */ + /* Method(_L12) { + * DBGO("\\_GPE\\_L12\n") + * } + */ + + /* GPM0 SCI event - Moved to USB.asl */ + /* Method(_L13) { + * DBGO("\\_GPE\\_L13\n") + * } + */ + + /* GPM1 SCI event - Moved to USB.asl */ + /* Method(_L14) { + * DBGO("\\_GPE\\_L14\n") + * } + */ + + /* GPM2 SCI event - Moved to USB.asl */ + /* Method(_L15) { + * DBGO("\\_GPE\\_L15\n") + * } + */ + + /* GPM3 SCI event - Moved to USB.asl */ + /* Method(_L16) { + * DBGO("\\_GPE\\_L16\n") + * } + */ + + /* GPM8 SCI event - Moved to USB.asl */ + /* Method(_L17) { + * DBGO("\\_GPE\\_L17\n") + * } + */ + + /* GPIO0 or GEvent8 event */ + Method(_L18) { + /* DBGO("\\_GPE\\_L18\n") */ + Notify(\_SB.PCI0.PBR4, 0x02) /* NOTIFY_DEVICE_WAKE */ +#if 0 + Notify(\_SB.PCI0.PBR5, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PCI0.PBR6, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PCI0.PBR7, 0x02) /* NOTIFY_DEVICE_WAKE */ +#endif + Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ + } + + /* GPM4 SCI event - Moved to USB.asl */ + /* Method(_L19) { + * DBGO("\\_GPE\\_L19\n") + * } + */ + + /* GPM5 SCI event - Moved to USB.asl */ + /* Method(_L1A) { + * DBGO("\\_GPE\\_L1A\n") + * } + */ + + /* Azalia SCI event */ + Method(_L1B) { + /* DBGO("\\_GPE\\_L1B\n") */ + Notify(\_SB.PCI0.AZHD, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ + } + + /* GPM6 SCI event - Reassigned to _L06 */ + /* Method(_L1C) { + * DBGO("\\_GPE\\_L1C\n") + * } + */ + + /* GPM7 SCI event - Reassigned to _L07 */ + /* Method(_L1D) { + * DBGO("\\_GPE\\_L1D\n") + * } + */ + + /* GPIO2 or GPIO66 SCI event */ + /* Method(_L1E) { + * DBGO("\\_GPE\\_L1E\n") + * } + */ + + /* SATA SCI event - Moved to sata.asl */ + /* Method(_L1F) { + * DBGO("\\_GPE\\_L1F\n") + * } + */ + + } /* End Scope GPE */ + + //#include "acpi/usb.asl" + + /* System Bus */ + Scope(\_SB) { /* Start \_SB scope */ + #include "../../../arch/x86/acpi/globutil.asl" /* global utility methods expected within the \_SB scope */ + + /* _SB.PCI0 */ + /* Note: Only need HID on Primary Bus */ + Device(PCI0) { + External (TOM1) + External (TOM2) + Name(_HID, EISAID("PNP0A03")) + Name(_ADR, 0x00180000) /* Dev# = BSP Dev#, Func# = 0 */ + Method(_BBN, 0) { /* Bus number = 0 */ + Return(0) + } + Method(_STA, 0) { + /* DBGO("\\_SB\\PCI0\\_STA\n") */ + Return(0x0B) /* Status is visible */ + } + + Method(_PRT,0) { + If(PMOD){ Return(APR0) } /* APIC mode */ + Return (PR0) /* PIC Mode */ + } /* end _PRT */ + + /* Describe the Northbridge devices Dev0 ,Func0*/ + Device(AMRT) { + Name(_ADR, 0x00000000) + } /* end AMRT */ + + /* Dev2 is also an external GFX bridge */ + Device(PBR2) { + Name(_ADR, 0x00020000) + Name(_PRW, Package() {0x18, 4}) + Method(_PRT,0) { + If(PMOD){ Return(APS2) } /* APIC mode */ + Return (PS2) /* PIC Mode */ + } /* end _PRT */ + } /* end PBR2 */ + + Device(PBR4) { + Name(_ADR, 0x00040000) + Name(_PRW, Package() {0x18, 4}) + Method(_PRT,0) { + If(PMOD){ Return(APS4) } /* APIC mode */ + Return (PS4) /* PIC Mode */ + } /* end _PRT */ + } /* end PBR4 */ + + /* PCI slot 1, 2, 3 */ + Device(PIBR) { + Name(_ADR, 0x00140004) + Name(_PRW, Package() {0x18, 4}) + /* TODO: non APIC rounting */ + Method(_PRT,0) { + Return (PCIB) + } + } + + /* Describe the Southbridge devices */ + /* PCIe 1x SB */ + Device(SBR0) { + Name(_ADR, 0x00150000) + Name(_PRW, Package() {0x18, 4}) + Method(_PRT,0) { + If(PMOD){ Return(ABR0) } /* APIC mode */ + Return (PBR0) /* PIC Mode */ + } /* end _PRT */ + } /* end SBR0 */ + + + /* Onboard network */ + Device(SBR1) { + Name(_ADR, 0x00150001) + Name(_PRW, Package() {0x18, 4}) + Method(_PRT, 0) { + If(PMOD){ Return(ABR1) } /* APIC mode */ + Return (PBR1) /* PIC Mode */ + } /* end _PRT */ + } /* end SBR1 */ + + Device(STCR) { + Name(_ADR, 0x00110000) + //#include "acpi/sata.asl" + } /* end STCR */ + + Device(UOH1) { + Name(_ADR, 0x00120000) + Name(_PRW, Package() {0x0B, 3}) + } /* end UOH1 */ + + Device(UOH2) { + Name(_ADR, 0x00120002) + Name(_PRW, Package() {0x0B, 3}) + } /* end UOH2 */ + + Device(UOH3) { + Name(_ADR, 0x00130000) + Name(_PRW, Package() {0x0B, 3}) + } /* end UOH3 */ + + Device(UOH4) { + Name(_ADR, 0x00130002) + Name(_PRW, Package() {0x0B, 3}) + } /* end UOH4 */ + + Device(UOH5) { + Name(_ADR, 0x00160000) + Name(_PRW, Package() {0x0B, 3}) + } /* end UOH5 */ + + Device(UOH6) { + Name(_ADR, 0x00160002) + Name(_PRW, Package() {0x0B, 3}) + } /* end UOH5 */ + + Device(UEH1) { + Name(_ADR, 0x00140005) + Name(_PRW, Package() {0x0B, 3}) + } /* end UEH1 */ + + Device(XHC0) { + Name(_ADR, 0x00100000) + Name(_PRW, Package() {0x0B, 4}) + } /* end XHC0 */ + Device(XHC1) { + Name(_ADR, 0x00100001) + Name(_PRW, Package() {0x0B, 4}) + } /* end XHC1 */ + + Device(SBUS) { + Name(_ADR, 0x00140000) + } /* end SBUS */ + + /* Primary (and only) IDE channel */ + Device(IDEC) { + Name(_ADR, 0x00140001) + //#include "acpi/ide.asl" + } /* end IDEC */ + + Device(AZHD) { + Name(_ADR, 0x00140002) + OperationRegion(AZPD, PCI_Config, 0x00, 0x100) + Field(AZPD, AnyAcc, NoLock, Preserve) { + offset (0x42), + NSDI, 1, + NSDO, 1, + NSEN, 1, + offset (0x44), + IPCR, 4, + offset (0x54), + PWST, 2, + , 6, + PMEB, 1, + , 6, + PMST, 1, + offset (0x62), + MMCR, 1, + offset (0x64), + MMLA, 32, + offset (0x68), + MMHA, 32, + offset (0x6C), + MMDT, 16, + } + + Method(_INI) { + If(LEqual(OSTP,3)){ /* If we are running Linux */ + Store(zero, NSEN) + Store(one, NSDO) + Store(one, NSDI) + } + } + } /* end AZHD */ + + Device(LIBR) { + Name(_ADR, 0x00140003) + /* Method(_INI) { + * DBGO("\\_SB\\PCI0\\LpcIsaBr\\_INI\n") + } */ /* End Method(_SB.SBRDG._INI) */ + + /* Real Time Clock Device */ + Device(RTC0) { + Name(_HID, EISAID("PNP0B00")) /* AT Real Time Clock (not PIIX4 compatible) */ + Name(_CRS, ResourceTemplate() { + IRQNoFlags(){8} + IO(Decode16,0x0070, 0x0070, 0, 2) + /* IO(Decode16,0x0070, 0x0070, 0, 4) */ + }) + } /* End Device(_SB.PCI0.LpcIsaBr.RTC0) */ + + Device(TMR) { /* Timer */ + Name(_HID,EISAID("PNP0100")) /* System Timer */ + Name(_CRS, ResourceTemplate() { + IRQNoFlags(){0} + IO(Decode16, 0x0040, 0x0040, 0, 4) + /* IO(Decode16, 0x0048, 0x0048, 0, 4) */ + }) + } /* End Device(_SB.PCI0.LpcIsaBr.TMR) */ + + Device(SPKR) { /* Speaker */ + Name(_HID,EISAID("PNP0800")) /* AT style speaker */ + Name(_CRS, ResourceTemplate() { + IO(Decode16, 0x0061, 0x0061, 0, 1) + }) + } /* End Device(_SB.PCI0.LpcIsaBr.SPKR) */ + + Device(PIC) { + Name(_HID,EISAID("PNP0000")) /* AT Interrupt Controller */ + Name(_CRS, ResourceTemplate() { + IRQNoFlags(){2} + IO(Decode16,0x0020, 0x0020, 0, 2) + IO(Decode16,0x00A0, 0x00A0, 0, 2) + /* IO(Decode16, 0x00D0, 0x00D0, 0x10, 0x02) */ + /* IO(Decode16, 0x04D0, 0x04D0, 0x10, 0x02) */ + }) + } /* End Device(_SB.PCI0.LpcIsaBr.PIC) */ + + Device(MAD) { /* 8257 DMA */ + Name(_HID,EISAID("PNP0200")) /* Hardware Device ID */ + Name(_CRS, ResourceTemplate() { + DMA(Compatibility,BusMaster,Transfer8){4} + IO(Decode16, 0x0000, 0x0000, 0x10, 0x10) + IO(Decode16, 0x0081, 0x0081, 0x01, 0x03) + IO(Decode16, 0x0087, 0x0087, 0x01, 0x01) + IO(Decode16, 0x0089, 0x0089, 0x01, 0x03) + IO(Decode16, 0x008F, 0x008F, 0x01, 0x01) + IO(Decode16, 0x00C0, 0x00C0, 0x10, 0x20) + }) /* End Name(_SB.PCI0.LpcIsaBr.MAD._CRS) */ + } /* End Device(_SB.PCI0.LpcIsaBr.MAD) */ + + Device(COPR) { + Name(_HID,EISAID("PNP0C04")) /* Math Coprocessor */ + Name(_CRS, ResourceTemplate() { + IO(Decode16, 0x00F0, 0x00F0, 0, 0x10) + IRQNoFlags(){13} + }) + } /* End Device(_SB.PCI0.LpcIsaBr.COPR) */ + } /* end LIBR */ + + Device(HPBR) { + Name(_ADR, 0x00140004) + } /* end HostPciBr */ + + Device(ACAD) { + Name(_ADR, 0x00140005) + } /* end Ac97audio */ + + Device(ACMD) { + Name(_ADR, 0x00140006) + } /* end Ac97modem */ + + Name(CRES, ResourceTemplate() { + IO(Decode16, 0x0CF8, 0x0CF8, 1, 8) + + WORDIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, + 0x0000, /* address granularity */ + 0x0000, /* range minimum */ + 0x0CF7, /* range maximum */ + 0x0000, /* translation */ + 0x0CF8 /* length */ + ) + WORDIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, + 0x0000, /* address granularity */ + 0x03B0, /* range minimum */ + 0x03DF, /* range maximum */ + 0x0000, /* translation */ + 0x0030 /* length */ + ) + + WORDIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, + 0x0000, /* address granularity */ + 0x0D00, /* range minimum */ + 0xFFFF, /* range maximum */ + 0x0000, /* translation */ + 0xF300 /* length */ + ) + + Memory32Fixed(READONLY, 0x000A0000, 0x00020000, VGAM) /* VGA memory space */ + Memory32Fixed(READONLY, 0x000C0000, 0x00020000, EMM1) /* Assume C0000-E0000 empty */ + /* memory space for PCI BARs below 4GB */ + Memory32Fixed(ReadOnly, 0x00000000, 0x00000000, MMIO) + }) /* End Name(_SB.PCI0.CRES) */ + + Method(_CRS, 0) { + /* DBGO("\\_SB\\PCI0\\_CRS\n") */ + CreateDWordField(CRES, ^MMIO._BAS, MM1B) + CreateDWordField(CRES, ^MMIO._LEN, MM1L) + /* + * Declare memory between TOM1 and 4GB as available + * for PCI MMIO. + * Use ShiftLeft to avoid 64bit constant (for XP). + * This will work even if the OS does 32bit arithmetic, as + * 32bit (0x00000000 - TOM1) will wrap and give the same + * result as 64bit (0x100000000 - TOM1). + */ + Store(TOM1, MM1B) + ShiftLeft(0x10000000, 4, Local0) + Subtract(Local0, TOM1, Local0) + Store(Local0, MM1L) + + Return(CRES) /* note to change the Name buffer */ + } /* end of Method(_SB.PCI0._CRS) */ + + /* + * + * FIRST METHOD CALLED UPON BOOT + * + * 1. If debugging, print current OS and ACPI interpreter. + * 2. Get PCI Interrupt routing from ACPI VSM, this + * value is based on user choice in BIOS setup. + */ + Method(_INI, 0) { + /* DBGO("\\_SB\\_INI\n") */ + /* DBGO(" DSDT.ASL code from ") */ + /* DBGO(__DATE__) */ + /* DBGO(" ") */ + /* DBGO(__TIME__) */ + /* DBGO("\n Sleep states supported: ") */ + /* DBGO("\n") */ + /* DBGO(" \\_OS=") */ + /* DBGO(\_OS) */ + /* DBGO("\n \\_REV=") */ + /* DBGO(\_REV) */ + /* DBGO("\n") */ + + /* Determine the OS we're running on */ + CkOT() + + /* On older chips, clear PciExpWakeDisEn */ + /*if (LLessEqual(\SBRI, 0x13)) { + * Store(0,\PWDE) + * } + */ + } /* End Method(_SB._INI) */ + } /* End Device(PCI0) */ + + Device(PWRB) { /* Start Power button device */ + Name(_HID, EISAID("PNP0C0C")) + Name(_UID, 0xAA) + Name(_PRW, Package () {3, 0x04}) /* wake from S1-S4 */ + Name(_STA, 0x0B) /* sata is invisible */ + } + } /* End \_SB scope */ + + Scope(\_SI) { + Method(_SST, 1) { + /* DBGO("\\_SI\\_SST\n") */ + /* DBGO(" New Indicator state: ") */ + /* DBGO(Arg0) */ + /* DBGO("\n") */ + } + } /* End Scope SI */ +} +/* End of ASL file */ diff --git a/src/mainboard/asus/f2a85-m/get_bus_conf.c b/src/mainboard/asus/f2a85-m/get_bus_conf.c new file mode 100644 index 0000000..3ae4c18 --- /dev/null +++ b/src/mainboard/asus/f2a85-m/get_bus_conf.c @@ -0,0 +1,139 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <console/console.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include <string.h> +#include <stdint.h> +#include <stdlib.h> +#include <cpu/amd/amdfam14.h> +#include "agesawrapper.h" + +/* Global variables for MB layouts and these will be shared by irqtable mptable + * and acpi_tables busnum is default. + */ +u8 bus_isa; +u8 bus_hudson[3]; +u32 apicid_hudson; + +/* + * Here you only need to set value in pci1234 for HT-IO that could be installed or not + * You may need to preset pci1234 for HTIO board, + * please refer to src/northbridge/amd/amdk8/get_sblk_pci1234.c for detail + */ +u32 pci1234x[] = { + 0x0000ff0, +}; + +u32 bus_type[256]; +u32 sbdn_hudson; + +static u32 get_bus_conf_done = 0; + +#if CONFIG_HAVE_ACPI_RESUME +extern u8 acpi_slp_type; +#endif +void get_bus_conf(void) +{ + u32 apicid_base; + u32 status; + + device_t dev; + int i, j; + + if (get_bus_conf_done == 1) + return; /* do it only once */ + + get_bus_conf_done = 1; + + /* + * This is the call to AmdInitLate. It is really in the wrong place, conceptually, + * but functionally within the coreboot model, this is the best place to make the + * call. The logically correct place to call AmdInitLate is after PCI scan is done, + * after the decision about S3 resume is made, and before the system tables are + * written into RAM. The routine that is responsible for writing the tables is + * "write_tables", called near the end of "hardwaremain". There is no platform + * specific entry point between the S3 resume decision point and the call to + * "write_tables", and the next platform specific entry points are the calls to + * the ACPI table write functions. The first of ose would seem to be the right + * place, but other table write functions, e.g. the PIRQ table write function, are + * called before the ACPI tables are written. This routine is called at the beginning + * of each of the write functions called prior to the ACPI write functions, so this + * becomes the best place for this call. + */ +#if CONFIG_HAVE_ACPI_RESUME + if (acpi_slp_type != 3) { + status = agesawrapper_amdinitlate(); + if(status) { + printk(BIOS_DEBUG, "agesawrapper_amdinitlate failed: %x \n", status); + } + status = agesawrapper_amdS3Save(); + if (status) { + printk(BIOS_DEBUG, "agesawrapper_amds3save failed: %x \n", status); + } + } +#else + status = agesawrapper_amdinitlate(); + if (status) + printk(BIOS_DEBUG, "agesawrapper_amdinitlate failed: %x \n", status); +#endif + + sbdn_hudson = 0; + + for (i = 0; i < 3; i++) { + bus_hudson[i] = 0; + } + + for (i = 0; i < 256; i++) { + bus_type[i] = 0; /* default ISA bus. */ + } + + bus_type[0] = 1; /* pci */ + + bus_hudson[0] = (pci1234x[0] >> 16) & 0xff; + + /* Hudson */ + dev = dev_find_slot(bus_hudson[0], PCI_DEVFN(sbdn_hudson + 0x14, 4)); + + if (dev) { + bus_hudson[1] = pci_read_config8(dev, PCI_SECONDARY_BUS); + + bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS); + bus_isa++; + for (j = bus_hudson[1]; j < bus_isa; j++) + bus_type[j] = 1; + } + + for (i = 0; i < 4; i++) { + dev = dev_find_slot(bus_hudson[0], PCI_DEVFN(sbdn_hudson + 0x14, i)); + if (dev) { + bus_hudson[2 + i] = pci_read_config8(dev, PCI_SECONDARY_BUS); + bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS); + bus_isa++; + } + } + for (j = bus_hudson[2]; j < bus_isa; j++) + bus_type[j] = 1; + + /* I/O APICs: APIC ID Version State Address */ + bus_isa = 10; + apicid_base = CONFIG_MAX_CPUS; + apicid_hudson = apicid_base; +} diff --git a/src/mainboard/asus/f2a85-m/irq_tables.c b/src/mainboard/asus/f2a85-m/irq_tables.c new file mode 100644 index 0000000..d7e223b --- /dev/null +++ b/src/mainboard/asus/f2a85-m/irq_tables.c @@ -0,0 +1,112 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <console/console.h> +#include <device/pci.h> +#include <string.h> +#include <stdint.h> +#include <arch/pirq_routing.h> +#include <cpu/amd/amdfam15.h> + +static void write_pirq_info(struct irq_info *pirq_info, u8 bus, u8 devfn, + u8 link0, u16 bitmap0, u8 link1, u16 bitmap1, + u8 link2, u16 bitmap2, u8 link3, u16 bitmap3, + u8 slot, u8 rfu) +{ + pirq_info->bus = bus; + pirq_info->devfn = devfn; + pirq_info->irq[0].link = link0; + pirq_info->irq[0].bitmap = bitmap0; + pirq_info->irq[1].link = link1; + pirq_info->irq[1].bitmap = bitmap1; + pirq_info->irq[2].link = link2; + pirq_info->irq[2].bitmap = bitmap2; + pirq_info->irq[3].link = link3; + pirq_info->irq[3].bitmap = bitmap3; + pirq_info->slot = slot; + pirq_info->rfu = rfu; +} + +extern u8 bus_isa; +extern u8 bus_hudson[2]; +extern unsigned long sbdn_hudson; + +unsigned long write_pirq_routing_table(unsigned long addr) +{ + struct irq_routing_table *pirq; + struct irq_info *pirq_info; + u32 slot_num; + u8 *v; + + u8 sum = 0; + int i; + + get_bus_conf(); /* it will find out all bus num and apic that share with mptable.c and mptable.c and acpi_tables.c */ + + /* Align the table to be 16 byte aligned. */ + addr += 15; + addr &= ~15; + + /* This table must be betweeen 0xf0000 & 0x100000 */ + printk(BIOS_INFO, "Writing IRQ routing tables to 0x%lx...", addr); + + pirq = (void *)(addr); + v = (u8 *) (addr); + + pirq->signature = PIRQ_SIGNATURE; + pirq->version = PIRQ_VERSION; + + pirq->rtr_bus = bus_hudson[0]; + pirq->rtr_devfn = ((sbdn_hudson + 0x14) << 3) | 4; + + pirq->exclusive_irqs = 0; + + pirq->rtr_vendor = 0x1002; + pirq->rtr_device = 0x4384; + + pirq->miniport_data = 0; + + memset(pirq->rfu, 0, sizeof(pirq->rfu)); + + pirq_info = (void *)(&pirq->checksum + 1); + slot_num = 0; + + /* pci bridge */ + write_pirq_info(pirq_info, bus_hudson[0], ((sbdn_hudson + 0x14) << 3) | 4, + 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, + 0); + pirq_info++; + + slot_num++; + + pirq->size = 32 + 16 * slot_num; + + for (i = 0; i < pirq->size; i++) + sum += v[i]; + + sum = pirq->checksum - sum; + + if (sum != pirq->checksum) { + pirq->checksum = sum; + } + + printk(BIOS_INFO, "write_pirq_routing_table done.\n"); + + return (unsigned long)pirq_info; +} diff --git a/src/mainboard/asus/f2a85-m/mainboard.c b/src/mainboard/asus/f2a85-m/mainboard.c new file mode 100644 index 0000000..266c813 --- /dev/null +++ b/src/mainboard/asus/f2a85-m/mainboard.c @@ -0,0 +1,68 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <console/console.h> +#include <device/device.h> +#include <device/pci.h> +#include <arch/io.h> +#include <cpu/x86/msr.h> +#include "BiosCallOuts.h" +#include <cpu/amd/mtrr.h> +#include <device/pci_def.h> +#include <arch/acpi.h> +#include <cpu/amd/agesa/s3_resume.h> +#include "agesawrapper.h" + +/************************************************* + * enable the dedicated function in thatcher board. + *************************************************/ +static void mainboard_enable(device_t dev) +{ + msr_t msr; + + printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n"); + + msr = rdmsr(0xC0011020); + msr.lo &= ~(1 << 28); + wrmsr(0xC0011020, msr); + + msr = rdmsr(0xC0011022); + msr.lo &= ~(1 << 4); + msr.lo &= ~(1 << 13); + wrmsr(0xC0011022, msr); + + msr = rdmsr(0xC0011023); + msr.lo &= ~(1 << 23); + wrmsr(0xC0011023, msr); + + /* + * The mainboard is the first place that we get control in ramstage. Check + * for S3 resume and call the approriate AGESA/CIMx resume functions. + */ +#if CONFIG_HAVE_ACPI_RESUME + acpi_slp_type = acpi_get_sleep_type(); + if (acpi_slp_type == 3) + agesawrapper_fchs3earlyrestore(); + +#endif +} + +struct chip_operations mainboard_ops = { + .enable_dev = mainboard_enable, +}; diff --git a/src/mainboard/asus/f2a85-m/mptable.c b/src/mainboard/asus/f2a85-m/mptable.c new file mode 100644 index 0000000..5b6136c --- /dev/null +++ b/src/mainboard/asus/f2a85-m/mptable.c @@ -0,0 +1,195 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <console/console.h> +#include <arch/smp/mpspec.h> +#include <device/pci.h> +#include <arch/io.h> +#include <string.h> +#include <stdint.h> +#include <cpu/amd/amdfam15.h> +#include <arch/cpu.h> +#include <cpu/x86/lapic.h> +#include "southbridge/amd/agesa/hudson/hudson.h" + + +//-#define IO_APIC_ID CONFIG_MAX_PHYSICAL_CPUS + 1 +#define IO_APIC_ID CONFIG_MAX_CPUS +extern u8 bus_hudson[3]; + +extern u32 bus_type[256]; +extern u32 sbdn_hudson; +extern u32 apicid_hudson; + +u8 picr_data[] = { + 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x0A,0xF1,0x00,0x00,0x1F,0x1F,0x1F,0x1F, + 0x09,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x1F,0x1F,0x1F,0x1F +}; +u8 intr_data[0x54] = { + 0x10,0x11,0x12,0x13,0x14,0x15,0x16,0x17,0x00,0x00,0x00,0x00,0x1F,0x1F,0x1F,0x1F, + 0x09,0x1F,0x1F,0x10,0x1F,0x10,0x1F,0x10,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x05,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x12,0x11,0x12,0x11,0x12,0x11,0x12,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x11,0x13,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x10,0x11,0x12,0x13 +}; + +static void smp_add_mpc_entry(struct mp_config_table *mc, unsigned length) +{ + mc->mpc_length += length; + mc->mpc_entry_count++; +} + +static void my_smp_write_bus(struct mp_config_table *mc, + unsigned char id, const char *bustype) +{ + struct mpc_config_bus *mpc; + mpc = smp_next_mpc_entry(mc); + memset(mpc, '\0', sizeof(*mpc)); + mpc->mpc_type = MP_BUS; + mpc->mpc_busid = id; + memcpy(mpc->mpc_bustype, bustype, sizeof(mpc->mpc_bustype)); + smp_add_mpc_entry(mc, sizeof(*mpc)); +} + +static void *smp_write_config_table(void *v) +{ + struct mp_config_table *mc; + int bus_isa; + u32 dword; + u8 byte; + + mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); + + mptable_init(mc, LOCAL_APIC_ADDR); + memcpy(mc->mpc_oem, "AMD ", 8); + + smp_write_processors(mc); + + get_bus_conf(); + + //mptable_write_buses(mc, NULL, &bus_isa); + my_smp_write_bus(mc, 0, "PCI "); + my_smp_write_bus(mc, 1, "PCI "); + bus_isa = 0x02; + my_smp_write_bus(mc, bus_isa, "ISA "); + + /* I/O APICs: APIC ID Version State Address */ + + dword = 0; + dword = pm_ioread(0x34) & 0xF0; + dword |= (pm_ioread(0x35) & 0xFF) << 8; + dword |= (pm_ioread(0x36) & 0xFF) << 16; + dword |= (pm_ioread(0x37) & 0xFF) << 24; + /* Set IO APIC ID onto IO_APIC_ID */ + write32 (dword, 0x00); + write32 (dword + 0x10, IO_APIC_ID << 24); + apicid_hudson = IO_APIC_ID; + smp_write_ioapic(mc, apicid_hudson, 0x21, dword); + + /* PIC IRQ routine */ + for (byte = 0x0; byte < sizeof(picr_data); byte ++) { + outb(byte, 0xC00); + outb(picr_data[byte], 0xC01); + } + + /* APIC IRQ routine */ + for (byte = 0x0; byte < sizeof(intr_data); byte ++) { + outb(byte | 0x80, 0xC00); + outb(intr_data[byte], 0xC01); + } + + /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ +#define IO_LOCAL_INT(type, intr, apicid, pin) \ + smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin)); + mptable_add_isa_interrupts(mc, bus_isa, apicid_hudson, 0); + + /* PCI interrupts are level triggered, and are + * associated with a specific bus/device/function tuple. + */ +#define PCI_INT(bus, dev, int_sign, pin) \ + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(int_sign)), apicid_hudson, (pin)) + + /* Internal VGA */ + PCI_INT(0x0, 0x01, 0x0, intr_data[0x02]); + PCI_INT(0x0, 0x01, 0x1, intr_data[0x03]); + + /* SMBUS */ + PCI_INT(0x0, 0x14, 0x0, 0x10); + + /* HD Audio */ + PCI_INT(0x0, 0x14, 0x0, intr_data[0x13]); + + /* USB */ + PCI_INT(0x0, 0x12, 0x0, intr_data[0x30]); + PCI_INT(0x0, 0x12, 0x1, intr_data[0x31]); + PCI_INT(0x0, 0x13, 0x0, intr_data[0x32]); + PCI_INT(0x0, 0x13, 0x1, intr_data[0x33]); + PCI_INT(0x0, 0x16, 0x0, intr_data[0x34]); + PCI_INT(0x0, 0x16, 0x1, intr_data[0x35]); + PCI_INT(0x0, 0x14, 0x2, intr_data[0x36]); + + /* sata */ + PCI_INT(0x0, 0x11, 0x0, intr_data[0x40]); + PCI_INT(0x0, 0x11, 0x0, intr_data[0x41]); + + /* on board NIC & Slot PCIE. */ + + /* PCI slots */ + /* PCI_SLOT 0. */ + PCI_INT(bus_hudson[1], 0x5, 0x0, 0x14); + PCI_INT(bus_hudson[1], 0x5, 0x1, 0x15); + PCI_INT(bus_hudson[1], 0x5, 0x2, 0x16); + PCI_INT(bus_hudson[1], 0x5, 0x3, 0x17); + + PCI_INT(bus_hudson[2], 0x0, 0x0, 0x12); + PCI_INT(bus_hudson[2], 0x0, 0x1, 0x13); + PCI_INT(bus_hudson[2], 0x0, 0x2, 0x14); + + /* PCIe Lan*/ + PCI_INT(0x0, 0x06, 0x0, 0x13); + + /* FCH PCIe PortA */ + PCI_INT(0x0, 0x15, 0x0, 0x10); + /* FCH PCIe PortB */ + PCI_INT(0x0, 0x15, 0x1, 0x11); + /* FCH PCIe PortC */ + PCI_INT(0x0, 0x15, 0x2, 0x12); + /* FCH PCIe PortD */ + PCI_INT(0x0, 0x15, 0x3, 0x13); + + /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ + IO_LOCAL_INT(mp_ExtINT, 0, MP_APIC_ALL, 0x0); + IO_LOCAL_INT(mp_NMI, 0, MP_APIC_ALL, 0x1); + /* There is no extension information... */ + + /* Compute the checksums */ + return mptable_finalize(mc); +} + +unsigned long write_smp_table(unsigned long addr) +{ + void *v; + v = smp_write_floating_table(addr, 0); + return (unsigned long)smp_write_config_table(v); +} diff --git a/src/mainboard/asus/f2a85-m/pmio.h b/src/mainboard/asus/f2a85-m/pmio.h new file mode 100644 index 0000000..35751f5 --- /dev/null +++ b/src/mainboard/asus/f2a85-m/pmio.h @@ -0,0 +1,33 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef _PMIO_H_ +#define _PMIO_H_ + +#define PM_INDEX 0xCD6 +#define PM_DATA 0xCD7 +#define PM2_INDEX 0xCD0 +#define PM2_DATA 0xCD1 + +void pm_iowrite(u8 reg, u8 value); +u8 pm_ioread(u8 reg); +void pm2_iowrite(u8 reg, u8 value); +u8 pm2_ioread(u8 reg); + +#endif diff --git a/src/mainboard/asus/f2a85-m/romstage.c b/src/mainboard/asus/f2a85-m/romstage.c new file mode 100644 index 0000000..8d35f8d --- /dev/null +++ b/src/mainboard/asus/f2a85-m/romstage.c @@ -0,0 +1,206 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * Copyright (C) 2012 Rudolf Marek <r.marek(a)assembler.cz> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <stdint.h> +#include <string.h> +#include <device/pci_def.h> +#include <device/pci_ids.h> +#include <arch/io.h> +#include <arch/stages.h> +#include <device/pnp_def.h> +#include <arch/romcc_io.h> +#include <arch/cpu.h> +#include <cpu/x86/lapic.h> +#include <console/console.h> +#include <console/loglevel.h> +#include "agesawrapper.h" +#include "cpu/x86/bist.h" +#include "cpu/x86/lapic/boot_cpu.c" +#include "southbridge/amd/agesa/hudson/hudson.h" +#include "southbridge/amd/agesa/hudson/smbus.h" +#include "superio/ite/it8712f/early_serial.c" +#include "cpu/amd/agesa/s3_resume.h" +#include "src/drivers/pc80/i8254.c" +#include "src/drivers/pc80/i8259.c" +#include "cbmem.h" + +void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx); +void disable_cache_as_ram(void); + +#define MMIO_NON_POSTED_START 0xfed00000 +#define MMIO_NON_POSTED_END 0xfedfffff +#define SB_MMIO 0xFED80000 +#define SB_MMIO_MISC32(x) *(volatile u32 *)(SB_MMIO + 0xE00 + (x)) + +static void sbxxx_enable_48mhzout(void) +{ + /* most likely programming to 48MHz out signal */ + u32 reg32; + reg32 = SB_MMIO_MISC32(0x28); + reg32 &= 0xffc7ffff; + reg32 |= 0x00100000; + SB_MMIO_MISC32(0x28) = reg32; + + reg32 = SB_MMIO_MISC32(0x40); + reg32 &= ~0x80u; + SB_MMIO_MISC32(0x40) = reg32; +} + +void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) +{ + u32 val; + u8 byte; + device_t dev; +#if CONFIG_HAVE_ACPI_RESUME + void *resume_backup_memory; +#endif + val = agesawrapper_amdinitmmio(); + + if (!cpu_init_detectedx && boot_cpu()) { + + /* enable SIO decode */ + dev = PCI_DEV(0, 0x14, 3); + byte = pci_read_config8(dev, 0x48); + byte |= 3; /* 2e, 2f */ + pci_write_config8(dev, 0x48, byte); + + post_code(0x30); + + /* enable SB MMIO space */ + outb(0x24, 0xcd6); + outb(0x1, 0xcd7); + + /* enable SIO clock */ + sbxxx_enable_48mhzout(); + it8712f_kill_watchdog(); + it8712f_enable_serial(0, CONFIG_TTYS0_BASE); + console_init(); + + /* turn on secondary smbus at b20 */ + outb(0x28, 0xcd6); + byte = inb(0xcd7); + byte |= 1; + outb(byte, 0xcd7); + + /* set DDR3 voltage */ + byte = CONFIG_BOARD_ASUS_F2A85_M_DDR3_VOLT_VAL; + + if (!byte) + do_smbus_write_byte(0xb20, 0x15, 0x3, byte); + } + + /* Halt if there was a built in self test failure */ + post_code(0x34); + report_bist_failure(bist); + + /* Load MPB */ + val = cpuid_eax(1); + printk(BIOS_DEBUG, "BSP Family_Model: %08x \n", val); + printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx \n", cpu_init_detectedx); + + post_code(0x37); + printk(BIOS_DEBUG, "agesawrapper_amdinitreset "); + val = agesawrapper_amdinitreset(); + if(val) { + printk(BIOS_DEBUG, "agesawrapper_amdinitreset failed: %x \n", val); + } + + post_code(0x39); + + val = agesawrapper_amdinitearly (); + if(val) { + printk(BIOS_DEBUG, "agesawrapper_amdinitearly failed: %x \n", val); + } + printk(BIOS_DEBUG, "Got past agesawrapper_amdinitearly\n"); + +#if CONFIG_HAVE_ACPI_RESUME + if (!acpi_is_wakeup_early()) { /* Check for S3 resume */ +#endif + post_code(0x40); + val = agesawrapper_amdinitpost (); + if(val) { + printk(BIOS_DEBUG, "agesawrapper_amdinitpost failed: %x \n", val); + } + printk(BIOS_DEBUG, "Got past agesawrapper_amdinitpost\n"); + + post_code(0x41); + val = agesawrapper_amdinitenv (); + if(val) { + printk(BIOS_DEBUG, "agesawrapper_amdinitenv failed: %x \n", val); + } + printk(BIOS_DEBUG, "Got past agesawrapper_amdinitenv\n"); + disable_cache_as_ram(); +#if CONFIG_HAVE_ACPI_RESUME + } else { /* S3 detect */ + printk(BIOS_INFO, "S3 detected\n"); + + post_code(0x60); + printk(BIOS_DEBUG, "agesawrapper_amdinitresume "); + val = agesawrapper_amdinitresume(); + if (val) + printk(BIOS_DEBUG, "error level: %x \n", val); + else + printk(BIOS_DEBUG, "passed.\n"); + + printk(BIOS_DEBUG, "agesawrapper_amds3laterestore "); + val = agesawrapper_amds3laterestore (); + if (val) + printk(BIOS_DEBUG, "error level: %x \n", val); + else + printk(BIOS_DEBUG, "passed.\n"); + + post_code(0x61); + printk(BIOS_DEBUG, "Find resume memory location\n"); + resume_backup_memory = (void *)backup_resume(); + + post_code(0x62); + printk(BIOS_DEBUG, "Move CAR stack.\n"); + move_stack_high_mem(); + printk(BIOS_DEBUG, "stack moved to: 0x%x\n", (u32) (resume_backup_memory + HIGH_MEMORY_SAVE)); + + post_code(0x63); + disable_cache_as_ram(); + printk(BIOS_DEBUG, "CAR disabled.\n"); + set_resume_cache(); + + /* + * Copy the system memory that is in the ramstage area to the + * reserved area. + */ + if (resume_backup_memory) + memcpy(resume_backup_memory, (void *)(CONFIG_RAMBASE), HIGH_MEMORY_SAVE); + + printk(BIOS_DEBUG, "System memory saved. OK to load ramstage.\n"); + } +#endif + + /* Initialize i8259 pic */ + post_code(0x41); + setup_i8259 (); + + /* Initialize i8254 timers */ + post_code(0x42); + setup_i8254 (); + + post_code(0x50); + copy_and_run(0); + + post_code(0x54); /* Should never see this post code. */ +}

1 0

New patch to review for coreboot: 6275503 Fix race condition building console code
by Stefan Reinauer March 21, 2013

March 21, 2013

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2873 -gerrit commit 6275503a7f43e697ccd6970fc8afa5ba83c3ecc2 Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Thu Mar 21 13:15:45 2013 -0700 Fix race condition building console code On ARMv7 the console code can also be built into the bootblock. Currently building the ARM targets on a reasonably fast machine can fail, because console.bootblock.o is attempted to build before build.h is created. This patch adds a specific rule for the bootblock variant of console.c, to match the other variants so that the race condition goes away. Change-Id: I52e4242c66a02f011ef26b854aa50c2606a1f81f Signed-off-by: Stefan Reinauer <reinauer(a)google.com> --- src/console/Makefile.inc | 1 + 1 file changed, 1 insertion(+) diff --git a/src/console/Makefile.inc b/src/console/Makefile.inc index 9499180..40bf357 100644 --- a/src/console/Makefile.inc +++ b/src/console/Makefile.inc @@ -28,3 +28,4 @@ ramstage-$(CONFIG_CONSOLE_CBMEM) += cbmem_console.c $(obj)/console/console.ramstage.o : $(obj)/build.h $(obj)/console/console.romstage.o : $(obj)/build.h +$(obj)/console/console.bootblock.o : $(obj)/build.h

1 0

New patch to review for coreboot: 95caa06 x86: Unify arch/io.h and arch/romcc_io.h
by Stefan Reinauer March 21, 2013

March 21, 2013

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2872 -gerrit commit 95caa06a5a6193563a4e0b6b90fdd24eb38d68eb Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Thu Mar 21 11:51:41 2013 -0700 x86: Unify arch/io.h and arch/romcc_io.h Here's the great news: From now on you don't have to worry about hitting the right io.h include anymore. Just forget about romcc_io.h and use io.h instead. This cleanup has a number of advantages, like you don't have to guard device/ includes for SMM and pre RAM anymore. This allows to get rid of a number of ifdefs and will generally make the code more readable and understandable. Potentially in the future some of the code in the io.h __PRE_RAM__ path should move to device.h or other device/ includes instead, but that's another incremental change. Change-Id: I356f06110e2e355e9a5b4b08c132591f36fec7d9 Signed-off-by: Stefan Reinauer <reinauer(a)google.com> --- src/arch/x86/include/arch/cpu.h | 3 +- src/arch/x86/include/arch/io.h | 343 ++++++++++++++++++++ src/arch/x86/include/arch/romcc_io.h | 350 --------------------- src/cpu/intel/haswell/bootblock.c | 1 - src/cpu/intel/haswell/romstage.c | 1 - src/cpu/intel/model_206ax/bootblock.c | 1 - src/cpu/x86/smm/smihandler.c | 1 - src/cpu/x86/smm/smiutil.c | 1 - src/cpu/x86/smm/smm_module_handler.c | 1 - src/drivers/oxford/oxpcie/oxpcie_early.c | 1 - src/ec/acpi/ec.c | 2 + src/ec/google/chromeec/ec.c | 5 +- src/ec/quanta/ene_kb3940q/ec.c | 2 +- src/ec/smsc/mec1308/ec.c | 2 + src/include/cpu/cpu.h | 4 +- src/include/device/device.h | 4 + src/include/device/pci.h | 2 +- src/include/device/pci_ops.h | 2 + src/include/device/pnp.h | 2 + src/include/lib.h | 2 +- src/lib/ne2k.c | 3 - src/mainboard/a-trend/atc-6220/romstage.c | 1 - src/mainboard/a-trend/atc-6240/romstage.c | 1 - src/mainboard/abit/be6-ii_v2_0/romstage.c | 1 - src/mainboard/advansus/a785e-i/reset.c | 6 +- src/mainboard/advansus/a785e-i/romstage.c | 1 - src/mainboard/advantech/pcm-5820/romstage.c | 1 - src/mainboard/amd/bimini_fam10/romstage.c | 1 - src/mainboard/amd/dbm690t/romstage.c | 1 - src/mainboard/amd/dinar/reset.c | 7 +- src/mainboard/amd/dinar/romstage.c | 1 - src/mainboard/amd/inagua/reset.c | 7 +- src/mainboard/amd/inagua/romstage.c | 1 - src/mainboard/amd/mahogany/romstage.c | 1 - src/mainboard/amd/mahogany_fam10/romstage.c | 1 - src/mainboard/amd/parmer/romstage.c | 1 - src/mainboard/amd/persimmon/reset.c | 7 +- src/mainboard/amd/persimmon/romstage.c | 1 - src/mainboard/amd/pistachio/romstage.c | 1 - src/mainboard/amd/serengeti_cheetah/ap_romstage.c | 1 - src/mainboard/amd/serengeti_cheetah/romstage.c | 1 - .../amd/serengeti_cheetah_fam10/romstage.c | 1 - src/mainboard/amd/south_station/reset.c | 7 +- src/mainboard/amd/south_station/romstage.c | 1 - src/mainboard/amd/thatcher/romstage.c | 1 - src/mainboard/amd/tilapia_fam10/romstage.c | 1 - src/mainboard/amd/torpedo/reset.c | 7 +- src/mainboard/amd/torpedo/romstage.c | 1 - src/mainboard/amd/union_station/reset.c | 7 +- src/mainboard/amd/union_station/romstage.c | 1 - src/mainboard/aopen/dxplplusu/romstage.c | 1 - src/mainboard/arima/hdama/romstage.c | 1 - src/mainboard/artecgroup/dbe61/romstage.c | 1 - src/mainboard/asi/mb_5blgp/romstage.c | 1 - src/mainboard/asi/mb_5blmp/romstage.c | 1 - src/mainboard/asrock/939a785gmh/romstage.c | 1 - src/mainboard/asrock/e350m1/reset.c | 7 +- src/mainboard/asrock/e350m1/romstage.c | 1 - src/mainboard/asus/a8n_e/romstage.c | 1 - src/mainboard/asus/a8v-e_deluxe/romstage.c | 1 - src/mainboard/asus/a8v-e_se/romstage.c | 1 - src/mainboard/asus/dsbf/romstage.c | 1 - src/mainboard/asus/k8v-x/romstage.c | 1 - src/mainboard/asus/m2n-e/romstage.c | 1 - src/mainboard/asus/m2v-mx_se/romstage.c | 1 - src/mainboard/asus/m2v/romstage.c | 1 - src/mainboard/asus/m4a78-em/romstage.c | 1 - src/mainboard/asus/m4a785-m/romstage.c | 1 - src/mainboard/asus/m5a88-v/reset.c | 6 +- src/mainboard/asus/m5a88-v/romstage.c | 1 - src/mainboard/asus/p2b-d/romstage.c | 1 - src/mainboard/asus/p2b-ds/romstage.c | 1 - src/mainboard/asus/p2b-f/romstage.c | 1 - src/mainboard/asus/p2b-ls/romstage.c | 1 - src/mainboard/asus/p2b/romstage.c | 1 - src/mainboard/asus/p3b-f/romstage.c | 1 - src/mainboard/avalue/eax-785e/reset.c | 6 +- src/mainboard/avalue/eax-785e/romstage.c | 1 - src/mainboard/axus/tc320/romstage.c | 1 - src/mainboard/azza/pt-6ibd/romstage.c | 1 - src/mainboard/bcom/winnet100/romstage.c | 1 - src/mainboard/bcom/winnetp680/romstage.c | 1 - src/mainboard/bifferos/bifferboard/romstage.c | 1 - src/mainboard/biostar/m6tba/romstage.c | 1 - src/mainboard/broadcom/blast/romstage.c | 1 - .../compaq/deskpro_en_sff_p600/romstage.c | 1 - src/mainboard/digitallogic/adl855pc/romstage.c | 1 - src/mainboard/digitallogic/msm586seg/romstage.c | 1 - src/mainboard/digitallogic/msm800sev/romstage.c | 1 - src/mainboard/eaglelion/5bcm/romstage.c | 1 - src/mainboard/emulation/qemu-x86/romstage.c | 1 - src/mainboard/getac/p470/romstage.c | 1 - src/mainboard/getac/p470/smihandler.c | 1 - src/mainboard/gigabyte/ga-6bxc/romstage.c | 1 - src/mainboard/gigabyte/ga-6bxe/romstage.c | 1 - src/mainboard/gigabyte/ga_2761gxdk/ap_romstage.c | 1 - src/mainboard/gigabyte/ga_2761gxdk/romstage.c | 1 - src/mainboard/gigabyte/m57sli/ap_romstage.c | 1 - src/mainboard/gigabyte/m57sli/romstage.c | 1 - src/mainboard/gigabyte/ma785gm/romstage.c | 1 - src/mainboard/gigabyte/ma785gmt/romstage.c | 1 - src/mainboard/gigabyte/ma78gm/romstage.c | 1 - src/mainboard/google/butterfly/chromeos.c | 4 - src/mainboard/google/butterfly/mainboard_smi.c | 1 - src/mainboard/google/butterfly/romstage.c | 1 - src/mainboard/google/link/chromeos.c | 4 - src/mainboard/google/link/mainboard_smi.c | 1 - src/mainboard/google/link/romstage.c | 1 - src/mainboard/google/parrot/chromeos.c | 5 - src/mainboard/google/parrot/romstage.c | 1 - src/mainboard/google/parrot/smihandler.c | 1 - src/mainboard/google/stout/chromeos.c | 4 - src/mainboard/google/stout/mainboard_smi.c | 1 - src/mainboard/google/stout/romstage.c | 1 - src/mainboard/hp/dl145_g1/romstage.c | 1 - src/mainboard/hp/dl145_g3/romstage.c | 1 - src/mainboard/hp/dl165_g6_fam10/romstage.c | 1 - src/mainboard/hp/e_vectra_p2706t/romstage.c | 1 - src/mainboard/ibase/mb899/romstage.c | 1 - src/mainboard/ibase/mb899/smihandler.c | 1 - src/mainboard/ibm/e325/romstage.c | 1 - src/mainboard/ibm/e326/romstage.c | 1 - src/mainboard/iei/juki-511p/romstage.c | 1 - src/mainboard/iei/kino-780am2-fam10/romstage.c | 1 - src/mainboard/iei/nova4899r/romstage.c | 1 - src/mainboard/intel/baskingridge/chromeos.c | 4 - src/mainboard/intel/baskingridge/mainboard_smi.c | 1 - src/mainboard/intel/d945gclf/romstage.c | 1 - src/mainboard/intel/d945gclf/smihandler.c | 1 - src/mainboard/intel/eagleheights/romstage.c | 1 - src/mainboard/intel/emeraldlake2/chromeos.c | 4 - src/mainboard/intel/emeraldlake2/romstage.c | 1 - src/mainboard/intel/emeraldlake2/smihandler.c | 1 - src/mainboard/intel/jarrell/jarrell_fixups.c | 2 +- src/mainboard/intel/jarrell/romstage.c | 1 - src/mainboard/intel/mtarvon/romstage.c | 1 - src/mainboard/intel/truxton/romstage.c | 1 - src/mainboard/intel/wtm1/chromeos.c | 4 - src/mainboard/intel/wtm1/mainboard_smi.c | 1 - src/mainboard/intel/wtm2/chromeos.c | 4 - src/mainboard/intel/wtm2/mainboard_smi.c | 1 - src/mainboard/intel/xe7501devkit/romstage.c | 1 - src/mainboard/iwave/iWRainbowG6/romstage.c | 1 - src/mainboard/iwave/iWRainbowG6/smihandler.c | 1 - src/mainboard/iwill/dk8_htx/romstage.c | 1 - src/mainboard/iwill/dk8s2/romstage.c | 1 - src/mainboard/iwill/dk8x/romstage.c | 1 - src/mainboard/jetway/j7f24/romstage.c | 1 - src/mainboard/jetway/pa78vm5/romstage.c | 1 - src/mainboard/kontron/986lcd-m/romstage.c | 1 - src/mainboard/kontron/986lcd-m/smihandler.c | 1 - src/mainboard/kontron/kt690/romstage.c | 1 - src/mainboard/lanner/em8510/romstage.c | 1 - src/mainboard/lenovo/t60/dock.c | 1 - src/mainboard/lenovo/t60/romstage.c | 1 - src/mainboard/lenovo/t60/smihandler.c | 1 - src/mainboard/lenovo/x60/romstage.c | 1 - src/mainboard/lenovo/x60/smihandler.c | 1 - src/mainboard/lippert/frontrunner-af/reset.c | 7 +- src/mainboard/lippert/frontrunner-af/romstage.c | 1 - src/mainboard/lippert/toucan-af/reset.c | 7 +- src/mainboard/lippert/toucan-af/romstage.c | 1 - src/mainboard/msi/ms6119/romstage.c | 1 - src/mainboard/msi/ms6147/romstage.c | 1 - src/mainboard/msi/ms6156/romstage.c | 1 - src/mainboard/msi/ms7135/romstage.c | 1 - src/mainboard/msi/ms7260/ap_romstage.c | 1 - src/mainboard/msi/ms7260/romstage.c | 1 - src/mainboard/msi/ms9185/romstage.c | 1 - src/mainboard/msi/ms9282/romstage.c | 1 - src/mainboard/msi/ms9652_fam10/romstage.c | 1 - src/mainboard/newisys/khepri/romstage.c | 1 - src/mainboard/nokia/ip530/romstage.c | 1 - src/mainboard/nvidia/l1_2pvv/ap_romstage.c | 1 - src/mainboard/nvidia/l1_2pvv/romstage.c | 1 - src/mainboard/pcengines/alix1c/romstage.c | 1 - src/mainboard/pcengines/alix2d/romstage.c | 1 - src/mainboard/rca/rm4100/romstage.c | 1 - src/mainboard/rca/rm4100/smihandler.c | 1 - src/mainboard/roda/rk886ex/romstage.c | 1 - src/mainboard/roda/rk886ex/smihandler.c | 1 - src/mainboard/roda/rk9/romstage.c | 1 - src/mainboard/roda/rk9/smihandler.c | 1 - src/mainboard/samsung/lumpy/chromeos.c | 4 - src/mainboard/samsung/lumpy/romstage.c | 1 - src/mainboard/samsung/lumpy/smihandler.c | 1 - src/mainboard/samsung/stumpy/chromeos.c | 4 - src/mainboard/samsung/stumpy/romstage.c | 1 - src/mainboard/samsung/stumpy/smihandler.c | 1 - src/mainboard/siemens/sitemp_g1p1/romstage.c | 1 - src/mainboard/soyo/sy-6ba-plus-iii/romstage.c | 1 - src/mainboard/sunw/ultra40/romstage.c | 1 - src/mainboard/supermicro/h8dme/ap_romstage.c | 1 - src/mainboard/supermicro/h8dme/romstage.c | 1 - src/mainboard/supermicro/h8dmr/ap_romstage.c | 1 - src/mainboard/supermicro/h8dmr/romstage.c | 1 - src/mainboard/supermicro/h8dmr_fam10/romstage.c | 1 - src/mainboard/supermicro/h8qgi/BiosCallOuts.c | 1 - src/mainboard/supermicro/h8qgi/reset.c | 7 +- src/mainboard/supermicro/h8qgi/romstage.c | 1 - src/mainboard/supermicro/h8qme_fam10/romstage.c | 1 - src/mainboard/supermicro/h8scm/reset.c | 7 +- src/mainboard/supermicro/h8scm/romstage.c | 1 - src/mainboard/supermicro/h8scm_fam10/romstage.c | 1 - src/mainboard/supermicro/x6dai_g/romstage.c | 1 - src/mainboard/supermicro/x6dhe_g/romstage.c | 1 - src/mainboard/supermicro/x6dhe_g2/romstage.c | 1 - src/mainboard/supermicro/x6dhr_ig/romstage.c | 1 - src/mainboard/supermicro/x6dhr_ig2/romstage.c | 1 - src/mainboard/supermicro/x7db8/romstage.c | 1 - src/mainboard/technexion/tim5690/romstage.c | 1 - src/mainboard/technexion/tim8690/romstage.c | 1 - src/mainboard/technologic/ts5300/romstage.c | 1 - src/mainboard/televideo/tc7020/romstage.c | 1 - src/mainboard/thomson/ip1000/romstage.c | 1 - src/mainboard/thomson/ip1000/smihandler.c | 1 - src/mainboard/tyan/s1846/romstage.c | 1 - src/mainboard/tyan/s2735/romstage.c | 1 - src/mainboard/tyan/s2850/romstage.c | 1 - src/mainboard/tyan/s2875/romstage.c | 1 - src/mainboard/tyan/s2880/romstage.c | 1 - src/mainboard/tyan/s2881/romstage.c | 1 - src/mainboard/tyan/s2882/romstage.c | 1 - src/mainboard/tyan/s2885/romstage.c | 1 - src/mainboard/tyan/s2891/romstage.c | 1 - src/mainboard/tyan/s2892/romstage.c | 1 - src/mainboard/tyan/s2895/romstage.c | 1 - src/mainboard/tyan/s2912/ap_romstage.c | 1 - src/mainboard/tyan/s2912/romstage.c | 1 - src/mainboard/tyan/s2912_fam10/romstage.c | 1 - src/mainboard/tyan/s4880/romstage.c | 1 - src/mainboard/tyan/s4882/romstage.c | 1 - src/mainboard/tyan/s8226/BiosCallOuts.c | 1 - src/mainboard/tyan/s8226/reset.c | 7 +- src/mainboard/tyan/s8226/romstage.c | 1 - src/mainboard/via/epia-cn/romstage.c | 1 - src/mainboard/via/epia-m/romstage.c | 1 - src/mainboard/via/epia-m700/romstage.c | 1 - src/mainboard/via/epia-n/romstage.c | 1 - src/mainboard/via/epia/romstage.c | 1 - src/mainboard/via/pc2500e/romstage.c | 1 - src/mainboard/via/vt8454c/romstage.c | 1 - src/northbridge/amd/amdfam10/bootblock.c | 1 - src/northbridge/amd/amdk8/bootblock.c | 1 - src/northbridge/amd/amdk8/coherent_ht.c | 2 +- src/northbridge/intel/e7505/debug.c | 1 - src/northbridge/intel/e7505/raminit.c | 1 - src/northbridge/intel/gm45/early_init.c | 1 - src/northbridge/intel/gm45/early_reset.c | 1 - src/northbridge/intel/gm45/igd.c | 1 - src/northbridge/intel/gm45/iommu.c | 1 - src/northbridge/intel/gm45/pcie.c | 1 - src/northbridge/intel/gm45/pm.c | 1 - src/northbridge/intel/gm45/ram_calc.c | 4 +- src/northbridge/intel/gm45/raminit.c | 1 - src/northbridge/intel/gm45/thermal.c | 1 - src/northbridge/intel/haswell/bootblock.c | 1 - src/northbridge/intel/haswell/early_init.c | 1 - src/northbridge/intel/haswell/finalize.c | 1 - src/northbridge/intel/haswell/raminit.c | 1 - src/northbridge/intel/haswell/report_platform.c | 2 - src/northbridge/intel/i440bx/debug.c | 1 - src/northbridge/intel/i440bx/raminit.c | 1 - src/northbridge/intel/i5000/raminit.c | 1 - src/northbridge/intel/i5000/raminit.h | 1 - src/northbridge/intel/i82810/debug.c | 1 - src/northbridge/intel/i82810/raminit.c | 1 - src/northbridge/intel/i82830/smihandler.c | 1 - src/northbridge/intel/i945/debug.c | 1 - src/northbridge/intel/i945/early_init.c | 1 - src/northbridge/intel/i945/raminit.c | 2 +- src/northbridge/intel/sandybridge/early_init.c | 1 - src/northbridge/intel/sandybridge/finalize.c | 1 - src/northbridge/intel/sandybridge/raminit.c | 1 - .../intel/sandybridge/report_platform.c | 1 - src/northbridge/intel/sch/port_access.c | 4 +- src/northbridge/via/cx700/early_serial.c | 2 +- src/northbridge/via/vx800/early_serial.c | 2 +- src/northbridge/via/vx800/examples/romstage.c | 1 - src/northbridge/via/vx800/pci_rawops.h | 2 +- src/southbridge/amd/agesa/hudson/bootblock.c | 1 - src/southbridge/amd/agesa/hudson/early_setup.c | 3 +- src/southbridge/amd/agesa/hudson/enable_usbdebug.c | 1 - src/southbridge/amd/agesa/hudson/reset.c | 8 +- src/southbridge/amd/amd8111/bootblock.c | 1 - src/southbridge/amd/cimx/sb700/bootblock.c | 2 - src/southbridge/amd/cimx/sb700/early.c | 6 +- src/southbridge/amd/cimx/sb800/bootblock.c | 1 - src/southbridge/amd/cimx/sb800/early.c | 4 - src/southbridge/amd/cimx/sb900/bootblock.c | 3 - src/southbridge/amd/cimx/sb900/early.c | 43 ++- src/southbridge/amd/sb600/bootblock.c | 1 - src/southbridge/amd/sb600/enable_usbdebug.c | 1 - src/southbridge/amd/sb600/reset.c | 6 +- src/southbridge/amd/sb700/bootblock.c | 1 - src/southbridge/amd/sb700/early_setup.c | 2 - src/southbridge/amd/sb700/enable_usbdebug.c | 1 - src/southbridge/amd/sb700/reset.c | 8 +- src/southbridge/amd/sb800/bootblock.c | 1 - src/southbridge/amd/sb800/enable_usbdebug.c | 1 - src/southbridge/amd/sb800/reset.c | 8 +- src/southbridge/amd/sr5650/early_setup.c | 1 - src/southbridge/broadcom/bcm5785/bootblock.c | 1 - src/southbridge/intel/bd82x6x/bootblock.c | 1 - src/southbridge/intel/bd82x6x/early_me.c | 1 - src/southbridge/intel/bd82x6x/early_smbus.c | 1 - src/southbridge/intel/bd82x6x/early_spi.c | 1 - src/southbridge/intel/bd82x6x/early_usb.c | 1 - src/southbridge/intel/bd82x6x/finalize.c | 1 - src/southbridge/intel/bd82x6x/gpio.c | 1 - src/southbridge/intel/bd82x6x/me.c | 1 - src/southbridge/intel/bd82x6x/me_8.x.c | 1 - src/southbridge/intel/bd82x6x/pch.c | 1 - src/southbridge/intel/bd82x6x/smihandler.c | 1 - src/southbridge/intel/bd82x6x/spi.c | 1 - src/southbridge/intel/bd82x6x/usb_debug.c | 1 - src/southbridge/intel/i82371eb/bootblock.c | 1 - src/southbridge/intel/i82371eb/early_pm.c | 1 - src/southbridge/intel/i82371eb/early_smbus.c | 1 - src/southbridge/intel/i82801ax/early_smbus.c | 1 - src/southbridge/intel/i82801bx/early_smbus.c | 1 - src/southbridge/intel/i82801dx/early_smbus.c | 1 - src/southbridge/intel/i82801dx/smihandler.c | 1 - src/southbridge/intel/i82801gx/bootblock.c | 1 - src/southbridge/intel/i82801gx/early_smbus.c | 1 - src/southbridge/intel/i82801gx/smihandler.c | 1 - src/southbridge/intel/i82801gx/usb_debug.c | 4 +- src/southbridge/intel/i82801ix/bootblock.c | 1 - src/southbridge/intel/i82801ix/dmi_setup.c | 1 - src/southbridge/intel/i82801ix/early_init.c | 1 - src/southbridge/intel/i82801ix/early_smbus.c | 1 - src/southbridge/intel/i82801ix/smihandler.c | 1 - src/southbridge/intel/lynxpoint/bootblock.c | 1 - src/southbridge/intel/lynxpoint/early_me.c | 1 - src/southbridge/intel/lynxpoint/early_pch.c | 1 - src/southbridge/intel/lynxpoint/early_smbus.c | 1 - src/southbridge/intel/lynxpoint/early_spi.c | 1 - src/southbridge/intel/lynxpoint/early_usb.c | 1 - src/southbridge/intel/lynxpoint/finalize.c | 1 - src/southbridge/intel/lynxpoint/gpio.c | 6 - src/southbridge/intel/lynxpoint/lp_gpio.c | 4 - src/southbridge/intel/lynxpoint/me_9.x.c | 9 +- src/southbridge/intel/lynxpoint/smihandler.c | 1 - src/southbridge/intel/lynxpoint/spi.c | 1 - src/southbridge/intel/lynxpoint/usb_debug.c | 1 - src/southbridge/intel/sch/early_smbus.c | 1 - src/southbridge/intel/sch/smihandler.c | 1 - src/southbridge/intel/sch/usb_debug.c | 1 - src/southbridge/nvidia/ck804/bootblock.c | 1 - src/southbridge/nvidia/ck804/early_smbus.c | 1 - src/southbridge/nvidia/ck804/enable_usbdebug.c | 1 - src/southbridge/nvidia/mcp55/bootblock.c | 1 - src/southbridge/nvidia/mcp55/enable_usbdebug.c | 1 - src/southbridge/rdc/r8610/bootblock.c | 1 - src/southbridge/sis/sis966/bootblock.c | 1 - src/southbridge/sis/sis966/enable_usbdebug.c | 1 - src/southbridge/via/vt8231/enable_rom.c | 1 - src/southbridge/via/vt8237r/bootblock.c | 1 - src/southbridge/via/vt8237r/smihandler.c | 1 - src/southbridge/via/vt82c686/early_serial.c | 2 +- src/superio/fintek/f71805f/early_serial.c | 2 +- src/superio/fintek/f71859/early_serial.c | 2 +- src/superio/fintek/f71863fg/early_serial.c | 2 +- src/superio/fintek/f71872/early_serial.c | 2 +- src/superio/fintek/f71889/early_serial.c | 2 +- src/superio/fintek/f81865f/f81865f_early_serial.c | 2 +- src/superio/intel/i3100/early_serial.c | 2 +- src/superio/ite/it8661f/early_serial.c | 2 +- src/superio/ite/it8671f/early_serial.c | 2 +- src/superio/ite/it8673f/early_serial.c | 2 +- src/superio/ite/it8705f/early_serial.c | 2 +- src/superio/ite/it8712f/early_serial.c | 2 +- src/superio/ite/it8716f/early_init.c | 2 +- src/superio/ite/it8716f/early_serial.c | 2 +- src/superio/ite/it8718f/early_serial.c | 2 +- src/superio/ite/it8721f/early_serial.c | 2 +- src/superio/ite/it8772f/early_serial.c | 2 +- src/superio/nsc/pc8374/early_init.c | 2 +- src/superio/nsc/pc87309/early_serial.c | 2 +- src/superio/nsc/pc87351/early_serial.c | 2 +- src/superio/nsc/pc87360/early_serial.c | 2 +- src/superio/nsc/pc87366/early_serial.c | 2 +- src/superio/nsc/pc87392/early_serial.c | 2 +- src/superio/nsc/pc87417/early_init.c | 2 +- src/superio/nsc/pc87417/early_serial.c | 2 +- src/superio/nsc/pc87427/early_init.c | 2 +- src/superio/nsc/pc97317/early_serial.c | 2 +- src/superio/nuvoton/wpcm450/early_init.c | 1 - src/superio/serverengines/pilot/early_serial.c | 2 +- src/superio/smsc/fdc37m60x/early_serial.c | 2 +- src/superio/smsc/kbc1100/kbc1100_early_init.c | 2 +- src/superio/smsc/lpc47b272/early_serial.c | 2 +- src/superio/smsc/lpc47b397/early_serial.c | 2 +- src/superio/smsc/lpc47m10x/early_serial.c | 2 +- src/superio/smsc/lpc47m15x/early_serial.c | 2 +- src/superio/smsc/lpc47n217/early_serial.c | 2 +- src/superio/smsc/lpc47n227/early_serial.c | 2 +- src/superio/smsc/sch4037/sch4037_early_init.c | 2 +- src/superio/smsc/sio1036/sio1036_early_init.c | 2 +- src/superio/smsc/smscsuperio/early_serial.c | 2 +- src/superio/winbond/w83627dhg/early_serial.c | 1 - src/superio/winbond/w83627ehg/early_init.c | 2 +- src/superio/winbond/w83627ehg/early_serial.c | 2 +- src/superio/winbond/w83627hf/early_init.c | 2 +- src/superio/winbond/w83627hf/early_serial.c | 2 +- src/superio/winbond/w83627thg/early_serial.c | 2 +- src/superio/winbond/w83627uhg/early_serial.c | 3 +- src/superio/winbond/w83697hf/early_serial.c | 3 +- src/superio/winbond/w83977f/early_serial.c | 2 +- src/superio/winbond/w83977tf/early_serial.c | 2 +- 410 files changed, 529 insertions(+), 876 deletions(-) diff --git a/src/arch/x86/include/arch/cpu.h b/src/arch/x86/include/arch/cpu.h index ed8148e..a3555d8 100644 --- a/src/arch/x86/include/arch/cpu.h +++ b/src/arch/x86/include/arch/cpu.h @@ -141,7 +141,7 @@ static inline unsigned int cpuid_edx(unsigned int op) #define X86_VENDOR_UNKNOWN 0xff #if !defined(__ROMCC__) -#if !defined(__PRE_RAM__) +#if !defined(__PRE_RAM__) && !defined(__SMM__) #include <device/device.h> int cpu_phys_address_size(void); @@ -162,7 +162,6 @@ struct device; struct cpu_driver *find_cpu_driver(struct device *cpu); #else #include <arch/io.h> -#include <arch/romcc_io.h> #endif struct cpu_info { diff --git a/src/arch/x86/include/arch/io.h b/src/arch/x86/include/arch/io.h index f4c6967..29c8339 100644 --- a/src/arch/x86/include/arch/io.h +++ b/src/arch/x86/include/arch/io.h @@ -163,5 +163,348 @@ static inline __attribute__((always_inline)) void write32(unsigned long addr, ui *((volatile uint32_t *)(addr)) = value; } +#if defined(__PRE_RAM__) || defined(__SMM__) +static inline int log2(int value) +{ + unsigned int r = 0; + __asm__ volatile ( + "bsrl %1, %0\n\t" + "jnz 1f\n\t" + "movl $-1, %0\n\t" + "1:\n\t" + : "=r" (r) : "r" (value)); + return r; + +} +static inline int log2f(int value) +{ + unsigned int r = 0; + __asm__ volatile ( + "bsfl %1, %0\n\t" + "jnz 1f\n\t" + "movl $-1, %0\n\t" + "1:\n\t" + : "=r" (r) : "r" (value)); + return r; + +} + +#define PCI_ADDR(SEGBUS, DEV, FN, WHERE) ( \ + (((SEGBUS) & 0xFFF) << 20) | \ + (((DEV) & 0x1F) << 15) | \ + (((FN) & 0x07) << 12) | \ + ((WHERE) & 0xFFF)) + +#define PCI_DEV(SEGBUS, DEV, FN) ( \ + (((SEGBUS) & 0xFFF) << 20) | \ + (((DEV) & 0x1F) << 15) | \ + (((FN) & 0x07) << 12)) + +#define PCI_ID(VENDOR_ID, DEVICE_ID) \ + ((((DEVICE_ID) & 0xFFFF) << 16) | ((VENDOR_ID) & 0xFFFF)) + + +#define PNP_DEV(PORT, FUNC) (((PORT) << 8) | (FUNC)) + +typedef unsigned device_t; /* pci and pci_mmio need to have different ways to have dev */ + +/* FIXME: We need to make the coreboot to run at 64bit mode, So when read/write memory above 4G, + * We don't need to set %fs, and %gs anymore + * Before that We need to use %gs, and leave %fs to other RAM access + */ + +static inline __attribute__((always_inline)) uint8_t pci_io_read_config8(device_t dev, unsigned where) +{ + unsigned addr; +#if !CONFIG_PCI_IO_CFG_EXT + addr = (dev>>4) | where; +#else + addr = (dev>>4) | (where & 0xff) | ((where & 0xf00)<<16); //seg == 0 +#endif + outl(0x80000000 | (addr & ~3), 0xCF8); + return inb(0xCFC + (addr & 3)); +} + +#if CONFIG_MMCONF_SUPPORT +static inline __attribute__((always_inline)) uint8_t pci_mmio_read_config8(device_t dev, unsigned where) +{ + unsigned addr; + addr = CONFIG_MMCONF_BASE_ADDRESS | dev | where; + return read8(addr); +} +#endif +static inline __attribute__((always_inline)) uint8_t pci_read_config8(device_t dev, unsigned where) +{ +#if CONFIG_MMCONF_SUPPORT_DEFAULT + return pci_mmio_read_config8(dev, where); +#else + return pci_io_read_config8(dev, where); +#endif +} + +static inline __attribute__((always_inline)) uint16_t pci_io_read_config16(device_t dev, unsigned where) +{ + unsigned addr; +#if !CONFIG_PCI_IO_CFG_EXT + addr = (dev>>4) | where; +#else + addr = (dev>>4) | (where & 0xff) | ((where & 0xf00)<<16); +#endif + outl(0x80000000 | (addr & ~3), 0xCF8); + return inw(0xCFC + (addr & 2)); +} + +#if CONFIG_MMCONF_SUPPORT +static inline __attribute__((always_inline)) uint16_t pci_mmio_read_config16(device_t dev, unsigned where) +{ + unsigned addr; + addr = CONFIG_MMCONF_BASE_ADDRESS | dev | (where & ~1); + return read16(addr); +} +#endif + +static inline __attribute__((always_inline)) uint16_t pci_read_config16(device_t dev, unsigned where) +{ +#if CONFIG_MMCONF_SUPPORT_DEFAULT + return pci_mmio_read_config16(dev, where); +#else + return pci_io_read_config16(dev, where); +#endif +} + + +static inline __attribute__((always_inline)) uint32_t pci_io_read_config32(device_t dev, unsigned where) +{ + unsigned addr; +#if !CONFIG_PCI_IO_CFG_EXT + addr = (dev>>4) | where; +#else + addr = (dev>>4) | (where & 0xff) | ((where & 0xf00)<<16); +#endif + outl(0x80000000 | (addr & ~3), 0xCF8); + return inl(0xCFC); +} + +#if CONFIG_MMCONF_SUPPORT +static inline __attribute__((always_inline)) uint32_t pci_mmio_read_config32(device_t dev, unsigned where) +{ + unsigned addr; + addr = CONFIG_MMCONF_BASE_ADDRESS | dev | (where & ~3); + return read32(addr); +} +#endif + +static inline __attribute__((always_inline)) uint32_t pci_read_config32(device_t dev, unsigned where) +{ +#if CONFIG_MMCONF_SUPPORT_DEFAULT + return pci_mmio_read_config32(dev, where); +#else + return pci_io_read_config32(dev, where); +#endif +} + +static inline __attribute__((always_inline)) void pci_io_write_config8(device_t dev, unsigned where, uint8_t value) +{ + unsigned addr; +#if !CONFIG_PCI_IO_CFG_EXT + addr = (dev>>4) | where; +#else + addr = (dev>>4) | (where & 0xff) | ((where & 0xf00)<<16); +#endif + outl(0x80000000 | (addr & ~3), 0xCF8); + outb(value, 0xCFC + (addr & 3)); +} + +#if CONFIG_MMCONF_SUPPORT +static inline __attribute__((always_inline)) void pci_mmio_write_config8(device_t dev, unsigned where, uint8_t value) +{ + unsigned addr; + addr = CONFIG_MMCONF_BASE_ADDRESS | dev | where; + write8(addr, value); +} +#endif + +static inline __attribute__((always_inline)) void pci_write_config8(device_t dev, unsigned where, uint8_t value) +{ +#if CONFIG_MMCONF_SUPPORT_DEFAULT + pci_mmio_write_config8(dev, where, value); +#else + pci_io_write_config8(dev, where, value); +#endif +} + + +static inline __attribute__((always_inline)) void pci_io_write_config16(device_t dev, unsigned where, uint16_t value) +{ + unsigned addr; +#if !CONFIG_PCI_IO_CFG_EXT + addr = (dev>>4) | where; +#else + addr = (dev>>4) | (where & 0xff) | ((where & 0xf00)<<16); +#endif + outl(0x80000000 | (addr & ~3), 0xCF8); + outw(value, 0xCFC + (addr & 2)); +} + +#if CONFIG_MMCONF_SUPPORT +static inline __attribute__((always_inline)) void pci_mmio_write_config16(device_t dev, unsigned where, uint16_t value) +{ + unsigned addr; + addr = CONFIG_MMCONF_BASE_ADDRESS | dev | (where & ~1); + write16(addr, value); +} +#endif + +static inline __attribute__((always_inline)) void pci_write_config16(device_t dev, unsigned where, uint16_t value) +{ +#if CONFIG_MMCONF_SUPPORT_DEFAULT + pci_mmio_write_config16(dev, where, value); +#else + pci_io_write_config16(dev, where, value); +#endif +} + + +static inline __attribute__((always_inline)) void pci_io_write_config32(device_t dev, unsigned where, uint32_t value) +{ + unsigned addr; +#if !CONFIG_PCI_IO_CFG_EXT + addr = (dev>>4) | where; +#else + addr = (dev>>4) | (where & 0xff) | ((where & 0xf00)<<16); +#endif + outl(0x80000000 | (addr & ~3), 0xCF8); + outl(value, 0xCFC); +} + +#if CONFIG_MMCONF_SUPPORT +static inline __attribute__((always_inline)) void pci_mmio_write_config32(device_t dev, unsigned where, uint32_t value) +{ + unsigned addr; + addr = CONFIG_MMCONF_BASE_ADDRESS | dev | (where & ~3); + write32(addr, value); +} +#endif + +static inline __attribute__((always_inline)) void pci_write_config32(device_t dev, unsigned where, uint32_t value) +{ +#if CONFIG_MMCONF_SUPPORT_DEFAULT + pci_mmio_write_config32(dev, where, value); +#else + pci_io_write_config32(dev, where, value); +#endif +} + +static inline __attribute__((always_inline)) void pci_or_config8(device_t dev, unsigned where, uint8_t value) +{ + pci_write_config8(dev, where, pci_read_config8(dev, where) | value); +} + +static inline __attribute__((always_inline)) void pci_or_config16(device_t dev, unsigned where, uint16_t value) +{ + pci_write_config16(dev, where, pci_read_config16(dev, where) | value); +} + +static inline __attribute__((always_inline)) void pci_or_config32(device_t dev, unsigned where, uint32_t value) +{ + pci_write_config32(dev, where, pci_read_config32(dev, where) | value); +} + +#define PCI_DEV_INVALID (0xffffffffU) +static inline device_t pci_io_locate_device(unsigned pci_id, device_t dev) +{ + for(; dev <= PCI_DEV(255, 31, 7); dev += PCI_DEV(0,0,1)) { + unsigned int id; + id = pci_io_read_config32(dev, 0); + if (id == pci_id) { + return dev; + } + } + return PCI_DEV_INVALID; +} + +static inline device_t pci_locate_device(unsigned pci_id, device_t dev) +{ + for(; dev <= PCI_DEV(255|(((1<<CONFIG_PCI_BUS_SEGN_BITS)-1)<<8), 31, 7); dev += PCI_DEV(0,0,1)) { + unsigned int id; + id = pci_read_config32(dev, 0); + if (id == pci_id) { + return dev; + } + } + return PCI_DEV_INVALID; +} + +static inline device_t pci_locate_device_on_bus(unsigned pci_id, unsigned bus) +{ + device_t dev, last; + + dev = PCI_DEV(bus, 0, 0); + last = PCI_DEV(bus, 31, 7); + + for(; dev <=last; dev += PCI_DEV(0,0,1)) { + unsigned int id; + id = pci_read_config32(dev, 0); + if (id == pci_id) { + return dev; + } + } + return PCI_DEV_INVALID; +} + +/* Generic functions for pnp devices */ +static inline __attribute__((always_inline)) void pnp_write_config(device_t dev, uint8_t reg, uint8_t value) +{ + unsigned port = dev >> 8; + outb(reg, port ); + outb(value, port +1); +} + +static inline __attribute__((always_inline)) uint8_t pnp_read_config(device_t dev, uint8_t reg) +{ + unsigned port = dev >> 8; + outb(reg, port); + return inb(port +1); +} + +static inline __attribute__((always_inline)) void pnp_set_logical_device(device_t dev) +{ + unsigned device = dev & 0xff; + pnp_write_config(dev, 0x07, device); +} + +static inline __attribute__((always_inline)) void pnp_set_enable(device_t dev, int enable) +{ + pnp_write_config(dev, 0x30, enable?0x1:0x0); +} + +static inline __attribute__((always_inline)) int pnp_read_enable(device_t dev) +{ + return !!pnp_read_config(dev, 0x30); +} + +static inline __attribute__((always_inline)) void pnp_set_iobase(device_t dev, unsigned index, unsigned iobase) +{ + pnp_write_config(dev, index + 0, (iobase >> 8) & 0xff); + pnp_write_config(dev, index + 1, iobase & 0xff); +} + +static inline __attribute__((always_inline)) uint16_t pnp_read_iobase(device_t dev, unsigned index) +{ + return ((uint16_t)(pnp_read_config(dev, index)) << 8) | pnp_read_config(dev, index + 1); +} + +static inline __attribute__((always_inline)) void pnp_set_irq(device_t dev, unsigned index, unsigned irq) +{ + pnp_write_config(dev, index, irq); +} + +static inline __attribute__((always_inline)) void pnp_set_drq(device_t dev, unsigned index, unsigned drq) +{ + pnp_write_config(dev, index, drq & 0xff); +} + +#endif /* __PRE_RAM__ */ + #endif diff --git a/src/arch/x86/include/arch/romcc_io.h b/src/arch/x86/include/arch/romcc_io.h deleted file mode 100644 index 0f949f5..0000000 --- a/src/arch/x86/include/arch/romcc_io.h +++ /dev/null @@ -1,350 +0,0 @@ -#ifndef ARCH_ROMCC_IO_H -#define ARCH_ROMCC_IO_H 1 - -#include <stdint.h> - -// arch/io.h is pulled in in many places but it could -// also be pulled in here for all romcc/romstage code. -// #include <arch/io.h> - -static inline int log2(int value) -{ - unsigned int r = 0; - __asm__ volatile ( - "bsrl %1, %0\n\t" - "jnz 1f\n\t" - "movl $-1, %0\n\t" - "1:\n\t" - : "=r" (r) : "r" (value)); - return r; - -} -static inline int log2f(int value) -{ - unsigned int r = 0; - __asm__ volatile ( - "bsfl %1, %0\n\t" - "jnz 1f\n\t" - "movl $-1, %0\n\t" - "1:\n\t" - : "=r" (r) : "r" (value)); - return r; - -} - -#define PCI_ADDR(SEGBUS, DEV, FN, WHERE) ( \ - (((SEGBUS) & 0xFFF) << 20) | \ - (((DEV) & 0x1F) << 15) | \ - (((FN) & 0x07) << 12) | \ - ((WHERE) & 0xFFF)) - -#define PCI_DEV(SEGBUS, DEV, FN) ( \ - (((SEGBUS) & 0xFFF) << 20) | \ - (((DEV) & 0x1F) << 15) | \ - (((FN) & 0x07) << 12)) - -#define PCI_ID(VENDOR_ID, DEVICE_ID) \ - ((((DEVICE_ID) & 0xFFFF) << 16) | ((VENDOR_ID) & 0xFFFF)) - - -#define PNP_DEV(PORT, FUNC) (((PORT) << 8) | (FUNC)) - -typedef unsigned device_t; /* pci and pci_mmio need to have different ways to have dev */ - -/* FIXME: We need to make the coreboot to run at 64bit mode, So when read/write memory above 4G, - * We don't need to set %fs, and %gs anymore - * Before that We need to use %gs, and leave %fs to other RAM access - */ - -static inline __attribute__((always_inline)) uint8_t pci_io_read_config8(device_t dev, unsigned where) -{ - unsigned addr; -#if !CONFIG_PCI_IO_CFG_EXT - addr = (dev>>4) | where; -#else - addr = (dev>>4) | (where & 0xff) | ((where & 0xf00)<<16); //seg == 0 -#endif - outl(0x80000000 | (addr & ~3), 0xCF8); - return inb(0xCFC + (addr & 3)); -} - -#if CONFIG_MMCONF_SUPPORT -static inline __attribute__((always_inline)) uint8_t pci_mmio_read_config8(device_t dev, unsigned where) -{ - unsigned addr; - addr = CONFIG_MMCONF_BASE_ADDRESS | dev | where; - return read8(addr); -} -#endif -static inline __attribute__((always_inline)) uint8_t pci_read_config8(device_t dev, unsigned where) -{ -#if CONFIG_MMCONF_SUPPORT_DEFAULT - return pci_mmio_read_config8(dev, where); -#else - return pci_io_read_config8(dev, where); -#endif -} - -static inline __attribute__((always_inline)) uint16_t pci_io_read_config16(device_t dev, unsigned where) -{ - unsigned addr; -#if !CONFIG_PCI_IO_CFG_EXT - addr = (dev>>4) | where; -#else - addr = (dev>>4) | (where & 0xff) | ((where & 0xf00)<<16); -#endif - outl(0x80000000 | (addr & ~3), 0xCF8); - return inw(0xCFC + (addr & 2)); -} - -#if CONFIG_MMCONF_SUPPORT -static inline __attribute__((always_inline)) uint16_t pci_mmio_read_config16(device_t dev, unsigned where) -{ - unsigned addr; - addr = CONFIG_MMCONF_BASE_ADDRESS | dev | (where & ~1); - return read16(addr); -} -#endif - -static inline __attribute__((always_inline)) uint16_t pci_read_config16(device_t dev, unsigned where) -{ -#if CONFIG_MMCONF_SUPPORT_DEFAULT - return pci_mmio_read_config16(dev, where); -#else - return pci_io_read_config16(dev, where); -#endif -} - - -static inline __attribute__((always_inline)) uint32_t pci_io_read_config32(device_t dev, unsigned where) -{ - unsigned addr; -#if !CONFIG_PCI_IO_CFG_EXT - addr = (dev>>4) | where; -#else - addr = (dev>>4) | (where & 0xff) | ((where & 0xf00)<<16); -#endif - outl(0x80000000 | (addr & ~3), 0xCF8); - return inl(0xCFC); -} - -#if CONFIG_MMCONF_SUPPORT -static inline __attribute__((always_inline)) uint32_t pci_mmio_read_config32(device_t dev, unsigned where) -{ - unsigned addr; - addr = CONFIG_MMCONF_BASE_ADDRESS | dev | (where & ~3); - return read32(addr); -} -#endif - -static inline __attribute__((always_inline)) uint32_t pci_read_config32(device_t dev, unsigned where) -{ -#if CONFIG_MMCONF_SUPPORT_DEFAULT - return pci_mmio_read_config32(dev, where); -#else - return pci_io_read_config32(dev, where); -#endif -} - -static inline __attribute__((always_inline)) void pci_io_write_config8(device_t dev, unsigned where, uint8_t value) -{ - unsigned addr; -#if !CONFIG_PCI_IO_CFG_EXT - addr = (dev>>4) | where; -#else - addr = (dev>>4) | (where & 0xff) | ((where & 0xf00)<<16); -#endif - outl(0x80000000 | (addr & ~3), 0xCF8); - outb(value, 0xCFC + (addr & 3)); -} - -#if CONFIG_MMCONF_SUPPORT -static inline __attribute__((always_inline)) void pci_mmio_write_config8(device_t dev, unsigned where, uint8_t value) -{ - unsigned addr; - addr = CONFIG_MMCONF_BASE_ADDRESS | dev | where; - write8(addr, value); -} -#endif - -static inline __attribute__((always_inline)) void pci_write_config8(device_t dev, unsigned where, uint8_t value) -{ -#if CONFIG_MMCONF_SUPPORT_DEFAULT - pci_mmio_write_config8(dev, where, value); -#else - pci_io_write_config8(dev, where, value); -#endif -} - - -static inline __attribute__((always_inline)) void pci_io_write_config16(device_t dev, unsigned where, uint16_t value) -{ - unsigned addr; -#if !CONFIG_PCI_IO_CFG_EXT - addr = (dev>>4) | where; -#else - addr = (dev>>4) | (where & 0xff) | ((where & 0xf00)<<16); -#endif - outl(0x80000000 | (addr & ~3), 0xCF8); - outw(value, 0xCFC + (addr & 2)); -} - -#if CONFIG_MMCONF_SUPPORT -static inline __attribute__((always_inline)) void pci_mmio_write_config16(device_t dev, unsigned where, uint16_t value) -{ - unsigned addr; - addr = CONFIG_MMCONF_BASE_ADDRESS | dev | (where & ~1); - write16(addr, value); -} -#endif - -static inline __attribute__((always_inline)) void pci_write_config16(device_t dev, unsigned where, uint16_t value) -{ -#if CONFIG_MMCONF_SUPPORT_DEFAULT - pci_mmio_write_config16(dev, where, value); -#else - pci_io_write_config16(dev, where, value); -#endif -} - - -static inline __attribute__((always_inline)) void pci_io_write_config32(device_t dev, unsigned where, uint32_t value) -{ - unsigned addr; -#if !CONFIG_PCI_IO_CFG_EXT - addr = (dev>>4) | where; -#else - addr = (dev>>4) | (where & 0xff) | ((where & 0xf00)<<16); -#endif - outl(0x80000000 | (addr & ~3), 0xCF8); - outl(value, 0xCFC); -} - -#if CONFIG_MMCONF_SUPPORT -static inline __attribute__((always_inline)) void pci_mmio_write_config32(device_t dev, unsigned where, uint32_t value) -{ - unsigned addr; - addr = CONFIG_MMCONF_BASE_ADDRESS | dev | (where & ~3); - write32(addr, value); -} -#endif - -static inline __attribute__((always_inline)) void pci_write_config32(device_t dev, unsigned where, uint32_t value) -{ -#if CONFIG_MMCONF_SUPPORT_DEFAULT - pci_mmio_write_config32(dev, where, value); -#else - pci_io_write_config32(dev, where, value); -#endif -} - -static inline __attribute__((always_inline)) void pci_or_config8(device_t dev, unsigned where, uint8_t value) -{ - pci_write_config8(dev, where, pci_read_config8(dev, where) | value); -} - -static inline __attribute__((always_inline)) void pci_or_config16(device_t dev, unsigned where, uint16_t value) -{ - pci_write_config16(dev, where, pci_read_config16(dev, where) | value); -} - -static inline __attribute__((always_inline)) void pci_or_config32(device_t dev, unsigned where, uint32_t value) -{ - pci_write_config32(dev, where, pci_read_config32(dev, where) | value); -} - -#define PCI_DEV_INVALID (0xffffffffU) -static inline device_t pci_io_locate_device(unsigned pci_id, device_t dev) -{ - for(; dev <= PCI_DEV(255, 31, 7); dev += PCI_DEV(0,0,1)) { - unsigned int id; - id = pci_io_read_config32(dev, 0); - if (id == pci_id) { - return dev; - } - } - return PCI_DEV_INVALID; -} - -static inline device_t pci_locate_device(unsigned pci_id, device_t dev) -{ - for(; dev <= PCI_DEV(255|(((1<<CONFIG_PCI_BUS_SEGN_BITS)-1)<<8), 31, 7); dev += PCI_DEV(0,0,1)) { - unsigned int id; - id = pci_read_config32(dev, 0); - if (id == pci_id) { - return dev; - } - } - return PCI_DEV_INVALID; -} - -static inline device_t pci_locate_device_on_bus(unsigned pci_id, unsigned bus) -{ - device_t dev, last; - - dev = PCI_DEV(bus, 0, 0); - last = PCI_DEV(bus, 31, 7); - - for(; dev <=last; dev += PCI_DEV(0,0,1)) { - unsigned int id; - id = pci_read_config32(dev, 0); - if (id == pci_id) { - return dev; - } - } - return PCI_DEV_INVALID; -} - -/* Generic functions for pnp devices */ -static inline __attribute__((always_inline)) void pnp_write_config(device_t dev, uint8_t reg, uint8_t value) -{ - unsigned port = dev >> 8; - outb(reg, port ); - outb(value, port +1); -} - -static inline __attribute__((always_inline)) uint8_t pnp_read_config(device_t dev, uint8_t reg) -{ - unsigned port = dev >> 8; - outb(reg, port); - return inb(port +1); -} - -static inline __attribute__((always_inline)) void pnp_set_logical_device(device_t dev) -{ - unsigned device = dev & 0xff; - pnp_write_config(dev, 0x07, device); -} - -static inline __attribute__((always_inline)) void pnp_set_enable(device_t dev, int enable) -{ - pnp_write_config(dev, 0x30, enable?0x1:0x0); -} - -static inline __attribute__((always_inline)) int pnp_read_enable(device_t dev) -{ - return !!pnp_read_config(dev, 0x30); -} - -static inline __attribute__((always_inline)) void pnp_set_iobase(device_t dev, unsigned index, unsigned iobase) -{ - pnp_write_config(dev, index + 0, (iobase >> 8) & 0xff); - pnp_write_config(dev, index + 1, iobase & 0xff); -} - -static inline __attribute__((always_inline)) uint16_t pnp_read_iobase(device_t dev, unsigned index) -{ - return ((uint16_t)(pnp_read_config(dev, index)) << 8) | pnp_read_config(dev, index + 1); -} - -static inline __attribute__((always_inline)) void pnp_set_irq(device_t dev, unsigned index, unsigned irq) -{ - pnp_write_config(dev, index, irq); -} - -static inline __attribute__((always_inline)) void pnp_set_drq(device_t dev, unsigned index, unsigned drq) -{ - pnp_write_config(dev, index, drq & 0xff); -} - -#endif /* ARCH_ROMCC_IO_H */ diff --git a/src/cpu/intel/haswell/bootblock.c b/src/cpu/intel/haswell/bootblock.c index f9c3ba8..bb065c8 100644 --- a/src/cpu/intel/haswell/bootblock.c +++ b/src/cpu/intel/haswell/bootblock.c @@ -23,7 +23,6 @@ #include <cpu/x86/msr.h> #include <cpu/x86/mtrr.h> #include <arch/io.h> -#include <arch/romcc_io.h> #include <cpu/intel/microcode/microcode.c> #include "haswell.h" diff --git a/src/cpu/intel/haswell/romstage.c b/src/cpu/intel/haswell/romstage.c index d62377e..a65f590 100644 --- a/src/cpu/intel/haswell/romstage.c +++ b/src/cpu/intel/haswell/romstage.c @@ -30,7 +30,6 @@ #include <timestamp.h> #include <arch/io.h> #include <arch/stages.h> -#include <arch/romcc_io.h> #include <device/pci_def.h> #include <cpu/x86/lapic.h> #include <cbmem.h> diff --git a/src/cpu/intel/model_206ax/bootblock.c b/src/cpu/intel/model_206ax/bootblock.c index a4f8fc3..d3579f7 100644 --- a/src/cpu/intel/model_206ax/bootblock.c +++ b/src/cpu/intel/model_206ax/bootblock.c @@ -23,7 +23,6 @@ #include <cpu/x86/msr.h> #include <cpu/x86/mtrr.h> #include <arch/io.h> -#include <arch/romcc_io.h> #include <cpu/intel/microcode/microcode.c> #include "model_206ax.h" diff --git a/src/cpu/x86/smm/smihandler.c b/src/cpu/x86/smm/smihandler.c index b4b7f36..fc30909 100644 --- a/src/cpu/x86/smm/smihandler.c +++ b/src/cpu/x86/smm/smihandler.c @@ -20,7 +20,6 @@ */ #include <arch/io.h> -#include <arch/romcc_io.h> #include <console/console.h> #include <cpu/x86/cache.h> #include <cpu/x86/smm.h> diff --git a/src/cpu/x86/smm/smiutil.c b/src/cpu/x86/smm/smiutil.c index 1d2c86f..c13b452 100644 --- a/src/cpu/x86/smm/smiutil.c +++ b/src/cpu/x86/smm/smiutil.c @@ -20,7 +20,6 @@ */ #include <arch/io.h> -#include <arch/romcc_io.h> #include <cpu/x86/cache.h> #include <cpu/x86/smm.h> #include <console/console.h> diff --git a/src/cpu/x86/smm/smm_module_handler.c b/src/cpu/x86/smm/smm_module_handler.c index 67802d6..116dafa 100644 --- a/src/cpu/x86/smm/smm_module_handler.c +++ b/src/cpu/x86/smm/smm_module_handler.c @@ -18,7 +18,6 @@ */ #include <arch/io.h> -#include <arch/romcc_io.h> #include <console/console.h> #include <cpu/x86/smm.h> diff --git a/src/drivers/oxford/oxpcie/oxpcie_early.c b/src/drivers/oxford/oxpcie/oxpcie_early.c index 3c33063..9899619 100644 --- a/src/drivers/oxford/oxpcie/oxpcie_early.c +++ b/src/drivers/oxford/oxpcie/oxpcie_early.c @@ -19,7 +19,6 @@ #include <stdint.h> #include <arch/io.h> -#include <arch/romcc_io.h> #include <cpu/x86/car.h> #include <delay.h> #include <uart8250.h> diff --git a/src/ec/acpi/ec.c b/src/ec/acpi/ec.c index ad297fb..d3a6aaf 100644 --- a/src/ec/acpi/ec.c +++ b/src/ec/acpi/ec.c @@ -138,6 +138,8 @@ void ec_set_ports(u16 cmd_reg, u16 data_reg) ec_data_reg = data_reg; } +#if !defined(__SMM__) && !defined(__PRE_RAM__) struct chip_operations ec_acpi_ops = { CHIP_NAME("ACPI Embedded Controller") }; +#endif diff --git a/src/ec/google/chromeec/ec.c b/src/ec/google/chromeec/ec.c index cd5471d..5ae0178 100644 --- a/src/ec/google/chromeec/ec.c +++ b/src/ec/google/chromeec/ec.c @@ -21,12 +21,9 @@ #include <console/console.h> #include <arch/io.h> #include <delay.h> - -#ifdef __PRE_RAM__ -#include <arch/romcc_io.h> -#else #include <device/device.h> #include <device/pnp.h> +#ifndef __PRE_RAM__ #include <elog.h> #include <stdlib.h> #include <string.h> diff --git a/src/ec/quanta/ene_kb3940q/ec.c b/src/ec/quanta/ene_kb3940q/ec.c index 1ef9712..137aa81 100644 --- a/src/ec/quanta/ene_kb3940q/ec.c +++ b/src/ec/quanta/ene_kb3940q/ec.c @@ -22,10 +22,10 @@ #ifndef __PRE_RAM__ #include <console/console.h> +#include <arch/io.h> #include <device/device.h> #include <device/pnp.h> #include <stdlib.h> -#include <arch/io.h> #include <delay.h> #include <elog.h> #include "ec.h" diff --git a/src/ec/smsc/mec1308/ec.c b/src/ec/smsc/mec1308/ec.c index bfd3c14..fdae5e4 100644 --- a/src/ec/smsc/mec1308/ec.c +++ b/src/ec/smsc/mec1308/ec.c @@ -119,6 +119,7 @@ void ec_set_ports(u16 cmd_reg, u16 data_reg) ec_data_reg = data_reg; } +#if !defined(__PRE_RAM__) && !defined(__SMM__) static void mec1308_enable(device_t dev) { struct ec_smsc_mec1308_config *conf = dev->chip_info; @@ -133,3 +134,4 @@ struct chip_operations ec_smsc_mec1308_ops = { CHIP_NAME("SMSC MEC1308 EC Mailbox Interface") .enable_dev = mec1308_enable }; +#endif diff --git a/src/include/cpu/cpu.h b/src/include/cpu/cpu.h index cf2d389..bed77de 100644 --- a/src/include/cpu/cpu.h +++ b/src/include/cpu/cpu.h @@ -3,7 +3,7 @@ #include <arch/cpu.h> -#if !defined(__ROMCC__) +#if !defined(__PRE_RAM__) && !defined(__SMM__) void cpu_initialize(unsigned int cpu_index); struct bus; void initialize_cpus(struct bus *cpu_bus); @@ -20,6 +20,6 @@ void smm_setup_structures(void *gnvs, void *tcg, void *smi1); extern struct cpu_driver cpu_drivers[]; /** end of compile time generated pci driver array */ extern struct cpu_driver ecpu_drivers[]; -#endif /* !__ROMCC__ */ +#endif /* !__PRE_RAM__ && !__SMM__ */ #endif /* CPU_CPU_H */ diff --git a/src/include/device/device.h b/src/include/device/device.h index b248aaf..5219310 100644 --- a/src/include/device/device.h +++ b/src/include/device/device.h @@ -1,6 +1,7 @@ #ifndef DEVICE_H #define DEVICE_H +#ifndef __SMM__ #include <stdint.h> #include <stddef.h> #include <device/resource.h> @@ -222,4 +223,7 @@ ROMSTAGE_CONST struct device * dev_find_slot (unsigned int bus, ROMSTAGE_CONST struct device * dev_find_slot_on_smbus (unsigned int bus, unsigned int addr); #endif +#else /* __SMM__ */ +#include <arch/io.h> +#endif /* __SMM__ */ #endif /* DEVICE_H */ diff --git a/src/include/device/pci.h b/src/include/device/pci.h index 132c48c..1f47daf 100644 --- a/src/include/device/pci.h +++ b/src/include/device/pci.h @@ -20,7 +20,7 @@ #include <device/pci_def.h> #include <device/resource.h> #include <device/device.h> -#ifndef __PRE_RAM__ +#if !defined(__PRE_RAM__) && !defined(__SMM__) #include <device/pci_ops.h> #include <device/pci_rom.h> diff --git a/src/include/device/pci_ops.h b/src/include/device/pci_ops.h index 2efbf9d..20fbb99 100644 --- a/src/include/device/pci_ops.h +++ b/src/include/device/pci_ops.h @@ -1,6 +1,7 @@ #ifndef PCI_OPS_H #define PCI_OPS_H +#ifndef __SMM__ #include <stdint.h> #include <device/device.h> #include <arch/pci_ops.h> @@ -20,5 +21,6 @@ void pci_mmio_write_config8(device_t dev, unsigned int where, u8 val); void pci_mmio_write_config16(device_t dev, unsigned int where, u16 val); void pci_mmio_write_config32(device_t dev, unsigned int where, u32 val); #endif +#endif #endif /* PCI_OPS_H */ diff --git a/src/include/device/pnp.h b/src/include/device/pnp.h index 7eb2ac5..f97b05d 100644 --- a/src/include/device/pnp.h +++ b/src/include/device/pnp.h @@ -5,6 +5,7 @@ #include <device/device.h> #include <device/pnp_def.h> +#if !defined(__PRE_RAM__) && !defined(__SMM__) /* Primitive PNP resource manipulation */ void pnp_write_config(device_t dev, u8 reg, u8 value); u8 pnp_read_config(device_t dev, u8 reg); @@ -50,4 +51,5 @@ struct resource *pnp_get_resource(device_t dev, unsigned index); void pnp_enable_devices(struct device *dev, struct device_operations *ops, unsigned int functions, struct pnp_info *info); +#endif #endif /* DEVICE_PNP_H */ diff --git a/src/include/lib.h b/src/include/lib.h index 9d81085..40c76f2 100644 --- a/src/include/lib.h +++ b/src/include/lib.h @@ -24,7 +24,7 @@ #include <stdint.h> #ifndef __ROMCC__ /* romcc doesn't support prototypes. */ -#ifndef __PRE_RAM__ /* Conflicts with romcc_io.h */ +#ifndef __PRE_RAM__ /* Conflicts with inline function in arch/io.h */ /* Defined in src/lib/clog2.c */ unsigned long log2(unsigned long x); #endif diff --git a/src/lib/ne2k.c b/src/lib/ne2k.c index 09925f6..31470fc 100644 --- a/src/lib/ne2k.c +++ b/src/lib/ne2k.c @@ -38,7 +38,6 @@ SMC8416 PIO support added by Andrew Bettison (andrewb(a)zip.com.au) on 4/3/02 #include <ip_checksum.h> #include <console/ne2k.h> #include <arch/io.h> -//#include <arch/romcc_io.h> #define MEM_SIZE MEM_32768 #define TX_START 64 @@ -343,8 +342,6 @@ void ne2k_transmit(unsigned int eth_nic_base) { #ifdef __PRE_RAM__ -#include <arch/romcc_io.h> - static void ns8390_reset(unsigned int eth_nic_base) { int i; diff --git a/src/mainboard/a-trend/atc-6220/romstage.c b/src/mainboard/a-trend/atc-6220/romstage.c index e8880de..63d34b2 100644 --- a/src/mainboard/a-trend/atc-6220/romstage.c +++ b/src/mainboard/a-trend/atc-6220/romstage.c @@ -22,7 +22,6 @@ #include <device/pci_def.h> #include <arch/io.h> #include <device/pnp_def.h> -#include <arch/romcc_io.h> #include <arch/hlt.h> #include <stdlib.h> #include <console/console.h> diff --git a/src/mainboard/a-trend/atc-6240/romstage.c b/src/mainboard/a-trend/atc-6240/romstage.c index dfa5ce0..9e4b35b 100644 --- a/src/mainboard/a-trend/atc-6240/romstage.c +++ b/src/mainboard/a-trend/atc-6240/romstage.c @@ -23,7 +23,6 @@ #include <device/pci_def.h> #include <arch/io.h> #include <device/pnp_def.h> -#include <arch/romcc_io.h> #include <arch/hlt.h> #include <console/console.h> #include "southbridge/intel/i82371eb/i82371eb.h" diff --git a/src/mainboard/abit/be6-ii_v2_0/romstage.c b/src/mainboard/abit/be6-ii_v2_0/romstage.c index 385ab7e..74f8404 100644 --- a/src/mainboard/abit/be6-ii_v2_0/romstage.c +++ b/src/mainboard/abit/be6-ii_v2_0/romstage.c @@ -23,7 +23,6 @@ #include <device/pci_def.h> #include <arch/io.h> #include <device/pnp_def.h> -#include <arch/romcc_io.h> #include <arch/hlt.h> #include <console/console.h> #include "southbridge/intel/i82371eb/i82371eb.h" diff --git a/src/mainboard/advansus/a785e-i/reset.c b/src/mainboard/advansus/a785e-i/reset.c index 3ce182e..678bc3d 100644 --- a/src/mainboard/advansus/a785e-i/reset.c +++ b/src/mainboard/advansus/a785e-i/reset.c @@ -17,9 +17,11 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#include <reset.h> +#ifndef __PRE_RAM__ +#define __PRE_RAM__ // Use simple device model for this file even in ramstage +#endif #include <arch/io.h> -#include <arch/romcc_io.h> +#include <reset.h> #define HT_INIT_CONTROL 0x6C #define HTIC_BIOSR_Detect (1<<5) diff --git a/src/mainboard/advansus/a785e-i/romstage.c b/src/mainboard/advansus/a785e-i/romstage.c index 9657ec3..ae283a4 100644 --- a/src/mainboard/advansus/a785e-i/romstage.c +++ b/src/mainboard/advansus/a785e-i/romstage.c @@ -32,7 +32,6 @@ #include <device/pci_ids.h> #include <arch/io.h> #include <device/pnp_def.h> -#include <arch/romcc_io.h> #include <cpu/x86/lapic.h> #include <console/console.h> #include <cpu/amd/model_10xxx_rev.h> diff --git a/src/mainboard/advantech/pcm-5820/romstage.c b/src/mainboard/advantech/pcm-5820/romstage.c index da47816..b710aad 100644 --- a/src/mainboard/advantech/pcm-5820/romstage.c +++ b/src/mainboard/advantech/pcm-5820/romstage.c @@ -21,7 +21,6 @@ #include <stdint.h> #include <arch/io.h> #include <device/pnp_def.h> -#include <arch/romcc_io.h> #include <arch/hlt.h> #include <console/console.h> #include "northbridge/amd/gx1/raminit.c" diff --git a/src/mainboard/amd/bimini_fam10/romstage.c b/src/mainboard/amd/bimini_fam10/romstage.c index aeb1bfb..f781216 100644 --- a/src/mainboard/amd/bimini_fam10/romstage.c +++ b/src/mainboard/amd/bimini_fam10/romstage.c @@ -31,7 +31,6 @@ #include <device/pci_ids.h> #include <arch/io.h> #include <device/pnp_def.h> -#include <arch/romcc_io.h> #include <cpu/x86/lapic.h> #include <console/console.h> #include <cpu/amd/model_10xxx_rev.h> diff --git a/src/mainboard/amd/dbm690t/romstage.c b/src/mainboard/amd/dbm690t/romstage.c index 5090681..44528a0 100644 --- a/src/mainboard/amd/dbm690t/romstage.c +++ b/src/mainboard/amd/dbm690t/romstage.c @@ -27,7 +27,6 @@ #include <device/pci_def.h> #include <arch/io.h> #include <device/pnp_def.h> -#include <arch/romcc_io.h> #include <cpu/x86/lapic.h> #include <pc80/mc146818rtc.h> #include <console/console.h> diff --git a/src/mainboard/amd/dinar/reset.c b/src/mainboard/amd/dinar/reset.c index d7ee532..f2a2bcd 100644 --- a/src/mainboard/amd/dinar/reset.c +++ b/src/mainboard/amd/dinar/reset.c @@ -17,10 +17,11 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ - +#ifndef __PRE_RAM__ +#define __PRE_RAM__ // Use simple device model for this file even in ramstage +#endif +#include <arch/io.h> #include <reset.h> -#include <arch/io.h> /*inb, outb*/ -#include <arch/romcc_io.h> /*pci_read_config32, device_t, PCI_DEV*/ #define HT_INIT_CONTROL 0x6C #define HTIC_BIOSR_Detect (1<<5) diff --git a/src/mainboard/amd/dinar/romstage.c b/src/mainboard/amd/dinar/romstage.c index e1e04d8..a59d142 100644 --- a/src/mainboard/amd/dinar/romstage.c +++ b/src/mainboard/amd/dinar/romstage.c @@ -24,7 +24,6 @@ #include <arch/io.h> #include <arch/stages.h> #include <device/pnp_def.h> -#include <arch/romcc_io.h> #include <cpu/x86/lapic.h> #include <console/console.h> #include <console/loglevel.h> diff --git a/src/mainboard/amd/inagua/reset.c b/src/mainboard/amd/inagua/reset.c index 5958e77..bb2482b 100644 --- a/src/mainboard/amd/inagua/reset.c +++ b/src/mainboard/amd/inagua/reset.c @@ -17,10 +17,11 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ - +#ifndef __PRE_RAM__ +#define __PRE_RAM__ // Use simple device model for this file even in ramstage +#endif +#include <arch/io.h> #include <reset.h> -#include <arch/io.h> /*inb, outb*/ -#include <arch/romcc_io.h> /*pci_read_config32, device_t, PCI_DEV*/ #define HT_INIT_CONTROL 0x6C #define HTIC_BIOSR_Detect (1<<5) diff --git a/src/mainboard/amd/inagua/romstage.c b/src/mainboard/amd/inagua/romstage.c index d1693c5..a03d5a7 100644 --- a/src/mainboard/amd/inagua/romstage.c +++ b/src/mainboard/amd/inagua/romstage.c @@ -25,7 +25,6 @@ #include <arch/io.h> #include <arch/stages.h> #include <device/pnp_def.h> -#include <arch/romcc_io.h> #include <arch/cpu.h> #include <cpu/x86/lapic.h> #include <console/console.h> diff --git a/src/mainboard/amd/mahogany/romstage.c b/src/mainboard/amd/mahogany/romstage.c index 75fda78..2963ada 100644 --- a/src/mainboard/amd/mahogany/romstage.c +++ b/src/mainboard/amd/mahogany/romstage.c @@ -27,7 +27,6 @@ #include <device/pci_def.h> #include <arch/io.h> #include <device/pnp_def.h> -#include <arch/romcc_io.h> #include <cpu/x86/lapic.h> #include <pc80/mc146818rtc.h> #include <console/console.h> diff --git a/src/mainboard/amd/mahogany_fam10/romstage.c b/src/mainboard/amd/mahogany_fam10/romstage.c index 98c91b4..d1c75ad 100644 --- a/src/mainboard/amd/mahogany_fam10/romstage.c +++ b/src/mainboard/amd/mahogany_fam10/romstage.c @@ -31,7 +31,6 @@ #include <device/pci_ids.h> #include <arch/io.h> #include <device/pnp_def.h> -#include <arch/romcc_io.h> #include <cpu/x86/lapic.h> #include <console/console.h> #include <cpu/amd/model_10xxx_rev.h> diff --git a/src/mainboard/amd/parmer/romstage.c b/src/mainboard/amd/parmer/romstage.c index 6076bc8..25f14e8 100644 --- a/src/mainboard/amd/parmer/romstage.c +++ b/src/mainboard/amd/parmer/romstage.c @@ -24,7 +24,6 @@ #include <arch/io.h> #include <arch/stages.h> #include <device/pnp_def.h> -#include <arch/romcc_io.h> #include <arch/cpu.h> #include <cpu/x86/lapic.h> #include <console/console.h> diff --git a/src/mainboard/amd/persimmon/reset.c b/src/mainboard/amd/persimmon/reset.c index 5958e77..bb2482b 100644 --- a/src/mainboard/amd/persimmon/reset.c +++ b/src/mainboard/amd/persimmon/reset.c @@ -17,10 +17,11 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ - +#ifndef __PRE_RAM__ +#define __PRE_RAM__ // Use simple device model for this file even in ramstage +#endif +#include <arch/io.h> #include <reset.h> -#include <arch/io.h> /*inb, outb*/ -#include <arch/romcc_io.h> /*pci_read_config32, device_t, PCI_DEV*/ #define HT_INIT_CONTROL 0x6C #define HTIC_BIOSR_Detect (1<<5) diff --git a/src/mainboard/amd/persimmon/romstage.c b/src/mainboard/amd/persimmon/romstage.c index 2ed4a77..0c8c456 100644 --- a/src/mainboard/amd/persimmon/romstage.c +++ b/src/mainboard/amd/persimmon/romstage.c @@ -24,7 +24,6 @@ #include <arch/io.h> #include <arch/stages.h> #include <device/pnp_def.h> -#include <arch/romcc_io.h> #include <arch/cpu.h> #include <cpu/x86/lapic.h> #include <console/console.h> diff --git a/src/mainboard/amd/pistachio/romstage.c b/src/mainboard/amd/pistachio/romstage.c index 2ace3d0..2735cda 100644 --- a/src/mainboard/amd/pistachio/romstage.c +++ b/src/mainboard/amd/pistachio/romstage.c @@ -22,7 +22,6 @@ #include <device/pci_def.h> #include <arch/io.h> #include <device/pnp_def.h> -#include <arch/romcc_io.h> #include <cpu/x86/lapic.h> #include <pc80/mc146818rtc.h> #include <console/console.h> diff --git a/src/mainboard/amd/serengeti_cheetah/ap_romstage.c b/src/mainboard/amd/serengeti_cheetah/ap_romstage.c index 710eae8..fa680fe 100644 --- a/src/mainboard/amd/serengeti_cheetah/ap_romstage.c +++ b/src/mainboard/amd/serengeti_cheetah/ap_romstage.c @@ -5,7 +5,6 @@ #include <device/pci_ids.h> #include <arch/io.h> #include <device/pnp_def.h> -#include <arch/romcc_io.h> #include <cpu/x86/lapic.h> #include <pc80/mc146818rtc.h> #include "console/console.c" diff --git a/src/mainboard/amd/serengeti_cheetah/romstage.c b/src/mainboard/amd/serengeti_cheetah/romstage.c index db8cdb0..8d985b7 100644 --- a/src/mainboard/amd/serengeti_cheetah/romstage.c +++ b/src/mainboard/amd/serengeti_cheetah/romstage.c @@ -8,7 +8,6 @@ #include <device/pci_ids.h> #include <arch/io.h> #include <device/pnp_def.h> -#include <arch/romcc_io.h> #include <pc80/mc146818rtc.h> #include <console/console.h> #include <cpu/amd/model_fxx_rev.h> diff --git a/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c b/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c index 478b26d..b773719 100644 --- a/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c +++ b/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c @@ -31,7 +31,6 @@ #include <device/pci_ids.h> #include <arch/io.h> #include <device/pnp_def.h> -#include <arch/romcc_io.h> #include <cpu/x86/lapic.h> #include <console/console.h> #include <cpu/amd/model_10xxx_rev.h> diff --git a/src/mainboard/amd/south_station/reset.c b/src/mainboard/amd/south_station/reset.c index 5958e77..bb2482b 100644 --- a/src/mainboard/amd/south_station/reset.c +++ b/src/mainboard/amd/south_station/reset.c @@ -17,10 +17,11 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ - +#ifndef __PRE_RAM__ +#define __PRE_RAM__ // Use simple device model for this file even in ramstage +#endif +#include <arch/io.h> #include <reset.h> -#include <arch/io.h> /*inb, outb*/ -#include <arch/romcc_io.h> /*pci_read_config32, device_t, PCI_DEV*/ #define HT_INIT_CONTROL 0x6C #define HTIC_BIOSR_Detect (1<<5) diff --git a/src/mainboard/amd/south_station/romstage.c b/src/mainboard/amd/south_station/romstage.c index 09b0900..88c6490 100644 --- a/src/mainboard/amd/south_station/romstage.c +++ b/src/mainboard/amd/south_station/romstage.c @@ -25,7 +25,6 @@ #include <arch/io.h> #include <arch/stages.h> #include <device/pnp_def.h> -#include <arch/romcc_io.h> #include <arch/cpu.h> #include <cpu/x86/lapic.h> #include <console/console.h> diff --git a/src/mainboard/amd/thatcher/romstage.c b/src/mainboard/amd/thatcher/romstage.c index 096dd7d..1f3e86d 100644 --- a/src/mainboard/amd/thatcher/romstage.c +++ b/src/mainboard/amd/thatcher/romstage.c @@ -24,7 +24,6 @@ #include <arch/io.h> #include <arch/stages.h> #include <device/pnp_def.h> -#include <arch/romcc_io.h> #include <arch/cpu.h> #include <cpu/x86/lapic.h> #include <console/console.h> diff --git a/src/mainboard/amd/tilapia_fam10/romstage.c b/src/mainboard/amd/tilapia_fam10/romstage.c index 1437329..a567c1b 100644 --- a/src/mainboard/amd/tilapia_fam10/romstage.c +++ b/src/mainboard/amd/tilapia_fam10/romstage.c @@ -31,7 +31,6 @@ #include <device/pci_ids.h> #include <arch/io.h> #include <device/pnp_def.h> -#include <arch/romcc_io.h> #include <cpu/x86/lapic.h> #include <console/console.h> #include <cpu/amd/model_10xxx_rev.h> diff --git a/src/mainboard/amd/torpedo/reset.c b/src/mainboard/amd/torpedo/reset.c index 5958e77..bb2482b 100644 --- a/src/mainboard/amd/torpedo/reset.c +++ b/src/mainboard/amd/torpedo/reset.c @@ -17,10 +17,11 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ - +#ifndef __PRE_RAM__ +#define __PRE_RAM__ // Use simple device model for this file even in ramstage +#endif +#include <arch/io.h> #include <reset.h> -#include <arch/io.h> /*inb, outb*/ -#include <arch/romcc_io.h> /*pci_read_config32, device_t, PCI_DEV*/ #define HT_INIT_CONTROL 0x6C #define HTIC_BIOSR_Detect (1<<5) diff --git a/src/mainboard/amd/torpedo/romstage.c b/src/mainboard/amd/torpedo/romstage.c index 0c454e8..8edba80 100644 --- a/src/mainboard/amd/torpedo/romstage.c +++ b/src/mainboard/amd/torpedo/romstage.c @@ -24,7 +24,6 @@ #include <arch/io.h> #include <arch/stages.h> #include <device/pnp_def.h> -#include <arch/romcc_io.h> #include <cpu/x86/lapic.h> #include <console/console.h> #include <console/loglevel.h> diff --git a/src/mainboard/amd/union_station/reset.c b/src/mainboard/amd/union_station/reset.c index 5958e77..bb2482b 100644 --- a/src/mainboard/amd/union_station/reset.c +++ b/src/mainboard/amd/union_station/reset.c @@ -17,10 +17,11 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ - +#ifndef __PRE_RAM__ +#define __PRE_RAM__ // Use simple device model for this file even in ramstage +#endif +#include <arch/io.h> #include <reset.h> -#include <arch/io.h> /*inb, outb*/ -#include <arch/romcc_io.h> /*pci_read_config32, device_t, PCI_DEV*/ #define HT_INIT_CONTROL 0x6C #define HTIC_BIOSR_Detect (1<<5) diff --git a/src/mainboard/amd/union_station/romstage.c b/src/mainboard/amd/union_station/romstage.c index 02aea1b..4538157 100644 --- a/src/mainboard/amd/union_station/romstage.c +++ b/src/mainboard/amd/union_station/romstage.c @@ -25,7 +25,6 @@ #include <arch/io.h> #include <arch/stages.h> #include <device/pnp_def.h> -#include <arch/romcc_io.h> #include <arch/cpu.h> #include <cpu/x86/lapic.h> #include <console/console.h> diff --git a/src/mainboard/aopen/dxplplusu/romstage.c b/src/mainboard/aopen/dxplplusu/romstage.c index c80551e..9b96792 100644 --- a/src/mainboard/aopen/dxplplusu/romstage.c +++ b/src/mainboard/aopen/dxplplusu/romstage.c @@ -20,7 +20,6 @@ #include <stdint.h> #include <device/pci_def.h> #include <arch/io.h> -#include <arch/romcc_io.h> #include <arch/cpu.h> #include <stdlib.h> #include <console/console.h> diff --git a/src/mainboard/arima/hdama/romstage.c b/src/mainboard/arima/hdama/romstage.c index 84dc7a3..4df8416 100644 --- a/src/mainboard/arima/hdama/romstage.c +++ b/src/mainboard/arima/hdama/romstage.c @@ -3,7 +3,6 @@ #include <device/pci_def.h> #include <arch/io.h> #include <device/pnp_def.h> -#include <arch/romcc_io.h> #include <pc80/mc146818rtc.h> #include <console/console.h> #include <cpu/amd/model_fxx_rev.h> diff --git a/src/mainboard/artecgroup/dbe61/romstage.c b/src/mainboard/artecgroup/dbe61/romstage.c index 8eec1fa..135daec 100644 --- a/src/mainboard/artecgroup/dbe61/romstage.c +++ b/src/mainboard/artecgroup/dbe61/romstage.c @@ -22,7 +22,6 @@ #include <device/pci_def.h> #include <arch/io.h> #include <device/pnp_def.h> -#include <arch/romcc_io.h> #include <arch/hlt.h> #include <stdlib.h> #include <console/console.h> diff --git a/src/mainboard/asi/mb_5blgp/romstage.c b/src/mainboard/asi/mb_5blgp/romstage.c index 327856b..d661387 100644 --- a/src/mainboard/asi/mb_5blgp/romstage.c +++ b/src/mainboard/asi/mb_5blgp/romstage.c @@ -21,7 +21,6 @@ #include <stdint.h> #include <arch/io.h> #include <device/pnp_def.h> -#include <arch/romcc_io.h> #include <arch/hlt.h> #include <console/console.h> #include "northbridge/amd/gx1/raminit.c" diff --git a/src/mainboard/asi/mb_5blmp/romstage.c b/src/mainboard/asi/mb_5blmp/romstage.c index abb137d..e8befe4 100644 --- a/src/mainboard/asi/mb_5blmp/romstage.c +++ b/src/mainboard/asi/mb_5blmp/romstage.c @@ -22,7 +22,6 @@ #include <device/pci_def.h> #include <arch/io.h> #include <device/pnp_def.h> -#include <arch/romcc_io.h> #include <arch/hlt.h> #include <console/console.h> #include "northbridge/amd/gx1/raminit.c" diff --git a/src/mainboard/asrock/939a785gmh/romstage.c b/src/mainboard/asrock/939a785gmh/romstage.c index 46b6ab0..74a5412 100644 --- a/src/mainboard/asrock/939a785gmh/romstage.c +++ b/src/mainboard/asrock/939a785gmh/romstage.c @@ -28,7 +28,6 @@ #include <device/pci_def.h> #include <arch/io.h> #include <device/pnp_def.h> -#include <arch/romcc_io.h> #include <cpu/x86/lapic.h> #include <pc80/mc146818rtc.h> #include <console/console.h> diff --git a/src/mainboard/asrock/e350m1/reset.c b/src/mainboard/asrock/e350m1/reset.c index 5958e77..bb2482b 100644 --- a/src/mainboard/asrock/e350m1/reset.c +++ b/src/mainboard/asrock/e350m1/reset.c @@ -17,10 +17,11 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ - +#ifndef __PRE_RAM__ +#define __PRE_RAM__ // Use simple device model for this file even in ramstage +#endif +#include <arch/io.h> #include <reset.h> -#include <arch/io.h> /*inb, outb*/ -#include <arch/romcc_io.h> /*pci_read_config32, device_t, PCI_DEV*/ #define HT_INIT_CONTROL 0x6C #define HTIC_BIOSR_Detect (1<<5) diff --git a/src/mainboard/asrock/e350m1/romstage.c b/src/mainboard/asrock/e350m1/romstage.c index 3a1e7aa..79f963b 100644 --- a/src/mainboard/asrock/e350m1/romstage.c +++ b/src/mainboard/asrock/e350m1/romstage.c @@ -24,7 +24,6 @@ #include <arch/io.h> #include <arch/stages.h> #include <device/pnp_def.h> -#include <arch/romcc_io.h> #include <arch/cpu.h> #include <cpu/x86/lapic.h> #include <console/console.h> diff --git a/src/mainboard/asus/a8n_e/romstage.c b/src/mainboard/asus/a8n_e/romstage.c index a9ab944..2d041b2 100644 --- a/src/mainboard/asus/a8n_e/romstage.c +++ b/src/mainboard/asus/a8n_e/romstage.c @@ -29,7 +29,6 @@ #include <device/pci_def.h> #include <arch/io.h> #include <device/pnp_def.h> -#include <arch/romcc_io.h> #include <cpu/x86/lapic.h> #include <pc80/mc146818rtc.h> #include "cpu/x86/lapic/boot_cpu.c" diff --git a/src/mainboard/asus/a8v-e_deluxe/romstage.c b/src/mainboard/asus/a8v-e_deluxe/romstage.c index 7441715..2219ff9 100644 --- a/src/mainboard/asus/a8v-e_deluxe/romstage.c +++ b/src/mainboard/asus/a8v-e_deluxe/romstage.c @@ -29,7 +29,6 @@ unsigned int get_sbdn(unsigned bus); #include <device/pci_def.h> #include <arch/io.h> #include <device/pnp_def.h> -#include <arch/romcc_io.h> #include <cpu/x86/lapic.h> #include <pc80/mc146818rtc.h> #include <console/console.h> diff --git a/src/mainboard/asus/a8v-e_se/romstage.c b/src/mainboard/asus/a8v-e_se/romstage.c index bb70a21..f4df332 100644 --- a/src/mainboard/asus/a8v-e_se/romstage.c +++ b/src/mainboard/asus/a8v-e_se/romstage.c @@ -29,7 +29,6 @@ unsigned int get_sbdn(unsigned bus); #include <device/pci_def.h> #include <arch/io.h> #include <device/pnp_def.h> -#include <arch/romcc_io.h> #include <cpu/x86/lapic.h> #include <pc80/mc146818rtc.h> #include <console/console.h> diff --git a/src/mainboard/asus/dsbf/romstage.c b/src/mainboard/asus/dsbf/romstage.c index 5251025..cb63f45 100644 --- a/src/mainboard/asus/dsbf/romstage.c +++ b/src/mainboard/asus/dsbf/romstage.c @@ -23,7 +23,6 @@ #include <stdint.h> #include <string.h> #include <arch/io.h> -#include <arch/romcc_io.h> #include <device/pci_def.h> #include <device/pnp_def.h> #include <cpu/x86/lapic.h> diff --git a/src/mainboard/asus/k8v-x/romstage.c b/src/mainboard/asus/k8v-x/romstage.c index 0cfdec8..ca6f4ca 100644 --- a/src/mainboard/asus/k8v-x/romstage.c +++ b/src/mainboard/asus/k8v-x/romstage.c @@ -29,7 +29,6 @@ unsigned int get_sbdn(unsigned bus); #include <device/pci_def.h> #include <arch/io.h> #include <device/pnp_def.h> -#include <arch/romcc_io.h> #include <cpu/x86/lapic.h> #include <pc80/mc146818rtc.h> #include <console/console.h> diff --git a/src/mainboard/asus/m2n-e/romstage.c b/src/mainboard/asus/m2n-e/romstage.c index bf81178..e534d48 100644 --- a/src/mainboard/asus/m2n-e/romstage.c +++ b/src/mainboard/asus/m2n-e/romstage.c @@ -30,7 +30,6 @@ #include <device/pci_ids.h> #include <arch/io.h> #include <device/pnp_def.h> -#include <arch/romcc_io.h> #include <cpu/x86/lapic.h> #include <pc80/mc146818rtc.h> #include <console/console.h> diff --git a/src/mainboard/asus/m2v-mx_se/romstage.c b/src/mainboard/asus/m2v-mx_se/romstage.c index 9e1ba92..dc60a6e 100644 --- a/src/mainboard/asus/m2v-mx_se/romstage.c +++ b/src/mainboard/asus/m2v-mx_se/romstage.c @@ -33,7 +33,6 @@ unsigned int get_sbdn(unsigned bus); #include <device/pci_def.h> #include <arch/io.h> #include <device/pnp_def.h> -#include <arch/romcc_io.h> #include <cpu/amd/mtrr.h> #include <cpu/x86/lapic.h> #include <pc80/mc146818rtc.h> diff --git a/src/mainboard/asus/m2v/romstage.c b/src/mainboard/asus/m2v/romstage.c index db6cfe4..509df90 100644 --- a/src/mainboard/asus/m2v/romstage.c +++ b/src/mainboard/asus/m2v/romstage.c @@ -33,7 +33,6 @@ unsigned int get_sbdn(unsigned bus); #include <device/pci_def.h> #include <arch/io.h> #include <device/pnp_def.h> -#include <arch/romcc_io.h> #include <cpu/amd/mtrr.h> #include <cpu/x86/lapic.h> #include <pc80/mc146818rtc.h> diff --git a/src/mainboard/asus/m4a78-em/romstage.c b/src/mainboard/asus/m4a78-em/romstage.c index 633cb50..3e8dad8 100644 --- a/src/mainboard/asus/m4a78-em/romstage.c +++ b/src/mainboard/asus/m4a78-em/romstage.c @@ -31,7 +31,6 @@ #include <device/pci_ids.h> #include <arch/io.h> #include <device/pnp_def.h> -#include <arch/romcc_io.h> #include <cpu/x86/lapic.h> #include <console/console.h> #include <cpu/amd/model_10xxx_rev.h> diff --git a/src/mainboard/asus/m4a785-m/romstage.c b/src/mainboard/asus/m4a785-m/romstage.c index f1b6314..a42b5dd 100644 --- a/src/mainboard/asus/m4a785-m/romstage.c +++ b/src/mainboard/asus/m4a785-m/romstage.c @@ -31,7 +31,6 @@ #include <device/pci_ids.h> #include <arch/io.h> #include <device/pnp_def.h> -#include <arch/romcc_io.h> #include <cpu/x86/lapic.h> #include <console/console.h> #include <cpu/amd/model_10xxx_rev.h> diff --git a/src/mainboard/asus/m5a88-v/reset.c b/src/mainboard/asus/m5a88-v/reset.c index 3ce182e..678bc3d 100644 --- a/src/mainboard/asus/m5a88-v/reset.c +++ b/src/mainboard/asus/m5a88-v/reset.c @@ -17,9 +17,11 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#include <reset.h> +#ifndef __PRE_RAM__ +#define __PRE_RAM__ // Use simple device model for this file even in ramstage +#endif #include <arch/io.h> -#include <arch/romcc_io.h> +#include <reset.h> #define HT_INIT_CONTROL 0x6C #define HTIC_BIOSR_Detect (1<<5) diff --git a/src/mainboard/asus/m5a88-v/romstage.c b/src/mainboard/asus/m5a88-v/romstage.c index 87dbdb8..dbae2d3 100644 --- a/src/mainboard/asus/m5a88-v/romstage.c +++ b/src/mainboard/asus/m5a88-v/romstage.c @@ -32,7 +32,6 @@ #include <device/pci_ids.h> #include <arch/io.h> #include <device/pnp_def.h> -#include <arch/romcc_io.h> #include <cpu/x86/lapic.h> #include <console/console.h> #include <cpu/amd/model_10xxx_rev.h> diff --git a/src/mainboard/asus/p2b-d/romstage.c b/src/mainboard/asus/p2b-d/romstage.c index a51e92b..213120d 100644 --- a/src/mainboard/asus/p2b-d/romstage.c +++ b/src/mainboard/asus/p2b-d/romstage.c @@ -22,7 +22,6 @@ #include <device/pci_def.h> #include <arch/io.h> #include <device/pnp_def.h> -#include <arch/romcc_io.h> #include <arch/hlt.h> #include <stdlib.h> #include <console/console.h> diff --git a/src/mainboard/asus/p2b-ds/romstage.c b/src/mainboard/asus/p2b-ds/romstage.c index 221c8c4..20c4b3f 100644 --- a/src/mainboard/asus/p2b-ds/romstage.c +++ b/src/mainboard/asus/p2b-ds/romstage.c @@ -22,7 +22,6 @@ #include <device/pci_def.h> #include <arch/io.h> #include <device/pnp_def.h> -#include <arch/romcc_io.h> #include <arch/hlt.h> #include <stdlib.h> #include <console/console.h> diff --git a/src/mainboard/asus/p2b-f/romstage.c b/src/mainboard/asus/p2b-f/romstage.c index 88be10c..93849c2 100644 --- a/src/mainboard/asus/p2b-f/romstage.c +++ b/src/mainboard/asus/p2b-f/romstage.c @@ -22,7 +22,6 @@ #include <device/pci_def.h> #include <arch/io.h> #include <device/pnp_def.h> -#include <arch/romcc_io.h> #include <arch/hlt.h> #include <stdlib.h> #include <console/console.h> diff --git a/src/mainboard/asus/p2b-ls/romstage.c b/src/mainboard/asus/p2b-ls/romstage.c index 0e4bfa9..f6daa5e 100644 --- a/src/mainboard/asus/p2b-ls/romstage.c +++ b/src/mainboard/asus/p2b-ls/romstage.c @@ -22,7 +22,6 @@ #include <device/pci_def.h> #include <arch/io.h> #include <device/pnp_def.h> -#include <arch/romcc_io.h> #include <arch/hlt.h> #include <stdlib.h> #include <console/console.h> diff --git a/src/mainboard/asus/p2b/romstage.c b/src/mainboard/asus/p2b/romstage.c index e8880de..63d34b2 100644 --- a/src/mainboard/asus/p2b/romstage.c +++ b/src/mainboard/asus/p2b/romstage.c @@ -22,7 +22,6 @@ #include <device/pci_def.h> #include <arch/io.h> #include <device/pnp_def.h> -#include <arch/romcc_io.h> #include <arch/hlt.h> #include <stdlib.h> #include <console/console.h> diff --git a/src/mainboard/asus/p3b-f/romstage.c b/src/mainboard/asus/p3b-f/romstage.c index 7e8ba57..3762948 100644 --- a/src/mainboard/asus/p3b-f/romstage.c +++ b/src/mainboard/asus/p3b-f/romstage.c @@ -22,7 +22,6 @@ #include <device/pci_def.h> #include <arch/io.h> #include <device/pnp_def.h> -#include <arch/romcc_io.h> #include <arch/hlt.h> #include <stdlib.h> #include <console/console.h> diff --git a/src/mainboard/avalue/eax-785e/reset.c b/src/mainboard/avalue/eax-785e/reset.c index 3ce182e..678bc3d 100644 --- a/src/mainboard/avalue/eax-785e/reset.c +++ b/src/mainboard/avalue/eax-785e/reset.c @@ -17,9 +17,11 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#include <reset.h> +#ifndef __PRE_RAM__ +#define __PRE_RAM__ // Use simple device model for this file even in ramstage +#endif #include <arch/io.h> -#include <arch/romcc_io.h> +#include <reset.h> #define HT_INIT_CONTROL 0x6C #define HTIC_BIOSR_Detect (1<<5) diff --git a/src/mainboard/avalue/eax-785e/romstage.c b/src/mainboard/avalue/eax-785e/romstage.c index 902c730..d4704e8 100644 --- a/src/mainboard/avalue/eax-785e/romstage.c +++ b/src/mainboard/avalue/eax-785e/romstage.c @@ -32,7 +32,6 @@ #include <device/pci_ids.h> #include <arch/io.h> #include <device/pnp_def.h> -#include <arch/romcc_io.h> #include <cpu/x86/lapic.h> #include <console/console.h> #include <cpu/amd/model_10xxx_rev.h> diff --git a/src/mainboard/axus/tc320/romstage.c b/src/mainboard/axus/tc320/romstage.c index e887a29..053da17 100644 --- a/src/mainboard/axus/tc320/romstage.c +++ b/src/mainboard/axus/tc320/romstage.c @@ -22,7 +22,6 @@ #include <device/pci_def.h> #include <arch/io.h> #include <device/pnp_def.h> -#include <arch/romcc_io.h> #include <arch/hlt.h> #include <console/console.h> #include "northbridge/amd/gx1/raminit.c" diff --git a/src/mainboard/azza/pt-6ibd/romstage.c b/src/mainboard/azza/pt-6ibd/romstage.c index f386440..c138d00 100644 --- a/src/mainboard/azza/pt-6ibd/romstage.c +++ b/src/mainboard/azza/pt-6ibd/romstage.c @@ -22,7 +22,6 @@ #include <device/pci_def.h> #include <arch/io.h> #include <device/pnp_def.h> -#include <arch/romcc_io.h> #include <arch/hlt.h> #include <stdlib.h> #include <console/console.h> diff --git a/src/mainboard/bcom/winnet100/romstage.c b/src/mainboard/bcom/winnet100/romstage.c index e887a29..053da17 100644 --- a/src/mainboard/bcom/winnet100/romstage.c +++ b/src/mainboard/bcom/winnet100/romstage.c @@ -22,7 +22,6 @@ #include <device/pci_def.h> #include <arch/io.h> #include <device/pnp_def.h> -#include <arch/romcc_io.h> #include <arch/hlt.h> #include <console/console.h> #include "northbridge/amd/gx1/raminit.c" diff --git a/src/mainboard/bcom/winnetp680/romstage.c b/src/mainboard/bcom/winnetp680/romstage.c index fa8f548..a57f9f7 100644 --- a/src/mainboard/bcom/winnetp680/romstage.c +++ b/src/mainboard/bcom/winnetp680/romstage.c @@ -24,7 +24,6 @@ #include <device/pci_ids.h> #include <arch/io.h> #include <device/pnp_def.h> -#include <arch/romcc_io.h> #include <arch/hlt.h> #include <console/console.h> #include "northbridge/via/cn700/raminit.h" diff --git a/src/mainboard/bifferos/bifferboard/romstage.c b/src/mainboard/bifferos/bifferboard/romstage.c index e2be9b3..cdf2544 100644 --- a/src/mainboard/bifferos/bifferboard/romstage.c +++ b/src/mainboard/bifferos/bifferboard/romstage.c @@ -22,7 +22,6 @@ #include <device/pci_ids.h> #include <arch/io.h> #include <device/pnp_def.h> -#include <arch/romcc_io.h> #include <arch/hlt.h> #include <pc80/mc146818rtc.h> #include <console/console.h> diff --git a/src/mainboard/biostar/m6tba/romstage.c b/src/mainboard/biostar/m6tba/romstage.c index ac3ea6c..029e21b 100644 --- a/src/mainboard/biostar/m6tba/romstage.c +++ b/src/mainboard/biostar/m6tba/romstage.c @@ -22,7 +22,6 @@ #include <device/pci_def.h> #include <arch/io.h> #include <device/pnp_def.h> -#include <arch/romcc_io.h> #include <arch/hlt.h> #include <stdlib.h> #include <console/console.h> diff --git a/src/mainboard/broadcom/blast/romstage.c b/src/mainboard/broadcom/blast/romstage.c index 4bf421c..f57e141 100644 --- a/src/mainboard/broadcom/blast/romstage.c +++ b/src/mainboard/broadcom/blast/romstage.c @@ -3,7 +3,6 @@ #include <device/pci_def.h> #include <arch/io.h> #include <device/pnp_def.h> -#include <arch/romcc_io.h> #include <cpu/x86/lapic.h> #include <pc80/mc146818rtc.h> #include <console/console.h> diff --git a/src/mainboard/compaq/deskpro_en_sff_p600/romstage.c b/src/mainboard/compaq/deskpro_en_sff_p600/romstage.c index 9d75f16..37b28df 100644 --- a/src/mainboard/compaq/deskpro_en_sff_p600/romstage.c +++ b/src/mainboard/compaq/deskpro_en_sff_p600/romstage.c @@ -22,7 +22,6 @@ #include <device/pci_def.h> #include <arch/io.h> #include <device/pnp_def.h> -#include <arch/romcc_io.h> #include <arch/hlt.h> #include <stdlib.h> #include <console/console.h> diff --git a/src/mainboard/digitallogic/adl855pc/romstage.c b/src/mainboard/digitallogic/adl855pc/romstage.c index e5c7917..7eefedd 100644 --- a/src/mainboard/digitallogic/adl855pc/romstage.c +++ b/src/mainboard/digitallogic/adl855pc/romstage.c @@ -2,7 +2,6 @@ #include <device/pci_def.h> #include <arch/io.h> #include <device/pnp_def.h> -#include <arch/romcc_io.h> #include <arch/hlt.h> #include <stdlib.h> #include <lib.h> diff --git a/src/mainboard/digitallogic/msm586seg/romstage.c b/src/mainboard/digitallogic/msm586seg/romstage.c index a293842..9f3da08 100644 --- a/src/mainboard/digitallogic/msm586seg/romstage.c +++ b/src/mainboard/digitallogic/msm586seg/romstage.c @@ -2,7 +2,6 @@ #include <device/pci_def.h> #include <arch/io.h> #include <device/pnp_def.h> -#include <arch/romcc_io.h> #include <arch/hlt.h> #include <pc80/mc146818rtc.h> #include <console/console.h> diff --git a/src/mainboard/digitallogic/msm800sev/romstage.c b/src/mainboard/digitallogic/msm800sev/romstage.c index caafd2f..da16c99 100644 --- a/src/mainboard/digitallogic/msm800sev/romstage.c +++ b/src/mainboard/digitallogic/msm800sev/romstage.c @@ -3,7 +3,6 @@ #include <device/pci_def.h> #include <arch/io.h> #include <device/pnp_def.h> -#include <arch/romcc_io.h> #include <arch/hlt.h> #include <console/console.h> #include "cpu/x86/bist.h" diff --git a/src/mainboard/eaglelion/5bcm/romstage.c b/src/mainboard/eaglelion/5bcm/romstage.c index f1ee25d..2f803aa 100644 --- a/src/mainboard/eaglelion/5bcm/romstage.c +++ b/src/mainboard/eaglelion/5bcm/romstage.c @@ -2,7 +2,6 @@ #include <device/pci_def.h> #include <arch/io.h> #include <device/pnp_def.h> -#include <arch/romcc_io.h> #include <arch/hlt.h> #include <stdlib.h> #include <console/console.h> diff --git a/src/mainboard/emulation/qemu-x86/romstage.c b/src/mainboard/emulation/qemu-x86/romstage.c index e5107db..3faf947 100644 --- a/src/mainboard/emulation/qemu-x86/romstage.c +++ b/src/mainboard/emulation/qemu-x86/romstage.c @@ -22,7 +22,6 @@ #include <device/pci_ids.h> #include <arch/io.h> #include <device/pnp_def.h> -#include <arch/romcc_io.h> #include <arch/hlt.h> #include <pc80/mc146818rtc.h> #include <console/console.h> diff --git a/src/mainboard/getac/p470/romstage.c b/src/mainboard/getac/p470/romstage.c index 90fc25f..90d38eb 100644 --- a/src/mainboard/getac/p470/romstage.c +++ b/src/mainboard/getac/p470/romstage.c @@ -22,7 +22,6 @@ #include <stdint.h> #include <string.h> #include <arch/io.h> -#include <arch/romcc_io.h> #include <device/pci_def.h> #include <device/pnp_def.h> #include <cpu/x86/lapic.h> diff --git a/src/mainboard/getac/p470/smihandler.c b/src/mainboard/getac/p470/smihandler.c index 4a5a3ff..6122c82 100644 --- a/src/mainboard/getac/p470/smihandler.c +++ b/src/mainboard/getac/p470/smihandler.c @@ -20,7 +20,6 @@ */ #include <arch/io.h> -#include <arch/romcc_io.h> #include <console/console.h> #include <cpu/x86/smm.h> #include "southbridge/intel/i82801gx/i82801gx.h" diff --git a/src/mainboard/gigabyte/ga-6bxc/romstage.c b/src/mainboard/gigabyte/ga-6bxc/romstage.c index 8fe0de6..89761c9 100644 --- a/src/mainboard/gigabyte/ga-6bxc/romstage.c +++ b/src/mainboard/gigabyte/ga-6bxc/romstage.c @@ -22,7 +22,6 @@ #include <device/pci_def.h> #include <arch/io.h> #include <device/pnp_def.h> -#include <arch/romcc_io.h> #include <arch/hlt.h> #include <stdlib.h> #include <console/console.h> diff --git a/src/mainboard/gigabyte/ga-6bxe/romstage.c b/src/mainboard/gigabyte/ga-6bxe/romstage.c index 2f5cb89..85a899a 100644 --- a/src/mainboard/gigabyte/ga-6bxe/romstage.c +++ b/src/mainboard/gigabyte/ga-6bxe/romstage.c @@ -22,7 +22,6 @@ #include <device/pci_def.h> #include <arch/io.h> #include <device/pnp_def.h> -#include <arch/romcc_io.h> #include <arch/hlt.h> #include <stdlib.h> #include <console/console.h> diff --git a/src/mainboard/gigabyte/ga_2761gxdk/ap_romstage.c b/src/mainboard/gigabyte/ga_2761gxdk/ap_romstage.c index f4be1a5..9def81d 100644 --- a/src/mainboard/gigabyte/ga_2761gxdk/ap_romstage.c +++ b/src/mainboard/gigabyte/ga_2761gxdk/ap_romstage.c @@ -28,7 +28,6 @@ #include <device/pci_ids.h> #include <arch/io.h> #include <device/pnp_def.h> -#include <arch/romcc_io.h> #include <cpu/x86/lapic.h> #include <pc80/mc146818rtc.h> diff --git a/src/mainboard/gigabyte/ga_2761gxdk/romstage.c b/src/mainboard/gigabyte/ga_2761gxdk/romstage.c index 838f602..07ef567 100644 --- a/src/mainboard/gigabyte/ga_2761gxdk/romstage.c +++ b/src/mainboard/gigabyte/ga_2761gxdk/romstage.c @@ -31,7 +31,6 @@ #include <device/pci_ids.h> #include <arch/io.h> #include <device/pnp_def.h> -#include <arch/romcc_io.h> #include <cpu/x86/lapic.h> #include <pc80/mc146818rtc.h> #include <console/console.h> diff --git a/src/mainboard/gigabyte/m57sli/ap_romstage.c b/src/mainboard/gigabyte/m57sli/ap_romstage.c index d6a5778..df00eed 100644 --- a/src/mainboard/gigabyte/m57sli/ap_romstage.c +++ b/src/mainboard/gigabyte/m57sli/ap_romstage.c @@ -26,7 +26,6 @@ #include <device/pci_ids.h> #include <arch/io.h> #include <device/pnp_def.h> -#include <arch/romcc_io.h> #include <cpu/x86/lapic.h> #include <pc80/mc146818rtc.h> diff --git a/src/mainboard/gigabyte/m57sli/romstage.c b/src/mainboard/gigabyte/m57sli/romstage.c index 1168a17..97bb3bb 100644 --- a/src/mainboard/gigabyte/m57sli/romstage.c +++ b/src/mainboard/gigabyte/m57sli/romstage.c @@ -29,7 +29,6 @@ #include <device/pci_ids.h> #include <arch/io.h> #include <device/pnp_def.h> -#include <arch/romcc_io.h> #include <cpu/x86/lapic.h> #include <pc80/mc146818rtc.h> #include <console/console.h> diff --git a/src/mainboard/gigabyte/ma785gm/romstage.c b/src/mainboard/gigabyte/ma785gm/romstage.c index d7a6aee..f7821f6 100644 --- a/src/mainboard/gigabyte/ma785gm/romstage.c +++ b/src/mainboard/gigabyte/ma785gm/romstage.c @@ -27,7 +27,6 @@ #include <device/pci_ids.h> #include <arch/io.h> #include <device/pnp_def.h> -#include <arch/romcc_io.h> #include <cpu/x86/lapic.h> #include <console/console.h> #include <cpu/amd/model_10xxx_rev.h> diff --git a/src/mainboard/gigabyte/ma785gmt/romstage.c b/src/mainboard/gigabyte/ma785gmt/romstage.c index d7a6aee..f7821f6 100644 --- a/src/mainboard/gigabyte/ma785gmt/romstage.c +++ b/src/mainboard/gigabyte/ma785gmt/romstage.c @@ -27,7 +27,6 @@ #include <device/pci_ids.h> #include <arch/io.h> #include <device/pnp_def.h> -#include <arch/romcc_io.h> #include <cpu/x86/lapic.h> #include <console/console.h> #include <cpu/amd/model_10xxx_rev.h> diff --git a/src/mainboard/gigabyte/ma78gm/romstage.c b/src/mainboard/gigabyte/ma78gm/romstage.c index c90f4e0..f097227 100644 --- a/src/mainboard/gigabyte/ma78gm/romstage.c +++ b/src/mainboard/gigabyte/ma78gm/romstage.c @@ -31,7 +31,6 @@ #include <device/pci_ids.h> #include <arch/io.h> #include <device/pnp_def.h> -#include <arch/romcc_io.h> #include <cpu/x86/lapic.h> #include <console/console.h> #include <cpu/amd/model_10xxx_rev.h> diff --git a/src/mainboard/google/butterfly/chromeos.c b/src/mainboard/google/butterfly/chromeos.c index 41abd95..9821a2f 100644 --- a/src/mainboard/google/butterfly/chromeos.c +++ b/src/mainboard/google/butterfly/chromeos.c @@ -21,12 +21,8 @@ #include <string.h> #include <vendorcode/google/chromeos/chromeos.h> #include <arch/io.h> -#ifdef __PRE_RAM__ -#include <arch/romcc_io.h> -#else #include <device/device.h> #include <device/pci.h> -#endif #include <southbridge/intel/bd82x6x/pch.h> #include <ec/quanta/ene_kb3940q/ec.h> diff --git a/src/mainboard/google/butterfly/mainboard_smi.c b/src/mainboard/google/butterfly/mainboard_smi.c index 4e02a3c..e2f00e1 100644 --- a/src/mainboard/google/butterfly/mainboard_smi.c +++ b/src/mainboard/google/butterfly/mainboard_smi.c @@ -18,7 +18,6 @@ */ #include <arch/io.h> -#include <arch/romcc_io.h> #include <console/console.h> #include <cpu/x86/smm.h> #include <southbridge/intel/bd82x6x/nvs.h> diff --git a/src/mainboard/google/butterfly/romstage.c b/src/mainboard/google/butterfly/romstage.c index 13cd454..5e2b713 100644 --- a/src/mainboard/google/butterfly/romstage.c +++ b/src/mainboard/google/butterfly/romstage.c @@ -24,7 +24,6 @@ #include <timestamp.h> #include <arch/byteorder.h> #include <arch/io.h> -#include <arch/romcc_io.h> #include <device/pci_def.h> #include <device/pnp_def.h> #include <cpu/x86/lapic.h> diff --git a/src/mainboard/google/link/chromeos.c b/src/mainboard/google/link/chromeos.c index 04f68a9..4ab5017 100644 --- a/src/mainboard/google/link/chromeos.c +++ b/src/mainboard/google/link/chromeos.c @@ -20,12 +20,8 @@ #include <string.h> #include <vendorcode/google/chromeos/chromeos.h> #include <arch/io.h> -#ifdef __PRE_RAM__ -#include <arch/romcc_io.h> -#else #include <device/device.h> #include <device/pci.h> -#endif #include <southbridge/intel/bd82x6x/pch.h> #include "ec.h" #include <ec/google/chromeec/ec.h> diff --git a/src/mainboard/google/link/mainboard_smi.c b/src/mainboard/google/link/mainboard_smi.c index 54cfb01..a4c4a50 100644 --- a/src/mainboard/google/link/mainboard_smi.c +++ b/src/mainboard/google/link/mainboard_smi.c @@ -18,7 +18,6 @@ */ #include <arch/io.h> -#include <arch/romcc_io.h> #include <console/console.h> #include <cpu/x86/smm.h> #include <southbridge/intel/bd82x6x/nvs.h> diff --git a/src/mainboard/google/link/romstage.c b/src/mainboard/google/link/romstage.c index 689d2b5..f20a722 100644 --- a/src/mainboard/google/link/romstage.c +++ b/src/mainboard/google/link/romstage.c @@ -24,7 +24,6 @@ #include <timestamp.h> #include <arch/byteorder.h> #include <arch/io.h> -#include <arch/romcc_io.h> #include <device/pci.h> #include <device/pci_def.h> #include <device/pnp_def.h> diff --git a/src/mainboard/google/parrot/chromeos.c b/src/mainboard/google/parrot/chromeos.c index d4054ef..5e4549d 100644 --- a/src/mainboard/google/parrot/chromeos.c +++ b/src/mainboard/google/parrot/chromeos.c @@ -21,13 +21,8 @@ #include <string.h> #include <vendorcode/google/chromeos/chromeos.h> #include <arch/io.h> - -#ifdef __PRE_RAM__ -#include <arch/romcc_io.h> -#else #include <device/device.h> #include <device/pci.h> -#endif #include <southbridge/intel/bd82x6x/pch.h> #include <ec/compal/ene932/ec.h> diff --git a/src/mainboard/google/parrot/romstage.c b/src/mainboard/google/parrot/romstage.c index fc14b9b..9968226 100644 --- a/src/mainboard/google/parrot/romstage.c +++ b/src/mainboard/google/parrot/romstage.c @@ -24,7 +24,6 @@ #include <timestamp.h> #include <arch/byteorder.h> #include <arch/io.h> -#include <arch/romcc_io.h> #include <device/pci_def.h> #include <device/pnp_def.h> #include <cpu/x86/lapic.h> diff --git a/src/mainboard/google/parrot/smihandler.c b/src/mainboard/google/parrot/smihandler.c index 6f83fd8..a5f6ba2 100644 --- a/src/mainboard/google/parrot/smihandler.c +++ b/src/mainboard/google/parrot/smihandler.c @@ -18,7 +18,6 @@ */ #include <arch/io.h> -#include <arch/romcc_io.h> #include <console/console.h> #include <cpu/x86/smm.h> #include <southbridge/intel/bd82x6x/nvs.h> diff --git a/src/mainboard/google/stout/chromeos.c b/src/mainboard/google/stout/chromeos.c index db94cb7..8c8f348 100644 --- a/src/mainboard/google/stout/chromeos.c +++ b/src/mainboard/google/stout/chromeos.c @@ -21,12 +21,8 @@ #include <vendorcode/google/chromeos/chromeos.h> #include <arch/io.h> #include <console/console.h> -#ifdef __PRE_RAM__ -#include <arch/romcc_io.h> -#else #include <device/device.h> #include <device/pci.h> -#endif #include <southbridge/intel/bd82x6x/pch.h> #include "ec.h" diff --git a/src/mainboard/google/stout/mainboard_smi.c b/src/mainboard/google/stout/mainboard_smi.c index f6663de..7981046 100644 --- a/src/mainboard/google/stout/mainboard_smi.c +++ b/src/mainboard/google/stout/mainboard_smi.c @@ -18,7 +18,6 @@ */ #include <arch/io.h> -#include <arch/romcc_io.h> #include <console/console.h> #include <cpu/x86/smm.h> #include <southbridge/intel/bd82x6x/nvs.h> diff --git a/src/mainboard/google/stout/romstage.c b/src/mainboard/google/stout/romstage.c index 2f4e1a7..14820dd 100644 --- a/src/mainboard/google/stout/romstage.c +++ b/src/mainboard/google/stout/romstage.c @@ -24,7 +24,6 @@ #include <timestamp.h> #include <arch/byteorder.h> #include <arch/io.h> -#include <arch/romcc_io.h> #include <device/pci_def.h> #include <device/pnp_def.h> #include <cpu/x86/lapic.h> diff --git a/src/mainboard/hp/dl145_g1/romstage.c b/src/mainboard/hp/dl145_g1/romstage.c index 60ffb19..0ae744f 100644 --- a/src/mainboard/hp/dl145_g1/romstage.c +++ b/src/mainboard/hp/dl145_g1/romstage.c @@ -4,7 +4,6 @@ #include <device/pci_ids.h> #include <arch/io.h> #include <device/pnp_def.h> -#include <arch/romcc_io.h> #include <pc80/mc146818rtc.h> #include <console/console.h> #include <cpu/amd/model_fxx_rev.h> diff --git a/src/mainboard/hp/dl145_g3/romstage.c b/src/mainboard/hp/dl145_g3/romstage.c index 9cd25cf..ff20289 100644 --- a/src/mainboard/hp/dl145_g3/romstage.c +++ b/src/mainboard/hp/dl145_g3/romstage.c @@ -35,7 +35,6 @@ #include <device/pci_ids.h> #include <arch/io.h> #include <device/pnp_def.h> -#include <arch/romcc_io.h> #include <cpu/x86/lapic.h> #include <pc80/mc146818rtc.h> #include <console/console.h> diff --git a/src/mainboard/hp/dl165_g6_fam10/romstage.c b/src/mainboard/hp/dl165_g6_fam10/romstage.c index ac624c0..2f78cbd 100644 --- a/src/mainboard/hp/dl165_g6_fam10/romstage.c +++ b/src/mainboard/hp/dl165_g6_fam10/romstage.c @@ -34,7 +34,6 @@ #include <device/pci_ids.h> #include <arch/io.h> #include <device/pnp_def.h> -#include <arch/romcc_io.h> #include <cpu/x86/lapic.h> #include "option_table.h" #include <console/console.h> diff --git a/src/mainboard/hp/e_vectra_p2706t/romstage.c b/src/mainboard/hp/e_vectra_p2706t/romstage.c index ce3a95a..81e1ad2 100644 --- a/src/mainboard/hp/e_vectra_p2706t/romstage.c +++ b/src/mainboard/hp/e_vectra_p2706t/romstage.c @@ -22,7 +22,6 @@ #include <device/pci_def.h> #include <arch/io.h> #include <device/pnp_def.h> -#include <arch/romcc_io.h> #include <arch/hlt.h> #include <stdlib.h> #include <console/console.h> diff --git a/src/mainboard/ibase/mb899/romstage.c b/src/mainboard/ibase/mb899/romstage.c index 148587d..79eaa0b 100644 --- a/src/mainboard/ibase/mb899/romstage.c +++ b/src/mainboard/ibase/mb899/romstage.c @@ -22,7 +22,6 @@ #include <stdint.h> #include <string.h> #include <arch/io.h> -#include <arch/romcc_io.h> #include <device/pci_def.h> #include <device/pnp_def.h> #include <cpu/x86/lapic.h> diff --git a/src/mainboard/ibase/mb899/smihandler.c b/src/mainboard/ibase/mb899/smihandler.c index 3e3bee7..064109b 100644 --- a/src/mainboard/ibase/mb899/smihandler.c +++ b/src/mainboard/ibase/mb899/smihandler.c @@ -18,7 +18,6 @@ */ #include <arch/io.h> -#include <arch/romcc_io.h> #include <console/console.h> #include <cpu/x86/smm.h> #include "southbridge/intel/i82801gx/nvs.h" diff --git a/src/mainboard/ibm/e325/romstage.c b/src/mainboard/ibm/e325/romstage.c index e5b315a..e4dea5f 100644 --- a/src/mainboard/ibm/e325/romstage.c +++ b/src/mainboard/ibm/e325/romstage.c @@ -3,7 +3,6 @@ #include <device/pci_def.h> #include <arch/io.h> #include <device/pnp_def.h> -#include <arch/romcc_io.h> #include <stdlib.h> #include <pc80/mc146818rtc.h> #include <console/console.h> diff --git a/src/mainboard/ibm/e326/romstage.c b/src/mainboard/ibm/e326/romstage.c index b4dddd5..3462fcb 100644 --- a/src/mainboard/ibm/e326/romstage.c +++ b/src/mainboard/ibm/e326/romstage.c @@ -3,7 +3,6 @@ #include <device/pci_def.h> #include <arch/io.h> #include <device/pnp_def.h> -#include <arch/romcc_io.h> #include <stdlib.h> #include <pc80/mc146818rtc.h> #include <console/console.h> diff --git a/src/mainboard/iei/juki-511p/romstage.c b/src/mainboard/iei/juki-511p/romstage.c index 353898e..8b26b40 100644 --- a/src/mainboard/iei/juki-511p/romstage.c +++ b/src/mainboard/iei/juki-511p/romstage.c @@ -22,7 +22,6 @@ #include <device/pci_def.h> #include <arch/io.h> #include <device/pnp_def.h> -#include <arch/romcc_io.h> #include <arch/hlt.h> #include <console/console.h> #include "superio/winbond/w83977f/early_serial.c" diff --git a/src/mainboard/iei/kino-780am2-fam10/romstage.c b/src/mainboard/iei/kino-780am2-fam10/romstage.c index 293e90f..fbc6395 100644 --- a/src/mainboard/iei/kino-780am2-fam10/romstage.c +++ b/src/mainboard/iei/kino-780am2-fam10/romstage.c @@ -31,7 +31,6 @@ #include <device/pci_ids.h> #include <arch/io.h> #include <device/pnp_def.h> -#include <arch/romcc_io.h> #include <cpu/x86/lapic.h> #include <console/console.h> #include <cpu/amd/model_10xxx_rev.h> diff --git a/src/mainboard/iei/nova4899r/romstage.c b/src/mainboard/iei/nova4899r/romstage.c index 2a5bcac..174953d 100644 --- a/src/mainboard/iei/nova4899r/romstage.c +++ b/src/mainboard/iei/nova4899r/romstage.c @@ -22,7 +22,6 @@ #include <device/pci_def.h> #include <arch/io.h> #include <device/pnp_def.h> -#include <arch/romcc_io.h> #include <arch/hlt.h> #include <console/console.h> #include "superio/winbond/w83977tf/early_serial.c" diff --git a/src/mainboard/intel/baskingridge/chromeos.c b/src/mainboard/intel/baskingridge/chromeos.c index 6a1bc26..9baf356 100644 --- a/src/mainboard/intel/baskingridge/chromeos.c +++ b/src/mainboard/intel/baskingridge/chromeos.c @@ -20,12 +20,8 @@ #include <string.h> #include <vendorcode/google/chromeos/chromeos.h> #include <arch/io.h> -#ifdef __PRE_RAM__ -#include <arch/romcc_io.h> -#else #include <device/device.h> #include <device/pci.h> -#endif #include <southbridge/intel/lynxpoint/pch.h> #include <southbridge/intel/lynxpoint/gpio.h> diff --git a/src/mainboard/intel/baskingridge/mainboard_smi.c b/src/mainboard/intel/baskingridge/mainboard_smi.c index ecfc385..e543494 100644 --- a/src/mainboard/intel/baskingridge/mainboard_smi.c +++ b/src/mainboard/intel/baskingridge/mainboard_smi.c @@ -18,7 +18,6 @@ */ #include <arch/io.h> -#include <arch/romcc_io.h> #include <console/console.h> #include <cpu/x86/smm.h> #include <southbridge/intel/lynxpoint/nvs.h> diff --git a/src/mainboard/intel/d945gclf/romstage.c b/src/mainboard/intel/d945gclf/romstage.c index a4cb3b2..a37f605 100644 --- a/src/mainboard/intel/d945gclf/romstage.c +++ b/src/mainboard/intel/d945gclf/romstage.c @@ -22,7 +22,6 @@ #include <stdint.h> #include <string.h> #include <arch/io.h> -#include <arch/romcc_io.h> #include <device/pci_def.h> #include <device/pnp_def.h> #include <cpu/x86/lapic.h> diff --git a/src/mainboard/intel/d945gclf/smihandler.c b/src/mainboard/intel/d945gclf/smihandler.c index dbd1a81..0643ad9 100644 --- a/src/mainboard/intel/d945gclf/smihandler.c +++ b/src/mainboard/intel/d945gclf/smihandler.c @@ -18,7 +18,6 @@ */ #include <arch/io.h> -#include <arch/romcc_io.h> #include <console/console.h> #include <cpu/x86/smm.h> #include "southbridge/intel/i82801gx/nvs.h" diff --git a/src/mainboard/intel/eagleheights/romstage.c b/src/mainboard/intel/eagleheights/romstage.c index 95ad59f..3aeb71c 100644 --- a/src/mainboard/intel/eagleheights/romstage.c +++ b/src/mainboard/intel/eagleheights/romstage.c @@ -23,7 +23,6 @@ #include <delay.h> #include <stdint.h> #include <arch/io.h> -#include <arch/romcc_io.h> #include <device/pci_def.h> #include <device/pnp_def.h> #include <cpu/x86/lapic.h> diff --git a/src/mainboard/intel/emeraldlake2/chromeos.c b/src/mainboard/intel/emeraldlake2/chromeos.c index 1c5913a..8e6a732 100644 --- a/src/mainboard/intel/emeraldlake2/chromeos.c +++ b/src/mainboard/intel/emeraldlake2/chromeos.c @@ -20,12 +20,8 @@ #include <string.h> #include <vendorcode/google/chromeos/chromeos.h> #include <arch/io.h> -#ifdef __PRE_RAM__ -#include <arch/romcc_io.h> -#else #include <device/device.h> #include <device/pci.h> -#endif #include <southbridge/intel/bd82x6x/pch.h> #ifndef __PRE_RAM__ diff --git a/src/mainboard/intel/emeraldlake2/romstage.c b/src/mainboard/intel/emeraldlake2/romstage.c index 4fda2d8..88bcced 100644 --- a/src/mainboard/intel/emeraldlake2/romstage.c +++ b/src/mainboard/intel/emeraldlake2/romstage.c @@ -23,7 +23,6 @@ #include <lib.h> #include <timestamp.h> #include <arch/io.h> -#include <arch/romcc_io.h> #include <device/pci_def.h> #include <device/pnp_def.h> #include <cpu/x86/lapic.h> diff --git a/src/mainboard/intel/emeraldlake2/smihandler.c b/src/mainboard/intel/emeraldlake2/smihandler.c index acc1fde..ba76eb8 100644 --- a/src/mainboard/intel/emeraldlake2/smihandler.c +++ b/src/mainboard/intel/emeraldlake2/smihandler.c @@ -18,7 +18,6 @@ */ #include <arch/io.h> -#include <arch/romcc_io.h> #include <console/console.h> #include <cpu/x86/smm.h> #include <southbridge/intel/bd82x6x/nvs.h> diff --git a/src/mainboard/intel/jarrell/jarrell_fixups.c b/src/mainboard/intel/jarrell/jarrell_fixups.c index 1261e61..9a57746 100644 --- a/src/mainboard/intel/jarrell/jarrell_fixups.c +++ b/src/mainboard/intel/jarrell/jarrell_fixups.c @@ -1,4 +1,4 @@ -#include <arch/romcc_io.h> +#include <arch/io.h> static void mch_reset(void) { diff --git a/src/mainboard/intel/jarrell/romstage.c b/src/mainboard/intel/jarrell/romstage.c index 784e7df..c6f014c 100644 --- a/src/mainboard/intel/jarrell/romstage.c +++ b/src/mainboard/intel/jarrell/romstage.c @@ -2,7 +2,6 @@ #include <device/pci_def.h> #include <arch/io.h> #include <device/pnp_def.h> -#include <arch/romcc_io.h> #include <cpu/x86/lapic.h> #include <stdlib.h> #include <console/console.h> diff --git a/src/mainboard/intel/mtarvon/romstage.c b/src/mainboard/intel/mtarvon/romstage.c index d6bbc5a..0cab9bd 100644 --- a/src/mainboard/intel/mtarvon/romstage.c +++ b/src/mainboard/intel/mtarvon/romstage.c @@ -23,7 +23,6 @@ #include <device/pci_ids.h> #include <arch/io.h> #include <device/pnp_def.h> -#include <arch/romcc_io.h> #include <cpu/x86/lapic.h> #include <pc80/mc146818rtc.h> #include <console/console.h> diff --git a/src/mainboard/intel/truxton/romstage.c b/src/mainboard/intel/truxton/romstage.c index d77108f..71c5f38 100644 --- a/src/mainboard/intel/truxton/romstage.c +++ b/src/mainboard/intel/truxton/romstage.c @@ -23,7 +23,6 @@ #include <device/pci_ids.h> #include <arch/io.h> #include <device/pnp_def.h> -#include <arch/romcc_io.h> #include <cpu/x86/lapic.h> #include <pc80/mc146818rtc.h> #include "drivers/pc80/udelay_io.c" diff --git a/src/mainboard/intel/wtm1/chromeos.c b/src/mainboard/intel/wtm1/chromeos.c index 1864754..8142e65 100644 --- a/src/mainboard/intel/wtm1/chromeos.c +++ b/src/mainboard/intel/wtm1/chromeos.c @@ -20,12 +20,8 @@ #include <string.h> #include <vendorcode/google/chromeos/chromeos.h> #include <arch/io.h> -#ifdef __PRE_RAM__ -#include <arch/romcc_io.h> -#else #include <device/device.h> #include <device/pci.h> -#endif #include <southbridge/intel/lynxpoint/pch.h> #ifndef __PRE_RAM__ diff --git a/src/mainboard/intel/wtm1/mainboard_smi.c b/src/mainboard/intel/wtm1/mainboard_smi.c index 281e061..3ffc684 100644 --- a/src/mainboard/intel/wtm1/mainboard_smi.c +++ b/src/mainboard/intel/wtm1/mainboard_smi.c @@ -18,7 +18,6 @@ */ #include <arch/io.h> -#include <arch/romcc_io.h> #include <console/console.h> #include <cpu/x86/smm.h> #include <southbridge/intel/lynxpoint/nvs.h> diff --git a/src/mainboard/intel/wtm2/chromeos.c b/src/mainboard/intel/wtm2/chromeos.c index 1864754..8142e65 100644 --- a/src/mainboard/intel/wtm2/chromeos.c +++ b/src/mainboard/intel/wtm2/chromeos.c @@ -20,12 +20,8 @@ #include <string.h> #include <vendorcode/google/chromeos/chromeos.h> #include <arch/io.h> -#ifdef __PRE_RAM__ -#include <arch/romcc_io.h> -#else #include <device/device.h> #include <device/pci.h> -#endif #include <southbridge/intel/lynxpoint/pch.h> #ifndef __PRE_RAM__ diff --git a/src/mainboard/intel/wtm2/mainboard_smi.c b/src/mainboard/intel/wtm2/mainboard_smi.c index 281e061..3ffc684 100644 --- a/src/mainboard/intel/wtm2/mainboard_smi.c +++ b/src/mainboard/intel/wtm2/mainboard_smi.c @@ -18,7 +18,6 @@ */ #include <arch/io.h> -#include <arch/romcc_io.h> #include <console/console.h> #include <cpu/x86/smm.h> #include <southbridge/intel/lynxpoint/nvs.h> diff --git a/src/mainboard/intel/xe7501devkit/romstage.c b/src/mainboard/intel/xe7501devkit/romstage.c index 4e37811..342e6f1 100644 --- a/src/mainboard/intel/xe7501devkit/romstage.c +++ b/src/mainboard/intel/xe7501devkit/romstage.c @@ -2,7 +2,6 @@ #include <device/pci_def.h> #include <arch/io.h> #include <device/pnp_def.h> -#include <arch/romcc_io.h> #include <cpu/x86/lapic.h> #include <arch/cpu.h> #include <stdlib.h> diff --git a/src/mainboard/iwave/iWRainbowG6/romstage.c b/src/mainboard/iwave/iWRainbowG6/romstage.c index 83ae657..39fce07 100644 --- a/src/mainboard/iwave/iWRainbowG6/romstage.c +++ b/src/mainboard/iwave/iWRainbowG6/romstage.c @@ -20,7 +20,6 @@ #include <stdint.h> #include <string.h> #include <arch/io.h> -#include <arch/romcc_io.h> #include <device/pci_def.h> #include <device/pnp_def.h> #include <cpu/x86/lapic.h> diff --git a/src/mainboard/iwave/iWRainbowG6/smihandler.c b/src/mainboard/iwave/iWRainbowG6/smihandler.c index fc4defb..f2fb1ec 100644 --- a/src/mainboard/iwave/iWRainbowG6/smihandler.c +++ b/src/mainboard/iwave/iWRainbowG6/smihandler.c @@ -18,7 +18,6 @@ */ #include <arch/io.h> -#include <arch/romcc_io.h> #include <console/console.h> #include <cpu/x86/smm.h> #include "southbridge/intel/i82801gx/nvs.h" // FIXME: this should point to its own copy of nvs diff --git a/src/mainboard/iwill/dk8_htx/romstage.c b/src/mainboard/iwill/dk8_htx/romstage.c index bb235d6..6944df0 100644 --- a/src/mainboard/iwill/dk8_htx/romstage.c +++ b/src/mainboard/iwill/dk8_htx/romstage.c @@ -8,7 +8,6 @@ #include <device/pci_ids.h> #include <arch/io.h> #include <device/pnp_def.h> -#include <arch/romcc_io.h> #include <pc80/mc146818rtc.h> #include <console/console.h> #include <cpu/amd/model_fxx_rev.h> diff --git a/src/mainboard/iwill/dk8s2/romstage.c b/src/mainboard/iwill/dk8s2/romstage.c index 27152a6..940e8a6 100644 --- a/src/mainboard/iwill/dk8s2/romstage.c +++ b/src/mainboard/iwill/dk8s2/romstage.c @@ -8,7 +8,6 @@ #include <device/pci_ids.h> #include <arch/io.h> #include <device/pnp_def.h> -#include <arch/romcc_io.h> #include <pc80/mc146818rtc.h> #include <console/console.h> #include <cpu/amd/model_fxx_rev.h> diff --git a/src/mainboard/iwill/dk8x/romstage.c b/src/mainboard/iwill/dk8x/romstage.c index 5ac8508..bab7760 100644 --- a/src/mainboard/iwill/dk8x/romstage.c +++ b/src/mainboard/iwill/dk8x/romstage.c @@ -8,7 +8,6 @@ #include <device/pci_ids.h> #include <arch/io.h> #include <device/pnp_def.h> -#include <arch/romcc_io.h> #include <pc80/mc146818rtc.h> #include <console/console.h> #include <cpu/amd/model_fxx_rev.h> diff --git a/src/mainboard/jetway/j7f24/romstage.c b/src/mainboard/jetway/j7f24/romstage.c index 132a5a6..928fcef 100644 --- a/src/mainboard/jetway/j7f24/romstage.c +++ b/src/mainboard/jetway/j7f24/romstage.c @@ -24,7 +24,6 @@ #include <device/pci_ids.h> #include <arch/io.h> #include <device/pnp_def.h> -#include <arch/romcc_io.h> #include <arch/hlt.h> #include <console/console.h> #include "northbridge/via/cn700/raminit.h" diff --git a/src/mainboard/jetway/pa78vm5/romstage.c b/src/mainboard/jetway/pa78vm5/romstage.c index f87013c..c55efa9 100644 --- a/src/mainboard/jetway/pa78vm5/romstage.c +++ b/src/mainboard/jetway/pa78vm5/romstage.c @@ -32,7 +32,6 @@ #include <device/pci_ids.h> #include <arch/io.h> #include <device/pnp_def.h> -#include <arch/romcc_io.h> #include <cpu/x86/lapic.h> #include <console/console.h> #include <cpu/amd/model_10xxx_rev.h> diff --git a/src/mainboard/kontron/986lcd-m/romstage.c b/src/mainboard/kontron/986lcd-m/romstage.c index df25fd4..03b24d8 100644 --- a/src/mainboard/kontron/986lcd-m/romstage.c +++ b/src/mainboard/kontron/986lcd-m/romstage.c @@ -23,7 +23,6 @@ #include <string.h> #include <lib.h> #include <arch/io.h> -#include <arch/romcc_io.h> #include <device/pci_def.h> #include <device/pnp_def.h> #include <cpu/x86/lapic.h> diff --git a/src/mainboard/kontron/986lcd-m/smihandler.c b/src/mainboard/kontron/986lcd-m/smihandler.c index 3e3bee7..064109b 100644 --- a/src/mainboard/kontron/986lcd-m/smihandler.c +++ b/src/mainboard/kontron/986lcd-m/smihandler.c @@ -18,7 +18,6 @@ */ #include <arch/io.h> -#include <arch/romcc_io.h> #include <console/console.h> #include <cpu/x86/smm.h> #include "southbridge/intel/i82801gx/nvs.h" diff --git a/src/mainboard/kontron/kt690/romstage.c b/src/mainboard/kontron/kt690/romstage.c index 62e02f4..084e55e 100644 --- a/src/mainboard/kontron/kt690/romstage.c +++ b/src/mainboard/kontron/kt690/romstage.c @@ -28,7 +28,6 @@ #include <device/pci_def.h> #include <arch/io.h> #include <device/pnp_def.h> -#include <arch/romcc_io.h> #include <cpu/x86/lapic.h> #include <pc80/mc146818rtc.h> #include <console/console.h> diff --git a/src/mainboard/lanner/em8510/romstage.c b/src/mainboard/lanner/em8510/romstage.c index 929e934..9a7314d 100644 --- a/src/mainboard/lanner/em8510/romstage.c +++ b/src/mainboard/lanner/em8510/romstage.c @@ -24,7 +24,6 @@ #include <device/pci_def.h> #include <arch/io.h> #include <device/pnp_def.h> -#include <arch/romcc_io.h> #include <arch/hlt.h> #include <stdlib.h> #include <lib.h> diff --git a/src/mainboard/lenovo/t60/dock.c b/src/mainboard/lenovo/t60/dock.c index 426286d..9921457 100644 --- a/src/mainboard/lenovo/t60/dock.c +++ b/src/mainboard/lenovo/t60/dock.c @@ -23,7 +23,6 @@ #include <device/device.h> #include <arch/io.h> #include <delay.h> -#include <arch/io.h> #include "dock.h" #include "superio/nsc/pc87384/pc87384.h" #include "ec/acpi/ec.h" diff --git a/src/mainboard/lenovo/t60/romstage.c b/src/mainboard/lenovo/t60/romstage.c index 046e354..5e11613 100644 --- a/src/mainboard/lenovo/t60/romstage.c +++ b/src/mainboard/lenovo/t60/romstage.c @@ -25,7 +25,6 @@ #include <stdint.h> #include <string.h> #include <arch/io.h> -#include <arch/romcc_io.h> #include <device/pci_def.h> #include <device/pnp_def.h> #include <cpu/x86/lapic.h> diff --git a/src/mainboard/lenovo/t60/smihandler.c b/src/mainboard/lenovo/t60/smihandler.c index 6ea5037..f4bad8b 100644 --- a/src/mainboard/lenovo/t60/smihandler.c +++ b/src/mainboard/lenovo/t60/smihandler.c @@ -20,7 +20,6 @@ */ #include <arch/io.h> -#include <arch/romcc_io.h> #include <console/console.h> #include <cpu/x86/smm.h> #include "southbridge/intel/i82801gx/nvs.h" diff --git a/src/mainboard/lenovo/x60/romstage.c b/src/mainboard/lenovo/x60/romstage.c index ee080ea..8d5f922 100644 --- a/src/mainboard/lenovo/x60/romstage.c +++ b/src/mainboard/lenovo/x60/romstage.c @@ -25,7 +25,6 @@ #include <stdint.h> #include <string.h> #include <arch/io.h> -#include <arch/romcc_io.h> #include <device/pci_def.h> #include <device/pnp_def.h> #include <cpu/x86/lapic.h> diff --git a/src/mainboard/lenovo/x60/smihandler.c b/src/mainboard/lenovo/x60/smihandler.c index c0d8440..5a7130f 100644 --- a/src/mainboard/lenovo/x60/smihandler.c +++ b/src/mainboard/lenovo/x60/smihandler.c @@ -20,7 +20,6 @@ */ #include <arch/io.h> -#include <arch/romcc_io.h> #include <console/console.h> #include <cpu/x86/smm.h> #include "southbridge/intel/i82801gx/nvs.h" diff --git a/src/mainboard/lippert/frontrunner-af/reset.c b/src/mainboard/lippert/frontrunner-af/reset.c index 5958e77..bb2482b 100644 --- a/src/mainboard/lippert/frontrunner-af/reset.c +++ b/src/mainboard/lippert/frontrunner-af/reset.c @@ -17,10 +17,11 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ - +#ifndef __PRE_RAM__ +#define __PRE_RAM__ // Use simple device model for this file even in ramstage +#endif +#include <arch/io.h> #include <reset.h> -#include <arch/io.h> /*inb, outb*/ -#include <arch/romcc_io.h> /*pci_read_config32, device_t, PCI_DEV*/ #define HT_INIT_CONTROL 0x6C #define HTIC_BIOSR_Detect (1<<5) diff --git a/src/mainboard/lippert/frontrunner-af/romstage.c b/src/mainboard/lippert/frontrunner-af/romstage.c index 14a003a..0e1b134 100644 --- a/src/mainboard/lippert/frontrunner-af/romstage.c +++ b/src/mainboard/lippert/frontrunner-af/romstage.c @@ -24,7 +24,6 @@ #include <arch/io.h> #include <arch/stages.h> #include <device/pnp_def.h> -#include <arch/romcc_io.h> #include <arch/cpu.h> #include <cpu/x86/lapic.h> #include <console/console.h> diff --git a/src/mainboard/lippert/toucan-af/reset.c b/src/mainboard/lippert/toucan-af/reset.c index 5958e77..bb2482b 100644 --- a/src/mainboard/lippert/toucan-af/reset.c +++ b/src/mainboard/lippert/toucan-af/reset.c @@ -17,10 +17,11 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ - +#ifndef __PRE_RAM__ +#define __PRE_RAM__ // Use simple device model for this file even in ramstage +#endif +#include <arch/io.h> #include <reset.h> -#include <arch/io.h> /*inb, outb*/ -#include <arch/romcc_io.h> /*pci_read_config32, device_t, PCI_DEV*/ #define HT_INIT_CONTROL 0x6C #define HTIC_BIOSR_Detect (1<<5) diff --git a/src/mainboard/lippert/toucan-af/romstage.c b/src/mainboard/lippert/toucan-af/romstage.c index fcec303..043af85 100644 --- a/src/mainboard/lippert/toucan-af/romstage.c +++ b/src/mainboard/lippert/toucan-af/romstage.c @@ -24,7 +24,6 @@ #include <arch/io.h> #include <arch/stages.h> #include <device/pnp_def.h> -#include <arch/romcc_io.h> #include <arch/cpu.h> #include <cpu/x86/lapic.h> #include <console/console.h> diff --git a/src/mainboard/msi/ms6119/romstage.c b/src/mainboard/msi/ms6119/romstage.c index a908aca..f597b26 100644 --- a/src/mainboard/msi/ms6119/romstage.c +++ b/src/mainboard/msi/ms6119/romstage.c @@ -23,7 +23,6 @@ #include <device/pci_def.h> #include <arch/io.h> #include <device/pnp_def.h> -#include <arch/romcc_io.h> #include <arch/hlt.h> #include <console/console.h> #include "southbridge/intel/i82371eb/i82371eb.h" diff --git a/src/mainboard/msi/ms6147/romstage.c b/src/mainboard/msi/ms6147/romstage.c index e68a59e..67fbdc7 100644 --- a/src/mainboard/msi/ms6147/romstage.c +++ b/src/mainboard/msi/ms6147/romstage.c @@ -23,7 +23,6 @@ #include <device/pci_def.h> #include <arch/io.h> #include <device/pnp_def.h> -#include <arch/romcc_io.h> #include <arch/hlt.h> #include <console/console.h> #include "southbridge/intel/i82371eb/i82371eb.h" diff --git a/src/mainboard/msi/ms6156/romstage.c b/src/mainboard/msi/ms6156/romstage.c index f52c427..f1f4a67 100644 --- a/src/mainboard/msi/ms6156/romstage.c +++ b/src/mainboard/msi/ms6156/romstage.c @@ -23,7 +23,6 @@ #include <device/pci_def.h> #include <arch/io.h> #include <device/pnp_def.h> -#include <arch/romcc_io.h> #include <arch/hlt.h> #include <console/console.h> #include "southbridge/intel/i82371eb/i82371eb.h" diff --git a/src/mainboard/msi/ms7135/romstage.c b/src/mainboard/msi/ms7135/romstage.c index f1c624d..c965d94 100644 --- a/src/mainboard/msi/ms7135/romstage.c +++ b/src/mainboard/msi/ms7135/romstage.c @@ -27,7 +27,6 @@ #include <device/pci_def.h> #include <arch/io.h> #include <device/pnp_def.h> -#include <arch/romcc_io.h> #include <cpu/x86/lapic.h> #include <pc80/mc146818rtc.h> #include "cpu/x86/lapic/boot_cpu.c" diff --git a/src/mainboard/msi/ms7260/ap_romstage.c b/src/mainboard/msi/ms7260/ap_romstage.c index 31f56c7..f0a3dc4 100644 --- a/src/mainboard/msi/ms7260/ap_romstage.c +++ b/src/mainboard/msi/ms7260/ap_romstage.c @@ -26,7 +26,6 @@ #include <device/pci_ids.h> #include <arch/io.h> #include <device/pnp_def.h> -#include <arch/romcc_io.h> #include <cpu/x86/lapic.h> #include <pc80/mc146818rtc.h> #include "lib/uart8259.c" diff --git a/src/mainboard/msi/ms7260/romstage.c b/src/mainboard/msi/ms7260/romstage.c index 9d3f85f..6ca0003 100644 --- a/src/mainboard/msi/ms7260/romstage.c +++ b/src/mainboard/msi/ms7260/romstage.c @@ -30,7 +30,6 @@ #include <device/pci_ids.h> #include <arch/io.h> #include <device/pnp_def.h> -#include <arch/romcc_io.h> #include <cpu/x86/lapic.h> #include <pc80/mc146818rtc.h> #include <console/console.h> diff --git a/src/mainboard/msi/ms9185/romstage.c b/src/mainboard/msi/ms9185/romstage.c index 7bf9c90..4910fe5 100644 --- a/src/mainboard/msi/ms9185/romstage.c +++ b/src/mainboard/msi/ms9185/romstage.c @@ -29,7 +29,6 @@ #include <device/pci_ids.h> #include <arch/io.h> #include <device/pnp_def.h> -#include <arch/romcc_io.h> #include <cpu/x86/lapic.h> #include <pc80/mc146818rtc.h> #include <console/console.h> diff --git a/src/mainboard/msi/ms9282/romstage.c b/src/mainboard/msi/ms9282/romstage.c index 53fbaf4..e766bd7 100644 --- a/src/mainboard/msi/ms9282/romstage.c +++ b/src/mainboard/msi/ms9282/romstage.c @@ -27,7 +27,6 @@ #include <device/pci_def.h> #include <arch/io.h> #include <device/pnp_def.h> -#include <arch/romcc_io.h> #include <cpu/x86/lapic.h> #include <pc80/mc146818rtc.h> #include <console/console.h> diff --git a/src/mainboard/msi/ms9652_fam10/romstage.c b/src/mainboard/msi/ms9652_fam10/romstage.c index ff15805..00b7940 100644 --- a/src/mainboard/msi/ms9652_fam10/romstage.c +++ b/src/mainboard/msi/ms9652_fam10/romstage.c @@ -28,7 +28,6 @@ #include <device/pci_ids.h> #include <arch/io.h> #include <device/pnp_def.h> -#include <arch/romcc_io.h> #include <cpu/x86/lapic.h> #include <console/console.h> #include <lib.h> diff --git a/src/mainboard/newisys/khepri/romstage.c b/src/mainboard/newisys/khepri/romstage.c index ae522d2..7af39e4 100644 --- a/src/mainboard/newisys/khepri/romstage.c +++ b/src/mainboard/newisys/khepri/romstage.c @@ -9,7 +9,6 @@ #include <device/pci_def.h> #include <arch/io.h> #include <device/pnp_def.h> -#include <arch/romcc_io.h> #include <pc80/mc146818rtc.h> #include <console/console.h> #include <lib.h> diff --git a/src/mainboard/nokia/ip530/romstage.c b/src/mainboard/nokia/ip530/romstage.c index 95f3139..627a047 100644 --- a/src/mainboard/nokia/ip530/romstage.c +++ b/src/mainboard/nokia/ip530/romstage.c @@ -22,7 +22,6 @@ #include <device/pci_def.h> #include <arch/io.h> #include <device/pnp_def.h> -#include <arch/romcc_io.h> #include <arch/hlt.h> #include <stdlib.h> #include <console/console.h> diff --git a/src/mainboard/nvidia/l1_2pvv/ap_romstage.c b/src/mainboard/nvidia/l1_2pvv/ap_romstage.c index 204ce0b..005de7b 100644 --- a/src/mainboard/nvidia/l1_2pvv/ap_romstage.c +++ b/src/mainboard/nvidia/l1_2pvv/ap_romstage.c @@ -26,7 +26,6 @@ #include <device/pci_ids.h> #include <arch/io.h> #include <device/pnp_def.h> -#include <arch/romcc_io.h> #include <cpu/x86/lapic.h> #include <pc80/mc146818rtc.h> #include "lib/uart8250.c" diff --git a/src/mainboard/nvidia/l1_2pvv/romstage.c b/src/mainboard/nvidia/l1_2pvv/romstage.c index ed25725..a63e851 100644 --- a/src/mainboard/nvidia/l1_2pvv/romstage.c +++ b/src/mainboard/nvidia/l1_2pvv/romstage.c @@ -29,7 +29,6 @@ #include <device/pci_ids.h> #include <arch/io.h> #include <device/pnp_def.h> -#include <arch/romcc_io.h> #include <cpu/x86/lapic.h> #include <pc80/mc146818rtc.h> #include <console/console.h> diff --git a/src/mainboard/pcengines/alix1c/romstage.c b/src/mainboard/pcengines/alix1c/romstage.c index 5c80ee8..113eb26 100644 --- a/src/mainboard/pcengines/alix1c/romstage.c +++ b/src/mainboard/pcengines/alix1c/romstage.c @@ -23,7 +23,6 @@ #include <device/pci_def.h> #include <arch/io.h> #include <device/pnp_def.h> -#include <arch/romcc_io.h> #include <arch/hlt.h> #include <console/console.h> #include <lib.h> diff --git a/src/mainboard/pcengines/alix2d/romstage.c b/src/mainboard/pcengines/alix2d/romstage.c index 3a8209a..aa1a856 100644 --- a/src/mainboard/pcengines/alix2d/romstage.c +++ b/src/mainboard/pcengines/alix2d/romstage.c @@ -23,7 +23,6 @@ #include <device/pci_def.h> #include <arch/io.h> #include <device/pnp_def.h> -#include <arch/romcc_io.h> #include <arch/hlt.h> #include <console/console.h> #include <lib.h> diff --git a/src/mainboard/rca/rm4100/romstage.c b/src/mainboard/rca/rm4100/romstage.c index 71eefa1..705803d 100644 --- a/src/mainboard/rca/rm4100/romstage.c +++ b/src/mainboard/rca/rm4100/romstage.c @@ -23,7 +23,6 @@ #include <device/pci_def.h> #include <arch/io.h> #include <device/pnp_def.h> -#include <arch/romcc_io.h> #include <arch/hlt.h> #include "drivers/pc80/udelay_io.c" #include <console/console.h> diff --git a/src/mainboard/rca/rm4100/smihandler.c b/src/mainboard/rca/rm4100/smihandler.c index 8cfefae..708e5c2 100644 --- a/src/mainboard/rca/rm4100/smihandler.c +++ b/src/mainboard/rca/rm4100/smihandler.c @@ -20,7 +20,6 @@ */ #include <arch/io.h> -#include <arch/romcc_io.h> #include <console/console.h> #include <cpu/x86/smm.h> diff --git a/src/mainboard/roda/rk886ex/romstage.c b/src/mainboard/roda/rk886ex/romstage.c index d75d33f..ab200d2 100644 --- a/src/mainboard/roda/rk886ex/romstage.c +++ b/src/mainboard/roda/rk886ex/romstage.c @@ -24,7 +24,6 @@ #include <stdint.h> #include <string.h> #include <arch/io.h> -#include <arch/romcc_io.h> #include <device/pci_def.h> #include <device/pnp_def.h> #include <cpu/x86/lapic.h> diff --git a/src/mainboard/roda/rk886ex/smihandler.c b/src/mainboard/roda/rk886ex/smihandler.c index 6736ace..1470511 100644 --- a/src/mainboard/roda/rk886ex/smihandler.c +++ b/src/mainboard/roda/rk886ex/smihandler.c @@ -20,7 +20,6 @@ */ #include <arch/io.h> -#include <arch/romcc_io.h> #include <console/console.h> #include <cpu/x86/smm.h> #include "southbridge/intel/i82801gx/nvs.h" diff --git a/src/mainboard/roda/rk9/romstage.c b/src/mainboard/roda/rk9/romstage.c index c6ca078..56eea84 100644 --- a/src/mainboard/roda/rk9/romstage.c +++ b/src/mainboard/roda/rk9/romstage.c @@ -24,7 +24,6 @@ #include <stdint.h> #include <string.h> #include <arch/io.h> -#include <arch/romcc_io.h> #include <cpu/x86/lapic.h> #include <cpu/x86/msr.h> #include <cpu/x86/tsc.h> diff --git a/src/mainboard/roda/rk9/smihandler.c b/src/mainboard/roda/rk9/smihandler.c index 8a87cd9..fe68c4b 100644 --- a/src/mainboard/roda/rk9/smihandler.c +++ b/src/mainboard/roda/rk9/smihandler.c @@ -18,7 +18,6 @@ */ #include <arch/io.h> -#include <arch/romcc_io.h> #include <console/console.h> #include <cpu/x86/smm.h> #include <southbridge/intel/i82801ix/nvs.h> diff --git a/src/mainboard/samsung/lumpy/chromeos.c b/src/mainboard/samsung/lumpy/chromeos.c index 67a79f0..2716bf2 100644 --- a/src/mainboard/samsung/lumpy/chromeos.c +++ b/src/mainboard/samsung/lumpy/chromeos.c @@ -20,12 +20,8 @@ #include <string.h> #include <vendorcode/google/chromeos/chromeos.h> #include <arch/io.h> -#ifdef __PRE_RAM__ -#include <arch/romcc_io.h> -#else #include <device/device.h> #include <device/pci.h> -#endif #include <northbridge/intel/sandybridge/sandybridge.h> #include <southbridge/intel/bd82x6x/pch.h> diff --git a/src/mainboard/samsung/lumpy/romstage.c b/src/mainboard/samsung/lumpy/romstage.c index 67004c7..b941021 100644 --- a/src/mainboard/samsung/lumpy/romstage.c +++ b/src/mainboard/samsung/lumpy/romstage.c @@ -23,7 +23,6 @@ #include <lib.h> #include <timestamp.h> #include <arch/io.h> -#include <arch/romcc_io.h> #include <arch/byteorder.h> #include <device/pci_def.h> #include <device/pnp_def.h> diff --git a/src/mainboard/samsung/lumpy/smihandler.c b/src/mainboard/samsung/lumpy/smihandler.c index 4e73a57..9306a02 100644 --- a/src/mainboard/samsung/lumpy/smihandler.c +++ b/src/mainboard/samsung/lumpy/smihandler.c @@ -18,7 +18,6 @@ */ #include <arch/io.h> -#include <arch/romcc_io.h> #include <console/console.h> #include <cpu/x86/smm.h> #include <southbridge/intel/bd82x6x/nvs.h> diff --git a/src/mainboard/samsung/stumpy/chromeos.c b/src/mainboard/samsung/stumpy/chromeos.c index 4222735..a408fd9 100644 --- a/src/mainboard/samsung/stumpy/chromeos.c +++ b/src/mainboard/samsung/stumpy/chromeos.c @@ -20,12 +20,8 @@ #include <string.h> #include <vendorcode/google/chromeos/chromeos.h> #include <arch/io.h> -#ifdef __PRE_RAM__ -#include <arch/romcc_io.h> -#else #include <device/device.h> #include <device/pci.h> -#endif #include <southbridge/intel/bd82x6x/pch.h> #define GPIO_SPI_WP 68 diff --git a/src/mainboard/samsung/stumpy/romstage.c b/src/mainboard/samsung/stumpy/romstage.c index 1fad949..dda3ab5 100644 --- a/src/mainboard/samsung/stumpy/romstage.c +++ b/src/mainboard/samsung/stumpy/romstage.c @@ -24,7 +24,6 @@ #include <timestamp.h> #include <arch/byteorder.h> #include <arch/io.h> -#include <arch/romcc_io.h> #include <device/pci_def.h> #include <device/pnp_def.h> #include <cpu/x86/lapic.h> diff --git a/src/mainboard/samsung/stumpy/smihandler.c b/src/mainboard/samsung/stumpy/smihandler.c index 5eda0a1..5c3e1b3 100644 --- a/src/mainboard/samsung/stumpy/smihandler.c +++ b/src/mainboard/samsung/stumpy/smihandler.c @@ -18,7 +18,6 @@ */ #include <arch/io.h> -#include <arch/romcc_io.h> #include <console/console.h> #include <cpu/x86/smm.h> #include <southbridge/intel/bd82x6x/nvs.h> diff --git a/src/mainboard/siemens/sitemp_g1p1/romstage.c b/src/mainboard/siemens/sitemp_g1p1/romstage.c index 108b762..8198c6c 100644 --- a/src/mainboard/siemens/sitemp_g1p1/romstage.c +++ b/src/mainboard/siemens/sitemp_g1p1/romstage.c @@ -33,7 +33,6 @@ #include <device/pci_def.h> #include <arch/io.h> #include <device/pnp_def.h> -#include <arch/romcc_io.h> #include <cpu/x86/lapic.h> #include <pc80/mc146818rtc.h> #include <console/console.h> diff --git a/src/mainboard/soyo/sy-6ba-plus-iii/romstage.c b/src/mainboard/soyo/sy-6ba-plus-iii/romstage.c index c4bb23c..632a311 100644 --- a/src/mainboard/soyo/sy-6ba-plus-iii/romstage.c +++ b/src/mainboard/soyo/sy-6ba-plus-iii/romstage.c @@ -22,7 +22,6 @@ #include <device/pci_def.h> #include <arch/io.h> #include <device/pnp_def.h> -#include <arch/romcc_io.h> #include <arch/hlt.h> #include <stdlib.h> #include <console/console.h> diff --git a/src/mainboard/sunw/ultra40/romstage.c b/src/mainboard/sunw/ultra40/romstage.c index d927396..d8dd781 100644 --- a/src/mainboard/sunw/ultra40/romstage.c +++ b/src/mainboard/sunw/ultra40/romstage.c @@ -3,7 +3,6 @@ #include <device/pci_def.h> #include <arch/io.h> #include <device/pnp_def.h> -#include <arch/romcc_io.h> #include <cpu/x86/lapic.h> #include <pc80/mc146818rtc.h> #include <console/console.h> diff --git a/src/mainboard/supermicro/h8dme/ap_romstage.c b/src/mainboard/supermicro/h8dme/ap_romstage.c index a85c182..ed2d16a 100644 --- a/src/mainboard/supermicro/h8dme/ap_romstage.c +++ b/src/mainboard/supermicro/h8dme/ap_romstage.c @@ -26,7 +26,6 @@ #include <device/pci_ids.h> #include <arch/io.h> #include <device/pnp_def.h> -#include <arch/romcc_io.h> #include <cpu/x86/lapic.h> #include <pc80/mc146818rtc.h> diff --git a/src/mainboard/supermicro/h8dme/romstage.c b/src/mainboard/supermicro/h8dme/romstage.c index 1d303a1..7ad9ec8 100644 --- a/src/mainboard/supermicro/h8dme/romstage.c +++ b/src/mainboard/supermicro/h8dme/romstage.c @@ -26,7 +26,6 @@ #include <device/pci_ids.h> #include <arch/io.h> #include <device/pnp_def.h> -#include <arch/romcc_io.h> #include <cpu/x86/lapic.h> #include <pc80/mc146818rtc.h> #include <console/console.h> diff --git a/src/mainboard/supermicro/h8dmr/ap_romstage.c b/src/mainboard/supermicro/h8dmr/ap_romstage.c index 351898e..8008bb2 100644 --- a/src/mainboard/supermicro/h8dmr/ap_romstage.c +++ b/src/mainboard/supermicro/h8dmr/ap_romstage.c @@ -26,7 +26,6 @@ #include <device/pci_ids.h> #include <arch/io.h> #include <device/pnp_def.h> -#include <arch/romcc_io.h> #include <cpu/x86/lapic.h> #include <pc80/mc146818rtc.h> diff --git a/src/mainboard/supermicro/h8dmr/romstage.c b/src/mainboard/supermicro/h8dmr/romstage.c index dca9248..0a89e0d 100644 --- a/src/mainboard/supermicro/h8dmr/romstage.c +++ b/src/mainboard/supermicro/h8dmr/romstage.c @@ -29,7 +29,6 @@ #include <device/pci_ids.h> #include <arch/io.h> #include <device/pnp_def.h> -#include <arch/romcc_io.h> #include <cpu/x86/lapic.h> #include <pc80/mc146818rtc.h> #include <console/console.h> diff --git a/src/mainboard/supermicro/h8dmr_fam10/romstage.c b/src/mainboard/supermicro/h8dmr_fam10/romstage.c index 03b39cc..c6792d3 100644 --- a/src/mainboard/supermicro/h8dmr_fam10/romstage.c +++ b/src/mainboard/supermicro/h8dmr_fam10/romstage.c @@ -28,7 +28,6 @@ #include <device/pci_ids.h> #include <arch/io.h> #include <device/pnp_def.h> -#include <arch/romcc_io.h> #include <cpu/x86/lapic.h> #include <console/console.h> #include <lib.h> diff --git a/src/mainboard/supermicro/h8qgi/BiosCallOuts.c b/src/mainboard/supermicro/h8qgi/BiosCallOuts.c index 178a788..2fbe70a 100644 --- a/src/mainboard/supermicro/h8qgi/BiosCallOuts.c +++ b/src/mainboard/supermicro/h8qgi/BiosCallOuts.c @@ -25,7 +25,6 @@ #include "heapManager.h" #include <northbridge/amd/agesa/family15/dimmSpd.h> #include <arch/io.h> -#include <arch/romcc_io.h> #ifdef __PRE_RAM__ /* These defines are used to select the appropriate socket for the SPD read diff --git a/src/mainboard/supermicro/h8qgi/reset.c b/src/mainboard/supermicro/h8qgi/reset.c index 46f97ec..7a96aa4 100644 --- a/src/mainboard/supermicro/h8qgi/reset.c +++ b/src/mainboard/supermicro/h8qgi/reset.c @@ -17,10 +17,11 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ - +#ifndef __PRE_RAM__ +#define __PRE_RAM__ // Use simple device model for this file even in ramstage +#endif +#include <arch/io.h> #include <reset.h> -#include <arch/io.h> /*inb, outb*/ -#include <arch/romcc_io.h> /*pci_read_config32, device_t, PCI_DEV*/ #define HT_INIT_CONTROL 0x6C #define HTIC_BIOSR_Detect (1<<5) diff --git a/src/mainboard/supermicro/h8qgi/romstage.c b/src/mainboard/supermicro/h8qgi/romstage.c index e415bf6..45422bb 100644 --- a/src/mainboard/supermicro/h8qgi/romstage.c +++ b/src/mainboard/supermicro/h8qgi/romstage.c @@ -21,7 +21,6 @@ #include <reset.h> #include <stdint.h> #include <arch/io.h> -#include <arch/romcc_io.h> #include <arch/cpu.h> #include <console/console.h> #include <arch/stages.h> diff --git a/src/mainboard/supermicro/h8qme_fam10/romstage.c b/src/mainboard/supermicro/h8qme_fam10/romstage.c index 3725db4..c2ccb01 100644 --- a/src/mainboard/supermicro/h8qme_fam10/romstage.c +++ b/src/mainboard/supermicro/h8qme_fam10/romstage.c @@ -28,7 +28,6 @@ #include <device/pci_ids.h> #include <arch/io.h> #include <device/pnp_def.h> -#include <arch/romcc_io.h> #include <cpu/x86/lapic.h> #include <console/console.h> #include <lib.h> diff --git a/src/mainboard/supermicro/h8scm/reset.c b/src/mainboard/supermicro/h8scm/reset.c index 46f97ec..7a96aa4 100644 --- a/src/mainboard/supermicro/h8scm/reset.c +++ b/src/mainboard/supermicro/h8scm/reset.c @@ -17,10 +17,11 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ - +#ifndef __PRE_RAM__ +#define __PRE_RAM__ // Use simple device model for this file even in ramstage +#endif +#include <arch/io.h> #include <reset.h> -#include <arch/io.h> /*inb, outb*/ -#include <arch/romcc_io.h> /*pci_read_config32, device_t, PCI_DEV*/ #define HT_INIT_CONTROL 0x6C #define HTIC_BIOSR_Detect (1<<5) diff --git a/src/mainboard/supermicro/h8scm/romstage.c b/src/mainboard/supermicro/h8scm/romstage.c index 2a988bb..3219fda 100644 --- a/src/mainboard/supermicro/h8scm/romstage.c +++ b/src/mainboard/supermicro/h8scm/romstage.c @@ -21,7 +21,6 @@ #include <reset.h> #include <stdint.h> #include <arch/io.h> -#include <arch/romcc_io.h> #include <arch/cpu.h> #include <console/console.h> #include <arch/stages.h> diff --git a/src/mainboard/supermicro/h8scm_fam10/romstage.c b/src/mainboard/supermicro/h8scm_fam10/romstage.c index 259302b..4ce9b74 100644 --- a/src/mainboard/supermicro/h8scm_fam10/romstage.c +++ b/src/mainboard/supermicro/h8scm_fam10/romstage.c @@ -31,7 +31,6 @@ #include <device/pci_ids.h> #include <arch/io.h> #include <device/pnp_def.h> -#include <arch/romcc_io.h> #include <cpu/x86/lapic.h> #include <console/console.h> #include <cpu/amd/model_10xxx_rev.h> diff --git a/src/mainboard/supermicro/x6dai_g/romstage.c b/src/mainboard/supermicro/x6dai_g/romstage.c index dda5817..f57adaf 100644 --- a/src/mainboard/supermicro/x6dai_g/romstage.c +++ b/src/mainboard/supermicro/x6dai_g/romstage.c @@ -2,7 +2,6 @@ #include <device/pci_def.h> #include <arch/io.h> #include <device/pnp_def.h> -#include <arch/romcc_io.h> #include <cpu/x86/lapic.h> #include <stdlib.h> #include <console/console.h> diff --git a/src/mainboard/supermicro/x6dhe_g/romstage.c b/src/mainboard/supermicro/x6dhe_g/romstage.c index 37fd2e4..071bb35 100644 --- a/src/mainboard/supermicro/x6dhe_g/romstage.c +++ b/src/mainboard/supermicro/x6dhe_g/romstage.c @@ -2,7 +2,6 @@ #include <device/pci_def.h> #include <arch/io.h> #include <device/pnp_def.h> -#include <arch/romcc_io.h> #include <cpu/x86/lapic.h> #include <stdlib.h> #include <console/console.h> diff --git a/src/mainboard/supermicro/x6dhe_g2/romstage.c b/src/mainboard/supermicro/x6dhe_g2/romstage.c index c9db699..c6350e8 100644 --- a/src/mainboard/supermicro/x6dhe_g2/romstage.c +++ b/src/mainboard/supermicro/x6dhe_g2/romstage.c @@ -2,7 +2,6 @@ #include <device/pci_def.h> #include <arch/io.h> #include <device/pnp_def.h> -#include <arch/romcc_io.h> #include <cpu/x86/lapic.h> #include <stdlib.h> #include <console/console.h> diff --git a/src/mainboard/supermicro/x6dhr_ig/romstage.c b/src/mainboard/supermicro/x6dhr_ig/romstage.c index 55e1ee7..9c61d60 100644 --- a/src/mainboard/supermicro/x6dhr_ig/romstage.c +++ b/src/mainboard/supermicro/x6dhr_ig/romstage.c @@ -2,7 +2,6 @@ #include <device/pci_def.h> #include <arch/io.h> #include <device/pnp_def.h> -#include <arch/romcc_io.h> #include <cpu/x86/lapic.h> #include <stdlib.h> #include <console/console.h> diff --git a/src/mainboard/supermicro/x6dhr_ig2/romstage.c b/src/mainboard/supermicro/x6dhr_ig2/romstage.c index 65bfdb2..7cfe818 100644 --- a/src/mainboard/supermicro/x6dhr_ig2/romstage.c +++ b/src/mainboard/supermicro/x6dhr_ig2/romstage.c @@ -2,7 +2,6 @@ #include <device/pci_def.h> #include <arch/io.h> #include <device/pnp_def.h> -#include <arch/romcc_io.h> #include <cpu/x86/lapic.h> #include <stdlib.h> #include <console/console.h> diff --git a/src/mainboard/supermicro/x7db8/romstage.c b/src/mainboard/supermicro/x7db8/romstage.c index 43ba238..fa73412 100644 --- a/src/mainboard/supermicro/x7db8/romstage.c +++ b/src/mainboard/supermicro/x7db8/romstage.c @@ -23,7 +23,6 @@ #include <stdint.h> #include <string.h> #include <arch/io.h> -#include <arch/romcc_io.h> #include <device/pci_def.h> #include <device/pnp_def.h> #include <cpu/x86/lapic.h> diff --git a/src/mainboard/technexion/tim5690/romstage.c b/src/mainboard/technexion/tim5690/romstage.c index 8bb0ea3..5588d8e 100644 --- a/src/mainboard/technexion/tim5690/romstage.c +++ b/src/mainboard/technexion/tim5690/romstage.c @@ -27,7 +27,6 @@ #include <device/pci_def.h> #include <arch/io.h> #include <device/pnp_def.h> -#include <arch/romcc_io.h> #include <cpu/x86/lapic.h> #include <pc80/mc146818rtc.h> #include <console/console.h> diff --git a/src/mainboard/technexion/tim8690/romstage.c b/src/mainboard/technexion/tim8690/romstage.c index 5ca1dce..b9969aa 100644 --- a/src/mainboard/technexion/tim8690/romstage.c +++ b/src/mainboard/technexion/tim8690/romstage.c @@ -27,7 +27,6 @@ #include <device/pci_def.h> #include <arch/io.h> #include <device/pnp_def.h> -#include <arch/romcc_io.h> #include <cpu/x86/lapic.h> #include <pc80/mc146818rtc.h> #include <console/console.h> diff --git a/src/mainboard/technologic/ts5300/romstage.c b/src/mainboard/technologic/ts5300/romstage.c index b9b2f17..6806187 100644 --- a/src/mainboard/technologic/ts5300/romstage.c +++ b/src/mainboard/technologic/ts5300/romstage.c @@ -8,7 +8,6 @@ #include <device/pci_def.h> #include <arch/io.h> #include <device/pnp_def.h> -#include <arch/romcc_io.h> #include <arch/hlt.h> #include <pc80/mc146818rtc.h> #include <console/console.h> diff --git a/src/mainboard/televideo/tc7020/romstage.c b/src/mainboard/televideo/tc7020/romstage.c index e887a29..053da17 100644 --- a/src/mainboard/televideo/tc7020/romstage.c +++ b/src/mainboard/televideo/tc7020/romstage.c @@ -22,7 +22,6 @@ #include <device/pci_def.h> #include <arch/io.h> #include <device/pnp_def.h> -#include <arch/romcc_io.h> #include <arch/hlt.h> #include <console/console.h> #include "northbridge/amd/gx1/raminit.c" diff --git a/src/mainboard/thomson/ip1000/romstage.c b/src/mainboard/thomson/ip1000/romstage.c index ca4813f..1e05d63 100644 --- a/src/mainboard/thomson/ip1000/romstage.c +++ b/src/mainboard/thomson/ip1000/romstage.c @@ -23,7 +23,6 @@ #include <device/pci_def.h> #include <arch/io.h> #include <device/pnp_def.h> -#include <arch/romcc_io.h> #include <arch/hlt.h> #include <arch/llshell.h> #include "drivers/pc80/udelay_io.c" diff --git a/src/mainboard/thomson/ip1000/smihandler.c b/src/mainboard/thomson/ip1000/smihandler.c index 8cfefae..708e5c2 100644 --- a/src/mainboard/thomson/ip1000/smihandler.c +++ b/src/mainboard/thomson/ip1000/smihandler.c @@ -20,7 +20,6 @@ */ #include <arch/io.h> -#include <arch/romcc_io.h> #include <console/console.h> #include <cpu/x86/smm.h> diff --git a/src/mainboard/tyan/s1846/romstage.c b/src/mainboard/tyan/s1846/romstage.c index 1d27da3..8e901b2 100644 --- a/src/mainboard/tyan/s1846/romstage.c +++ b/src/mainboard/tyan/s1846/romstage.c @@ -22,7 +22,6 @@ #include <device/pci_def.h> #include <arch/io.h> #include <device/pnp_def.h> -#include <arch/romcc_io.h> #include <arch/hlt.h> #include <stdlib.h> #include <console/console.h> diff --git a/src/mainboard/tyan/s2735/romstage.c b/src/mainboard/tyan/s2735/romstage.c index 2bbbf34..4e71559 100644 --- a/src/mainboard/tyan/s2735/romstage.c +++ b/src/mainboard/tyan/s2735/romstage.c @@ -3,7 +3,6 @@ #include <device/pci_def.h> #include <arch/io.h> #include <device/pnp_def.h> -#include <arch/romcc_io.h> #include <cpu/x86/lapic.h> #include <pc80/mc146818rtc.h> #include <console/console.h> diff --git a/src/mainboard/tyan/s2850/romstage.c b/src/mainboard/tyan/s2850/romstage.c index 4f14eab..5e62f33 100644 --- a/src/mainboard/tyan/s2850/romstage.c +++ b/src/mainboard/tyan/s2850/romstage.c @@ -3,7 +3,6 @@ #include <device/pci_def.h> #include <arch/io.h> #include <device/pnp_def.h> -#include <arch/romcc_io.h> #include <stdlib.h> #include <pc80/mc146818rtc.h> #include <console/console.h> diff --git a/src/mainboard/tyan/s2875/romstage.c b/src/mainboard/tyan/s2875/romstage.c index 68422f3..d35c65a 100644 --- a/src/mainboard/tyan/s2875/romstage.c +++ b/src/mainboard/tyan/s2875/romstage.c @@ -3,7 +3,6 @@ #include <device/pci_def.h> #include <arch/io.h> #include <device/pnp_def.h> -#include <arch/romcc_io.h> #include <stdlib.h> #include <pc80/mc146818rtc.h> #include <console/console.h> diff --git a/src/mainboard/tyan/s2880/romstage.c b/src/mainboard/tyan/s2880/romstage.c index 20d829c..5f30796 100644 --- a/src/mainboard/tyan/s2880/romstage.c +++ b/src/mainboard/tyan/s2880/romstage.c @@ -3,7 +3,6 @@ #include <device/pci_def.h> #include <arch/io.h> #include <device/pnp_def.h> -#include <arch/romcc_io.h> #include <stdlib.h> #include <pc80/mc146818rtc.h> #include <console/console.h> diff --git a/src/mainboard/tyan/s2881/romstage.c b/src/mainboard/tyan/s2881/romstage.c index b75e387..404c2df 100644 --- a/src/mainboard/tyan/s2881/romstage.c +++ b/src/mainboard/tyan/s2881/romstage.c @@ -3,7 +3,6 @@ #include <device/pci_def.h> #include <arch/io.h> #include <device/pnp_def.h> -#include <arch/romcc_io.h> #include <pc80/mc146818rtc.h> #include <console/console.h> #include <lib.h> diff --git a/src/mainboard/tyan/s2882/romstage.c b/src/mainboard/tyan/s2882/romstage.c index 20d829c..5f30796 100644 --- a/src/mainboard/tyan/s2882/romstage.c +++ b/src/mainboard/tyan/s2882/romstage.c @@ -3,7 +3,6 @@ #include <device/pci_def.h> #include <arch/io.h> #include <device/pnp_def.h> -#include <arch/romcc_io.h> #include <stdlib.h> #include <pc80/mc146818rtc.h> #include <console/console.h> diff --git a/src/mainboard/tyan/s2885/romstage.c b/src/mainboard/tyan/s2885/romstage.c index 1e41d74..00dff67 100644 --- a/src/mainboard/tyan/s2885/romstage.c +++ b/src/mainboard/tyan/s2885/romstage.c @@ -3,7 +3,6 @@ #include <device/pci_def.h> #include <arch/io.h> #include <device/pnp_def.h> -#include <arch/romcc_io.h> #include <pc80/mc146818rtc.h> #include <console/console.h> #include <lib.h> diff --git a/src/mainboard/tyan/s2891/romstage.c b/src/mainboard/tyan/s2891/romstage.c index c57948f..7a28e80 100644 --- a/src/mainboard/tyan/s2891/romstage.c +++ b/src/mainboard/tyan/s2891/romstage.c @@ -3,7 +3,6 @@ #include <device/pci_def.h> #include <arch/io.h> #include <device/pnp_def.h> -#include <arch/romcc_io.h> #include <cpu/x86/lapic.h> #include <pc80/mc146818rtc.h> #include <console/console.h> diff --git a/src/mainboard/tyan/s2892/romstage.c b/src/mainboard/tyan/s2892/romstage.c index 443ded0..8f98e2c 100644 --- a/src/mainboard/tyan/s2892/romstage.c +++ b/src/mainboard/tyan/s2892/romstage.c @@ -3,7 +3,6 @@ #include <device/pci_def.h> #include <arch/io.h> #include <device/pnp_def.h> -#include <arch/romcc_io.h> #include <cpu/x86/lapic.h> #include <pc80/mc146818rtc.h> #include <console/console.h> diff --git a/src/mainboard/tyan/s2895/romstage.c b/src/mainboard/tyan/s2895/romstage.c index 1b5d21d..bc6763b 100644 --- a/src/mainboard/tyan/s2895/romstage.c +++ b/src/mainboard/tyan/s2895/romstage.c @@ -3,7 +3,6 @@ #include <device/pci_def.h> #include <arch/io.h> #include <device/pnp_def.h> -#include <arch/romcc_io.h> #include <cpu/x86/lapic.h> #include <pc80/mc146818rtc.h> #include <console/console.h> diff --git a/src/mainboard/tyan/s2912/ap_romstage.c b/src/mainboard/tyan/s2912/ap_romstage.c index 7d9c4b1..e22d2a5 100644 --- a/src/mainboard/tyan/s2912/ap_romstage.c +++ b/src/mainboard/tyan/s2912/ap_romstage.c @@ -26,7 +26,6 @@ #include <device/pci_ids.h> #include <arch/io.h> #include <device/pnp_def.h> -#include <arch/romcc_io.h> #include <cpu/x86/lapic.h> #include <pc80/mc146818rtc.h> #include "console/console.c" diff --git a/src/mainboard/tyan/s2912/romstage.c b/src/mainboard/tyan/s2912/romstage.c index a65b550..3cb8176 100644 --- a/src/mainboard/tyan/s2912/romstage.c +++ b/src/mainboard/tyan/s2912/romstage.c @@ -29,7 +29,6 @@ #include <device/pci_ids.h> #include <arch/io.h> #include <device/pnp_def.h> -#include <arch/romcc_io.h> #include <cpu/x86/lapic.h> #include <pc80/mc146818rtc.h> #include <console/console.h> diff --git a/src/mainboard/tyan/s2912_fam10/romstage.c b/src/mainboard/tyan/s2912_fam10/romstage.c index a2b344c..11394c7 100644 --- a/src/mainboard/tyan/s2912_fam10/romstage.c +++ b/src/mainboard/tyan/s2912_fam10/romstage.c @@ -28,7 +28,6 @@ #include <device/pci_ids.h> #include <arch/io.h> #include <device/pnp_def.h> -#include <arch/romcc_io.h> #include <cpu/x86/lapic.h> #include <console/console.h> #include <lib.h> diff --git a/src/mainboard/tyan/s4880/romstage.c b/src/mainboard/tyan/s4880/romstage.c index bd9c747..23efa10 100644 --- a/src/mainboard/tyan/s4880/romstage.c +++ b/src/mainboard/tyan/s4880/romstage.c @@ -3,7 +3,6 @@ #include <device/pci_def.h> #include <arch/io.h> #include <device/pnp_def.h> -#include <arch/romcc_io.h> #include <stdlib.h> #include <pc80/mc146818rtc.h> #include <console/console.h> diff --git a/src/mainboard/tyan/s4882/romstage.c b/src/mainboard/tyan/s4882/romstage.c index 363f3bb..e21cca3 100644 --- a/src/mainboard/tyan/s4882/romstage.c +++ b/src/mainboard/tyan/s4882/romstage.c @@ -3,7 +3,6 @@ #include <device/pci_def.h> #include <arch/io.h> #include <device/pnp_def.h> -#include <arch/romcc_io.h> #include <pc80/mc146818rtc.h> #include <console/console.h> #include <lib.h> diff --git a/src/mainboard/tyan/s8226/BiosCallOuts.c b/src/mainboard/tyan/s8226/BiosCallOuts.c index 8cb5b5c..0d6e175 100644 --- a/src/mainboard/tyan/s8226/BiosCallOuts.c +++ b/src/mainboard/tyan/s8226/BiosCallOuts.c @@ -25,7 +25,6 @@ #include "heapManager.h" #include <northbridge/amd/agesa/family15/dimmSpd.h> #include <arch/io.h> -#include <arch/romcc_io.h> #ifdef __PRE_RAM__ /* These defines are used to select the appropriate socket for the SPD read diff --git a/src/mainboard/tyan/s8226/reset.c b/src/mainboard/tyan/s8226/reset.c index 46f97ec..7a96aa4 100644 --- a/src/mainboard/tyan/s8226/reset.c +++ b/src/mainboard/tyan/s8226/reset.c @@ -17,10 +17,11 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ - +#ifndef __PRE_RAM__ +#define __PRE_RAM__ // Use simple device model for this file even in ramstage +#endif +#include <arch/io.h> #include <reset.h> -#include <arch/io.h> /*inb, outb*/ -#include <arch/romcc_io.h> /*pci_read_config32, device_t, PCI_DEV*/ #define HT_INIT_CONTROL 0x6C #define HTIC_BIOSR_Detect (1<<5) diff --git a/src/mainboard/tyan/s8226/romstage.c b/src/mainboard/tyan/s8226/romstage.c index 02f0c37..ee16ceb 100644 --- a/src/mainboard/tyan/s8226/romstage.c +++ b/src/mainboard/tyan/s8226/romstage.c @@ -21,7 +21,6 @@ #include <reset.h> #include <stdint.h> #include <arch/io.h> -#include <arch/romcc_io.h> #include <arch/cpu.h> #include <console/console.h> #include <arch/stages.h> diff --git a/src/mainboard/via/epia-cn/romstage.c b/src/mainboard/via/epia-cn/romstage.c index 6995f43..2d780db 100644 --- a/src/mainboard/via/epia-cn/romstage.c +++ b/src/mainboard/via/epia-cn/romstage.c @@ -24,7 +24,6 @@ #include <device/pci_ids.h> #include <arch/io.h> #include <device/pnp_def.h> -#include <arch/romcc_io.h> #include <arch/hlt.h> #include <console/console.h> #include <lib.h> diff --git a/src/mainboard/via/epia-m/romstage.c b/src/mainboard/via/epia-m/romstage.c index a424841..ebe6a50 100644 --- a/src/mainboard/via/epia-m/romstage.c +++ b/src/mainboard/via/epia-m/romstage.c @@ -3,7 +3,6 @@ #include <device/pci_ids.h> #include <arch/io.h> #include <device/pnp_def.h> -#include <arch/romcc_io.h> #include <arch/hlt.h> #include <stdlib.h> #include <console/console.h> diff --git a/src/mainboard/via/epia-m700/romstage.c b/src/mainboard/via/epia-m700/romstage.c index a7dcd72..1936052 100644 --- a/src/mainboard/via/epia-m700/romstage.c +++ b/src/mainboard/via/epia-m700/romstage.c @@ -29,7 +29,6 @@ #include <device/pci_ids.h> #include <arch/io.h> #include <device/pnp_def.h> -#include <arch/romcc_io.h> #include <arch/hlt.h> #include <console/console.h> #include <lib.h> diff --git a/src/mainboard/via/epia-n/romstage.c b/src/mainboard/via/epia-n/romstage.c index 6f5afab..568dab5 100644 --- a/src/mainboard/via/epia-n/romstage.c +++ b/src/mainboard/via/epia-n/romstage.c @@ -24,7 +24,6 @@ #include <device/pci_ids.h> #include <arch/io.h> #include <device/pnp_def.h> -#include <arch/romcc_io.h> #include <arch/hlt.h> #include <console/console.h> #include "northbridge/via/cn400/raminit.h" diff --git a/src/mainboard/via/epia/romstage.c b/src/mainboard/via/epia/romstage.c index fd053b6..b1e6c54 100644 --- a/src/mainboard/via/epia/romstage.c +++ b/src/mainboard/via/epia/romstage.c @@ -2,7 +2,6 @@ #include <device/pci_def.h> #include <arch/io.h> #include <device/pnp_def.h> -#include <arch/romcc_io.h> #include <arch/hlt.h> #include <stdlib.h> #include <console/console.h> diff --git a/src/mainboard/via/pc2500e/romstage.c b/src/mainboard/via/pc2500e/romstage.c index 5916971..0728154 100644 --- a/src/mainboard/via/pc2500e/romstage.c +++ b/src/mainboard/via/pc2500e/romstage.c @@ -23,7 +23,6 @@ #include <device/pci_ids.h> #include <arch/io.h> #include <device/pnp_def.h> -#include <arch/romcc_io.h> #include <arch/hlt.h> #include <pc80/mc146818rtc.h> #include <console/console.h> diff --git a/src/mainboard/via/vt8454c/romstage.c b/src/mainboard/via/vt8454c/romstage.c index 3fc7091..e1532be 100644 --- a/src/mainboard/via/vt8454c/romstage.c +++ b/src/mainboard/via/vt8454c/romstage.c @@ -24,7 +24,6 @@ #include <device/pci_ids.h> #include <arch/io.h> #include <device/pnp_def.h> -#include <arch/romcc_io.h> #include <arch/hlt.h> #include <console/console.h> #include <lib.h> diff --git a/src/northbridge/amd/amdfam10/bootblock.c b/src/northbridge/amd/amdfam10/bootblock.c index 612004a..de1b7d1 100644 --- a/src/northbridge/amd/amdfam10/bootblock.c +++ b/src/northbridge/amd/amdfam10/bootblock.c @@ -1,5 +1,4 @@ #include <arch/io.h> -#include <arch/romcc_io.h> #include <device/pci_def.h> #include "northbridge/amd/amdfam10/early_ht.c" diff --git a/src/northbridge/amd/amdk8/bootblock.c b/src/northbridge/amd/amdk8/bootblock.c index b5395bb..3a185a6 100644 --- a/src/northbridge/amd/amdk8/bootblock.c +++ b/src/northbridge/amd/amdk8/bootblock.c @@ -1,5 +1,4 @@ #include <arch/io.h> -#include <arch/romcc_io.h> #include <device/pci_def.h> #include "northbridge/amd/amdk8/early_ht.c" diff --git a/src/northbridge/amd/amdk8/coherent_ht.c b/src/northbridge/amd/amdk8/coherent_ht.c index 9ad3423..22d74c2 100644 --- a/src/northbridge/amd/amdk8/coherent_ht.c +++ b/src/northbridge/amd/amdk8/coherent_ht.c @@ -67,7 +67,7 @@ #include <device/pci_ids.h> #include <device/hypertransport_def.h> #include <stdlib.h> -#include "arch/romcc_io.h" +#include <arch/io.h> #include <pc80/mc146818rtc.h> #if CONFIG_HAVE_OPTION_TABLE #include "option_table.h" diff --git a/src/northbridge/intel/e7505/debug.c b/src/northbridge/intel/e7505/debug.c index 87569a5..3d6ca2a 100644 --- a/src/northbridge/intel/e7505/debug.c +++ b/src/northbridge/intel/e7505/debug.c @@ -3,7 +3,6 @@ #include <console/console.h> #include <stdlib.h> #include <arch/io.h> -#include <arch/romcc_io.h> #include <spd.h> #include "raminit.h" diff --git a/src/northbridge/intel/e7505/raminit.c b/src/northbridge/intel/e7505/raminit.c index 9fba602..ae02a7c 100644 --- a/src/northbridge/intel/e7505/raminit.c +++ b/src/northbridge/intel/e7505/raminit.c @@ -15,7 +15,6 @@ #include <stdint.h> #include <device/pci_def.h> #include <arch/io.h> -#include <arch/romcc_io.h> #include <arch/cpu.h> #include <stdlib.h> #include <console/console.h> diff --git a/src/northbridge/intel/gm45/early_init.c b/src/northbridge/intel/gm45/early_init.c index 09a166d..052c517 100644 --- a/src/northbridge/intel/gm45/early_init.c +++ b/src/northbridge/intel/gm45/early_init.c @@ -19,7 +19,6 @@ #include <stdint.h> #include <arch/io.h> -#include <arch/romcc_io.h> #include "gm45.h" void gm45_early_init(void) diff --git a/src/northbridge/intel/gm45/early_reset.c b/src/northbridge/intel/gm45/early_reset.c index f3902be..fccb97f 100644 --- a/src/northbridge/intel/gm45/early_reset.c +++ b/src/northbridge/intel/gm45/early_reset.c @@ -21,7 +21,6 @@ #include <types.h> #include <arch/io.h> -#include <arch/romcc_io.h> #include "gm45.h" void gm45_early_reset(void/*const timings_t *const timings*/) diff --git a/src/northbridge/intel/gm45/igd.c b/src/northbridge/intel/gm45/igd.c index c07fdfc2..d54ee41 100644 --- a/src/northbridge/intel/gm45/igd.c +++ b/src/northbridge/intel/gm45/igd.c @@ -22,7 +22,6 @@ #include <stdint.h> #include <stddef.h> #include <arch/io.h> -#include <arch/romcc_io.h> #include <device/pci_def.h> #include <console/console.h> diff --git a/src/northbridge/intel/gm45/iommu.c b/src/northbridge/intel/gm45/iommu.c index 89770ee..e40954a 100644 --- a/src/northbridge/intel/gm45/iommu.c +++ b/src/northbridge/intel/gm45/iommu.c @@ -23,7 +23,6 @@ #include <string.h> #include <arch/io.h> -#include <arch/romcc_io.h> #include <device/pci_def.h> #include <arch/acpi.h> diff --git a/src/northbridge/intel/gm45/pcie.c b/src/northbridge/intel/gm45/pcie.c index 6b42e15..39791a6 100644 --- a/src/northbridge/intel/gm45/pcie.c +++ b/src/northbridge/intel/gm45/pcie.c @@ -23,7 +23,6 @@ #include <stddef.h> #include <string.h> #include <arch/io.h> -#include <arch/romcc_io.h> #include <device/pci_def.h> #include <device/pnp_def.h> #include <console/console.h> diff --git a/src/northbridge/intel/gm45/pm.c b/src/northbridge/intel/gm45/pm.c index 32a5ba7..b9ac7f0 100644 --- a/src/northbridge/intel/gm45/pm.c +++ b/src/northbridge/intel/gm45/pm.c @@ -23,7 +23,6 @@ #include <stddef.h> #include <string.h> #include <arch/io.h> -#include <arch/romcc_io.h> #include <device/pci_def.h> #include <device/pnp_def.h> #include <console/console.h> diff --git a/src/northbridge/intel/gm45/ram_calc.c b/src/northbridge/intel/gm45/ram_calc.c index 1da9e87..9e54c10 100644 --- a/src/northbridge/intel/gm45/ram_calc.c +++ b/src/northbridge/intel/gm45/ram_calc.c @@ -19,9 +19,11 @@ * MA 02110-1301 USA */ +#ifndef __PRE_RAM__ +#define __PRE_RAM__ // Use simple device model for this file even in ramstage +#endif #include <stdint.h> #include <arch/io.h> -#include <arch/romcc_io.h> #include <device/pci_def.h> #include <console/console.h> #include "gm45.h" diff --git a/src/northbridge/intel/gm45/raminit.c b/src/northbridge/intel/gm45/raminit.c index 68c8120..d607f84 100644 --- a/src/northbridge/intel/gm45/raminit.c +++ b/src/northbridge/intel/gm45/raminit.c @@ -22,7 +22,6 @@ #include <stdint.h> #include <arch/cpu.h> #include <arch/io.h> -#include <arch/romcc_io.h> #include <device/pci_def.h> #include <device/pnp_def.h> #include <spd.h> diff --git a/src/northbridge/intel/gm45/thermal.c b/src/northbridge/intel/gm45/thermal.c index a74bcc5..c2ab2a5 100644 --- a/src/northbridge/intel/gm45/thermal.c +++ b/src/northbridge/intel/gm45/thermal.c @@ -23,7 +23,6 @@ #include <stddef.h> #include <string.h> #include <arch/io.h> -#include <arch/romcc_io.h> #include <device/pci_def.h> #include <device/pnp_def.h> #include <spd.h> diff --git a/src/northbridge/intel/haswell/bootblock.c b/src/northbridge/intel/haswell/bootblock.c index 35f357f..743007e 100644 --- a/src/northbridge/intel/haswell/bootblock.c +++ b/src/northbridge/intel/haswell/bootblock.c @@ -1,5 +1,4 @@ #include <arch/io.h> -#include <arch/romcc_io.h> /* Just re-define this instead of including haswell.h. It blows up romcc. */ #define PCIEXBAR 0x60 diff --git a/src/northbridge/intel/haswell/early_init.c b/src/northbridge/intel/haswell/early_init.c index 681af42..e3d218e 100644 --- a/src/northbridge/intel/haswell/early_init.c +++ b/src/northbridge/intel/haswell/early_init.c @@ -22,7 +22,6 @@ #include <stdlib.h> #include <console/console.h> #include <arch/io.h> -#include <arch/romcc_io.h> #include <device/pci_def.h> #include <elog.h> #include "haswell.h" diff --git a/src/northbridge/intel/haswell/finalize.c b/src/northbridge/intel/haswell/finalize.c index 58052f9..457f4af 100644 --- a/src/northbridge/intel/haswell/finalize.c +++ b/src/northbridge/intel/haswell/finalize.c @@ -19,7 +19,6 @@ */ #include <arch/io.h> -#include <arch/romcc_io.h> #include <stdlib.h> #include "haswell.h" diff --git a/src/northbridge/intel/haswell/raminit.c b/src/northbridge/intel/haswell/raminit.c index 1439200..9a9bb1c 100644 --- a/src/northbridge/intel/haswell/raminit.c +++ b/src/northbridge/intel/haswell/raminit.c @@ -21,7 +21,6 @@ #include <string.h> #include <arch/hlt.h> #include <arch/io.h> -#include <arch/romcc_io.h> #include <cbmem.h> #include <arch/cbfs.h> #include <cbfs.h> diff --git a/src/northbridge/intel/haswell/report_platform.c b/src/northbridge/intel/haswell/report_platform.c index 9a141b6..8bb4a05 100644 --- a/src/northbridge/intel/haswell/report_platform.c +++ b/src/northbridge/intel/haswell/report_platform.c @@ -22,9 +22,7 @@ #include <string.h> #include "southbridge/intel/lynxpoint/pch.h" #include <arch/io.h> -#include <arch/io.h> #include <cpu/x86/msr.h> -#include <arch/romcc_io.h> #include "haswell.h" static void report_cpu_info(void) diff --git a/src/northbridge/intel/i440bx/debug.c b/src/northbridge/intel/i440bx/debug.c index ef2f45c..ef9d513 100644 --- a/src/northbridge/intel/i440bx/debug.c +++ b/src/northbridge/intel/i440bx/debug.c @@ -1,6 +1,5 @@ #include <console/console.h> #include <arch/io.h> -#include <arch/romcc_io.h> #include <spd.h> #include "raminit.h" #include <spd.h> diff --git a/src/northbridge/intel/i440bx/raminit.c b/src/northbridge/intel/i440bx/raminit.c index 7472cc9..e3cfbdf 100644 --- a/src/northbridge/intel/i440bx/raminit.c +++ b/src/northbridge/intel/i440bx/raminit.c @@ -24,7 +24,6 @@ #include <stdint.h> #include <stdlib.h> #include <arch/io.h> -#include <arch/romcc_io.h> #include <device/pci_def.h> #include <console/console.h> #include "i440bx.h" diff --git a/src/northbridge/intel/i5000/raminit.c b/src/northbridge/intel/i5000/raminit.c index 3c913cf..48499da 100644 --- a/src/northbridge/intel/i5000/raminit.c +++ b/src/northbridge/intel/i5000/raminit.c @@ -21,7 +21,6 @@ #include "raminit.h" #include <arch/io.h> -#include <arch/romcc_io.h> #include <device/pci_def.h> #include <device/pnp_def.h> #include <cpu/x86/lapic.h> diff --git a/src/northbridge/intel/i5000/raminit.h b/src/northbridge/intel/i5000/raminit.h index d3fa16a..aa14092 100644 --- a/src/northbridge/intel/i5000/raminit.h +++ b/src/northbridge/intel/i5000/raminit.h @@ -24,7 +24,6 @@ #include <types.h> #include <arch/io.h> -#include <arch/romcc_io.h> #define I5000_MAX_BRANCH 2 #define I5000_MAX_CHANNEL 2 diff --git a/src/northbridge/intel/i82810/debug.c b/src/northbridge/intel/i82810/debug.c index 88adc24..c3e4fb9 100644 --- a/src/northbridge/intel/i82810/debug.c +++ b/src/northbridge/intel/i82810/debug.c @@ -1,6 +1,5 @@ #include <console/console.h> #include <arch/io.h> -#include <arch/romcc_io.h> #include <spd.h> #include "i82810.h" #include "raminit.h" diff --git a/src/northbridge/intel/i82810/raminit.c b/src/northbridge/intel/i82810/raminit.c index 6a85221..2c379e7 100644 --- a/src/northbridge/intel/i82810/raminit.c +++ b/src/northbridge/intel/i82810/raminit.c @@ -24,7 +24,6 @@ #include <delay.h> #include <stdint.h> #include <arch/io.h> -#include <arch/romcc_io.h> #include <device/pci_def.h> #include <console/console.h> #include "i82810.h" diff --git a/src/northbridge/intel/i82830/smihandler.c b/src/northbridge/intel/i82830/smihandler.c index 37b138a..e4d93cf 100644 --- a/src/northbridge/intel/i82830/smihandler.c +++ b/src/northbridge/intel/i82830/smihandler.c @@ -22,7 +22,6 @@ #include <types.h> #include <string.h> #include <arch/io.h> -#include <arch/romcc_io.h> #include <console/console.h> #include <cpu/x86/cache.h> #include <cpu/x86/smm.h> diff --git a/src/northbridge/intel/i945/debug.c b/src/northbridge/intel/i945/debug.c index 859a1ef..e47f762 100644 --- a/src/northbridge/intel/i945/debug.c +++ b/src/northbridge/intel/i945/debug.c @@ -22,7 +22,6 @@ #include <spd.h> #include <lib.h> #include <arch/io.h> -#include <arch/romcc_io.h> #include <device/pci_def.h> #include <console/console.h> #include "i945.h" diff --git a/src/northbridge/intel/i945/early_init.c b/src/northbridge/intel/i945/early_init.c index 12e320b..d91930f 100644 --- a/src/northbridge/intel/i945/early_init.c +++ b/src/northbridge/intel/i945/early_init.c @@ -21,7 +21,6 @@ #include <stdlib.h> #include <console/console.h> #include <arch/io.h> -#include <arch/romcc_io.h> #include <device/pci_def.h> #include "i945.h" #include "pcie_config.c" diff --git a/src/northbridge/intel/i945/raminit.c b/src/northbridge/intel/i945/raminit.c index bbd6528..b1a0684 100644 --- a/src/northbridge/intel/i945/raminit.c +++ b/src/northbridge/intel/i945/raminit.c @@ -23,7 +23,7 @@ #include <pc80/mc146818rtc.h> #include <spd.h> #include <string.h> -#include <arch/romcc_io.h> +#include <arch/io.h> #include "raminit.h" #include "i945.h" #include <cbmem.h> diff --git a/src/northbridge/intel/sandybridge/early_init.c b/src/northbridge/intel/sandybridge/early_init.c index fc10d34..c2d4909 100644 --- a/src/northbridge/intel/sandybridge/early_init.c +++ b/src/northbridge/intel/sandybridge/early_init.c @@ -22,7 +22,6 @@ #include <stdlib.h> #include <console/console.h> #include <arch/io.h> -#include <arch/romcc_io.h> #include <device/pci_def.h> #include <elog.h> #include "sandybridge.h" diff --git a/src/northbridge/intel/sandybridge/finalize.c b/src/northbridge/intel/sandybridge/finalize.c index 81512e7..0fa8d1a 100644 --- a/src/northbridge/intel/sandybridge/finalize.c +++ b/src/northbridge/intel/sandybridge/finalize.c @@ -19,7 +19,6 @@ */ #include <arch/io.h> -#include <arch/romcc_io.h> #include <stdlib.h> #include "pcie_config.c" #include "sandybridge.h" diff --git a/src/northbridge/intel/sandybridge/raminit.c b/src/northbridge/intel/sandybridge/raminit.c index 7597b02..78eedb8 100644 --- a/src/northbridge/intel/sandybridge/raminit.c +++ b/src/northbridge/intel/sandybridge/raminit.c @@ -21,7 +21,6 @@ #include <string.h> #include <arch/hlt.h> #include <arch/io.h> -#include <arch/romcc_io.h> #include <cbmem.h> #include <arch/cbfs.h> #include <cbfs.h> diff --git a/src/northbridge/intel/sandybridge/report_platform.c b/src/northbridge/intel/sandybridge/report_platform.c index 6e96c94..cc74841 100644 --- a/src/northbridge/intel/sandybridge/report_platform.c +++ b/src/northbridge/intel/sandybridge/report_platform.c @@ -22,7 +22,6 @@ #include <string.h> #include "southbridge/intel/bd82x6x/pch.h" #include <arch/io.h> -#include <arch/romcc_io.h> #include "sandybridge.h" static void report_cpu_info(void) diff --git a/src/northbridge/intel/sch/port_access.c b/src/northbridge/intel/sch/port_access.c index d3ba70d..c73f709 100644 --- a/src/northbridge/intel/sch/port_access.c +++ b/src/northbridge/intel/sch/port_access.c @@ -17,9 +17,11 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#ifndef __PRE_RAM__ +#define __PRE_RAM__ // Use simple device model for this file even in ramstage +#endif #include <stdint.h> #include <arch/io.h> -#include <arch/romcc_io.h> #include <device/pci_def.h> #include <device/pnp_def.h> #include <cpu/x86/lapic.h> diff --git a/src/northbridge/via/cx700/early_serial.c b/src/northbridge/via/cx700/early_serial.c index cde0b31..ae59295 100644 --- a/src/northbridge/via/cx700/early_serial.c +++ b/src/northbridge/via/cx700/early_serial.c @@ -21,7 +21,7 @@ * Enable the serial devices on the VIA CX700 */ -#include <arch/romcc_io.h> +#include <arch/io.h> static void cx700_writepnpaddr(u8 val) { diff --git a/src/northbridge/via/vx800/early_serial.c b/src/northbridge/via/vx800/early_serial.c index b6f58ac..b3ebde1 100644 --- a/src/northbridge/via/vx800/early_serial.c +++ b/src/northbridge/via/vx800/early_serial.c @@ -20,7 +20,7 @@ /* * Enable the serial devices on the VIA */ -#include <arch/romcc_io.h> +#include <arch/io.h> /* The base address is 0x15c, 0x2e, depending on config bytes */ diff --git a/src/northbridge/via/vx800/examples/romstage.c b/src/northbridge/via/vx800/examples/romstage.c index 228cc7e..7c3fb7a 100644 --- a/src/northbridge/via/vx800/examples/romstage.c +++ b/src/northbridge/via/vx800/examples/romstage.c @@ -24,7 +24,6 @@ #include <device/pci_ids.h> #include <arch/io.h> #include <device/pnp_def.h> -#include <arch/romcc_io.h> #include <arch/hlt.h> #include "console/console.c" #include "lib/ramtest.c" diff --git a/src/northbridge/via/vx800/pci_rawops.h b/src/northbridge/via/vx800/pci_rawops.h index 8e77560..33eebc4 100644 --- a/src/northbridge/via/vx800/pci_rawops.h +++ b/src/northbridge/via/vx800/pci_rawops.h @@ -22,7 +22,7 @@ #define NORTHBRIDGE_VIA_VX800_PCI_RAWOPS_H #include <stdint.h> -#include <arch/romcc_io.h> +#include <arch/io.h> struct VIA_PCI_REG_INIT_TABLE { u8 ChipRevisionStart; diff --git a/src/southbridge/amd/agesa/hudson/bootblock.c b/src/southbridge/amd/agesa/hudson/bootblock.c index 23be162..65810fa 100644 --- a/src/southbridge/amd/agesa/hudson/bootblock.c +++ b/src/southbridge/amd/agesa/hudson/bootblock.c @@ -19,7 +19,6 @@ #include <stdint.h> #include <arch/io.h> -#include <arch/romcc_io.h> #include <device/pci_ids.h> /* diff --git a/src/southbridge/amd/agesa/hudson/early_setup.c b/src/southbridge/amd/agesa/hudson/early_setup.c index 00ca7c6..a0319ab 100644 --- a/src/southbridge/amd/agesa/hudson/early_setup.c +++ b/src/southbridge/amd/agesa/hudson/early_setup.c @@ -21,8 +21,7 @@ #define _HUDSON_EARLY_SETUP_C_ #include <stdint.h> -#include <arch/io.h> /* inl, outl */ -#include <arch/romcc_io.h> /* device_t */ +#include <arch/io.h> #include <arch/acpi.h> #include <console/console.h> #include <reset.h> diff --git a/src/southbridge/amd/agesa/hudson/enable_usbdebug.c b/src/southbridge/amd/agesa/hudson/enable_usbdebug.c index e1e885c..c74ac9a 100644 --- a/src/southbridge/amd/agesa/hudson/enable_usbdebug.c +++ b/src/southbridge/amd/agesa/hudson/enable_usbdebug.c @@ -18,7 +18,6 @@ */ #include <stdint.h> #include <arch/io.h> -#include <arch/romcc_io.h> #include <usbdebug.h> #include <device/pci_def.h> #include "hudson.h" diff --git a/src/southbridge/amd/agesa/hudson/reset.c b/src/southbridge/amd/agesa/hudson/reset.c index c48aaeb..315a065 100644 --- a/src/southbridge/amd/agesa/hudson/reset.c +++ b/src/southbridge/amd/agesa/hudson/reset.c @@ -17,11 +17,13 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#include <reset.h> +#ifndef __PRE_RAM__ +#define __PRE_RAM__ // Use simple device model for this file even in ramstage +#endif #include <arch/io.h> -#include <arch/romcc_io.h> +#include <reset.h> -#include "../../../northbridge/amd/amdk8/reset_test.c" +#include <northbridge/amd/amdk8/reset_test.c> void hard_reset(void) { diff --git a/src/southbridge/amd/amd8111/bootblock.c b/src/southbridge/amd/amd8111/bootblock.c index 2df1fb9..ba3dc43 100644 --- a/src/southbridge/amd/amd8111/bootblock.c +++ b/src/southbridge/amd/amd8111/bootblock.c @@ -20,7 +20,6 @@ #include <stdint.h> #include <arch/io.h> -#include <arch/romcc_io.h> #include <device/pci_ids.h> /* Enable 5MB ROM access at 0xFFB00000 - 0xFFFFFFFF. */ diff --git a/src/southbridge/amd/cimx/sb700/bootblock.c b/src/southbridge/amd/cimx/sb700/bootblock.c index 8d77d22..fc7f3c5 100644 --- a/src/southbridge/amd/cimx/sb700/bootblock.c +++ b/src/southbridge/amd/cimx/sb700/bootblock.c @@ -19,8 +19,6 @@ #include <arch/io.h> -#include <arch/romcc_io.h> - #if CONFIG_CONSOLE_POST diff --git a/src/southbridge/amd/cimx/sb700/early.c b/src/southbridge/amd/cimx/sb700/early.c index d9ce75a..13c6379 100644 --- a/src/southbridge/amd/cimx/sb700/early.c +++ b/src/southbridge/amd/cimx/sb700/early.c @@ -17,12 +17,9 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ - -//#include <config.h> #include <stdint.h> #include <device/pci_ids.h> -#include <arch/io.h> /* inl, outl */ -#include <arch/romcc_io.h> /* device_t */ +#include <arch/io.h> #include "Platform.h" #include "sb_cimx.h" #include "sb700_cfg.h" /*sb700_cimx_config*/ @@ -30,7 +27,6 @@ #include <console/loglevel.h> #include "smbus.h" - #if CONFIG_RAMINIT_SYSINFO /** * @brief Get SouthBridge device number diff --git a/src/southbridge/amd/cimx/sb800/bootblock.c b/src/southbridge/amd/cimx/sb800/bootblock.c index d21b4fd..ac9351e 100644 --- a/src/southbridge/amd/cimx/sb800/bootblock.c +++ b/src/southbridge/amd/cimx/sb800/bootblock.c @@ -18,7 +18,6 @@ */ #include <arch/io.h> -#include <arch/romcc_io.h> static void enable_rom(void) { diff --git a/src/southbridge/amd/cimx/sb800/early.c b/src/southbridge/amd/cimx/sb800/early.c index 33afdcf..83087f5 100644 --- a/src/southbridge/amd/cimx/sb800/early.c +++ b/src/southbridge/amd/cimx/sb800/early.c @@ -17,19 +17,15 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ - -//#include <config.h> #include <stdint.h> #include <device/pci_ids.h> #include <arch/io.h> /* inl, outl */ -#include <arch/romcc_io.h> /* device_t */ #include <arch/acpi.h> #include "SBPLATFORM.h" #include "sb_cimx.h" #include "cfg.h" /*sb800_cimx_config*/ #include "cbmem.h" - #if CONFIG_RAMINIT_SYSINFO /** * @brief Get SouthBridge device number diff --git a/src/southbridge/amd/cimx/sb900/bootblock.c b/src/southbridge/amd/cimx/sb900/bootblock.c index c88a9fa..106f664 100644 --- a/src/southbridge/amd/cimx/sb900/bootblock.c +++ b/src/southbridge/amd/cimx/sb900/bootblock.c @@ -17,10 +17,7 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ - #include <arch/io.h> -#include <arch/romcc_io.h> - #if CONFIG_CONSOLE_POST diff --git a/src/southbridge/amd/cimx/sb900/early.c b/src/southbridge/amd/cimx/sb900/early.c index 5acbfa0..d6036dd 100644 --- a/src/southbridge/amd/cimx/sb900/early.c +++ b/src/southbridge/amd/cimx/sb900/early.c @@ -17,19 +17,18 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ - -//#include <config.h> +#ifndef __PRE_RAM__ +#define __PRE_RAM__ // Use simple device model for this file even in ramstage +#endif #include <stdint.h> #include <device/pci_ids.h> -#include <arch/io.h> /* inl, outl */ -#include <arch/romcc_io.h> /* device_t */ +#include <arch/io.h> #include "SbPlatform.h" #include "SbEarly.h" #include <console/console.h> #include <console/loglevel.h> #include "smbus.h" - /** * @brief Get SouthBridge device number * @param[in] bus target bus number @@ -39,13 +38,13 @@ u32 get_sbdn(u32 bus) { device_t dev; - printk(BIOS_INFO, "SB900 - Early.c - get_sbdn - Start.\n"); - //dev = PCI_DEV(bus, 0x14, 0); - dev = pci_locate_device_on_bus( - PCI_ID(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_ATI_SB900_SM), - bus); + printk(BIOS_SPEW, "SB900 - Early.c - get_sbdn - Start.\n"); + + dev = pci_locate_device_on_bus(PCI_ID(PCI_VENDOR_ID_AMD, + PCI_DEVICE_ID_ATI_SB900_SM), bus); + + printk(BIOS_SPEW, "SB900 - Early.c - get_sbdn - End.\n"); - printk(BIOS_INFO, "SB900 - Early.c - get_sbdn - End.\n"); return (dev >> 15) & 0x1f; } @@ -59,7 +58,7 @@ void sb_poweron_init(void) AMDSBCFG sb_early_cfg; u8 data; - printk(BIOS_INFO, "SB900 - Early.c - sb_poweron_init - Start.\n"); + printk(BIOS_SPEW, "SB900 - Early.c - sb_poweron_init - Start.\n"); //Enable/Disable PCI Bridge Device 14 Function 4. outb(0xEA, 0xCD6); @@ -77,7 +76,7 @@ void sb_poweron_init(void) //AMD_IMAGE_HEADER was missing, when using AmdSbDispatcher, // VerifyImage() will fail, LocateImage() take minitues to find the image. sbPowerOnInit(&sb_early_cfg); - printk(BIOS_INFO, "SB900 - Early.c - sb_poweron_init - End.\n"); + printk(BIOS_SPEW, "SB900 - Early.c - sb_poweron_init - End.\n"); } /** @@ -88,7 +87,7 @@ void sb_before_pci_init(void) { AMDSBCFG sb_early_cfg; - printk(BIOS_INFO, "SB900 - Early.c - sb_before_pci_init - Start.\n"); + printk(BIOS_SPEW, "SB900 - Early.c - sb_before_pci_init - Start.\n"); sb900_cimx_config(&sb_early_cfg); //sb_early_cfg.StdHeader.Func = SB_POWERON_INIT; //AmdSbDispatcher(&sb_early_cfg); @@ -96,14 +95,14 @@ void sb_before_pci_init(void) //AMD_IMAGE_HEADER was missing, when using AmdSbDispatcher, // VerifyImage() will fail, LocateImage() take minitues to find the image. sbBeforePciInit(&sb_early_cfg); - printk(BIOS_INFO, "SB900 - Early.c - sb_before_pci_init - End.\n"); + printk(BIOS_SPEW, "SB900 - Early.c - sb_before_pci_init - End.\n"); } void sb_After_Pci_Init(void) { AMDSBCFG sb_early_cfg; - printk(BIOS_INFO, "SB900 - Early.c - sb_After_Pci_Init - Start.\n"); + printk(BIOS_SPEW, "SB900 - Early.c - sb_After_Pci_Init - Start.\n"); sb900_cimx_config(&sb_early_cfg); //sb_early_cfg.StdHeader.Func = SB_POWERON_INIT; //AmdSbDispatcher(&sb_early_cfg); @@ -111,14 +110,14 @@ void sb_After_Pci_Init(void) //AMD_IMAGE_HEADER was missing, when using AmdSbDispatcher, // VerifyImage() will fail, LocateImage() take minitues to find the image. sbAfterPciInit(&sb_early_cfg); - printk(BIOS_INFO, "SB900 - Early.c - sb_After_Pci_Init - End.\n"); + printk(BIOS_SPEW, "SB900 - Early.c - sb_After_Pci_Init - End.\n"); } void sb_Mid_Post_Init(void) { AMDSBCFG sb_early_cfg; - printk(BIOS_INFO, "SB900 - Early.c - sb_Mid_Post_Init - Start.\n"); + printk(BIOS_SPEW, "SB900 - Early.c - sb_Mid_Post_Init - Start.\n"); sb900_cimx_config(&sb_early_cfg); //sb_early_cfg.StdHeader.Func = SB_POWERON_INIT; //AmdSbDispatcher(&sb_early_cfg); @@ -126,7 +125,7 @@ void sb_Mid_Post_Init(void) //AMD_IMAGE_HEADER was missing, when using AmdSbDispatcher, // VerifyImage() will fail, LocateImage() take minitues to find the image. sbMidPostInit(&sb_early_cfg); - printk(BIOS_INFO, "SB900 - Early.c - sb_Mid_Post_Init - End.\n"); + printk(BIOS_SPEW, "SB900 - Early.c - sb_Mid_Post_Init - End.\n"); } void sb_Late_Post(void) @@ -134,7 +133,7 @@ void sb_Late_Post(void) AMDSBCFG sb_early_cfg; u8 data; - printk(BIOS_INFO, "SB900 - Early.c - sb_Late_Post - Start.\n"); + printk(BIOS_SPEW, "SB900 - Early.c - sb_Late_Post - Start.\n"); sb900_cimx_config(&sb_early_cfg); //sb_early_cfg.StdHeader.Func = SB_POWERON_INIT; //AmdSbDispatcher(&sb_early_cfg); @@ -160,7 +159,5 @@ void sb_Late_Post(void) outb(data, 0x4D0); } - printk(BIOS_INFO, "SB900 - Early.c - sb_Late_Post - End.\n"); + printk(BIOS_SPEW, "SB900 - Early.c - sb_Late_Post - End.\n"); } - - diff --git a/src/southbridge/amd/sb600/bootblock.c b/src/southbridge/amd/sb600/bootblock.c index e848189..e31a96c 100644 --- a/src/southbridge/amd/sb600/bootblock.c +++ b/src/southbridge/amd/sb600/bootblock.c @@ -19,7 +19,6 @@ #include <stdint.h> #include <arch/io.h> -#include <arch/romcc_io.h> #include <device/pci_ids.h> /* diff --git a/src/southbridge/amd/sb600/enable_usbdebug.c b/src/southbridge/amd/sb600/enable_usbdebug.c index 4130dd5..305362f 100644 --- a/src/southbridge/amd/sb600/enable_usbdebug.c +++ b/src/southbridge/amd/sb600/enable_usbdebug.c @@ -19,7 +19,6 @@ #include <stdint.h> #include <arch/io.h> -#include <arch/romcc_io.h> #include <usbdebug.h> #include <device/pci_def.h> #include "sb600.h" diff --git a/src/southbridge/amd/sb600/reset.c b/src/southbridge/amd/sb600/reset.c index 0c94136..0936516 100644 --- a/src/southbridge/amd/sb600/reset.c +++ b/src/southbridge/amd/sb600/reset.c @@ -17,11 +17,13 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#ifndef __PRE_RAM__ +#define __PRE_RAM__ // Use simple device model for this file even in ramstage +#endif #include <arch/io.h> -#include <arch/romcc_io.h> #include <reset.h> -#include "northbridge/amd/amdk8/reset_test.c" +#include <northbridge/amd/amdk8/reset_test.c> void hard_reset(void) { diff --git a/src/southbridge/amd/sb700/bootblock.c b/src/southbridge/amd/sb700/bootblock.c index cffa5ca..c290806 100644 --- a/src/southbridge/amd/sb700/bootblock.c +++ b/src/southbridge/amd/sb700/bootblock.c @@ -19,7 +19,6 @@ #include <stdint.h> #include <arch/io.h> -#include <arch/romcc_io.h> #include <device/pci_ids.h> /* diff --git a/src/southbridge/amd/sb700/early_setup.c b/src/southbridge/amd/sb700/early_setup.c index bc6f910..a16fc9f 100644 --- a/src/southbridge/amd/sb700/early_setup.c +++ b/src/southbridge/amd/sb700/early_setup.c @@ -23,7 +23,6 @@ #include <stdint.h> #include <arch/cpu.h> #include <arch/io.h> -#include <arch/romcc_io.h> #include <console/console.h> #include <cpu/x86/msr.h> @@ -33,7 +32,6 @@ #include "sb700.h" #include "smbus.h" - static void pmio_write(u8 reg, u8 value) { outb(reg, PM_INDEX); diff --git a/src/southbridge/amd/sb700/enable_usbdebug.c b/src/southbridge/amd/sb700/enable_usbdebug.c index a816253..2a7fc38 100644 --- a/src/southbridge/amd/sb700/enable_usbdebug.c +++ b/src/southbridge/amd/sb700/enable_usbdebug.c @@ -20,7 +20,6 @@ #include <stdint.h> #include <arch/io.h> -#include <arch/romcc_io.h> #include <usbdebug.h> #include <device/pci_def.h> #include "sb700.h" diff --git a/src/southbridge/amd/sb700/reset.c b/src/southbridge/amd/sb700/reset.c index 9203b2b..ef4115e 100644 --- a/src/southbridge/amd/sb700/reset.c +++ b/src/southbridge/amd/sb700/reset.c @@ -17,9 +17,11 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#include <reset.h> /* hard_reset, soft_rest*/ -#include <arch/io.h> /* inb, outb */ -#include <arch/romcc_io.h> /* pci_read_config32, device_t, PCI_DEV */ +#ifndef __PRE_RAM__ +#define __PRE_RAM__ // Use simple device model for this file even in ramstage +#endif +#include <arch/io.h> +#include <reset.h> #define HT_INIT_CONTROL 0x6C #define HTIC_BIOSR_Detect (1<<5) diff --git a/src/southbridge/amd/sb800/bootblock.c b/src/southbridge/amd/sb800/bootblock.c index 9d90a34..9311b97 100644 --- a/src/southbridge/amd/sb800/bootblock.c +++ b/src/southbridge/amd/sb800/bootblock.c @@ -19,7 +19,6 @@ #include <stdint.h> #include <arch/io.h> -#include <arch/romcc_io.h> #include <device/pci_ids.h> /* diff --git a/src/southbridge/amd/sb800/enable_usbdebug.c b/src/southbridge/amd/sb800/enable_usbdebug.c index bdb4bde..f085eab 100644 --- a/src/southbridge/amd/sb800/enable_usbdebug.c +++ b/src/southbridge/amd/sb800/enable_usbdebug.c @@ -18,7 +18,6 @@ */ #include <stdint.h> #include <arch/io.h> -#include <arch/romcc_io.h> #include <usbdebug.h> #include <device/pci_def.h> #include "sb800.h" diff --git a/src/southbridge/amd/sb800/reset.c b/src/southbridge/amd/sb800/reset.c index c48aaeb..315a065 100644 --- a/src/southbridge/amd/sb800/reset.c +++ b/src/southbridge/amd/sb800/reset.c @@ -17,11 +17,13 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#include <reset.h> +#ifndef __PRE_RAM__ +#define __PRE_RAM__ // Use simple device model for this file even in ramstage +#endif #include <arch/io.h> -#include <arch/romcc_io.h> +#include <reset.h> -#include "../../../northbridge/amd/amdk8/reset_test.c" +#include <northbridge/amd/amdk8/reset_test.c> void hard_reset(void) { diff --git a/src/southbridge/amd/sr5650/early_setup.c b/src/southbridge/amd/sr5650/early_setup.c index cc73cec..65bce13 100644 --- a/src/southbridge/amd/sr5650/early_setup.c +++ b/src/southbridge/amd/sr5650/early_setup.c @@ -20,7 +20,6 @@ #include <stdint.h> #include <arch/cpu.h> #include <arch/io.h> -#include <arch/romcc_io.h> #include <console/console.h> #include <cpu/x86/msr.h> #include "sr5650.h" diff --git a/src/southbridge/broadcom/bcm5785/bootblock.c b/src/southbridge/broadcom/bcm5785/bootblock.c index 23ac1ee..166464c 100644 --- a/src/southbridge/broadcom/bcm5785/bootblock.c +++ b/src/southbridge/broadcom/bcm5785/bootblock.c @@ -20,7 +20,6 @@ #include <stdint.h> #include <arch/io.h> -#include <arch/romcc_io.h> #include <device/pci_ids.h> /* Enable 4MB ROM access at 0xFFC00000 - 0xFFFFFFFF. */ diff --git a/src/southbridge/intel/bd82x6x/bootblock.c b/src/southbridge/intel/bd82x6x/bootblock.c index 7f4f577..85a940e 100644 --- a/src/southbridge/intel/bd82x6x/bootblock.c +++ b/src/southbridge/intel/bd82x6x/bootblock.c @@ -18,7 +18,6 @@ */ #include <arch/io.h> -#include <arch/romcc_io.h> #include <cpu/x86/tsc.h> #include "pch.h" diff --git a/src/southbridge/intel/bd82x6x/early_me.c b/src/southbridge/intel/bd82x6x/early_me.c index 5b266cc..670e1ce 100644 --- a/src/southbridge/intel/bd82x6x/early_me.c +++ b/src/southbridge/intel/bd82x6x/early_me.c @@ -21,7 +21,6 @@ #include <arch/hlt.h> #include <arch/io.h> -#include <arch/romcc_io.h> #include <console/console.h> #include <delay.h> #include <device/pci_ids.h> diff --git a/src/southbridge/intel/bd82x6x/early_smbus.c b/src/southbridge/intel/bd82x6x/early_smbus.c index a626649..9de97e7 100644 --- a/src/southbridge/intel/bd82x6x/early_smbus.c +++ b/src/southbridge/intel/bd82x6x/early_smbus.c @@ -19,7 +19,6 @@ */ #include <arch/io.h> -#include <arch/romcc_io.h> #include <console/console.h> #include <device/pci_ids.h> #include <device/pci_def.h> diff --git a/src/southbridge/intel/bd82x6x/early_spi.c b/src/southbridge/intel/bd82x6x/early_spi.c index ddfc4c2..6f57f63 100644 --- a/src/southbridge/intel/bd82x6x/early_spi.c +++ b/src/southbridge/intel/bd82x6x/early_spi.c @@ -19,7 +19,6 @@ */ #include <arch/io.h> -#include <arch/romcc_io.h> #include <console/console.h> #include <device/pci_ids.h> #include <device/pci_def.h> diff --git a/src/southbridge/intel/bd82x6x/early_usb.c b/src/southbridge/intel/bd82x6x/early_usb.c index bbe792f..f4e526d 100644 --- a/src/southbridge/intel/bd82x6x/early_usb.c +++ b/src/southbridge/intel/bd82x6x/early_usb.c @@ -19,7 +19,6 @@ */ #include <arch/io.h> -#include <arch/romcc_io.h> #include <console/console.h> #include <device/pci_ids.h> #include <device/pci_def.h> diff --git a/src/southbridge/intel/bd82x6x/finalize.c b/src/southbridge/intel/bd82x6x/finalize.c index be6d480..bcc2f3d 100644 --- a/src/southbridge/intel/bd82x6x/finalize.c +++ b/src/southbridge/intel/bd82x6x/finalize.c @@ -19,7 +19,6 @@ */ #include <arch/io.h> -#include <arch/romcc_io.h> #include <console/post_codes.h> #include <northbridge/intel/sandybridge/pcie_config.c> #include "pch.h" diff --git a/src/southbridge/intel/bd82x6x/gpio.c b/src/southbridge/intel/bd82x6x/gpio.c index 25eda9a..39241d6 100644 --- a/src/southbridge/intel/bd82x6x/gpio.c +++ b/src/southbridge/intel/bd82x6x/gpio.c @@ -20,7 +20,6 @@ #include <stdint.h> #include <string.h> #include <arch/io.h> -#include <arch/romcc_io.h> #include "pch.h" #include "gpio.h" diff --git a/src/southbridge/intel/bd82x6x/me.c b/src/southbridge/intel/bd82x6x/me.c index b9aff37..7fdf926 100644 --- a/src/southbridge/intel/bd82x6x/me.c +++ b/src/southbridge/intel/bd82x6x/me.c @@ -38,7 +38,6 @@ #include <elog.h> #ifdef __SMM__ -# include <arch/romcc_io.h> # include <northbridge/intel/sandybridge/pcie_config.c> #else # include <device/device.h> diff --git a/src/southbridge/intel/bd82x6x/me_8.x.c b/src/southbridge/intel/bd82x6x/me_8.x.c index b71f7ea..f79adf5 100644 --- a/src/southbridge/intel/bd82x6x/me_8.x.c +++ b/src/southbridge/intel/bd82x6x/me_8.x.c @@ -38,7 +38,6 @@ #include <elog.h> #ifdef __SMM__ -# include <arch/romcc_io.h> # include <northbridge/intel/sandybridge/pcie_config.c> #else # include <device/device.h> diff --git a/src/southbridge/intel/bd82x6x/pch.c b/src/southbridge/intel/bd82x6x/pch.c index f2c7dc1..37a0b64 100644 --- a/src/southbridge/intel/bd82x6x/pch.c +++ b/src/southbridge/intel/bd82x6x/pch.c @@ -23,7 +23,6 @@ #include <delay.h> #ifdef __SMM__ #include <arch/io.h> -#include <arch/romcc_io.h> #include <device/pci_def.h> #else /* !__SMM__ */ #include <device/device.h> diff --git a/src/southbridge/intel/bd82x6x/smihandler.c b/src/southbridge/intel/bd82x6x/smihandler.c index 5d5dad1..545e268 100644 --- a/src/southbridge/intel/bd82x6x/smihandler.c +++ b/src/southbridge/intel/bd82x6x/smihandler.c @@ -22,7 +22,6 @@ #include <types.h> #include <arch/hlt.h> #include <arch/io.h> -#include <arch/romcc_io.h> #include <console/console.h> #include <cpu/x86/cache.h> #include <device/pci_def.h> diff --git a/src/southbridge/intel/bd82x6x/spi.c b/src/southbridge/intel/bd82x6x/spi.c index 4303dd0..09169b1 100644 --- a/src/southbridge/intel/bd82x6x/spi.c +++ b/src/southbridge/intel/bd82x6x/spi.c @@ -34,7 +34,6 @@ #define min(a, b) ((a)<(b)?(a):(b)) #ifdef __SMM__ -#include <arch/romcc_io.h> #include <northbridge/intel/sandybridge/pcie_config.c> #define pci_read_config_byte(dev, reg, targ)\ *(targ) = pcie_read_config8(dev, reg) diff --git a/src/southbridge/intel/bd82x6x/usb_debug.c b/src/southbridge/intel/bd82x6x/usb_debug.c index 607a88c..79a43bd 100644 --- a/src/southbridge/intel/bd82x6x/usb_debug.c +++ b/src/southbridge/intel/bd82x6x/usb_debug.c @@ -25,7 +25,6 @@ #include "pch.h" #ifdef __PRE_RAM__ -#include <arch/romcc_io.h> void enable_usbdebug(unsigned int port) { u32 dbgctl; diff --git a/src/southbridge/intel/i82371eb/bootblock.c b/src/southbridge/intel/i82371eb/bootblock.c index 135cbc0..b350bde 100644 --- a/src/southbridge/intel/i82371eb/bootblock.c +++ b/src/southbridge/intel/i82371eb/bootblock.c @@ -20,7 +20,6 @@ #include <stdint.h> #include <arch/io.h> -#include <arch/romcc_io.h> #include <device/pci_ids.h> #include "i82371eb.h" diff --git a/src/southbridge/intel/i82371eb/early_pm.c b/src/southbridge/intel/i82371eb/early_pm.c index aaf8611..a2f055b 100644 --- a/src/southbridge/intel/i82371eb/early_pm.c +++ b/src/southbridge/intel/i82371eb/early_pm.c @@ -20,7 +20,6 @@ #include <stdint.h> #include <arch/io.h> -#include <arch/romcc_io.h> #include <device/pci_def.h> #include <device/pci_ids.h> #include <console/console.h> diff --git a/src/southbridge/intel/i82371eb/early_smbus.c b/src/southbridge/intel/i82371eb/early_smbus.c index d0abcf4..80a4de9 100644 --- a/src/southbridge/intel/i82371eb/early_smbus.c +++ b/src/southbridge/intel/i82371eb/early_smbus.c @@ -20,7 +20,6 @@ #include <stdint.h> #include <arch/io.h> -#include <arch/romcc_io.h> #include <console/console.h> #include <device/pci_ids.h> #include <device/pci_def.h> diff --git a/src/southbridge/intel/i82801ax/early_smbus.c b/src/southbridge/intel/i82801ax/early_smbus.c index dde9f33..716652a 100644 --- a/src/southbridge/intel/i82801ax/early_smbus.c +++ b/src/southbridge/intel/i82801ax/early_smbus.c @@ -21,7 +21,6 @@ */ #include <arch/io.h> -#include <arch/romcc_io.h> #include <console/console.h> #include <device/pci_ids.h> #include <device/pci_def.h> diff --git a/src/southbridge/intel/i82801bx/early_smbus.c b/src/southbridge/intel/i82801bx/early_smbus.c index 0522e49..26c9e85 100644 --- a/src/southbridge/intel/i82801bx/early_smbus.c +++ b/src/southbridge/intel/i82801bx/early_smbus.c @@ -21,7 +21,6 @@ */ #include <arch/io.h> -#include <arch/romcc_io.h> #include <console/console.h> #include <device/pci_ids.h> #include <device/pci_def.h> diff --git a/src/southbridge/intel/i82801dx/early_smbus.c b/src/southbridge/intel/i82801dx/early_smbus.c index ca453a1..6f4d4f8 100644 --- a/src/southbridge/intel/i82801dx/early_smbus.c +++ b/src/southbridge/intel/i82801dx/early_smbus.c @@ -19,7 +19,6 @@ */ #include <arch/io.h> -#include <arch/romcc_io.h> #include <device/pci_def.h> #include <console/console.h> diff --git a/src/southbridge/intel/i82801dx/smihandler.c b/src/southbridge/intel/i82801dx/smihandler.c index 1d306da..61ac901 100644 --- a/src/southbridge/intel/i82801dx/smihandler.c +++ b/src/southbridge/intel/i82801dx/smihandler.c @@ -21,7 +21,6 @@ #include <types.h> #include <arch/io.h> -#include <arch/romcc_io.h> #include <console/console.h> #include <cpu/x86/cache.h> #include <cpu/x86/smm.h> diff --git a/src/southbridge/intel/i82801gx/bootblock.c b/src/southbridge/intel/i82801gx/bootblock.c index fc05206..b352fca 100644 --- a/src/southbridge/intel/i82801gx/bootblock.c +++ b/src/southbridge/intel/i82801gx/bootblock.c @@ -18,7 +18,6 @@ */ #include <arch/io.h> -#include <arch/romcc_io.h> static void enable_spi_prefetch(void) { diff --git a/src/southbridge/intel/i82801gx/early_smbus.c b/src/southbridge/intel/i82801gx/early_smbus.c index 7744e71..b11e4fa 100644 --- a/src/southbridge/intel/i82801gx/early_smbus.c +++ b/src/southbridge/intel/i82801gx/early_smbus.c @@ -19,7 +19,6 @@ */ #include <arch/io.h> -#include <arch/romcc_io.h> #include <console/console.h> #include <device/pci_ids.h> #include <device/pci_def.h> diff --git a/src/southbridge/intel/i82801gx/smihandler.c b/src/southbridge/intel/i82801gx/smihandler.c index 9d71fa3..f199b84 100644 --- a/src/southbridge/intel/i82801gx/smihandler.c +++ b/src/southbridge/intel/i82801gx/smihandler.c @@ -21,7 +21,6 @@ #include <types.h> #include <arch/io.h> -#include <arch/romcc_io.h> #include <console/console.h> #include <cpu/x86/cache.h> #include <cpu/x86/smm.h> diff --git a/src/southbridge/intel/i82801gx/usb_debug.c b/src/southbridge/intel/i82801gx/usb_debug.c index d5a743c..f447f7b 100644 --- a/src/southbridge/intel/i82801gx/usb_debug.c +++ b/src/southbridge/intel/i82801gx/usb_debug.c @@ -17,9 +17,11 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#ifndef __PRE_RAM__ +#define __PRE_RAM__ // Use simple device model for this file even in ramstage +#endif #include <stdint.h> #include <arch/io.h> -#include <arch/romcc_io.h> #include <console/console.h> #include <usbdebug.h> #include <device/pci_def.h> diff --git a/src/southbridge/intel/i82801ix/bootblock.c b/src/southbridge/intel/i82801ix/bootblock.c index fc05206..b352fca 100644 --- a/src/southbridge/intel/i82801ix/bootblock.c +++ b/src/southbridge/intel/i82801ix/bootblock.c @@ -18,7 +18,6 @@ */ #include <arch/io.h> -#include <arch/romcc_io.h> static void enable_spi_prefetch(void) { diff --git a/src/southbridge/intel/i82801ix/dmi_setup.c b/src/southbridge/intel/i82801ix/dmi_setup.c index c25c234..0514719 100644 --- a/src/southbridge/intel/i82801ix/dmi_setup.c +++ b/src/southbridge/intel/i82801ix/dmi_setup.c @@ -19,7 +19,6 @@ */ #include <arch/io.h> -#include <arch/romcc_io.h> #include <device/pci_def.h> #include <console/console.h> #include <northbridge/intel/gm45/gm45.h> diff --git a/src/southbridge/intel/i82801ix/early_init.c b/src/southbridge/intel/i82801ix/early_init.c index af2e63f..8849cfa 100644 --- a/src/southbridge/intel/i82801ix/early_init.c +++ b/src/southbridge/intel/i82801ix/early_init.c @@ -19,7 +19,6 @@ */ #include <arch/io.h> -#include <arch/romcc_io.h> #include "i82801ix.h" void i82801ix_early_init(void) diff --git a/src/southbridge/intel/i82801ix/early_smbus.c b/src/southbridge/intel/i82801ix/early_smbus.c index 74b36e6..226afac 100644 --- a/src/southbridge/intel/i82801ix/early_smbus.c +++ b/src/southbridge/intel/i82801ix/early_smbus.c @@ -20,7 +20,6 @@ */ #include <arch/io.h> -#include <arch/romcc_io.h> #include <console/console.h> #include <device/pci_ids.h> #include <device/pci_def.h> diff --git a/src/southbridge/intel/i82801ix/smihandler.c b/src/southbridge/intel/i82801ix/smihandler.c index 4e8edfe..913223b 100644 --- a/src/southbridge/intel/i82801ix/smihandler.c +++ b/src/southbridge/intel/i82801ix/smihandler.c @@ -22,7 +22,6 @@ #include <types.h> #include <arch/io.h> -#include <arch/romcc_io.h> #include <console/console.h> #include <cpu/x86/cache.h> #include <cpu/x86/smm.h> diff --git a/src/southbridge/intel/lynxpoint/bootblock.c b/src/southbridge/intel/lynxpoint/bootblock.c index 2770d55..9629118 100644 --- a/src/southbridge/intel/lynxpoint/bootblock.c +++ b/src/southbridge/intel/lynxpoint/bootblock.c @@ -18,7 +18,6 @@ */ #include <arch/io.h> -#include <arch/romcc_io.h> #include <cpu/x86/tsc.h> #include "pch.h" diff --git a/src/southbridge/intel/lynxpoint/early_me.c b/src/southbridge/intel/lynxpoint/early_me.c index e41b801..6b61eac 100644 --- a/src/southbridge/intel/lynxpoint/early_me.c +++ b/src/southbridge/intel/lynxpoint/early_me.c @@ -21,7 +21,6 @@ #include <arch/hlt.h> #include <arch/io.h> -#include <arch/romcc_io.h> #include <console/console.h> #include <delay.h> #include <device/pci_ids.h> diff --git a/src/southbridge/intel/lynxpoint/early_pch.c b/src/southbridge/intel/lynxpoint/early_pch.c index 848eb56..de583f0 100644 --- a/src/southbridge/intel/lynxpoint/early_pch.c +++ b/src/southbridge/intel/lynxpoint/early_pch.c @@ -20,7 +20,6 @@ #include <console/console.h> #include <arch/io.h> -#include <arch/romcc_io.h> #include <device/pci_def.h> #include <elog.h> #include "pch.h" diff --git a/src/southbridge/intel/lynxpoint/early_smbus.c b/src/southbridge/intel/lynxpoint/early_smbus.c index a626649..9de97e7 100644 --- a/src/southbridge/intel/lynxpoint/early_smbus.c +++ b/src/southbridge/intel/lynxpoint/early_smbus.c @@ -19,7 +19,6 @@ */ #include <arch/io.h> -#include <arch/romcc_io.h> #include <console/console.h> #include <device/pci_ids.h> #include <device/pci_def.h> diff --git a/src/southbridge/intel/lynxpoint/early_spi.c b/src/southbridge/intel/lynxpoint/early_spi.c index ddfc4c2..6f57f63 100644 --- a/src/southbridge/intel/lynxpoint/early_spi.c +++ b/src/southbridge/intel/lynxpoint/early_spi.c @@ -19,7 +19,6 @@ */ #include <arch/io.h> -#include <arch/romcc_io.h> #include <console/console.h> #include <device/pci_ids.h> #include <device/pci_def.h> diff --git a/src/southbridge/intel/lynxpoint/early_usb.c b/src/southbridge/intel/lynxpoint/early_usb.c index b2e0091..ebd5c2c 100644 --- a/src/southbridge/intel/lynxpoint/early_usb.c +++ b/src/southbridge/intel/lynxpoint/early_usb.c @@ -19,7 +19,6 @@ */ #include <arch/io.h> -#include <arch/romcc_io.h> #include <console/console.h> #include <device/pci_ids.h> #include <device/pci_def.h> diff --git a/src/southbridge/intel/lynxpoint/finalize.c b/src/southbridge/intel/lynxpoint/finalize.c index 2cece13..d9bc225 100644 --- a/src/southbridge/intel/lynxpoint/finalize.c +++ b/src/southbridge/intel/lynxpoint/finalize.c @@ -19,7 +19,6 @@ */ #include <arch/io.h> -#include <arch/romcc_io.h> #include <console/post_codes.h> #include <spi-generic.h> #include "pch.h" diff --git a/src/southbridge/intel/lynxpoint/gpio.c b/src/southbridge/intel/lynxpoint/gpio.c index 9d36887..b492068 100644 --- a/src/southbridge/intel/lynxpoint/gpio.c +++ b/src/southbridge/intel/lynxpoint/gpio.c @@ -20,14 +20,8 @@ #include <stdint.h> #include <string.h> #include <arch/io.h> - -#ifdef __PRE_RAM__ -#include <arch/romcc_io.h> -#else #include <device/device.h> #include <device/pci.h> -#endif - #include "pch.h" #include "gpio.h" diff --git a/src/southbridge/intel/lynxpoint/lp_gpio.c b/src/southbridge/intel/lynxpoint/lp_gpio.c index 2d2e057..a6e4f5c 100644 --- a/src/southbridge/intel/lynxpoint/lp_gpio.c +++ b/src/southbridge/intel/lynxpoint/lp_gpio.c @@ -20,12 +20,8 @@ #include <stdint.h> #include <string.h> #include <arch/io.h> -#ifdef __PRE_RAM__ -#include <arch/romcc_io.h> -#else #include <device/device.h> #include <device/pci.h> -#endif #include "pch.h" #include "lp_gpio.h" diff --git a/src/southbridge/intel/lynxpoint/me_9.x.c b/src/southbridge/intel/lynxpoint/me_9.x.c index 63b5205..21ff922 100644 --- a/src/southbridge/intel/lynxpoint/me_9.x.c +++ b/src/southbridge/intel/lynxpoint/me_9.x.c @@ -31,19 +31,14 @@ #include <arch/hlt.h> #include <arch/io.h> #include <console/console.h> +#include <device/device.h> +#include <device/pci.h> #include <device/pci_ids.h> #include <device/pci_def.h> #include <string.h> #include <delay.h> #include <elog.h> -#ifdef __SMM__ -# include <arch/romcc_io.h> -#else -# include <device/device.h> -# include <device/pci.h> -#endif - #include "me.h" #include "pch.h" diff --git a/src/southbridge/intel/lynxpoint/smihandler.c b/src/southbridge/intel/lynxpoint/smihandler.c index 48dca2c..4aa6cb3 100644 --- a/src/southbridge/intel/lynxpoint/smihandler.c +++ b/src/southbridge/intel/lynxpoint/smihandler.c @@ -22,7 +22,6 @@ #include <types.h> #include <arch/hlt.h> #include <arch/io.h> -#include <arch/romcc_io.h> #include <console/console.h> #include <cpu/x86/cache.h> #include <device/pci_def.h> diff --git a/src/southbridge/intel/lynxpoint/spi.c b/src/southbridge/intel/lynxpoint/spi.c index 123c6a9..eaa17d5 100644 --- a/src/southbridge/intel/lynxpoint/spi.c +++ b/src/southbridge/intel/lynxpoint/spi.c @@ -34,7 +34,6 @@ #define min(a, b) ((a)<(b)?(a):(b)) #ifdef __SMM__ -#include <arch/romcc_io.h> #define pci_read_config_byte(dev, reg, targ)\ *(targ) = pci_read_config8(dev, reg) #define pci_read_config_word(dev, reg, targ)\ diff --git a/src/southbridge/intel/lynxpoint/usb_debug.c b/src/southbridge/intel/lynxpoint/usb_debug.c index 1cee353..d8da7b5 100644 --- a/src/southbridge/intel/lynxpoint/usb_debug.c +++ b/src/southbridge/intel/lynxpoint/usb_debug.c @@ -19,7 +19,6 @@ #include <stdint.h> #include <arch/io.h> -#include <arch/romcc_io.h> #include <console/console.h> #include <usbdebug.h> #include <device/pci_def.h> diff --git a/src/southbridge/intel/sch/early_smbus.c b/src/southbridge/intel/sch/early_smbus.c index 9a01504..8adc04d 100644 --- a/src/southbridge/intel/sch/early_smbus.c +++ b/src/southbridge/intel/sch/early_smbus.c @@ -19,7 +19,6 @@ */ #include <arch/io.h> -#include <arch/romcc_io.h> #include <console/console.h> #include <device/pci_ids.h> #include <device/pci_def.h> diff --git a/src/southbridge/intel/sch/smihandler.c b/src/southbridge/intel/sch/smihandler.c index 99ae018..bbaf4bb 100644 --- a/src/southbridge/intel/sch/smihandler.c +++ b/src/southbridge/intel/sch/smihandler.c @@ -20,7 +20,6 @@ */ #include <arch/io.h> -#include <arch/romcc_io.h> #include <console/console.h> #include <cpu/x86/cache.h> #include <cpu/x86/smm.h> diff --git a/src/southbridge/intel/sch/usb_debug.c b/src/southbridge/intel/sch/usb_debug.c index 1986258..4189716 100644 --- a/src/southbridge/intel/sch/usb_debug.c +++ b/src/southbridge/intel/sch/usb_debug.c @@ -19,7 +19,6 @@ #include <stdint.h> #include <arch/io.h> -#include <arch/romcc_io.h> #include <console/console.h> #include <usbdebug.h> #include <device/pci_def.h> diff --git a/src/southbridge/nvidia/ck804/bootblock.c b/src/southbridge/nvidia/ck804/bootblock.c index a8d0cc9..e2f6bc0 100644 --- a/src/southbridge/nvidia/ck804/bootblock.c +++ b/src/southbridge/nvidia/ck804/bootblock.c @@ -19,7 +19,6 @@ */ #include <arch/io.h> -#include <arch/romcc_io.h> #if CONFIG_HT_CHAIN_END_UNITID_BASE < CONFIG_HT_CHAIN_UNITID_BASE #define CK804_DEVN_BASE CONFIG_HT_CHAIN_END_UNITID_BASE diff --git a/src/southbridge/nvidia/ck804/early_smbus.c b/src/southbridge/nvidia/ck804/early_smbus.c index 993ff2e..a8c12a2 100644 --- a/src/southbridge/nvidia/ck804/early_smbus.c +++ b/src/southbridge/nvidia/ck804/early_smbus.c @@ -20,7 +20,6 @@ #include <stdint.h> #include <arch/io.h> -#include <arch/romcc_io.h> #include <console/console.h> #include <device/pci_def.h> #include <device/pci_ids.h> diff --git a/src/southbridge/nvidia/ck804/enable_usbdebug.c b/src/southbridge/nvidia/ck804/enable_usbdebug.c index c4b62e2..659fdc6 100644 --- a/src/southbridge/nvidia/ck804/enable_usbdebug.c +++ b/src/southbridge/nvidia/ck804/enable_usbdebug.c @@ -23,7 +23,6 @@ #include <stdint.h> #include <arch/io.h> -#include <arch/romcc_io.h> #include <usbdebug.h> #include <device/pci_def.h> #include "ck804.h" diff --git a/src/southbridge/nvidia/mcp55/bootblock.c b/src/southbridge/nvidia/mcp55/bootblock.c index 59a0aae..431c426 100644 --- a/src/southbridge/nvidia/mcp55/bootblock.c +++ b/src/southbridge/nvidia/mcp55/bootblock.c @@ -23,7 +23,6 @@ #include <stdint.h> #include <arch/io.h> -#include <arch/romcc_io.h> #include "mcp55.h" static void mcp55_enable_rom(void) diff --git a/src/southbridge/nvidia/mcp55/enable_usbdebug.c b/src/southbridge/nvidia/mcp55/enable_usbdebug.c index 4a03a27..f753c78 100644 --- a/src/southbridge/nvidia/mcp55/enable_usbdebug.c +++ b/src/southbridge/nvidia/mcp55/enable_usbdebug.c @@ -23,7 +23,6 @@ #include <stdint.h> #include <arch/io.h> -#include <arch/romcc_io.h> #include <usbdebug.h> #include <device/pci_def.h> #include "mcp55.h" diff --git a/src/southbridge/rdc/r8610/bootblock.c b/src/southbridge/rdc/r8610/bootblock.c index c87940a..2e5e360 100644 --- a/src/southbridge/rdc/r8610/bootblock.c +++ b/src/southbridge/rdc/r8610/bootblock.c @@ -18,7 +18,6 @@ */ #include <arch/io.h> -#include <arch/romcc_io.h> #include <device/pci_def.h> static void bootblock_southbridge_init(void) { diff --git a/src/southbridge/sis/sis966/bootblock.c b/src/southbridge/sis/sis966/bootblock.c index f4cb264..ac4919a 100644 --- a/src/southbridge/sis/sis966/bootblock.c +++ b/src/southbridge/sis/sis966/bootblock.c @@ -25,7 +25,6 @@ #include <stdint.h> #include <arch/io.h> -#include <arch/romcc_io.h> #include <device/pci_ids.h> #include "sis966.h" diff --git a/src/southbridge/sis/sis966/enable_usbdebug.c b/src/southbridge/sis/sis966/enable_usbdebug.c index cf19577..78a3838 100644 --- a/src/southbridge/sis/sis966/enable_usbdebug.c +++ b/src/southbridge/sis/sis966/enable_usbdebug.c @@ -25,7 +25,6 @@ #include <stdint.h> #include <arch/io.h> -#include <arch/romcc_io.h> #include <usbdebug.h> #include <device/pci_def.h> #include "sis966.h" diff --git a/src/southbridge/via/vt8231/enable_rom.c b/src/southbridge/via/vt8231/enable_rom.c index f2d0866..618adf8 100644 --- a/src/southbridge/via/vt8231/enable_rom.c +++ b/src/southbridge/via/vt8231/enable_rom.c @@ -19,7 +19,6 @@ */ #include <arch/io.h> -#include <arch/romcc_io.h> #include <device/pci_ids.h> static void vt8231_enable_rom(void) diff --git a/src/southbridge/via/vt8237r/bootblock.c b/src/southbridge/via/vt8237r/bootblock.c index 9829791..0d92073 100644 --- a/src/southbridge/via/vt8237r/bootblock.c +++ b/src/southbridge/via/vt8237r/bootblock.c @@ -18,7 +18,6 @@ */ #include <arch/io.h> -#include <arch/romcc_io.h> #include <device/pci_ids.h> static void bootblock_southbridge_init(void) diff --git a/src/southbridge/via/vt8237r/smihandler.c b/src/southbridge/via/vt8237r/smihandler.c index 357e517..d46c4ec 100644 --- a/src/southbridge/via/vt8237r/smihandler.c +++ b/src/southbridge/via/vt8237r/smihandler.c @@ -22,7 +22,6 @@ #include <types.h> #include <arch/io.h> -#include <arch/romcc_io.h> #include <console/console.h> #include <cpu/x86/cache.h> #include <cpu/x86/smm.h> diff --git a/src/southbridge/via/vt82c686/early_serial.c b/src/southbridge/via/vt82c686/early_serial.c index 8ac79d6..70b6b54 100644 --- a/src/southbridge/via/vt82c686/early_serial.c +++ b/src/southbridge/via/vt82c686/early_serial.c @@ -22,7 +22,7 @@ /* This has been ported to the VIA VT82C686(A/B) from the SMSC FDC37M60x * by Corey Osgood. See vt82c686.h for more information. */ -#include <arch/romcc_io.h> +#include <arch/io.h> #include <device/pci_ids.h> #include "vt82c686.h" diff --git a/src/superio/fintek/f71805f/early_serial.c b/src/superio/fintek/f71805f/early_serial.c index e774f0c..827f870 100644 --- a/src/superio/fintek/f71805f/early_serial.c +++ b/src/superio/fintek/f71805f/early_serial.c @@ -20,7 +20,7 @@ /* Pre-RAM driver for the Fintek F71805F/FG Super I/O chip. */ -#include <arch/romcc_io.h> +#include <arch/io.h> #include "f71805f.h" static void pnp_enter_conf_state(device_t dev) diff --git a/src/superio/fintek/f71859/early_serial.c b/src/superio/fintek/f71859/early_serial.c index 6781ad7..4401714 100644 --- a/src/superio/fintek/f71859/early_serial.c +++ b/src/superio/fintek/f71859/early_serial.c @@ -20,7 +20,7 @@ /* Pre-RAM driver for the Fintek F71859 Super I/O chip. */ -#include <arch/romcc_io.h> +#include <arch/io.h> #include "f71859.h" static void pnp_enter_conf_state(device_t dev) diff --git a/src/superio/fintek/f71863fg/early_serial.c b/src/superio/fintek/f71863fg/early_serial.c index bf6c9ab..5d1cfb7 100644 --- a/src/superio/fintek/f71863fg/early_serial.c +++ b/src/superio/fintek/f71863fg/early_serial.c @@ -20,7 +20,7 @@ /* Pre-RAM driver for the Fintek F71863FG Super I/O chip. */ -#include <arch/romcc_io.h> +#include <arch/io.h> #include "f71863fg.h" static void pnp_enter_conf_state(device_t dev) diff --git a/src/superio/fintek/f71872/early_serial.c b/src/superio/fintek/f71872/early_serial.c index 55646a4..af5cdb3 100644 --- a/src/superio/fintek/f71872/early_serial.c +++ b/src/superio/fintek/f71872/early_serial.c @@ -20,7 +20,7 @@ /* Pre-RAM driver for the Fintek F71872F/FG Super I/O chip. */ -#include <arch/romcc_io.h> +#include <arch/io.h> #include "f71872.h" static void pnp_enter_conf_state(device_t dev) diff --git a/src/superio/fintek/f71889/early_serial.c b/src/superio/fintek/f71889/early_serial.c index 4548e1c..9623cbd 100644 --- a/src/superio/fintek/f71889/early_serial.c +++ b/src/superio/fintek/f71889/early_serial.c @@ -19,7 +19,7 @@ */ #include <stdint.h> -#include <arch/romcc_io.h> +#include <arch/io.h> #include "f71889.h" static void pnp_enter_conf_state(device_t dev) diff --git a/src/superio/fintek/f81865f/f81865f_early_serial.c b/src/superio/fintek/f81865f/f81865f_early_serial.c index 80af5aa..2989b5f 100644 --- a/src/superio/fintek/f81865f/f81865f_early_serial.c +++ b/src/superio/fintek/f81865f/f81865f_early_serial.c @@ -20,7 +20,7 @@ /* Pre-RAM driver for the Fintek F81865F/FG Super I/O chip. */ -#include <arch/romcc_io.h> +#include <arch/io.h> #include "f81865f.h" static void pnp_enter_conf_state(device_t dev) diff --git a/src/superio/intel/i3100/early_serial.c b/src/superio/intel/i3100/early_serial.c index 9508bc3..f95cf8a 100644 --- a/src/superio/intel/i3100/early_serial.c +++ b/src/superio/intel/i3100/early_serial.c @@ -18,7 +18,7 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#include <arch/romcc_io.h> +#include <arch/io.h> #include "i3100.h" static void pnp_enter_ext_func_mode(device_t dev) diff --git a/src/superio/ite/it8661f/early_serial.c b/src/superio/ite/it8661f/early_serial.c index 4bc88b1..ee132fa 100644 --- a/src/superio/ite/it8661f/early_serial.c +++ b/src/superio/ite/it8661f/early_serial.c @@ -18,7 +18,7 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#include <arch/romcc_io.h> +#include <arch/io.h> #include "it8661f.h" /* Perform MB PnP setup to put the SIO chip at 0x3f0. */ diff --git a/src/superio/ite/it8671f/early_serial.c b/src/superio/ite/it8671f/early_serial.c index 7b9e1b5..c2ba6e0 100644 --- a/src/superio/ite/it8671f/early_serial.c +++ b/src/superio/ite/it8671f/early_serial.c @@ -18,7 +18,7 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#include <arch/romcc_io.h> +#include <arch/io.h> #include "it8671f.h" /* The base address is 0x3f0, 0x3bd, or 0x370, depending on config bytes. */ diff --git a/src/superio/ite/it8673f/early_serial.c b/src/superio/ite/it8673f/early_serial.c index 61e8eff..987b5e6 100644 --- a/src/superio/ite/it8673f/early_serial.c +++ b/src/superio/ite/it8673f/early_serial.c @@ -18,7 +18,7 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#include <arch/romcc_io.h> +#include <arch/io.h> #include "it8673f.h" /* The base address is 0x3f0, 0x3bd, or 0x370, depending on config bytes. */ diff --git a/src/superio/ite/it8705f/early_serial.c b/src/superio/ite/it8705f/early_serial.c index d1e6b4f..ccc92c2 100644 --- a/src/superio/ite/it8705f/early_serial.c +++ b/src/superio/ite/it8705f/early_serial.c @@ -18,7 +18,7 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#include <arch/romcc_io.h> +#include <arch/io.h> #include "it8705f.h" /* The base address is 0x2e or 0x4e, depending on config bytes. */ diff --git a/src/superio/ite/it8712f/early_serial.c b/src/superio/ite/it8712f/early_serial.c index 6cf5afd..51564fc 100644 --- a/src/superio/ite/it8712f/early_serial.c +++ b/src/superio/ite/it8712f/early_serial.c @@ -18,7 +18,7 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#include <arch/romcc_io.h> +#include <arch/io.h> #include "it8712f.h" /* The base address is 0x2e or 0x4e, depending on config bytes. */ diff --git a/src/superio/ite/it8716f/early_init.c b/src/superio/ite/it8716f/early_init.c index 8d684b6..cfac2a9 100644 --- a/src/superio/ite/it8716f/early_init.c +++ b/src/superio/ite/it8716f/early_init.c @@ -19,7 +19,7 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#include <arch/romcc_io.h> +#include <arch/io.h> #include "it8716f.h" void it8716f_disable_dev(device_t dev) diff --git a/src/superio/ite/it8716f/early_serial.c b/src/superio/ite/it8716f/early_serial.c index 55047f8..02f0304 100644 --- a/src/superio/ite/it8716f/early_serial.c +++ b/src/superio/ite/it8716f/early_serial.c @@ -21,7 +21,7 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#include <arch/romcc_io.h> +#include <arch/io.h> #include "it8716f.h" /* The base address is 0x2e or 0x4e, depending on config bytes. */ diff --git a/src/superio/ite/it8718f/early_serial.c b/src/superio/ite/it8718f/early_serial.c index a4335f3..308b67c 100644 --- a/src/superio/ite/it8718f/early_serial.c +++ b/src/superio/ite/it8718f/early_serial.c @@ -18,7 +18,7 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#include <arch/romcc_io.h> +#include <arch/io.h> #include "it8718f.h" /* The base address is 0x2e or 0x4e, depending on config bytes. */ diff --git a/src/superio/ite/it8721f/early_serial.c b/src/superio/ite/it8721f/early_serial.c index 8272ef6..20e19b6 100644 --- a/src/superio/ite/it8721f/early_serial.c +++ b/src/superio/ite/it8721f/early_serial.c @@ -19,7 +19,7 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#include <arch/romcc_io.h> +#include <arch/io.h> #include "it8721f.h" /* The base address is 0x2e or 0x4e, depending on config bytes. */ diff --git a/src/superio/ite/it8772f/early_serial.c b/src/superio/ite/it8772f/early_serial.c index 8cf459a..8bf2964 100644 --- a/src/superio/ite/it8772f/early_serial.c +++ b/src/superio/ite/it8772f/early_serial.c @@ -18,7 +18,7 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#include <arch/romcc_io.h> +#include <arch/io.h> #include <device/pnp_def.h> #include "it8772f.h" diff --git a/src/superio/nsc/pc8374/early_init.c b/src/superio/nsc/pc8374/early_init.c index f5e4e80..d3f601d 100644 --- a/src/superio/nsc/pc8374/early_init.c +++ b/src/superio/nsc/pc8374/early_init.c @@ -19,7 +19,7 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#include <arch/romcc_io.h> +#include <arch/io.h> #include "pc8374.h" static void pc8374_enable(u16 iobase, u8 *init) diff --git a/src/superio/nsc/pc87309/early_serial.c b/src/superio/nsc/pc87309/early_serial.c index f6be3ed..131f0aa 100644 --- a/src/superio/nsc/pc87309/early_serial.c +++ b/src/superio/nsc/pc87309/early_serial.c @@ -18,7 +18,7 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#include <arch/romcc_io.h> +#include <arch/io.h> #include "pc87309.h" static void pc87309_enable_serial(device_t dev, u16 iobase) diff --git a/src/superio/nsc/pc87351/early_serial.c b/src/superio/nsc/pc87351/early_serial.c index 6f97a76..c34538f 100644 --- a/src/superio/nsc/pc87351/early_serial.c +++ b/src/superio/nsc/pc87351/early_serial.c @@ -19,7 +19,7 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#include <arch/romcc_io.h> +#include <arch/io.h> #include "pc87351.h" static void pc87351_enable_serial(device_t dev, u16 iobase) diff --git a/src/superio/nsc/pc87360/early_serial.c b/src/superio/nsc/pc87360/early_serial.c index 657cd68..da4abdb 100644 --- a/src/superio/nsc/pc87360/early_serial.c +++ b/src/superio/nsc/pc87360/early_serial.c @@ -19,7 +19,7 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#include <arch/romcc_io.h> +#include <arch/io.h> #include "pc87360.h" static void pc87360_enable_serial(device_t dev, u16 iobase) diff --git a/src/superio/nsc/pc87366/early_serial.c b/src/superio/nsc/pc87366/early_serial.c index e0bc2c5..e173afd 100644 --- a/src/superio/nsc/pc87366/early_serial.c +++ b/src/superio/nsc/pc87366/early_serial.c @@ -19,7 +19,7 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#include <arch/romcc_io.h> +#include <arch/io.h> #include "pc87366.h" static void pc87366_enable_serial(device_t dev, u16 iobase) diff --git a/src/superio/nsc/pc87392/early_serial.c b/src/superio/nsc/pc87392/early_serial.c index a485ddb..6e85fb9 100644 --- a/src/superio/nsc/pc87392/early_serial.c +++ b/src/superio/nsc/pc87392/early_serial.c @@ -18,7 +18,7 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#include <arch/romcc_io.h> +#include <arch/io.h> #include "pc87392.h" static void pc87392_enable_serial(device_t dev, u16 iobase) diff --git a/src/superio/nsc/pc87417/early_init.c b/src/superio/nsc/pc87417/early_init.c index 59f1ab6..d1870f9 100644 --- a/src/superio/nsc/pc87417/early_init.c +++ b/src/superio/nsc/pc87417/early_init.c @@ -20,7 +20,7 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#include <arch/romcc_io.h> +#include <arch/io.h> #include "pc87417.h" static void pc87417_disable_dev(device_t dev) diff --git a/src/superio/nsc/pc87417/early_serial.c b/src/superio/nsc/pc87417/early_serial.c index 0e87fc5..33bae7e 100644 --- a/src/superio/nsc/pc87417/early_serial.c +++ b/src/superio/nsc/pc87417/early_serial.c @@ -20,7 +20,7 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#include <arch/romcc_io.h> +#include <arch/io.h> #include "pc87417.h" void pc87417_enable_serial(device_t dev, u16 iobase) diff --git a/src/superio/nsc/pc87427/early_init.c b/src/superio/nsc/pc87427/early_init.c index 512e440..6df1b9f 100644 --- a/src/superio/nsc/pc87427/early_init.c +++ b/src/superio/nsc/pc87427/early_init.c @@ -19,7 +19,7 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#include <arch/romcc_io.h> +#include <arch/io.h> #include "pc87427.h" static void pc87427_disable_dev(device_t dev) diff --git a/src/superio/nsc/pc97317/early_serial.c b/src/superio/nsc/pc97317/early_serial.c index 593c22e..0c21561 100644 --- a/src/superio/nsc/pc97317/early_serial.c +++ b/src/superio/nsc/pc97317/early_serial.c @@ -18,7 +18,7 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#include <arch/romcc_io.h> +#include <arch/io.h> #include "pc97317.h" #define PM_DEV PNP_DEV(0x2e, PC97317_PM) diff --git a/src/superio/nuvoton/wpcm450/early_init.c b/src/superio/nuvoton/wpcm450/early_init.c index a90f266..d95eaae 100644 --- a/src/superio/nuvoton/wpcm450/early_init.c +++ b/src/superio/nuvoton/wpcm450/early_init.c @@ -19,7 +19,6 @@ */ #include <arch/io.h> -#include <arch/romcc_io.h> #include <device/pnp_def.h> #include "wpcm450.h" diff --git a/src/superio/serverengines/pilot/early_serial.c b/src/superio/serverengines/pilot/early_serial.c index f339d8e..4112901 100644 --- a/src/superio/serverengines/pilot/early_serial.c +++ b/src/superio/serverengines/pilot/early_serial.c @@ -21,7 +21,7 @@ /* PILOT Super I/O is only based on LPC observation done on factory system. */ -#include <arch/romcc_io.h> +#include <arch/io.h> #include "pilot.h" /* Pilot uses 0x5A/0xA5 pattern to actiavte deactivate config access. */ diff --git a/src/superio/smsc/fdc37m60x/early_serial.c b/src/superio/smsc/fdc37m60x/early_serial.c index a3539b15..38cb0f8 100644 --- a/src/superio/smsc/fdc37m60x/early_serial.c +++ b/src/superio/smsc/fdc37m60x/early_serial.c @@ -18,7 +18,7 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#include <arch/romcc_io.h> +#include <arch/io.h> #include "fdc37m60x.h" /* The base address is 0x3f0 or 0x370, depending on the SYSOPT pin. */ diff --git a/src/superio/smsc/kbc1100/kbc1100_early_init.c b/src/superio/smsc/kbc1100/kbc1100_early_init.c index e12db31..5d74c32 100644 --- a/src/superio/smsc/kbc1100/kbc1100_early_init.c +++ b/src/superio/smsc/kbc1100/kbc1100_early_init.c @@ -19,7 +19,7 @@ /* Pre-RAM driver for the SMSC KBC1100 Super I/O chip */ -#include <arch/romcc_io.h> +#include <arch/io.h> #include "kbc1100.h" static inline void pnp_enter_conf_state(device_t dev) diff --git a/src/superio/smsc/lpc47b272/early_serial.c b/src/superio/smsc/lpc47b272/early_serial.c index 54e854c..b2f0d1b 100644 --- a/src/superio/smsc/lpc47b272/early_serial.c +++ b/src/superio/smsc/lpc47b272/early_serial.c @@ -20,7 +20,7 @@ /* Pre-RAM driver for SMSC LPC47B272 Super I/O chip. */ -#include <arch/romcc_io.h> +#include <arch/io.h> #include "lpc47b272.h" static void pnp_enter_conf_state(device_t dev) diff --git a/src/superio/smsc/lpc47b397/early_serial.c b/src/superio/smsc/lpc47b397/early_serial.c index 930e41a..31d515b 100644 --- a/src/superio/smsc/lpc47b397/early_serial.c +++ b/src/superio/smsc/lpc47b397/early_serial.c @@ -20,7 +20,7 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#include <arch/romcc_io.h> +#include <arch/io.h> #include "lpc47b397.h" static void pnp_enter_conf_state(device_t dev) diff --git a/src/superio/smsc/lpc47m10x/early_serial.c b/src/superio/smsc/lpc47m10x/early_serial.c index 99aebbc..fc6efb9 100644 --- a/src/superio/smsc/lpc47m10x/early_serial.c +++ b/src/superio/smsc/lpc47m10x/early_serial.c @@ -18,7 +18,7 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#include <arch/romcc_io.h> +#include <arch/io.h> #include "lpc47m10x.h" static void pnp_enter_conf_state(device_t dev) diff --git a/src/superio/smsc/lpc47m15x/early_serial.c b/src/superio/smsc/lpc47m15x/early_serial.c index bd57a28..7d75bae 100644 --- a/src/superio/smsc/lpc47m15x/early_serial.c +++ b/src/superio/smsc/lpc47m15x/early_serial.c @@ -19,7 +19,7 @@ /* Pre-RAM driver for the SMSC LPC47M15X Super I/O chip */ -#include <arch/romcc_io.h> +#include <arch/io.h> #include "lpc47m15x.h" static void pnp_enter_conf_state(device_t dev) diff --git a/src/superio/smsc/lpc47n217/early_serial.c b/src/superio/smsc/lpc47n217/early_serial.c index 6c02769..451628a 100644 --- a/src/superio/smsc/lpc47n217/early_serial.c +++ b/src/superio/smsc/lpc47n217/early_serial.c @@ -20,7 +20,7 @@ /* Pre-RAM driver for SMSC LPC47N217 Super I/O chip. */ -#include <arch/romcc_io.h> +#include <arch/io.h> #include <assert.h> #include "lpc47n217.h" diff --git a/src/superio/smsc/lpc47n227/early_serial.c b/src/superio/smsc/lpc47n227/early_serial.c index b20bc80..4aea7c5 100644 --- a/src/superio/smsc/lpc47n227/early_serial.c +++ b/src/superio/smsc/lpc47n227/early_serial.c @@ -20,7 +20,7 @@ /* Pre-RAM driver for SMSC LPC47N227 Super I/O chip. */ -#include <arch/romcc_io.h> +#include <arch/io.h> #include "lpc47n227.h" static void pnp_enter_conf_state(device_t dev) diff --git a/src/superio/smsc/sch4037/sch4037_early_init.c b/src/superio/smsc/sch4037/sch4037_early_init.c index fc9aaf5..dfacd24 100644 --- a/src/superio/smsc/sch4037/sch4037_early_init.c +++ b/src/superio/smsc/sch4037/sch4037_early_init.c @@ -18,7 +18,7 @@ */ -#include <arch/romcc_io.h> +#include <arch/io.h> #include "sch4037.h" static inline void pnp_enter_conf_state(device_t dev) diff --git a/src/superio/smsc/sio1036/sio1036_early_init.c b/src/superio/smsc/sio1036/sio1036_early_init.c index 289d83f..314ea75 100644 --- a/src/superio/smsc/sio1036/sio1036_early_init.c +++ b/src/superio/smsc/sio1036/sio1036_early_init.c @@ -19,7 +19,7 @@ /* Pre-RAM driver for the SMSC KBC1100 Super I/O chip */ -#include <arch/romcc_io.h> +#include <arch/io.h> #include "sio1036.h" #ifndef CONFIG_TTYS0_BASE diff --git a/src/superio/smsc/smscsuperio/early_serial.c b/src/superio/smsc/smscsuperio/early_serial.c index 85f7b46..5e9aadb 100644 --- a/src/superio/smsc/smscsuperio/early_serial.c +++ b/src/superio/smsc/smscsuperio/early_serial.c @@ -18,7 +18,7 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#include <arch/romcc_io.h> +#include <arch/io.h> #include <device/pnp_def.h> /* All known/supported SMSC Super I/Os have the same logical device IDs diff --git a/src/superio/winbond/w83627dhg/early_serial.c b/src/superio/winbond/w83627dhg/early_serial.c index 8ea29ea..ec9e81e 100644 --- a/src/superio/winbond/w83627dhg/early_serial.c +++ b/src/superio/winbond/w83627dhg/early_serial.c @@ -20,7 +20,6 @@ */ #include <arch/io.h> -#include <arch/romcc_io.h> #include <device/pnp_def.h> #include <stdint.h> #include "w83627dhg.h" diff --git a/src/superio/winbond/w83627ehg/early_init.c b/src/superio/winbond/w83627ehg/early_init.c index 24cc451..7be5e37 100644 --- a/src/superio/winbond/w83627ehg/early_init.c +++ b/src/superio/winbond/w83627ehg/early_init.c @@ -20,7 +20,7 @@ */ #include <stdint.h> -#include <arch/romcc_io.h> +#include <arch/io.h> #include "w83627ehg.h" void w83627ehg_disable_dev(device_t dev) diff --git a/src/superio/winbond/w83627ehg/early_serial.c b/src/superio/winbond/w83627ehg/early_serial.c index 03e72f3..1a895c6 100644 --- a/src/superio/winbond/w83627ehg/early_serial.c +++ b/src/superio/winbond/w83627ehg/early_serial.c @@ -19,7 +19,7 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#include <arch/romcc_io.h> +#include <arch/io.h> #include "w83627ehg.h" static void pnp_enter_ext_func_mode(device_t dev) diff --git a/src/superio/winbond/w83627hf/early_init.c b/src/superio/winbond/w83627hf/early_init.c index b61922d..66b4098 100644 --- a/src/superio/winbond/w83627hf/early_init.c +++ b/src/superio/winbond/w83627hf/early_init.c @@ -20,7 +20,7 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#include <arch/romcc_io.h> +#include <arch/io.h> #include "w83627hf.h" void w83627hf_disable_dev(device_t dev) diff --git a/src/superio/winbond/w83627hf/early_serial.c b/src/superio/winbond/w83627hf/early_serial.c index 0e857cf..db2827b 100644 --- a/src/superio/winbond/w83627hf/early_serial.c +++ b/src/superio/winbond/w83627hf/early_serial.c @@ -21,7 +21,7 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#include <arch/romcc_io.h> +#include <arch/io.h> #include "w83627hf.h" static void pnp_enter_ext_func_mode(device_t dev) diff --git a/src/superio/winbond/w83627thg/early_serial.c b/src/superio/winbond/w83627thg/early_serial.c index 6803aab..8ba1a30 100644 --- a/src/superio/winbond/w83627thg/early_serial.c +++ b/src/superio/winbond/w83627thg/early_serial.c @@ -20,7 +20,7 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#include <arch/romcc_io.h> +#include <arch/io.h> #include "w83627thg.h" static void pnp_enter_ext_func_mode(device_t dev) diff --git a/src/superio/winbond/w83627uhg/early_serial.c b/src/superio/winbond/w83627uhg/early_serial.c index 43946bd..bfd08a3 100644 --- a/src/superio/winbond/w83627uhg/early_serial.c +++ b/src/superio/winbond/w83627uhg/early_serial.c @@ -18,8 +18,7 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#include <arch/romcc_io.h> -#include <stdint.h> +#include <arch/io.h> #include "w83627uhg.h" static void pnp_enter_ext_func_mode(device_t dev) diff --git a/src/superio/winbond/w83697hf/early_serial.c b/src/superio/winbond/w83697hf/early_serial.c index e26168e..e435645 100644 --- a/src/superio/winbond/w83697hf/early_serial.c +++ b/src/superio/winbond/w83697hf/early_serial.c @@ -18,8 +18,7 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#include <stdint.h> -#include <arch/romcc_io.h> +#include <arch/io.h> #include "w83697hf.h" static void pnp_enter_ext_func_mode(device_t dev) diff --git a/src/superio/winbond/w83977f/early_serial.c b/src/superio/winbond/w83977f/early_serial.c index 400cb86..c572dcb 100644 --- a/src/superio/winbond/w83977f/early_serial.c +++ b/src/superio/winbond/w83977f/early_serial.c @@ -18,7 +18,7 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#include <arch/romcc_io.h> +#include <arch/io.h> #include "w83977f.h" static void pnp_enter_ext_func_mode(device_t dev) diff --git a/src/superio/winbond/w83977tf/early_serial.c b/src/superio/winbond/w83977tf/early_serial.c index 208bc68..c016515 100644 --- a/src/superio/winbond/w83977tf/early_serial.c +++ b/src/superio/winbond/w83977tf/early_serial.c @@ -20,7 +20,7 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#include <arch/romcc_io.h> +#include <arch/io.h> #include "w83977tf.h" static void pnp_enter_ext_func_mode(device_t dev)

1 0

Patch set updated for coreboot: 12bfc95 Add support for ASUS F2A85-M board
by Rudolf Marek March 21, 2013

March 21, 2013

Rudolf Marek (r.marek(a)assembler.cz) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2038 -gerrit commit 12bfc9593dbd5a1d4123d833a9a5146f982f3d74 Author: Rudolf Marek <r.marek(a)assembler.cz> Date: Wed Mar 20 21:43:50 2013 +0100 Add support for ASUS F2A85-M board The patch is based on Thatcher board. So far it boots Linux (3.2/3.7), internal network adapter works, AHCI works. External PCI/PCIe slots works too. Power management/ACPI seems to work. Internal VGA works with dumped ROM (VGA/DVI), but lacks GART. PCI pref devices are being relocated by Linux, reason unknown. This is a good start. USB and XHCI untested but visible. Change-Id: I1869aecb2634d548b00b3c9139517d6a0e0c9817 Signed-off-by: Rudolf Marek <r.marek(a)assembler.cz> --- 3rdparty | 2 +- src/mainboard/asus/Kconfig | 3 + src/mainboard/asus/f2a85-m/BiosCallOuts.c | 126 ++ src/mainboard/asus/f2a85-m/BiosCallOuts.h | 31 + src/mainboard/asus/f2a85-m/Kconfig | 133 ++ src/mainboard/asus/f2a85-m/Makefile.inc | 28 + src/mainboard/asus/f2a85-m/OptionsIds.h | 67 + src/mainboard/asus/f2a85-m/PlatformGnbPcie.c | 206 +++ .../asus/f2a85-m/PlatformGnbPcieComplex.h | 72 + src/mainboard/asus/f2a85-m/acpi/AmdImc.asl | 97 ++ src/mainboard/asus/f2a85-m/acpi/cpstate.asl | 115 ++ src/mainboard/asus/f2a85-m/acpi/ide.asl | 244 ++++ src/mainboard/asus/f2a85-m/acpi/routing.asl | 207 +++ src/mainboard/asus/f2a85-m/acpi/sata.asl | 148 ++ src/mainboard/asus/f2a85-m/acpi/usb.asl | 114 ++ src/mainboard/asus/f2a85-m/acpi_tables.c | 329 +++++ src/mainboard/asus/f2a85-m/agesawrapper.c | 775 +++++++++++ src/mainboard/asus/f2a85-m/agesawrapper.h | 97 ++ src/mainboard/asus/f2a85-m/buildOpts.c | 517 +++++++ src/mainboard/asus/f2a85-m/cmos.layout | 114 ++ src/mainboard/asus/f2a85-m/devicetree.cb | 130 ++ src/mainboard/asus/f2a85-m/dsdt.asl | 1411 ++++++++++++++++++++ src/mainboard/asus/f2a85-m/get_bus_conf.c | 139 ++ src/mainboard/asus/f2a85-m/irq_tables.c | 112 ++ src/mainboard/asus/f2a85-m/mainboard.c | 68 + src/mainboard/asus/f2a85-m/mptable.c | 195 +++ src/mainboard/asus/f2a85-m/pmio.h | 33 + src/mainboard/asus/f2a85-m/romstage.c | 206 +++ 28 files changed, 5718 insertions(+), 1 deletion(-) diff --git a/3rdparty b/3rdparty index ba8caa3..f933fda 160000 --- a/3rdparty +++ b/3rdparty @@ -1 +1 @@ -Subproject commit ba8caa30bd5ed6d89dbfd40e17c75c94d43804c6 +Subproject commit f933fda7906abc981ebe2972b60865028bbe15e3 diff --git a/src/mainboard/asus/Kconfig b/src/mainboard/asus/Kconfig index 6e6b420..66057df 100644 --- a/src/mainboard/asus/Kconfig +++ b/src/mainboard/asus/Kconfig @@ -27,6 +27,8 @@ config BOARD_ASUS_A8V_E_SE bool "A8V-E SE" config BOARD_ASUS_A8V_E_DELUXE bool "A8V-E Deluxe" +config BOARD_ASUS_F2A85_M + bool "F2A85-M" config BOARD_ASUS_K8V_X bool "K8V-X" config BOARD_ASUS_M2N_E @@ -66,6 +68,7 @@ endchoice source "src/mainboard/asus/a8n_e/Kconfig" source "src/mainboard/asus/a8v-e_se/Kconfig" source "src/mainboard/asus/a8v-e_deluxe/Kconfig" +source "src/mainboard/asus/f2a85-m/Kconfig" source "src/mainboard/asus/k8v-x/Kconfig" source "src/mainboard/asus/m2n-e/Kconfig" source "src/mainboard/asus/m2v/Kconfig" diff --git a/src/mainboard/asus/f2a85-m/BiosCallOuts.c b/src/mainboard/asus/f2a85-m/BiosCallOuts.c new file mode 100644 index 0000000..f976001 --- /dev/null +++ b/src/mainboard/asus/f2a85-m/BiosCallOuts.c @@ -0,0 +1,126 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include "agesawrapper.h" +#include "amdlib.h" +#include "BiosCallOuts.h" +#include "Ids.h" +#include "OptionsIds.h" +#include "heapManager.h" +#include "FchPlatform.h" +#include "cbfs.h" + +STATIC CONST BIOS_CALLOUT_STRUCT BiosCallouts[] = +{ + {AGESA_ALLOCATE_BUFFER, fam15tn_AllocateBuffer }, + {AGESA_DEALLOCATE_BUFFER, fam15tn_DeallocateBuffer }, + {AGESA_DO_RESET, fam15tn_Reset }, + {AGESA_LOCATE_BUFFER, fam15tn_LocateBuffer }, + {AGESA_READ_SPD, fam15tn_ReadSpd }, + {AGESA_READ_SPD_RECOVERY, fam15tn_DefaultRet }, + {AGESA_RUNFUNC_ONAP, fam15tn_RunFuncOnAp }, + {AGESA_GET_IDS_INIT_DATA, fam15tn_GetIdsInitData }, + {AGESA_HOOKBEFORE_DQS_TRAINING, fam15tn_HookBeforeDQSTraining }, + {AGESA_HOOKBEFORE_EXIT_SELF_REF, fam15tn_HookBeforeExitSelfRefresh }, + {AGESA_FCH_OEM_CALLOUT, Fch_Oem_config }, + {AGESA_GNB_GFX_GET_VBIOS_IMAGE, fam15tn_HookGfxGetVbiosImage } +}; + +AGESA_STATUS GetBiosCallout (UINT32 Func, UINT32 Data, VOID *ConfigPtr) +{ + UINTN i; + AGESA_STATUS CalloutStatus; + UINTN CallOutCount = sizeof (BiosCallouts) / sizeof (BiosCallouts [0]); + + for (i = 0; i < CallOutCount; i++) + { + if (BiosCallouts[i].CalloutName == Func) + break; + } + + if(i >= CallOutCount) + return AGESA_UNSUPPORTED; + + CalloutStatus = BiosCallouts[i].CalloutPtr (Func, Data, ConfigPtr); + + return CalloutStatus; +} + +/** + * AMD Thatcher Platform ALC272 Verb Table + */ +const CODEC_ENTRY Thatcher_Alc272_VerbTbl[] = { + {0x11, 0x411111F0}, + {0x12, 0x411111F0}, + {0x13, 0x411111F0}, + {0x14, 0x411111F0}, + {0x15, 0x411111F0}, + {0x16, 0x411111F0}, + {0x17, 0x411111F0}, + {0x18, 0x01a19840}, + {0x19, 0x411111F0}, + {0x1a, 0x01813030}, + {0x1b, 0x411111F0}, + {0x1d, 0x40130605}, + {0x1e, 0x01441120}, + {0x21, 0x01211010}, + {0xff, 0xffffffff} +}; + +const CODEC_TBL_LIST ThatcherCodecTableList[] = +{ + {0x10ec0272, (CODEC_ENTRY*)&Thatcher_Alc272_VerbTbl[0]}, + {(UINT32)0x0FFFFFFFF, (CODEC_ENTRY*)0x0FFFFFFFFUL} +}; + +/** + * Fch Oem setting callback + * + * Configure platform specific Hudson device, + * such Azalia, SATA, GEC, IMC etc. + */ +AGESA_STATUS Fch_Oem_config(UINT32 Func, UINT32 FchData, VOID *ConfigPtr) +{ + FCH_RESET_DATA_BLOCK *FchParams = (FCH_RESET_DATA_BLOCK *)FchData; + + if (FchParams->StdHeader->Func == AMD_INIT_RESET) { +#if CONFIG_HUDSON_LEGACY_FREE + FCH_RESET_DATA_BLOCK *FchParams_reset = (FCH_RESET_DATA_BLOCK *) FchData; + FchParams_reset->LegacyFree = 1; +#endif + printk(BIOS_DEBUG, "Fch OEM config in INIT RESET "); + } else if (FchParams->StdHeader->Func == AMD_INIT_ENV) { + FCH_DATA_BLOCK *FchParams_env = (FCH_DATA_BLOCK *)FchData; + printk(BIOS_DEBUG, "Fch OEM config in INIT ENV "); + + /* Azalia Controller OEM Codec Table Pointer */ + FchParams_env->Azalia.AzaliaOemCodecTablePtr = (CODEC_TBL_LIST *)(&ThatcherCodecTableList[0]); + /* Azalia Controller Front Panel OEM Table Pointer */ + FchParams_env->Imc.ImcEnable = FALSE; + FchParams_env->Hwm.HwMonitorEnable = FALSE; + FchParams_env->Hwm.HwmFchtsiAutoPoll = FALSE;/* 1 enable, 0 disable TSI Auto Polling */ + + /* XHCI configuration */ + FchParams_env->Usb.Xhci0Enable = TRUE; + FchParams_env->Usb.Xhci1Enable = TRUE; + } + printk(BIOS_DEBUG, "Done\n"); + + return AGESA_SUCCESS; +} diff --git a/src/mainboard/asus/f2a85-m/BiosCallOuts.h b/src/mainboard/asus/f2a85-m/BiosCallOuts.h new file mode 100644 index 0000000..9132fac --- /dev/null +++ b/src/mainboard/asus/f2a85-m/BiosCallOuts.h @@ -0,0 +1,31 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef _BIOS_CALLOUT_H_ +#define _BIOS_CALLOUT_H_ + +#include <northbridge/amd/agesa/family15tn/fam15tn_callouts.h> + +/* CALLOUT Initialization */ +AGESA_STATUS GetBiosCallout (UINT32 Func, UINT32 Data, VOID *ConfigPtr); + +/* FCH OEM Config*/ +AGESA_STATUS Fch_Oem_config(UINT32 Func, UINT32 FchData, VOID *ConfigPtr); + +#endif //_BIOS_CALLOUT_H_ diff --git a/src/mainboard/asus/f2a85-m/Kconfig b/src/mainboard/asus/f2a85-m/Kconfig new file mode 100644 index 0000000..e8f573e --- /dev/null +++ b/src/mainboard/asus/f2a85-m/Kconfig @@ -0,0 +1,133 @@ +# +# This file is part of the coreboot project. +# +# Copyright (C) 2012 Advanced Micro Devices, Inc. +# Copyright (C) 2012 Rudolf Marek <r.marek(a)assembler.cz> +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +# + +if BOARD_ASUS_F2A85_M + +config BOARD_SPECIFIC_OPTIONS # dummy + def_bool y + select ARCH_X86 + select CPU_AMD_AGESA_FAMILY15_TN + select NORTHBRIDGE_AMD_AGESA_FAMILY15_TN_ROOT_COMPLEX + select NORTHBRIDGE_AMD_AGESA_FAMILY15_TN + select SOUTHBRIDGE_AMD_AGESA_HUDSON + select HAVE_OPTION_TABLE + select HAVE_PIRQ_TABLE + select HAVE_MP_TABLE + select HAVE_ACPI_RESUME + select HAVE_HARD_RESET + select SB_HT_CHAIN_UNITID_OFFSET_ONLY + select LIFT_BSP_APIC_ID + select SERIAL_CPU_INIT + select AMDMCT + select HAVE_ACPI_TABLES + select SUPERIO_ITE_IT8712F + select BOARD_ROMSIZE_KB_8192 + select GFXUMA + select UDELAY_LAPIC + +choice + prompt "DDR3 memory voltage" + default BOARD_ASUS_F2A85_M_DDR3_VOLT_150 + +config BOARD_ASUS_F2A85_M_DDR3_VOLT_135 + bool "1.35V" + help + Set DRR3 memory voltage to 1.35V +config BOARD_ASUS_F2A85_M_DDR3_VOLT_150 + bool "1.50V" + help + Set DRR3 memory voltage to 1.50V +config BOARD_ASUS_F2A85_M_DDR3_VOLT_165 + bool "1.65V" + help + Set DRR3 memory voltage to 1.65V +endchoice + +config BOARD_ASUS_F2A85_M_DDR3_VOLT_VAL + hex + default 0x9e if BOARD_ASUS_F2A85_M_DDR3_VOLT_135 + default 0x0 if BOARD_ASUS_F2A85_M_DDR3_VOLT_150 + default 0x1e if BOARD_ASUS_F2A85_M_DDR3_VOLT_165 + +config MAINBOARD_DIR + string + default asus/f2a85-m + +config APIC_ID_OFFSET + hex + default 0x0 + +config MAINBOARD_PART_NUMBER + string + default "F2A85-M" + +config HW_MEM_HOLE_SIZEK + hex + default 0x200000 + +config MAX_CPUS + int + default 4 + +config MAX_PHYSICAL_CPUS + int + default 1 + +config HW_MEM_HOLE_SIZE_AUTO_INC + bool + default n + +config MEM_TRAIN_SEQ + int + default 2 + +config IRQ_SLOT_COUNT + int + default 11 + +config RAMTOP + hex + default 0x1000000 + +config HEAP_SIZE + hex + default 0xc0000 + +config STACK_SIZE + hex + default 0x10000 + +config RAMBASE + hex + default 0x200000 + +config ONBOARD_VGA_IS_PRIMARY + bool + default y + +config VGA_BIOS_ID + string + default "1002,9993" + +config HUDSON_LEGACY_FREE + bool + default y + +endif # BOARD_ASUS_F2A85_M diff --git a/src/mainboard/asus/f2a85-m/Makefile.inc b/src/mainboard/asus/f2a85-m/Makefile.inc new file mode 100644 index 0000000..3103f70 --- /dev/null +++ b/src/mainboard/asus/f2a85-m/Makefile.inc @@ -0,0 +1,28 @@ +# +# This file is part of the coreboot project. +# +# Copyright (C) 2012 Advanced Micro Devices, Inc. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +# + +romstage-y += buildOpts.c +romstage-y += agesawrapper.c +romstage-y += BiosCallOuts.c +romstage-y += PlatformGnbPcie.c + +ramstage-y += buildOpts.c +ramstage-y += agesawrapper.c +ramstage-y += BiosCallOuts.c +ramstage-y += PlatformGnbPcie.c diff --git a/src/mainboard/asus/f2a85-m/OptionsIds.h b/src/mainboard/asus/f2a85-m/OptionsIds.h new file mode 100644 index 0000000..bf7eedc --- /dev/null +++ b/src/mainboard/asus/f2a85-m/OptionsIds.h @@ -0,0 +1,67 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/** + * @file + * + * IDS Option File + * + * This file is used to switch on/off IDS features. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: Core + * @e \$Revision: 12067 $ @e \$Date: 2009-04-11 04:34:13 +0800 (Sat, 11 Apr 2009) $ + */ +#ifndef _OPTION_IDS_H_ +#define _OPTION_IDS_H_ + +/** + * + * This file generates the defaults tables for the Integrated Debug Support + * Module. The documented build options are imported from a user controlled + * file for processing. The build options for the Integrated Debug Support + * Module are listed below: + * + * IDSOPT_IDS_ENABLED + * IDSOPT_ERROR_TRAP_ENABLED + * IDSOPT_CONTROL_ENABLED + * IDSOPT_TRACING_ENABLED + * IDSOPT_PERF_ANALYSIS + * IDSOPT_ASSERT_ENABLED + * IDS_DEBUG_PORT + * IDSOPT_CAR_CORRUPTION_CHECK_ENABLED + * + **/ + +//#define IDSOPT_IDS_ENABLED TRUE +//#define IDSOPT_CONTROL_ENABLED TRUE +#define IDSOPT_TRACING_ENABLED TRUE +#define IDSOPT_TRACING_CONSOLE_SERIALPORT TRUE +//#define IDSOPT_PERF_ANALYSIS TRUE +#define IDSOPT_ASSERT_ENABLED TRUE +//#undef IDSOPT_DEBUG_ENABLED +//#define IDSOPT_DEBUG_ENABLED FALSE +//#undef IDSOPT_HOST_SIMNOW +//#define IDSOPT_HOST_SIMNOW FALSE +//#undef IDSOPT_HOST_HDT +//#define IDSOPT_HOST_HDT FALSE +//#define IDS_DEBUG_PORT 0x80 + +#endif diff --git a/src/mainboard/asus/f2a85-m/PlatformGnbPcie.c b/src/mainboard/asus/f2a85-m/PlatformGnbPcie.c new file mode 100644 index 0000000..8ee6707 --- /dev/null +++ b/src/mainboard/asus/f2a85-m/PlatformGnbPcie.c @@ -0,0 +1,206 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include "AGESA.h" +#include "amdlib.h" +#include "Ids.h" +#include "heapManager.h" +#include "PlatformGnbPcieComplex.h" +#include "Filecode.h" + +#define FILECODE PROC_GNB_PCIE_FAMILY_0X15_F15PCIECOMPLEXCONFIG_FILECODE + +PCIe_PORT_DESCRIPTOR PortList [] = { + /* PCIe port, Lanes 8:23, PCI Device Number 2 */ + { + 0, /* Descriptor flags */ + PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 8, 23), + PCIE_PORT_DATA_INITIALIZER (PortEnabled, ChannelTypeExt6db, 2, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 1) + }, + /* PCIe port, Lanes 16:23, PCI Device Number 3 */ + { + 0, /* Descriptor flags */ + PCIE_ENGINE_DATA_INITIALIZER (PcieUnusedEngine, 16, 23), + PCIE_PORT_DATA_INITIALIZER (PortDisabled, ChannelTypeExt6db, 3, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 1) + }, + + /* PCIe port, Lanes 4, PCI Device Number 4, PCIE MINI0 */ + { + 0, /* Descriptor flags */ + PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 4, 4), + PCIE_PORT_DATA_INITIALIZER (PortEnabled, ChannelTypeExt6db, 4, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 1) + }, + + /* PCIe port, Lanes 5, PCI Device Number 5, PCIE MINI1 */ + { + 0, /* Descriptor flags */ + PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 5, 5), + PCIE_PORT_DATA_INITIALIZER (PortEnabled, ChannelTypeExt6db, 5, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 1) + }, + + /* PCIe port, Lanes 6, PCI Device Number 6, PCIE SLOT1, TODO: Disabled. */ + { + 0, /* Descriptor flags */ + PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 6, 6), + PCIE_PORT_DATA_INITIALIZER (PortEnabled, ChannelTypeExt6db, 6, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 1) + }, + + /* PCIe port, Lanes 7, PCI Device Number 7, LAN , TODO: not the last entry.*/ + { + 0, /* Descriptor flags !!!IMPORTANT!!! Terminate last element of array */ + PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 7, 7), + PCIE_PORT_DATA_INITIALIZER (PortEnabled, ChannelTypeExt6db, 7, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 1) + }, + +#if 1 + /* Initialize Port descriptor (PCIe port, Lanes ?, PCI Device Number 8, ...) */ + { + DESCRIPTOR_TERMINATE_LIST, /* Descriptor flags !!!IMPORTANT!!! Terminate last element of array */ + PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 0, 3), + PCIE_PORT_DATA_INITIALIZER (PortEnabled, ChannelTypeExt6db, 8, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 0) + }, +#endif +}; + +PCIe_DDI_DESCRIPTOR DdiList [] = { + // DP0 to HDMI0/DP + { + 0, + PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 24, 27), + PCIE_DDI_DATA_INITIALIZER (ConnectorTypeHDMI, Aux1, Hdp1) + }, + // DP1 to FCH + { + 0, + PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 28, 31), + PCIE_DDI_DATA_INITIALIZER (ConnectorTypeNutmegDpToVga, Aux2, Hdp2) + }, + // DP2 to HDMI1/DP + { + 0, +// PCIE_ENGINE_DATA_INITIALIZER (PcieUnusedEngine, 32, 38), + PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 32, 35), + //PCIE_DDI_DATA_INITIALIZER (ConnectorTypeEDP, Aux3, Hdp3) + PCIE_DDI_DATA_INITIALIZER (ConnectorTypeHDMI, Aux3, Hdp3) + }, + // GFX Lane 15-12 + { + 0, + PCIE_ENGINE_DATA_INITIALIZER (PcieUnusedEngine, 12, 15), + PCIE_DDI_DATA_INITIALIZER (ConnectorTypeHDMI, Aux4, Hdp4) + }, + // GFX Lane 11-8 + { + 0, + PCIE_ENGINE_DATA_INITIALIZER (PcieUnusedEngine, 16, 19), + PCIE_DDI_DATA_INITIALIZER (ConnectorTypeHDMI, Aux5, Hdp5) + }, + // GFX Lane 7-4 + { + DESCRIPTOR_TERMINATE_LIST, + PCIE_ENGINE_DATA_INITIALIZER (PcieUnusedEngine, 20, 23), + PCIE_DDI_DATA_INITIALIZER (ConnectorTypeHDMI, Aux6, Hdp6) + } +}; + +PCIe_COMPLEX_DESCRIPTOR Trinity = { + DESCRIPTOR_TERMINATE_LIST, + 0, + &PortList[0], + &DdiList[0] +}; + +/*---------------------------------------------------------------------------------------*/ +/** + * OemCustomizeInitEarly + * + * Description: + * This stub function will call the host environment through the binary block + * interface (call-out port) to provide a user hook opportunity + * + * Parameters: + * @param[in] **PeiServices + * @param[in] *InitEarly + * + * @retval VOID + * + **/ +/*---------------------------------------------------------------------------------------*/ +VOID +OemCustomizeInitEarly ( + IN OUT AMD_EARLY_PARAMS *InitEarly + ) +{ + AGESA_STATUS Status; + VOID *TrinityPcieComplexListPtr; + VOID *TrinityPciePortPtr; + VOID *TrinityPcieDdiPtr; + + ALLOCATE_HEAP_PARAMS AllocHeapParams; + + // GNB PCIe topology Porting + + // + // Allocate buffer for PCIe_COMPLEX_DESCRIPTOR , PCIe_PORT_DESCRIPTOR and PCIe_DDI_DESCRIPTOR + // + AllocHeapParams.RequestedBufferSize = (sizeof (PCIe_COMPLEX_DESCRIPTOR) + + sizeof (PCIe_PORT_DESCRIPTOR) * 7 + + sizeof (PCIe_DDI_DESCRIPTOR)) * 6; + + AllocHeapParams.BufferHandle = AMD_MEM_MISC_HANDLES_START; + AllocHeapParams.Persist = HEAP_LOCAL_CACHE; + Status = HeapAllocateBuffer (&AllocHeapParams, &InitEarly->StdHeader); + if ( Status!= AGESA_SUCCESS) { + // Could not allocate buffer for PCIe_COMPLEX_DESCRIPTOR , PCIe_PORT_DESCRIPTOR and PCIe_DDI_DESCRIPTOR + ASSERT(FALSE); + return; + } + + TrinityPcieComplexListPtr = (PCIe_COMPLEX_DESCRIPTOR *) AllocHeapParams.BufferPtr; + + AllocHeapParams.BufferPtr += sizeof (PCIe_COMPLEX_DESCRIPTOR); + TrinityPciePortPtr = (PCIe_PORT_DESCRIPTOR *)AllocHeapParams.BufferPtr; + + AllocHeapParams.BufferPtr += sizeof (PCIe_PORT_DESCRIPTOR) * 7; + TrinityPcieDdiPtr = (PCIe_DDI_DESCRIPTOR *) AllocHeapParams.BufferPtr; + + LibAmdMemFill (TrinityPcieComplexListPtr, + 0, + sizeof (PCIe_COMPLEX_DESCRIPTOR), + &InitEarly->StdHeader); + + LibAmdMemFill (TrinityPciePortPtr, + 0, + sizeof (PCIe_PORT_DESCRIPTOR) * 7, + &InitEarly->StdHeader); + + LibAmdMemFill (TrinityPcieDdiPtr, + 0, + sizeof (PCIe_DDI_DESCRIPTOR) * 6, + &InitEarly->StdHeader); + + LibAmdMemCopy (TrinityPcieComplexListPtr, &Trinity, sizeof (PCIe_COMPLEX_DESCRIPTOR), &InitEarly->StdHeader); + LibAmdMemCopy (TrinityPciePortPtr, &PortList[0], sizeof (PCIe_PORT_DESCRIPTOR) * 7, &InitEarly->StdHeader); + LibAmdMemCopy (TrinityPcieDdiPtr, &DdiList[0], sizeof (PCIe_DDI_DESCRIPTOR) * 6, &InitEarly->StdHeader); + + ((PCIe_COMPLEX_DESCRIPTOR*)TrinityPcieComplexListPtr)->PciePortList = (PCIe_PORT_DESCRIPTOR*)TrinityPciePortPtr; + ((PCIe_COMPLEX_DESCRIPTOR*)TrinityPcieComplexListPtr)->DdiLinkList = (PCIe_DDI_DESCRIPTOR*)TrinityPcieDdiPtr; + + InitEarly->GnbConfig.PcieComplexList = TrinityPcieComplexListPtr; +} diff --git a/src/mainboard/asus/f2a85-m/PlatformGnbPcieComplex.h b/src/mainboard/asus/f2a85-m/PlatformGnbPcieComplex.h new file mode 100644 index 0000000..3f14805 --- /dev/null +++ b/src/mainboard/asus/f2a85-m/PlatformGnbPcieComplex.h @@ -0,0 +1,72 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef _PLATFORM_GNB_PCIE_COMPLEX_H +#define _PLATFORM_GNB_PCIE_COMPLEX_H + +#include "Porting.h" +#include "AGESA.h" +#include "amdlib.h" + +//GNB GPP Port4 +#define GNB_GPP_PORT4_PORT_PRESENT 1 //0:Disable 1:Enable +#define GNB_GPP_PORT4_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2 +#define GNB_GPP_PORT4_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1 +#define GNB_GPP_PORT4_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) + //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) +#define GNB_GPP_PORT4_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced + +//GNB GPP Port5 +#define GNB_GPP_PORT5_PORT_PRESENT 1 //0:Disable 1:Enable +#define GNB_GPP_PORT5_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2 +#define GNB_GPP_PORT5_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1 +#define GNB_GPP_PORT5_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) + //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) +#define GNB_GPP_PORT5_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced + +//GNB GPP Port6 +#define GNB_GPP_PORT6_PORT_PRESENT 1 //0:Disable 1:Enable +#define GNB_GPP_PORT6_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2 +#define GNB_GPP_PORT6_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1 +#define GNB_GPP_PORT6_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) + //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) +#define GNB_GPP_PORT6_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced + +//GNB GPP Port7 +#define GNB_GPP_PORT7_PORT_PRESENT 1 //0:Disable 1:Enable +#define GNB_GPP_PORT7_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2 +#define GNB_GPP_PORT7_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1 +#define GNB_GPP_PORT7_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) + //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) +#define GNB_GPP_PORT7_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced + +//GNB GPP Port8 +#define GNB_GPP_PORT8_PORT_PRESENT 1 //0:Disable 1:Enable +#define GNB_GPP_PORT8_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2 +#define GNB_GPP_PORT8_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1 +#define GNB_GPP_PORT8_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) + //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) +#define GNB_GPP_PORT8_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced + +VOID +OemCustomizeInitEarly ( + IN OUT AMD_EARLY_PARAMS *InitEarly + ); + +#endif //_PLATFORM_GNB_PCIE_COMPLEX_H diff --git a/src/mainboard/asus/f2a85-m/acpi/AmdImc.asl b/src/mainboard/asus/f2a85-m/acpi/AmdImc.asl new file mode 100644 index 0000000..f55a12a --- /dev/null +++ b/src/mainboard/asus/f2a85-m/acpi/AmdImc.asl @@ -0,0 +1,97 @@ +//BTDC Due to IMC Fan, ACPI control codes +OperationRegion(IMIO, SystemIO, 0x3E, 0x02) +Field(IMIO , ByteAcc, NoLock, Preserve) { + IMCX,8, + IMCA,8 +} + +IndexField(IMCX, IMCA, ByteAcc, NoLock, Preserve) { + Offset(0x80), + MSTI, 8, + MITS, 8, + MRG0, 8, + MRG1, 8, + MRG2, 8, + MRG3, 8, +} + +Method(WACK, 0) +{ + Store(0, Local0) + Store(50, Local1) + While (LAnd (LNotEqual(Local0, 0xFA), LGreater(Local1,0))) { + Store(MRG0, Local0) + Sleep(10) + Decrement(Local1) + } +} + +//Init +Method (ITZE, 0) +{ + Store(0, MRG0) + Store(0xB5, MRG1) + Store(0, MRG2) + Store(0x96, MSTI) + WACK() + + Store(0, MRG0) + Store(0, MRG1) + Store(0, MRG2) + Store(0x80, MSTI) + WACK() + + Or(MRG2, 0x01, Local0) + + Store(0, MRG0) + Store(0, MRG1) + Store(Local0, MRG2) + Store(0x81, MSTI) + WACK() +} + +//Sleep +Method (IMSP, 0) +{ + Store(0, MRG0) + Store(0xB5, MRG1) + Store(0, MRG2) + Store(0x96, MSTI) + WACK() + + Store(0, MRG0) + Store(1, MRG1) + Store(0, MRG2) + Store(0x98, MSTI) + WACK() + + Store(0, MRG0) + Store(0xB4, MRG1) + Store(0, MRG2) + Store(0x96, MSTI) + WACK() +} + +//Wake +Method (IMWK, 0) +{ + Store(0, MRG0) + Store(0xB5, MRG1) + Store(0, MRG2) + Store(0x96, MSTI) + WACK() + + Store(0, MRG0) + Store(0, MRG1) + Store(0, MRG2) + Store(0x80, MSTI) + WACK() + + Or(MRG2, 0x01, Local0) + + Store(0, MRG0) + Store(0, MRG1) + Store(Local0, MRG2) + Store(0x81, MSTI) + WACK() +} diff --git a/src/mainboard/asus/f2a85-m/acpi/cpstate.asl b/src/mainboard/asus/f2a85-m/acpi/cpstate.asl new file mode 100644 index 0000000..2240fd6 --- /dev/null +++ b/src/mainboard/asus/f2a85-m/acpi/cpstate.asl @@ -0,0 +1,115 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* This file defines the processor and performance state capability + * for each core in the system. It is included into the DSDT for each + * core. It assumes that each core of the system has the same performance + * characteristics. +*/ +/* +DefinitionBlock ("DSDT.AML","DSDT",0x01,"XXXXXX","XXXXXXXX",0x00010001) + { + Scope (\_PR) { + Processor(CPU0,0,0x808,0x06) { + #include "cpstate.asl" + } + Processor(CPU1,1,0x0,0x0) { + #include "cpstate.asl" + } + Processor(CPU2,2,0x0,0x0) { + #include "cpstate.asl" + } + Processor(CPU3,3,0x0,0x0) { + #include "cpstate.asl" + } + } +*/ + /* P-state support: The maximum number of P-states supported by the */ + /* CPUs we'll use is 6. */ + /* Get from AMI BIOS. */ + Name(_PSS, Package(){ + Package() + { + 0x00000D48, + 0x00011170, + 0x00000004, + 0x00000004, + 0x00000000, + 0x00000000 + }, + + Package() + { + 0x00000AF0, + 0x0000C544, + 0x00000004, + 0x00000004, + 0x00000001, + 0x00000001 + }, + + Package() + { + 0x000009C4, + 0x0000B3B0, + 0x00000004, + 0x00000004, + 0x00000002, + 0x00000002 + }, + + Package() + { + 0x00000898, + 0x0000ABE0, + 0x00000004, + 0x00000004, + 0x00000003, + 0x00000003 + }, + + Package() + { + 0x00000708, + 0x0000A410, + 0x00000004, + 0x00000004, + 0x00000004, + 0x00000004 + }, + + Package() + { + 0x00000578, + 0x00006F54, + 0x00000004, + 0x00000004, + 0x00000005, + 0x00000005 + } + }) + + Name(_PCT, Package(){ + ResourceTemplate(){Register(FFixedHW, 0, 0, 0)}, + ResourceTemplate(){Register(FFixedHW, 0, 0, 0)} + }) + + Method(_PPC, 0){ + Return(0) + } diff --git a/src/mainboard/asus/f2a85-m/acpi/ide.asl b/src/mainboard/asus/f2a85-m/acpi/ide.asl new file mode 100644 index 0000000..1ff2e79 --- /dev/null +++ b/src/mainboard/asus/f2a85-m/acpi/ide.asl @@ -0,0 +1,244 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* +Scope (_SB) { + Device(PCI0) { + Device(IDEC) { + Name(_ADR, 0x00140001) + #include "ide.asl" + } + } +} +*/ + +/* Some timing tables */ +Name(UDTT, Package(){ /* Udma timing table */ + 120, 90, 60, 45, 30, 20, 15, 0 /* UDMA modes 0 -> 6 */ +}) + +Name(MDTT, Package(){ /* MWDma timing table */ + 480, 150, 120, 0 /* Legacy DMA modes 0 -> 2 */ +}) + +Name(POTT, Package(){ /* Pio timing table */ + 600, 390, 270, 180, 120, 0 /* PIO modes 0 -> 4 */ +}) + +/* Some timing register value tables */ +Name(MDRT, Package(){ /* MWDma timing register table */ + 0x77, 0x21, 0x20, 0xFF /* Legacy DMA modes 0 -> 2 */ +}) + +Name(PORT, Package(){ + 0x99, 0x47, 0x34, 0x22, 0x20, 0x99 /* PIO modes 0 -> 4 */ +}) + +OperationRegion(ICRG, PCI_Config, 0x40, 0x20) /* ide control registers */ + Field(ICRG, AnyAcc, NoLock, Preserve) +{ + PPTS, 8, /* Primary PIO Slave Timing */ + PPTM, 8, /* Primary PIO Master Timing */ + OFFSET(0x04), PMTS, 8, /* Primary MWDMA Slave Timing */ + PMTM, 8, /* Primary MWDMA Master Timing */ + OFFSET(0x08), PPCR, 8, /* Primary PIO Control */ + OFFSET(0x0A), PPMM, 4, /* Primary PIO master Mode */ + PPSM, 4, /* Primary PIO slave Mode */ + OFFSET(0x14), PDCR, 2, /* Primary UDMA Control */ + OFFSET(0x16), PDMM, 4, /* Primary UltraDMA Mode */ + PDSM, 4, /* Primary UltraDMA Mode */ +} + +Method(GTTM, 1) /* get total time*/ +{ + Store(And(Arg0, 0x0F), Local0) /* Recovery Width */ + Increment(Local0) + Store(ShiftRight(Arg0, 4), Local1) /* Command Width */ + Increment(Local1) + Return(Multiply(30, Add(Local0, Local1))) +} + +Device(PRID) +{ + Name (_ADR, Zero) + Method(_GTM, 0) + { + NAME(OTBF, Buffer(20) { /* out buffer */ + 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00 + }) + + CreateDwordField(OTBF, 0, PSD0) /* PIO spd0 */ + CreateDwordField(OTBF, 4, DSD0) /* DMA spd0 */ + CreateDwordField(OTBF, 8, PSD1) /* PIO spd1 */ + CreateDwordField(OTBF, 12, DSD1) /* DMA spd1 */ + CreateDwordField(OTBF, 16, BFFG) /* buffer flags */ + + /* Just return if the channel is disabled */ + If(And(PPCR, 0x01)) { /* primary PIO control */ + Return(OTBF) + } + + /* Always tell them independent timing available and IOChannelReady used on both drives */ + Or(BFFG, 0x1A, BFFG) + + Store(GTTM(PPTM), PSD0) /* save total time of primary PIO master timming to PIO spd0 */ + Store(GTTM(PPTS), PSD1) /* save total time of primary PIO slave Timing to PIO spd1 */ + + If(And(PDCR, 0x01)) { /* It's under UDMA mode */ + Or(BFFG, 0x01, BFFG) + Store(DerefOf(Index(UDTT, PDMM)), DSD0) + } + Else { + Store(GTTM(PMTM), DSD0) /* Primary MWDMA Master Timing, DmaSpd0 */ + } + + If(And(PDCR, 0x02)) { /* It's under UDMA mode */ + Or(BFFG, 0x04, BFFG) + Store(DerefOf(Index(UDTT, PDSM)), DSD1) + } + Else { + Store(GTTM(PMTS), DSD1) /* Primary MWDMA Slave Timing, DmaSpd0 */ + } + + Return(OTBF) /* out buffer */ + } /* End Method(_GTM) */ + + Method(_STM, 3, NotSerialized) + { + NAME(INBF, Buffer(20) { /* in buffer */ + 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00 + }) + + CreateDwordField(INBF, 0, PSD0) /* PIO spd0 */ + CreateDwordField(INBF, 4, DSD0) /* PIO spd0 */ + CreateDwordField(INBF, 8, PSD1) /* PIO spd1 */ + CreateDwordField(INBF, 12, DSD1) /* DMA spd1 */ + CreateDwordField(INBF, 16, BFFG) /*buffer flag */ + + Store(Match(POTT, MLE, PSD0, MTR, 0, 0), Local0) + Divide(Local0, 5, PPMM,) /* Primary PIO master Mode */ + Store(Match(POTT, MLE, PSD1, MTR, 0, 0), Local1) + Divide(Local1, 5, PPSM,) /* Primary PIO slave Mode */ + + Store(DerefOf(Index(PORT, Local0)), PPTM) /* Primary PIO Master Timing */ + Store(DerefOf(Index(PORT, Local1)), PPTS) /* Primary PIO Slave Timing */ + + If(And(BFFG, 0x01)) { /* Drive 0 is under UDMA mode */ + Store(Match(UDTT, MLE, DSD0, MTR, 0, 0), Local0) + Divide(Local0, 7, PDMM,) + Or(PDCR, 0x01, PDCR) + } + Else { + If(LNotEqual(DSD0, 0xFFFFFFFF)) { + Store(Match(MDTT, MLE, DSD0, MTR, 0, 0), Local0) + Store(DerefOf(Index(MDRT, Local0)), PMTM) + } + } + + If(And(BFFG, 0x04)) { /* Drive 1 is under UDMA mode */ + Store(Match(UDTT, MLE, DSD1, MTR, 0, 0), Local0) + Divide(Local0, 7, PDSM,) + Or(PDCR, 0x02, PDCR) + } + Else { + If(LNotEqual(DSD1, 0xFFFFFFFF)) { + Store(Match(MDTT, MLE, DSD1, MTR, 0, 0), Local0) + Store(DerefOf(Index(MDRT, Local0)), PMTS) + } + } + /* Return(INBF) */ + } /*End Method(_STM) */ + Device(MST) + { + Name(_ADR, 0) + Method(_GTF) { + Name(CMBF, Buffer(21) { + 0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF, + 0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF5 + }) + CreateByteField(CMBF, 1, POMD) + CreateByteField(CMBF, 8, DMMD) + CreateByteField(CMBF, 5, CMDA) + CreateByteField(CMBF, 12, CMDB) + CreateByteField(CMBF, 19, CMDC) + + Store(0xA0, CMDA) + Store(0xA0, CMDB) + Store(0xA0, CMDC) + + Or(PPMM, 0x08, POMD) + + If(And(PDCR, 0x01)) { + Or(PDMM, 0x40, DMMD) + } + Else { + Store(Match + (MDTT, MLE, GTTM(PMTM), + MTR, 0, 0), Local0) + If(LLess(Local0, 3)) { + Or(0x20, Local0, DMMD) + } + } + Return(CMBF) + } + } /* End Device(MST) */ + + Device(SLAV) + { + Name(_ADR, 1) + Method(_GTF) { + Name(CMBF, Buffer(21) { + 0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF, + 0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF5 + }) + CreateByteField(CMBF, 1, POMD) + CreateByteField(CMBF, 8, DMMD) + CreateByteField(CMBF, 5, CMDA) + CreateByteField(CMBF, 12, CMDB) + CreateByteField(CMBF, 19, CMDC) + + Store(0xB0, CMDA) + Store(0xB0, CMDB) + Store(0xB0, CMDC) + + Or(PPSM, 0x08, POMD) + + If(And(PDCR, 0x02)) { + Or(PDSM, 0x40, DMMD) + } + Else { + Store(Match + (MDTT, MLE, GTTM(PMTS), + MTR, 0, 0), Local0) + If(LLess(Local0, 3)) { + Or(0x20, Local0, DMMD) + } + } + Return(CMBF) + } + } /* End Device(SLAV) */ +} diff --git a/src/mainboard/asus/f2a85-m/acpi/routing.asl b/src/mainboard/asus/f2a85-m/acpi/routing.asl new file mode 100644 index 0000000..03027c3 --- /dev/null +++ b/src/mainboard/asus/f2a85-m/acpi/routing.asl @@ -0,0 +1,207 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* +DefinitionBlock ("DSDT.AML","DSDT",0x01,"XXXXXX","XXXXXXXX",0x00010001 + ) + { + #include "routing.asl" + } +*/ + +/* Routing is in System Bus scope */ +Scope(\_SB) { + Name(PR0, Package(){ + /* NB devices */ + /* Bus 0, Dev 0 - F15 Host Controller */ + /* Bus 0, Dev 1 - PCI Bridge for Internal Graphics(IGP) */ + Package(){0x0001FFFF, 0, INTB, 0 }, + Package(){0x0001FFFF, 1, INTC, 0 }, + + /* Bus 0, Dev 2 - PCIe Bridge for x16 slot */ + Package(){0x0002FFFF, 0, INTC, 0 }, + Package(){0x0002FFFF, 1, INTD, 0 }, + Package(){0x0002FFFF, 2, INTA, 0 }, + Package(){0x0002FFFF, 3, INTB, 0 }, + + /* Bus 0, Dev 4 - PCIe Bridge for 4x slot */ + Package(){0x0004FFFF, 0, INTA, 0 }, + Package(){0x0004FFFF, 1, INTB, 0 }, + Package(){0x0004FFFF, 2, INTC, 0 }, + Package(){0x0004FFFF, 3, INTD, 0 }, + + + /* Bus 0, Funct 8 - Southbridge port (normally hidden) */ + + /* SB devices */ + /* Bus 0, Dev 20 - F0:SMBus/ACPI,F1:IDE;F2:HDAudio;F3:LPC;F4:PCIBridge;F5:USB */ + Package(){0x0014FFFF, 0, INTA, 0 }, + Package(){0x0014FFFF, 1, INTB, 0 }, + Package(){0x0014FFFF, 2, INTC, 0 }, + Package(){0x0014FFFF, 3, INTD, 0 }, + + /* Bus 0, Dev 19 - USB: OHCI, dev 18,19 func 0-2, dev 20 func 5; + * EHCI, dev 18, 19 func 2 */ + Package(){0x0012FFFF, 0, INTC, 0 }, + Package(){0x0012FFFF, 1, INTB, 0 }, + + Package(){0x0013FFFF, 0, INTC, 0 }, + Package(){0x0013FFFF, 1, INTB, 0 }, + + Package(){0x0016FFFF, 0, INTC, 0 }, + Package(){0x0016FFFF, 1, INTB, 0 }, + + /* Bus 0, Dev 10 - USB: XHCI func 0, 1 */ + Package(){0x0010FFFF, 0, INTC, 0 }, + Package(){0x0010FFFF, 1, INTB, 0 }, + + /* Bus 0, Dev 17 - SATA controller */ + Package(){0x0011FFFF, 0, INTD, 0 }, + + /* Bus 0, Dev 21 Pcie Bridge */ + Package(){0x0015FFFF, 0, INTA, 0 }, + Package(){0x0015FFFF, 1, INTB, 0 }, + Package(){0x0015FFFF, 2, INTC, 0 }, + Package(){0x0015FFFF, 3, INTD, 0 }, + }) + + Name(APR0, Package(){ + /* NB devices in APIC mode */ + /* Bus 0, Dev 0 - F15 Host Controller */ + + /* Bus 0, Dev 1 - PCI Bridge for Internal Graphics(IGP) */ + Package(){0x0001FFFF, 0, 0, 17 }, + package(){0x0001FFFF, 1, 0, 18 }, + + /* Bus 0, Dev 2 - PCIe Bridge for x16 PCIe Slot */ + Package(){0x0002FFFF, 0, 0, 18 }, + Package(){0x0002FFFF, 1, 0, 19 }, + Package(){0x0002FFFF, 2, 0, 16 }, + Package(){0x0002FFFF, 3, 0, 17 }, + + /* Bus 0, Dev 4 - PCIe Bridge for x4 PCIe Slot black */ + Package(){0x0004FFFF, 0, 0, 16 }, + Package(){0x0004FFFF, 1, 0, 17 }, + Package(){0x0004FFFF, 2, 0, 18 }, + Package(){0x0004FFFF, 3, 0, 19 }, + + /* Bus 0, Funct 8 - Southbridge port (normally hidden) */ + + /* SB devices in APIC mode */ + /* Bus 0, Dev 20 - F0:SMBus/ACPI, F1:IDE; F2:HDAudio; F3:LPC; F4:PCIBridge; F5:USB */ + Package(){0x0014FFFF, 0, 0, 16 }, + Package(){0x0014FFFF, 1, 0, 17 }, + Package(){0x0014FFFF, 2, 0, 18 }, + Package(){0x0014FFFF, 3, 0, 19 }, + + /* Bus 0, Dev 19 - USB: OHCI, dev 18,19 func 0-2, dev 20 func 5; + * EHCI, dev 18, 19 func 2 */ + Package(){0x0012FFFF, 0, 0, 18 }, + Package(){0x0012FFFF, 1, 0, 17 }, + + Package(){0x0013FFFF, 0, 0, 18 }, + Package(){0x0013FFFF, 1, 0, 17 }, + + Package(){0x0016FFFF, 0, 0, 18 }, + Package(){0x0016FFFF, 1, 0, 17 }, + + /* Bus 0, Dev 10 - USB: XHCI func 0, 1 */ + Package(){0x0010FFFF, 0, 0, 0x12}, + Package(){0x0010FFFF, 1, 0, 0x11}, + + /* Bus 0, Dev 17 - SATA controller */ + Package(){0x0011FFFF, 0, 0, 19 }, + + /* Bus0, Dev 21 PCIE Bridge */ + Package(){0x0015FFFF, 0, 0, 16 }, + Package(){0x0015FFFF, 1, 0, 17 }, + Package(){0x0015FFFF, 2, 0, 18 }, + Package(){0x0015FFFF, 3, 0, 19 }, + }) + + Name(PS2, Package(){ + /* The external GFX - Hooked to PCIe slot 2 */ + Package(){0x0000FFFF, 0, INTD, 0 }, + Package(){0x0000FFFF, 1, INTA, 0 }, + Package(){0x0000FFFF, 2, INTB, 0 }, + Package(){0x0000FFFF, 3, INTC, 0 }, + }) + Name(APS2, Package(){ + /* The external GFX - Hooked to PCIe slot 2 */ + Package(){0x0000FFFF, 0, 0, 0x12 }, + Package(){0x0000FFFF, 1, 0, 0x13 }, + Package(){0x0000FFFF, 2, 0, 0x10 }, + Package(){0x0000FFFF, 3, 0, 0x11 }, + }) + + /* black slot */ + Name(PS4, Package(){ + /* PCIe slot - Hooked to PCIe slot x4 */ + Package(){0x0000FFFF, 0, INTA, 0 }, + Package(){0x0000FFFF, 1, INTB, 0 }, + Package(){0x0000FFFF, 2, INTC, 0 }, + Package(){0x0000FFFF, 3, INTD, 0 }, + }) + Name(APS4, Package(){ + /* PCIe slot - Hooked to PCIe slot x4 */ + Package(){0x0000FFFF, 0, 0, 0x10 }, + Package(){0x0000FFFF, 1, 0, 0x11 }, + Package(){0x0000FFFF, 2, 0, 0x12 }, + Package(){0x0000FFFF, 3, 0, 0x13 }, + }) + + Name(PBR0, Package(){ + /* PCIx1 on SB */ + Package(){0x0000FFFF, 0, INTA, 0 }, + Package(){0x0000FFFF, 1, INTB, 0 }, + Package(){0x0000FFFF, 2, INTC, 0 }, + Package(){0x0000FFFF, 3, INTD, 0 }, + }) + Name(ABR0, Package(){ + /* PCIx1 on SB */ + Package(){0x0000FFFF, 0, 0, 0x10 }, + Package(){0x0000FFFF, 1, 0, 0x11 }, + Package(){0x0000FFFF, 2, 0, 0x12 }, + Package(){0x0000FFFF, 3, 0, 0x13 }, + }) + + Name(PBR1, Package(){ + /* Onboard network */ + Package(){0x0000FFFF, 0, INTB, 0 }, + Package(){0x0000FFFF, 1, INTC, 0 }, + Package(){0x0000FFFF, 2, INTD, 0 }, + Package(){0x0000FFFF, 3, INTA, 0 }, + }) + Name(ABR1, Package(){ + /* Onboard network */ + Package(){0x0000FFFF, 0, 0, 0x11 }, + Package(){0x0000FFFF, 1, 0, 0x12 }, + Package(){0x0000FFFF, 2, 0, 0x13 }, + Package(){0x0000FFFF, 3, 0, 0x10 }, + }) + + /* SB PCI Bridge */ + Name(PCIB, Package(){ + /* PCI slots: slot 0 behind Dev14, Fun4. */ + Package(){0x0005FFFF, 0, 0, 0x14 }, + Package(){0x0005FFFF, 1, 0, 0x15 }, + Package(){0x0005FFFF, 2, 0, 0x16 }, + Package(){0x0005FFFF, 3, 0, 0x17 }, + }) +} diff --git a/src/mainboard/asus/f2a85-m/acpi/sata.asl b/src/mainboard/asus/f2a85-m/acpi/sata.asl new file mode 100644 index 0000000..c817b6e --- /dev/null +++ b/src/mainboard/asus/f2a85-m/acpi/sata.asl @@ -0,0 +1,148 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* simple name description */ + +/* +Scope (_SB) { + Device(PCI0) { + Device(SATA) { + Name(_ADR, 0x00110000) + #include "sata.asl" + } + } +} +*/ + +Name(STTM, Buffer(20) { + 0x78, 0x00, 0x00, 0x00, 0x0f, 0x00, 0x00, 0x00, + 0x78, 0x00, 0x00, 0x00, 0x0f, 0x00, 0x00, 0x00, + 0x1f, 0x00, 0x00, 0x00 +}) + +/* Start by clearing the PhyRdyChg bits */ +Method(_INI) { + \_GPE._L1F() +} + +Device(PMRY) +{ + Name(_ADR, 0) + Method(_GTM, 0x0, NotSerialized) { + Return(STTM) + } + Method(_STM, 0x3, NotSerialized) {} + + Device(PMST) { + Name(_ADR, 0) + Method(_STA,0) { + if (LGreater(P0IS,0)) { + return (0x0F) /* sata is visible */ + } + else { + return (0x00) /* sata is missing */ + } + } + }/* end of PMST */ + + Device(PSLA) + { + Name(_ADR, 1) + Method(_STA,0) { + if (LGreater(P1IS,0)) { + return (0x0F) /* sata is visible */ + } + else { + return (0x00) /* sata is missing */ + } + } + } /* end of PSLA */ +} /* end of PMRY */ + +Device(SEDY) +{ + Name(_ADR, 1) /* IDE Scondary Channel */ + Method(_GTM, 0x0, NotSerialized) { + Return(STTM) + } + Method(_STM, 0x3, NotSerialized) {} + + Device(SMST) + { + Name(_ADR, 0) + Method(_STA,0) { + if (LGreater(P2IS,0)) { + return (0x0F) /* sata is visible */ + } + else { + return (0x00) /* sata is missing */ + } + } + } /* end of SMST */ + + Device(SSLA) + { + Name(_ADR, 1) + Method(_STA,0) { + if (LGreater(P3IS,0)) { + return (0x0F) /* sata is visible */ + } + else { + return (0x00) /* sata is missing */ + } + } + } /* end of SSLA */ +} /* end of SEDY */ + +/* SATA Hot Plug Support */ +Scope(\_GPE) { + Method(_L1F,0x0,NotSerialized) { + if (\_SB.P0PR) { + if (LGreater(\_SB.P0IS,0)) { + sleep(32) + } + Notify(\_SB.PCI0.STCR.PMRY.PMST, 0x01) /* NOTIFY_DEVICE_CHECK */ + store(one, \_SB.P0PR) + } + + if (\_SB.P1PR) { + if (LGreater(\_SB.P1IS,0)) { + sleep(32) + } + Notify(\_SB.PCI0.STCR.PMRY.PSLA, 0x01) /* NOTIFY_DEVICE_CHECK */ + store(one, \_SB.P1PR) + } + + if (\_SB.P2PR) { + if (LGreater(\_SB.P2IS,0)) { + sleep(32) + } + Notify(\_SB.PCI0.STCR.SEDY.SMST, 0x01) /* NOTIFY_DEVICE_CHECK */ + store(one, \_SB.P2PR) + } + + if (\_SB.P3PR) { + if (LGreater(\_SB.P3IS,0)) { + sleep(32) + } + Notify(\_SB.PCI0.STCR.SEDY.SSLA, 0x01) /* NOTIFY_DEVICE_CHECK */ + store(one, \_SB.P3PR) + } + } +} diff --git a/src/mainboard/asus/f2a85-m/acpi/usb.asl b/src/mainboard/asus/f2a85-m/acpi/usb.asl new file mode 100644 index 0000000..857c78f --- /dev/null +++ b/src/mainboard/asus/f2a85-m/acpi/usb.asl @@ -0,0 +1,114 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* simple name description */ +/* +DefinitionBlock ("DSDT.AML","DSDT",0x01,"XXXXXX","XXXXXXXX",0x00010001 + ) + { + #include "usb.asl" + } +*/ +Method(UCOC, 0) { + Sleep(20) + Store(0x13,CMTI) + Store(0,GPSL) +} + +/* USB Port 0 overcurrent uses Gpm 0 */ +If(LLessEqual(UOM0,9)) { + Scope (\_GPE) { + Method (_L13) { + } + } +} + +/* USB Port 1 overcurrent uses Gpm 1 */ +If (LLessEqual(UOM1,9)) { + Scope (\_GPE) { + Method (_L14) { + } + } +} + +/* USB Port 2 overcurrent uses Gpm 2 */ +If (LLessEqual(UOM2,9)) { + Scope (\_GPE) { + Method (_L15) { + } + } +} + +/* USB Port 3 overcurrent uses Gpm 3 */ +If (LLessEqual(UOM3,9)) { + Scope (\_GPE) { + Method (_L16) { + } + } +} + +/* USB Port 4 overcurrent uses Gpm 4 */ +If (LLessEqual(UOM4,9)) { + Scope (\_GPE) { + Method (_L19) { + } + } +} + +/* USB Port 5 overcurrent uses Gpm 5 */ +If (LLessEqual(UOM5,9)) { + Scope (\_GPE) { + Method (_L1A) { + } + } +} + +/* USB Port 6 overcurrent uses Gpm 6 */ +If (LLessEqual(UOM6,9)) { + Scope (\_GPE) { + /* Method (_L1C) { */ + Method (_L06) { + } + } +} + +/* USB Port 7 overcurrent uses Gpm 7 */ +If (LLessEqual(UOM7,9)) { + Scope (\_GPE) { + /* Method (_L1D) { */ + Method (_L07) { + } + } +} + +/* USB Port 8 overcurrent uses Gpm 8 */ +If (LLessEqual(UOM8,9)) { + Scope (\_GPE) { + Method (_L17) { + } + } +} + +/* USB Port 9 overcurrent uses Gpm 9 */ +If (LLessEqual(UOM9,9)) { + Scope (\_GPE) { + Method (_L0E) { + } + } +} diff --git a/src/mainboard/asus/f2a85-m/acpi_tables.c b/src/mainboard/asus/f2a85-m/acpi_tables.c new file mode 100644 index 0000000..d93fecc --- /dev/null +++ b/src/mainboard/asus/f2a85-m/acpi_tables.c @@ -0,0 +1,329 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <console/console.h> +#include <string.h> +#include <arch/acpi.h> +#include <arch/acpigen.h> +#include <arch/ioapic.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include <cpu/x86/msr.h> +#include "agesawrapper.h" +#include <cpu/amd/mtrr.h> +#include <cpu/amd/amdfam15.h> + +#include "agesawrapper.h" + +#define DUMP_ACPI_TABLES 0 + +#if DUMP_ACPI_TABLES == 1 + +static void dump_mem(u32 start, u32 end) +{ + u32 i; + print_debug("dump_mem:"); + for (i = start; i < end; i++) { + if ((i & 0xf) == 0) { + printk(BIOS_DEBUG, "\n%08x:", i); + } + printk(BIOS_DEBUG, " %02x", (u8)*((u8 *)i)); + } + print_debug("\n"); +} +#endif + +extern const unsigned char AmlCode[]; + +unsigned long acpi_fill_mcfg(unsigned long current) +{ + /* Just a dummy */ + return current; +} + +unsigned long acpi_fill_madt(unsigned long current) +{ + /* create all subtables for processors */ + current = acpi_create_madt_lapics(current); + + /* Write Hudson IOAPIC, only one */ + current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, CONFIG_MAX_CPUS, + IO_APIC_ADDR, 0); + + current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) + current, 0, 0, 2, 0); + current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) + current, 0, 9, 9, 0xF); + /* 0: mean bus 0--->ISA */ + /* 0: PIC 0 */ + /* 2: APIC 2 */ + /* 5 mean: 0101 --> Edige-triggered, Active high */ + + /* create all subtables for processors */ + current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *)current, 0xff, 5, 1); + /* 1: LINT1 connect to NMI */ + + return current; +} + +unsigned long acpi_fill_hest(acpi_hest_t *hest) +{ + void *addr, *current; + + /* Skip the HEST header. */ + current = (void *)(hest + 1); + + addr = agesawrapper_getlateinitptr(PICK_WHEA_MCE); + if (addr != NULL) + current += acpi_create_hest_error_source(hest, current, 0, (void *)((u32)addr + 2), *(UINT16 *)addr - 2); + + addr = agesawrapper_getlateinitptr(PICK_WHEA_CMC); + if (addr != NULL) + current += acpi_create_hest_error_source(hest, current, 1, (void *)((u32)addr + 2), *(UINT16 *)addr - 2); + + return (unsigned long)current; +} + +unsigned long acpi_fill_slit(unsigned long current) +{ + /* Not implemented */ + return current; +} + +unsigned long acpi_fill_srat(unsigned long current) +{ + /* No NUMA, no SRAT */ + return current; +} + +unsigned long acpi_fill_ssdt_generator(unsigned long current, const char *oem_table_id) +{ + int lens; + msr_t msr; + char pscope[] = "\\_SB.PCI0"; + + lens = acpigen_write_scope(pscope); + msr = rdmsr(TOP_MEM); + lens += acpigen_write_name_dword("TOM1", msr.lo); + msr = rdmsr(TOP_MEM2); + /* + * Since XP only implements parts of ACPI 2.0, we can't use a qword + * here. + * See http://www.acpi.info/presentations/S01USMOBS169_OS%2520new.ppt + * slide 22ff. + * Shift value right by 20 bit to make it fit into 32bit, + * giving us 1MB granularity and a limit of almost 4Exabyte of memory. + */ + lens += acpigen_write_name_dword("TOM2", (msr.hi << 12) | msr.lo >> 20); + acpigen_patch_len(lens - 1); + return (unsigned long) (acpigen_get_current()); +} + +unsigned long write_acpi_tables(unsigned long start) +{ + unsigned long current; + acpi_rsdp_t *rsdp; + acpi_rsdt_t *rsdt; + acpi_hpet_t *hpet; + acpi_madt_t *madt; + acpi_srat_t *srat; + acpi_slit_t *slit; + acpi_fadt_t *fadt; + acpi_facs_t *facs; + acpi_header_t *dsdt; + acpi_header_t *ssdt; + acpi_header_t *alib; + acpi_header_t *ivrs; + acpi_hest_t *hest; + + get_bus_conf(); /* it will get sblk, pci1234, hcdn, and sbdn */ + + /* Align ACPI tables to 16 bytes */ + start = ALIGN(start, 16); + current = start; + + printk(BIOS_INFO, "ACPI: Writing ACPI tables at %lx...\n", start); + + /* We need at least an RSDP and an RSDT Table */ + rsdp = (acpi_rsdp_t *) current; + current += sizeof(acpi_rsdp_t); + rsdt = (acpi_rsdt_t *) current; + current += sizeof(acpi_rsdt_t); + + /* clear all table memory */ + memset((void *)start, 0, current - start); + + acpi_write_rsdp(rsdp, rsdt, NULL); + acpi_write_rsdt(rsdt); + + /* DSDT */ + current = ALIGN(current, 8); + printk(BIOS_DEBUG, "ACPI: * DSDT at %lx\n", current); + dsdt = (acpi_header_t *)current; /* it will used by fadt */ + memcpy(dsdt, &AmlCode, sizeof(acpi_header_t)); + current += dsdt->length; + memcpy(dsdt, &AmlCode, dsdt->length); + printk(BIOS_DEBUG, "ACPI: * DSDT @ %p Length %x\n",dsdt,dsdt->length); + + /* FACS */ /* it needs 64 bit alignment */ + current = ALIGN(current, 8); + printk(BIOS_DEBUG, "ACPI: * FACS at %lx\n", current); + facs = (acpi_facs_t *) current; /* it will be used by fadt */ + current += sizeof(acpi_facs_t); + acpi_create_facs(facs); + + /* FADT */ + current = ALIGN(current, 8); + printk(BIOS_DEBUG, "ACPI: * FADT at %lx\n", current); + fadt = (acpi_fadt_t *) current; + current += sizeof(acpi_fadt_t); + + acpi_create_fadt(fadt, facs, dsdt); + acpi_add_table(rsdp, fadt); + + /* + * We explicitly add these tables later on: + */ + current = ALIGN(current, 8); + printk(BIOS_DEBUG, "ACPI: * HPET at %lx\n", current); + hpet = (acpi_hpet_t *) current; + current += sizeof(acpi_hpet_t); + acpi_create_hpet(hpet); + acpi_add_table(rsdp, hpet); + + /* If we want to use HPET Timers Linux wants an MADT */ + current = ALIGN(current, 8); + printk(BIOS_DEBUG, "ACPI: * MADT at %lx\n",current); + madt = (acpi_madt_t *) current; + acpi_create_madt(madt); + current += madt->header.length; + acpi_add_table(rsdp, madt); + + /* HEST */ + current = ALIGN(current, 8); + hest = (acpi_hest_t *)current; + acpi_write_hest((void *)current); + acpi_add_table(rsdp, (void *)current); + current += ((acpi_header_t *)current)->length; + + current = ALIGN(current, 8); + printk(BIOS_DEBUG, "ACPI: * IVRS at %lx\n", current); + ivrs = agesawrapper_getlateinitptr(PICK_IVRS); + if (ivrs != NULL) { + memcpy((void *)current, ivrs, ivrs->length); + ivrs = (acpi_header_t *) current; + current += ivrs->length; + acpi_add_table(rsdp, ivrs); + } else { + printk(BIOS_DEBUG, " AGESA IVRS table NULL. Skipping.\n"); + } + + /* SRAT */ + current = ALIGN(current, 8); + printk(BIOS_DEBUG, "ACPI: * SRAT at %lx\n", current); + srat = (acpi_srat_t *) agesawrapper_getlateinitptr (PICK_SRAT); + if (srat != NULL) { + memcpy((void *)current, srat, srat->header.length); + srat = (acpi_srat_t *) current; + current += srat->header.length; + acpi_add_table(rsdp, srat); + } else { + printk(BIOS_DEBUG, " AGESA SRAT table NULL. Skipping.\n"); + } + + /* SLIT */ + current = ALIGN(current, 8); + printk(BIOS_DEBUG, "ACPI: * SLIT at %lx\n", current); + slit = (acpi_slit_t *) agesawrapper_getlateinitptr (PICK_SLIT); + if (slit != NULL) { + memcpy((void *)current, slit, slit->header.length); + slit = (acpi_slit_t *) current; + current += slit->header.length; + acpi_add_table(rsdp, slit); + } else { + printk(BIOS_DEBUG, " AGESA SLIT table NULL. Skipping.\n"); + } + + /* ALIB */ + current = ALIGN(current, 16); + printk(BIOS_DEBUG, "ACPI: * AGESA ALIB SSDT at %lx\n", current); + alib = (acpi_header_t *)agesawrapper_getlateinitptr (PICK_ALIB); + if (alib != NULL) { + memcpy((void *)current, alib, alib->length); + alib = (acpi_header_t *) current; + current += alib->length; + acpi_add_table(rsdp, (void *)alib); + } + else { + printk(BIOS_DEBUG, " AGESA ALIB SSDT table NULL. Skipping.\n"); + } + + /* this pstate ssdt may cause Blue Screen: Fixed: Keep this comment for a while. */ + /* SSDT */ + current = ALIGN(current, 16); + printk(BIOS_DEBUG, "ACPI: * SSDT at %lx\n", current); + ssdt = (acpi_header_t *)agesawrapper_getlateinitptr (PICK_PSTATE); + if (ssdt != NULL) { + memcpy((void *)current, ssdt, ssdt->length); + ssdt = (acpi_header_t *) current; + current += ssdt->length; + } + else { + printk(BIOS_DEBUG, " AGESA PState table NULL. Skipping.\n"); + } + acpi_add_table(rsdp,ssdt); + + printk(BIOS_DEBUG, "ACPI: * SSDT for PState at %lx\n", current); + + printk(BIOS_DEBUG, "ACPI: * SSDT\n"); + ssdt = (acpi_header_t *)current; + + acpi_create_ssdt_generator(ssdt, ACPI_TABLE_CREATOR); + current += ssdt->length; + acpi_add_table(rsdp, ssdt); + +#if DUMP_ACPI_TABLES == 1 + printk(BIOS_DEBUG, "rsdp\n"); + dump_mem(rsdp, ((void *)rsdp) + sizeof(acpi_rsdp_t)); + + printk(BIOS_DEBUG, "rsdt\n"); + dump_mem(rsdt, ((void *)rsdt) + sizeof(acpi_rsdt_t)); + + printk(BIOS_DEBUG, "madt\n"); + dump_mem(madt, ((void *)madt) + madt->header.length); + + printk(BIOS_DEBUG, "srat\n"); + dump_mem(srat, ((void *)srat) + srat->header.length); + + printk(BIOS_DEBUG, "slit\n"); + dump_mem(slit, ((void *)slit) + slit->header.length); + + printk(BIOS_DEBUG, "ssdt\n"); + dump_mem(ssdt, ((void *)ssdt) + ssdt->length); + + printk(BIOS_DEBUG, "fadt\n"); + dump_mem(fadt, ((void *)fadt) + fadt->header.length); + + printk(BIOS_DEBUG, "hest\n"); + dump_mem(hest, ((void *)hest) + hest->header.length); +#endif + + printk(BIOS_INFO, "ACPI: done.\n"); + return current; +} diff --git a/src/mainboard/asus/f2a85-m/agesawrapper.c b/src/mainboard/asus/f2a85-m/agesawrapper.c new file mode 100644 index 0000000..df45148 --- /dev/null +++ b/src/mainboard/asus/f2a85-m/agesawrapper.c @@ -0,0 +1,775 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ + +#include <stdint.h> +#include <string.h> +#include "agesawrapper.h" +#include "BiosCallOuts.h" +#include "cpuRegisters.h" +#include "cpuCacheInit.h" +#include "cpuApicUtilities.h" +#include "cpuEarlyInit.h" +#include "cpuLateInit.h" +#include "Dispatcher.h" +#include "cpuCacheInit.h" +#include "amdlib.h" +#include "PlatformGnbPcieComplex.h" +#include "Filecode.h" +#include "heapManager.h" +#include "FchPlatform.h" +#include "Fch.h" +#include <cpu/amd/agesa/s3_resume.h> +#include <cbmem.h> +#include <arch/acpi.h> +#include <arch/io.h> + +VOID FchInitS3LateRestore (IN FCH_DATA_BLOCK *FchDataPtr); +VOID FchInitS3EarlyRestore (IN FCH_DATA_BLOCK *FchDataPtr); + +#define FILECODE UNASSIGNED_FILE_FILECODE + +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + +/* ACPI table pointers returned by AmdInitLate */ +VOID *DmiTable = NULL; +VOID *AcpiPstate = NULL; +VOID *AcpiSrat = NULL; +VOID *AcpiSlit = NULL; + +VOID *AcpiWheaMce = NULL; +VOID *AcpiWheaCmc = NULL; +VOID *AcpiAlib = NULL; +VOID *AcpiIvrs = NULL; + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * E X P O R T E D F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + +/*--------------------------------------------------------------------------------------- + * L O C A L F U N C T I O N S + *--------------------------------------------------------------------------------------- + */ +UINT32 +agesawrapper_amdinitcpuio ( + VOID + ) +{ + AGESA_STATUS Status; + UINT64 MsrReg; + UINT32 PciData; + PCI_ADDR PciAddress; + AMD_CONFIG_PARAMS StdHeader; + + /* Enable legacy video routing: D18F1xF4 VGA Enable */ + PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0xF4); + PciData = 1; + LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); + + /* The platform BIOS needs to ensure the memory ranges of Hudson legacy + * devices (TPM, HPET, BIOS RAM, Watchdog Timer, I/O APIC and ACPI) are + * set to non-posted regions. + */ + PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x84); + PciData = 0x00FEDF00; /* last address before processor local APIC at FEE00000 */ + PciData |= 1 << 7; /* set NP (non-posted) bit */ + LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); + PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x80); + PciData = (0xFED00000 >> 8) | 3; /* lowest NP address is HPET at FED00000 */ + LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); + + /* Map the remaining PCI hole as posted MMIO */ + PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x8C); + PciData = 0x00FECF00; /* last address before non-posted range */ + LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); + LibAmdMsrRead (0xC001001A, &MsrReg, &StdHeader); + MsrReg = (MsrReg >> 8) | 3; + PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x88); + PciData = (UINT32)MsrReg; + LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); + + /* Send all IO (0000-FFFF) to southbridge. */ + PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0xC4); + PciData = 0x0000F000; + LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); + PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0xC0); + PciData = 0x00000003; + LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); + Status = AGESA_SUCCESS; + return (UINT32)Status; +} + +UINT32 +agesawrapper_amdinitmmio ( + VOID + ) +{ + AGESA_STATUS Status; + UINT64 MsrReg; + UINT32 PciData; + PCI_ADDR PciAddress; + AMD_CONFIG_PARAMS StdHeader; + + /* + Set the MMIO Configuration Base Address and Bus Range onto MMIO configuration base + Address MSR register. + */ + MsrReg = CONFIG_MMCONF_BASE_ADDRESS | (LibAmdBitScanReverse (CONFIG_MMCONF_BUS_NUMBER) << 2) | 1; + LibAmdMsrWrite (0xC0010058, &MsrReg, &StdHeader); + + /* + Set the NB_CFG MSR register. Enable CF8 extended configuration cycles. + */ + LibAmdMsrRead (0xC001001F, &MsrReg, &StdHeader); + MsrReg = MsrReg | 0x0000400000000000; + LibAmdMsrWrite (0xC001001F, &MsrReg, &StdHeader); + + /* For serial port */ + PciData = 0xFF03FFD5; + PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x14, 0x3, 0x44); + LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); + + /* Set ROM cache onto WP to decrease post time */ + MsrReg = (0x0100000000ull - CONFIG_ROM_SIZE) | 5ull; + LibAmdMsrWrite (0x20C, &MsrReg, &StdHeader); + MsrReg = ((1ULL << CONFIG_CPU_ADDR_BITS) - CONFIG_ROM_SIZE) | 0x800ull; + LibAmdMsrWrite (0x20D, &MsrReg, &StdHeader); + + Status = AGESA_SUCCESS; + return (UINT32)Status; +} + +UINT32 +agesawrapper_amdinitreset ( + VOID + ) +{ + AGESA_STATUS status; + AMD_INTERFACE_PARAMS AmdParamStruct; + AMD_RESET_PARAMS AmdResetParams; + + LibAmdMemFill (&AmdParamStruct, + 0, + sizeof (AMD_INTERFACE_PARAMS), + &(AmdParamStruct.StdHeader)); + + LibAmdMemFill (&AmdResetParams, + 0, + sizeof (AMD_RESET_PARAMS), + &(AmdResetParams.StdHeader)); + + AmdParamStruct.AgesaFunctionName = AMD_INIT_RESET; + AmdParamStruct.AllocationMethod = ByHost; + AmdParamStruct.NewStructSize = sizeof(AMD_RESET_PARAMS); + AmdParamStruct.NewStructPtr = &AmdResetParams; + AmdParamStruct.StdHeader.AltImageBasePtr = 0; + AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; + AmdParamStruct.StdHeader.Func = 0; + AmdParamStruct.StdHeader.ImageBasePtr = 0; + AmdCreateStruct (&AmdParamStruct); + AmdResetParams.HtConfig.Depth = 0; + + status = AmdInitReset ((AMD_RESET_PARAMS *)AmdParamStruct.NewStructPtr); + if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog(AmdParamStruct.StdHeader.HeapStatus); + AmdReleaseStruct (&AmdParamStruct); + return (UINT32)status; +} + +UINT32 +agesawrapper_amdinitearly ( + VOID + ) +{ + AGESA_STATUS status; + AMD_INTERFACE_PARAMS AmdParamStruct; + AMD_EARLY_PARAMS *AmdEarlyParamsPtr; + + LibAmdMemFill (&AmdParamStruct, + 0, + sizeof (AMD_INTERFACE_PARAMS), + &(AmdParamStruct.StdHeader)); + + AmdParamStruct.AgesaFunctionName = AMD_INIT_EARLY; + AmdParamStruct.AllocationMethod = PreMemHeap; + AmdParamStruct.StdHeader.AltImageBasePtr = 0; + AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; + AmdParamStruct.StdHeader.Func = 0; + AmdParamStruct.StdHeader.ImageBasePtr = 0; + AmdCreateStruct (&AmdParamStruct); + + AmdEarlyParamsPtr = (AMD_EARLY_PARAMS *)AmdParamStruct.NewStructPtr; + OemCustomizeInitEarly (AmdEarlyParamsPtr); + + status = AmdInitEarly ((AMD_EARLY_PARAMS *)AmdParamStruct.NewStructPtr); + if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog(AmdParamStruct.StdHeader.HeapStatus); + AmdReleaseStruct (&AmdParamStruct); + + return (UINT32)status; +} + +UINT32 GetHeapBase( + AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT32 heap; + +#if CONFIG_HAVE_ACPI_RESUME + /* Both romstage and ramstage has this S3 detect. */ + if (acpi_get_sleep_type() == 3) + heap = (UINT32)cbmem_find(CBMEM_ID_RESUME_SCRATCH) + (CONFIG_HIGH_SCRATCH_MEMORY_SIZE - BIOS_HEAP_SIZE); /* base + high_stack_size */ + else +#endif + heap = BIOS_HEAP_START_ADDRESS; /* Low mem */ + + return heap; +} + +UINT32 +agesawrapper_amdinitpost ( + VOID + ) +{ + AGESA_STATUS status; + UINT16 i; + UINT32 *HeadPtr; + AMD_INTERFACE_PARAMS AmdParamStruct; + AMD_POST_PARAMS *PostParams; + BIOS_HEAP_MANAGER *BiosManagerPtr; + + LibAmdMemFill (&AmdParamStruct, + 0, + sizeof (AMD_INTERFACE_PARAMS), + &(AmdParamStruct.StdHeader)); + + AmdParamStruct.AgesaFunctionName = AMD_INIT_POST; + AmdParamStruct.AllocationMethod = PreMemHeap; + AmdParamStruct.StdHeader.AltImageBasePtr = 0; + AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; + AmdParamStruct.StdHeader.Func = 0; + AmdParamStruct.StdHeader.ImageBasePtr = 0; + + AmdCreateStruct (&AmdParamStruct); + PostParams = (AMD_POST_PARAMS *)AmdParamStruct.NewStructPtr; + status = AmdInitPost (PostParams); + if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog(PostParams->StdHeader.HeapStatus); + AmdReleaseStruct (&AmdParamStruct); + /* Initialize heap space */ + BiosManagerPtr = (BIOS_HEAP_MANAGER *)GetHeapBase(&AmdParamStruct.StdHeader); + + HeadPtr = (UINT32 *) ((UINT8 *) BiosManagerPtr + sizeof (BIOS_HEAP_MANAGER)); + for (i = 0; i < ((BIOS_HEAP_SIZE/4) - (sizeof (BIOS_HEAP_MANAGER)/4)); i++) + { + *HeadPtr = 0x00000000; + HeadPtr++; + } + BiosManagerPtr->StartOfAllocatedNodes = 0; + BiosManagerPtr->StartOfFreedNodes = 0; + + return (UINT32)status; +} + +UINT32 +agesawrapper_amdinitenv ( + VOID + ) +{ + AGESA_STATUS status; + AMD_INTERFACE_PARAMS AmdParamStruct; + AMD_ENV_PARAMS *EnvParam; + + LibAmdMemFill (&AmdParamStruct, + 0, + sizeof (AMD_INTERFACE_PARAMS), + &(AmdParamStruct.StdHeader)); + + AmdParamStruct.AgesaFunctionName = AMD_INIT_ENV; + AmdParamStruct.AllocationMethod = PostMemDram; + AmdParamStruct.StdHeader.AltImageBasePtr = 0; + AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; + AmdParamStruct.StdHeader.Func = 0; + AmdParamStruct.StdHeader.ImageBasePtr = 0; + status = AmdCreateStruct (&AmdParamStruct); + EnvParam = (AMD_ENV_PARAMS *)AmdParamStruct.NewStructPtr; + + status = AmdInitEnv (EnvParam); + if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog(EnvParam->StdHeader.HeapStatus); + /* Initialize Subordinate Bus Number and Secondary Bus Number + * In platform BIOS this address is allocated by PCI enumeration code + Modify D1F0x18 + */ + + return (UINT32)status; +} + +VOID * +agesawrapper_getlateinitptr ( + int pick + ) +{ + switch (pick) { + case PICK_DMI: + return DmiTable; + case PICK_PSTATE: + return AcpiPstate; + case PICK_SRAT: + return AcpiSrat; + case PICK_SLIT: + return AcpiSlit; + case PICK_WHEA_MCE: + return AcpiWheaMce; + case PICK_WHEA_CMC: + return AcpiWheaCmc; + case PICK_ALIB: + return AcpiAlib; + case PICK_IVRS: + return AcpiIvrs; + default: + return NULL; + } +} + +UINT32 +agesawrapper_amdinitmid ( + VOID + ) +{ + AGESA_STATUS status; + AMD_INTERFACE_PARAMS AmdParamStruct; + + /* Enable MMIO on AMD CPU Address Map Controller */ + agesawrapper_amdinitcpuio (); + + LibAmdMemFill (&AmdParamStruct, + 0, + sizeof (AMD_INTERFACE_PARAMS), + &(AmdParamStruct.StdHeader)); + + AmdParamStruct.AgesaFunctionName = AMD_INIT_MID; + AmdParamStruct.AllocationMethod = PostMemDram; + AmdParamStruct.StdHeader.AltImageBasePtr = 0; + AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; + AmdParamStruct.StdHeader.Func = 0; + AmdParamStruct.StdHeader.ImageBasePtr = 0; + + AmdCreateStruct (&AmdParamStruct); + + ((AMD_MID_PARAMS *)AmdParamStruct.NewStructPtr)->GnbMidConfiguration.iGpuVgaMode = 0;/* 0 iGpuVgaAdapter, 1 iGpuVgaNonAdapter; */ + status = AmdInitMid ((AMD_MID_PARAMS *)AmdParamStruct.NewStructPtr); + if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog(AmdParamStruct.StdHeader.HeapStatus); + AmdReleaseStruct (&AmdParamStruct); + + return (UINT32)status; +} + +UINT32 +agesawrapper_amdinitlate ( + VOID + ) +{ + AGESA_STATUS Status; + AMD_INTERFACE_PARAMS AmdParamStruct; + AMD_LATE_PARAMS *AmdLateParams; + + LibAmdMemFill (&AmdParamStruct, + 0, + sizeof (AMD_INTERFACE_PARAMS), + &(AmdParamStruct.StdHeader)); + + AmdParamStruct.AgesaFunctionName = AMD_INIT_LATE; + AmdParamStruct.AllocationMethod = PostMemDram; + AmdParamStruct.StdHeader.AltImageBasePtr = 0; + AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; + AmdParamStruct.StdHeader.HeapStatus = HEAP_SYSTEM_MEM; + AmdParamStruct.StdHeader.Func = 0; + AmdParamStruct.StdHeader.ImageBasePtr = 0; + + /* NOTE: if not call amdcreatestruct, the initializer(AmdInitLateInitializer) would not be called */ + AmdCreateStruct(&AmdParamStruct); + AmdLateParams = (AMD_LATE_PARAMS *)AmdParamStruct.NewStructPtr; + Status = AmdInitLate(AmdLateParams); + /* CDIT table is not created. */ + if (Status != AGESA_SUCCESS) { + agesawrapper_amdreadeventlog(AmdLateParams->StdHeader.HeapStatus); + ASSERT(Status == AGESA_SUCCESS); + } + + DmiTable = AmdLateParams->DmiTable; + AcpiPstate = AmdLateParams->AcpiPState; + AcpiSrat = AmdLateParams->AcpiSrat; + AcpiSlit = AmdLateParams->AcpiSlit; + + AcpiWheaMce = AmdLateParams->AcpiWheaMce; + AcpiWheaCmc = AmdLateParams->AcpiWheaCmc; + AcpiAlib = AmdLateParams->AcpiAlib; + AcpiIvrs = AmdLateParams->AcpiIvrs; + + printk(BIOS_DEBUG, "DmiTable:%x, AcpiPstatein: %x, AcpiSrat:%x," + "AcpiSlit:%x, Mce:%x, Cmc:%x," + "Alib:%x, AcpiIvrs:%x in %s\n", + (unsigned int)DmiTable, (unsigned int)AcpiPstate, (unsigned int)AcpiSrat, + (unsigned int)AcpiSlit, (unsigned int)AcpiWheaMce, (unsigned int)AcpiWheaCmc, + (unsigned int)AcpiAlib, (unsigned int)AcpiIvrs, __func__); + + /* AmdReleaseStruct (&AmdParamStruct); */ + return (UINT32)Status; +} + +UINT32 +agesawrapper_amdlaterunaptask ( + UINT32 Func, + UINT32 Data, + VOID *ConfigPtr + ) +{ + AGESA_STATUS Status; + AP_EXE_PARAMS ApExeParams; + + LibAmdMemFill (&ApExeParams, + 0, + sizeof (AP_EXE_PARAMS), + &(ApExeParams.StdHeader)); + + ApExeParams.StdHeader.AltImageBasePtr = 0; + ApExeParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; + ApExeParams.StdHeader.Func = 0; + ApExeParams.StdHeader.ImageBasePtr = 0; + ApExeParams.FunctionNumber = Func; + ApExeParams.RelatedDataBlock = ConfigPtr; + + Status = AmdLateRunApTask (&ApExeParams); + if (Status != AGESA_SUCCESS) { + /* agesawrapper_amdreadeventlog(); */ + ASSERT(Status == AGESA_SUCCESS); + } + + return (UINT32)Status; +} + +#if CONFIG_HAVE_ACPI_RESUME + +UINT32 agesawrapper_amdinitresume(VOID) +{ + AGESA_STATUS status; + AMD_INTERFACE_PARAMS AmdParamStruct; + AMD_RESUME_PARAMS *AmdResumeParamsPtr; + S3_DATA_TYPE S3DataType; + + LibAmdMemFill (&AmdParamStruct, + 0, + sizeof (AMD_INTERFACE_PARAMS), + &(AmdParamStruct.StdHeader)); + + AmdParamStruct.AgesaFunctionName = AMD_INIT_RESUME; + AmdParamStruct.AllocationMethod = PreMemHeap; + AmdParamStruct.StdHeader.AltImageBasePtr = 0; + AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; + AmdParamStruct.StdHeader.Func = 0; + AmdParamStruct.StdHeader.ImageBasePtr = 0; + AmdCreateStruct (&AmdParamStruct); + + AmdResumeParamsPtr = (AMD_RESUME_PARAMS *)AmdParamStruct.NewStructPtr; + + AmdResumeParamsPtr->S3DataBlock.NvStorageSize = 0; + AmdResumeParamsPtr->S3DataBlock.VolatileStorageSize = 0; + S3DataType = S3DataTypeNonVolatile; +#if 1 /* TODO: Get the param from Nv storage. */ + OemAgesaGetS3Info (S3DataType, + (u32 *) &AmdResumeParamsPtr->S3DataBlock.NvStorageSize, + (void **) &AmdResumeParamsPtr->S3DataBlock.NvStorage); +#endif + + status = AmdInitResume ((AMD_RESUME_PARAMS *)AmdParamStruct.NewStructPtr); + + if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog(AmdParamStruct.StdHeader.HeapStatus); + AmdReleaseStruct (&AmdParamStruct); + + return (UINT32)status; +} + +#ifndef __PRE_RAM__ + +extern FCH_DATA_BLOCK InitEnvCfgDefault; +STATIC VOID s3_resume_init_data(FCH_DATA_BLOCK *FchParams) +{ + FchParams->Gpp.GppLinkConfig = UserOptions.FchBldCfg->CfgFchGppLinkConfig; + FchParams->Gpp.PortCfg[0].PortPresent = UserOptions.FchBldCfg->CfgFchGppPort0Present; + FchParams->Gpp.PortCfg[1].PortPresent = UserOptions.FchBldCfg->CfgFchGppPort1Present; + FchParams->Gpp.PortCfg[2].PortPresent = UserOptions.FchBldCfg->CfgFchGppPort2Present; + FchParams->Gpp.PortCfg[3].PortPresent = UserOptions.FchBldCfg->CfgFchGppPort3Present; + FchParams->Gpp.PortCfg[0].PortHotPlug = UserOptions.FchBldCfg->CfgFchGppPort0HotPlug; + FchParams->Gpp.PortCfg[1].PortHotPlug = UserOptions.FchBldCfg->CfgFchGppPort1HotPlug; + FchParams->Gpp.PortCfg[2].PortHotPlug = UserOptions.FchBldCfg->CfgFchGppPort2HotPlug; + FchParams->Gpp.PortCfg[3].PortHotPlug = UserOptions.FchBldCfg->CfgFchGppPort3HotPlug; + FchParams->Gpp.GppFunctionEnable = TRUE; /* GppEnable */ + FchParams->Gpp.GppPhyPllPowerDown = TRUE; + FchParams->Gpp.GppDynamicPowerSaving = TRUE; + FchParams->Gpp.UmiPhyPllPowerDown = TRUE; + FchParams->Gpp.NewGppAlgorithm = TRUE; + FchParams->Gpp.GppPortMinPollingTime = 40; + + FchParams->Spi.SpiSpeed = 2; + FchParams->Ir.IrConfig = 3; + + FchParams->HwAcpi.Smbus0BaseAddress = UserOptions.FchBldCfg->CfgSmbus0BaseAddress; + FchParams->HwAcpi.Smbus1BaseAddress = UserOptions.FchBldCfg->CfgSmbus1BaseAddress; + FchParams->HwAcpi.SioPmeBaseAddress = UserOptions.FchBldCfg->CfgSioPmeBaseAddress; + FchParams->HwAcpi.AcpiPm1EvtBlkAddr = UserOptions.FchBldCfg->CfgAcpiPm1EvtBlkAddr; + FchParams->HwAcpi.AcpiPm1CntBlkAddr = UserOptions.FchBldCfg->CfgAcpiPm1CntBlkAddr; + FchParams->HwAcpi.AcpiPmTmrBlkAddr = UserOptions.FchBldCfg->CfgAcpiPmTmrBlkAddr; + FchParams->HwAcpi.CpuControlBlkAddr = UserOptions.FchBldCfg->CfgCpuControlBlkAddr; + FchParams->HwAcpi.AcpiGpe0BlkAddr = UserOptions.FchBldCfg->CfgAcpiGpe0BlkAddr; + FchParams->HwAcpi.SmiCmdPortAddr = UserOptions.FchBldCfg->CfgSmiCmdPortAddr; + FchParams->HwAcpi.AcpiPmaCntBlkAddr = UserOptions.FchBldCfg->CfgAcpiPmaCntBlkAddr; + FchParams->HwAcpi.WatchDogTimerBase = UserOptions.FchBldCfg->CfgWatchDogTimerBase; + FchParams->Sata.SataRaid5Ssid = UserOptions.FchBldCfg->CfgSataRaid5Ssid; + FchParams->Sata.SataRaidSsid = UserOptions.FchBldCfg->CfgSataRaidSsid; + FchParams->Sata.SataAhciSsid = UserOptions.FchBldCfg->CfgSataAhciSsid; + FchParams->Sata.SataIdeSsid = UserOptions.FchBldCfg->CfgSataIdeSsid; + FchParams->Gec.GecShadowRomBase = UserOptions.FchBldCfg->CfgGecShadowRomBase; + FchParams->Spi.RomBaseAddress = UserOptions.FchBldCfg->CfgSpiRomBaseAddress; + FchParams->Sd.SdSsid = UserOptions.FchBldCfg->CfgSdSsid; + FchParams->Spi.LpcSsid = UserOptions.FchBldCfg->CfgLpcSsid; + FchParams->Hpet.HpetBase = UserOptions.FchBldCfg->CfgHpetBaseAddress; + FchParams->Azalia.AzaliaSsid = UserOptions.FchBldCfg->CfgAzaliaSsid; + FchParams->Smbus.SmbusSsid = UserOptions.FchBldCfg->CfgSmbusSsid; + FchParams->Ide.IdeSsid = UserOptions.FchBldCfg->CfgIdeSsid; + FchParams->Usb.EhciSsid = UserOptions.FchBldCfg->CfgEhciSsid; + FchParams->Usb.OhciSsid = UserOptions.FchBldCfg->CfgOhciSsid; + FchParams->Usb.XhciSsid = UserOptions.FchBldCfg->CfgXhciSsid; + FchParams->Ir.IrPinControl = UserOptions.FchBldCfg->CfgFchIrPinControl; + FchParams->Sd.SdClockControl = UserOptions.FchBldCfg->CfgFchSdClockControl; +} + +UINT32 agesawrapper_fchs3earlyrestore (VOID) +{ + AGESA_STATUS status = AGESA_SUCCESS; + + FCH_DATA_BLOCK FchParams; + AMD_CONFIG_PARAMS StdHeader; + + StdHeader.HeapStatus = HEAP_SYSTEM_MEM; + StdHeader.HeapBasePtr = GetHeapBase(&StdHeader) + 0x10; + StdHeader.AltImageBasePtr = 0; + StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; + StdHeader.Func = 0; + StdHeader.ImageBasePtr = 0; + + FchParams = InitEnvCfgDefault; + FchParams.StdHeader = &StdHeader; + s3_resume_init_data(&FchParams); + + FchInitS3EarlyRestore(&FchParams); + + return status; +} +#endif + +UINT32 agesawrapper_amds3laterestore (VOID) +{ + AGESA_STATUS Status; + AMD_INTERFACE_PARAMS AmdInterfaceParams; + AMD_S3LATE_PARAMS AmdS3LateParams; + AMD_S3LATE_PARAMS *AmdS3LateParamsPtr; + S3_DATA_TYPE S3DataType; + + agesawrapper_amdinitcpuio(); + LibAmdMemFill (&AmdS3LateParams, + 0, + sizeof (AMD_S3LATE_PARAMS), + &(AmdS3LateParams.StdHeader)); + AmdInterfaceParams.StdHeader.ImageBasePtr = 0; + AmdInterfaceParams.AllocationMethod = ByHost; + AmdInterfaceParams.AgesaFunctionName = AMD_S3LATE_RESTORE; + AmdInterfaceParams.NewStructPtr = &AmdS3LateParams; + AmdInterfaceParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; + AmdS3LateParamsPtr = &AmdS3LateParams; + AmdInterfaceParams.NewStructSize = sizeof (AMD_S3LATE_PARAMS); + + AmdCreateStruct (&AmdInterfaceParams); + + AmdS3LateParamsPtr->S3DataBlock.VolatileStorageSize = 0; + S3DataType = S3DataTypeVolatile; + +#if 1 /* TODO:Get params from Volatile storage. */ + OemAgesaGetS3Info (S3DataType, + (u32 *) &AmdS3LateParamsPtr->S3DataBlock.VolatileStorageSize, + (void **) &AmdS3LateParamsPtr->S3DataBlock.VolatileStorage); +#endif + + Status = AmdS3LateRestore (AmdS3LateParamsPtr); + if (Status != AGESA_SUCCESS) { + agesawrapper_amdreadeventlog(AmdInterfaceParams.StdHeader.HeapStatus); + ASSERT(Status == AGESA_SUCCESS); + } + + return (UINT32)Status; +} + +#ifndef __PRE_RAM__ + +extern UINT8 picr_data[0x54], intr_data[0x54]; + +UINT32 agesawrapper_fchs3laterestore (VOID) +{ + AGESA_STATUS status = AGESA_SUCCESS; + + FCH_DATA_BLOCK FchParams; + AMD_CONFIG_PARAMS StdHeader; + UINT8 byte; + + StdHeader.HeapStatus = HEAP_SYSTEM_MEM; + StdHeader.HeapBasePtr = GetHeapBase(&StdHeader) + 0x10; + StdHeader.AltImageBasePtr = 0; + StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; + StdHeader.Func = 0; + StdHeader.ImageBasePtr = 0; + + FchParams = InitEnvCfgDefault; + FchParams.StdHeader = &StdHeader; + s3_resume_init_data(&FchParams); + FchInitS3LateRestore(&FchParams); + /* PIC IRQ routine */ + for (byte = 0x0; byte < sizeof(picr_data); byte ++) { + outb(byte, 0xC00); + outb(picr_data[byte], 0xC01); + } + + /* APIC IRQ routine */ + for (byte = 0x0; byte < sizeof(intr_data); byte ++) { + outb(byte | 0x80, 0xC00); + outb(intr_data[byte], 0xC01); + } + + return status; +} +#endif + +#ifndef __PRE_RAM__ + +UINT32 agesawrapper_amdS3Save(VOID) +{ + AGESA_STATUS Status; + AMD_S3SAVE_PARAMS *AmdS3SaveParamsPtr; + AMD_INTERFACE_PARAMS AmdInterfaceParams; + S3_DATA_TYPE S3DataType; + + LibAmdMemFill (&AmdInterfaceParams, + 0, + sizeof (AMD_INTERFACE_PARAMS), + &(AmdInterfaceParams.StdHeader)); + + AmdInterfaceParams.StdHeader.ImageBasePtr = 0; + AmdInterfaceParams.StdHeader.HeapStatus = HEAP_SYSTEM_MEM; + AmdInterfaceParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; + AmdInterfaceParams.AllocationMethod = PostMemDram; + AmdInterfaceParams.AgesaFunctionName = AMD_S3_SAVE; + AmdInterfaceParams.StdHeader.AltImageBasePtr = 0; + AmdInterfaceParams.StdHeader.Func = 0; + + AmdCreateStruct(&AmdInterfaceParams); + AmdS3SaveParamsPtr = (AMD_S3SAVE_PARAMS *)AmdInterfaceParams.NewStructPtr; + AmdS3SaveParamsPtr->StdHeader = AmdInterfaceParams.StdHeader; + + Status = AmdS3Save(AmdS3SaveParamsPtr); + if (Status != AGESA_SUCCESS) { + agesawrapper_amdreadeventlog(AmdInterfaceParams.StdHeader.HeapStatus); + ASSERT(Status == AGESA_SUCCESS); + } + + S3DataType = S3DataTypeNonVolatile; + printk(BIOS_DEBUG, "NvStorageSize=%x, NvStorage=%x\n", + (unsigned int)AmdS3SaveParamsPtr->S3DataBlock.NvStorageSize, + (unsigned int)AmdS3SaveParamsPtr->S3DataBlock.NvStorage); +#if 1 /* TODO: Save the params to NvStorage */ + Status = OemAgesaSaveS3Info ( + S3DataType, + AmdS3SaveParamsPtr->S3DataBlock.NvStorageSize, + AmdS3SaveParamsPtr->S3DataBlock.NvStorage); +#endif + printk(BIOS_DEBUG, "VolatileStorageSize=%x, VolatileStorage=%x\n", + (unsigned int)AmdS3SaveParamsPtr->S3DataBlock.VolatileStorageSize, + (unsigned int)AmdS3SaveParamsPtr->S3DataBlock.VolatileStorage); + + if (AmdS3SaveParamsPtr->S3DataBlock.VolatileStorageSize != 0) { + S3DataType = S3DataTypeVolatile; + +#if 1 /* TODO: Save the params to VolatileStorage */ + Status = OemAgesaSaveS3Info ( + S3DataType, + AmdS3SaveParamsPtr->S3DataBlock.VolatileStorageSize, + AmdS3SaveParamsPtr->S3DataBlock.VolatileStorage + ); +#endif + } + OemAgesaSaveMtrr(); + + AmdReleaseStruct (&AmdInterfaceParams); + + return (UINT32)Status; +} + +#endif /* #ifndef __PRE_RAM__ */ +#endif /* CONFIG_HAVE_ACPI_RESUME */ + +UINT32 +agesawrapper_amdreadeventlog ( + UINT8 HeapStatus + ) +{ + AGESA_STATUS Status; + EVENT_PARAMS AmdEventParams; + + LibAmdMemFill (&AmdEventParams, + 0, + sizeof (EVENT_PARAMS), + &(AmdEventParams.StdHeader)); + + AmdEventParams.StdHeader.AltImageBasePtr = 0; + AmdEventParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; + AmdEventParams.StdHeader.Func = 0; + AmdEventParams.StdHeader.ImageBasePtr = 0; + AmdEventParams.StdHeader.HeapStatus = HeapStatus; + Status = AmdReadEventLog (&AmdEventParams); + while (AmdEventParams.EventClass != 0) { + printk(BIOS_DEBUG,"\nEventLog: EventClass = %x, EventInfo = %x.\n", (unsigned int)AmdEventParams.EventClass,(unsigned int)AmdEventParams.EventInfo); + printk(BIOS_DEBUG," Param1 = %x, Param2 = %x.\n",(unsigned int)AmdEventParams.DataParam1, (unsigned int)AmdEventParams.DataParam2); + printk(BIOS_DEBUG," Param3 = %x, Param4 = %x.\n",(unsigned int)AmdEventParams.DataParam3, (unsigned int)AmdEventParams.DataParam4); + Status = AmdReadEventLog (&AmdEventParams); + } + + return (UINT32)Status; +} diff --git a/src/mainboard/asus/f2a85-m/agesawrapper.h b/src/mainboard/asus/f2a85-m/agesawrapper.h new file mode 100644 index 0000000..5007510 --- /dev/null +++ b/src/mainboard/asus/f2a85-m/agesawrapper.h @@ -0,0 +1,97 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ + +#ifndef _AGESAWRAPPER_H_ +#define _AGESAWRAPPER_H_ + +#include <stdint.h> +#include "Porting.h" +#include "AGESA.h" + +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ +/* Define AMD Ontario APPU SSID/SVID */ +#define AMD_APU_SVID 0x1022 +#define AMD_APU_SSID 0x1234 +#define PCIE_BASE_ADDRESS CONFIG_MMCONF_BASE_ADDRESS + +enum { + PICK_DMI, /* DMI Interface */ + PICK_PSTATE, /* Acpi Pstate SSDT Table */ + PICK_SRAT, /* SRAT Table */ + PICK_SLIT, /* SLIT Table */ + PICK_WHEA_MCE, /* WHEA MCE table */ + PICK_WHEA_CMC, /* WHEA CMV table */ + PICK_ALIB, /* SACPI SSDT table with ALIB implementation */ + PICK_IVRS, /* IOMMU ACPI IVRS(I/O Virtualization Reporting Structure) table */ +}; + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + +typedef struct { + UINT32 CalloutName; + AGESA_STATUS (*CalloutPtr) (UINT32 Func, UINT32 Data, VOID* ConfigPtr); +} BIOS_CALLOUT_STRUCT; + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * E X P O R T E D F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + +/*--------------------------------------------------------------------------------------- + * L O C A L F U N C T I O N S + *--------------------------------------------------------------------------------------- + */ + +UINT32 agesawrapper_amdinitreset (void); +UINT32 agesawrapper_amdinitearly (void); +UINT32 agesawrapper_amdinitenv (void); +UINT32 agesawrapper_amdinitlate (void); +UINT32 agesawrapper_amdinitpost (void); +UINT32 agesawrapper_amdinitmid (void); +UINT32 agesawrapper_amdreadeventlog (UINT8 HeapStatus); +UINT32 agesawrapper_amdinitmmio (void); +UINT32 agesawrapper_amdinitcpuio (void); +void *agesawrapper_getlateinitptr (int pick); +UINT32 agesawrapper_amdlaterunaptask (UINT32 Func, UINT32 Data, void *ConfigPtr); +UINT32 agesawrapper_amdS3Save(VOID); +UINT32 agesawrapper_amdinitresume(VOID); +UINT32 agesawrapper_amds3laterestore (VOID); + +UINT32 agesawrapper_fchs3earlyrestore (VOID); +UINT32 agesawrapper_fchs3laterestore (VOID); + +UINT32 GetHeapBase(AMD_CONFIG_PARAMS *StdHeader); + +#endif diff --git a/src/mainboard/asus/f2a85-m/buildOpts.c b/src/mainboard/asus/f2a85-m/buildOpts.c new file mode 100644 index 0000000..7f893f9 --- /dev/null +++ b/src/mainboard/asus/f2a85-m/buildOpts.c @@ -0,0 +1,517 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/** + * @file + * + * AMD User options selection for a Brazos platform solution system + * + * This file is placed in the user's platform directory and contains the + * build option selections desired for that platform. + * + * For Information about this file, see @ref platforminstall. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: Core + * @e \$Revision: 23714 $ @e \$Date: 2009-12-09 17:28:37 -0600 (Wed, 09 Dec 2009) $ + */ + +#include "AGESA.h" +//#include "CommonReturns.h" +#include "Filecode.h" +#define FILECODE PLATFORM_SPECIFIC_OPTIONS_FILECODE + +/* Select the cpu family. */ +#define INSTALL_FAMILY_10_SUPPORT FALSE +#define INSTALL_FAMILY_12_SUPPORT FALSE +#define INSTALL_FAMILY_14_SUPPORT FALSE +#define INSTALL_FAMILY_15_MODEL_1x_SUPPORT TRUE + +/* Select the cpu socket type. */ +#define INSTALL_G34_SOCKET_SUPPORT FALSE +#define INSTALL_C32_SOCKET_SUPPORT FALSE +#define INSTALL_S1G3_SOCKET_SUPPORT FALSE +#define INSTALL_S1G4_SOCKET_SUPPORT FALSE +#define INSTALL_ASB2_SOCKET_SUPPORT FALSE +#define INSTALL_FS1_SOCKET_SUPPORT FALSE +#define INSTALL_FM1_SOCKET_SUPPORT FALSE +#define INSTALL_FP2_SOCKET_SUPPORT FALSE +#define INSTALL_FT1_SOCKET_SUPPORT FALSE +#define INSTALL_AM3_SOCKET_SUPPORT FALSE + +#define INSTALL_FM2_SOCKET_SUPPORT TRUE + +//#define BLDOPT_REMOVE_UDIMMS_SUPPORT TRUE +#define BLDOPT_REMOVE_SODIMMS_SUPPORT TRUE +#define BLDOPT_REMOVE_RDIMMS_SUPPORT TRUE +#define BLDOPT_REMOVE_LRDIMMS_SUPPORT TRUE +#define BLDOPT_REMOVE_ECC_SUPPORT TRUE +//#define BLDOPT_REMOVE_BANK_INTERLEAVE TRUE +//#define BLDOPT_REMOVE_DCT_INTERLEAVE TRUE +#define BLDOPT_REMOVE_NODE_INTERLEAVE TRUE +#define BLDOPT_REMOVE_PARALLEL_TRAINING TRUE +#define BLDOPT_REMOVE_ONLINE_SPARE_SUPPORT TRUE +//#define BLDOPT_REMOVE_MEM_RESTORE_SUPPORT TRUE +#define BLDOPT_REMOVE_MULTISOCKET_SUPPORT TRUE +//#define BLDOPT_REMOVE_ACPI_PSTATES FALSE +#define BLDOPT_REMOVE_SRAT FALSE //TRUE +#define BLDOPT_REMOVE_SLIT FALSE //TRUE +#define BLDOPT_REMOVE_WHEA FALSE //TRUE +#define BLDOPT_REMOVE_CRAT TRUE +//#define BLDOPT_REMOVE_DMI FALSE //TRUE +//#define BLDOPT_REMOVE_EARLY_SAMPLES FALSE +//#define BLDCFG_REMOVE_ACPI_PSTATES_PPC TRUE +//#define BLDCFG_REMOVE_ACPI_PSTATES_PCT TRUE +//#define BLDCFG_REMOVE_ACPI_PSTATES_PSD TRUE +//#define BLDCFG_REMOVE_ACPI_PSTATES_PSS TRUE +//#define BLDCFG_REMOVE_ACPI_PSTATES_XPSS TRUE + +//This element selects whether P-States should be forced to be independent, +// as reported by the ACPI _PSD object. For single-link processors, +// setting TRUE for OS to support this feature. + +//#define BLDCFG_FORCE_INDEPENDENT_PSD_OBJECT TRUE + +#define BLDCFG_PCI_MMIO_BASE CONFIG_MMCONF_BASE_ADDRESS +#define BLDCFG_PCI_MMIO_SIZE CONFIG_MMCONF_BUS_NUMBER +/* Build configuration values here. + */ +#define BLDCFG_VRM_CURRENT_LIMIT 90000 +#define BLDCFG_VRM_LOW_POWER_THRESHOLD 0 +#define BLDCFG_VRM_MAXIMUM_CURRENT_LIMIT 0 +#define BLDCFG_PLAT_NUM_IO_APICS 3 +#define BLDCFG_CORE_LEVELING_MODE CORE_LEVEL_LOWEST +#define BLDCFG_MEM_INIT_PSTATE 0 + +#define BLDCFG_AMD_PLATFORM_TYPE AMD_PLATFORM_MOBILE + +#define BLDCFG_MEMORY_BUS_FREQUENCY_LIMIT DDR1866_FREQUENCY +#define BLDCFG_MEMORY_MODE_UNGANGED TRUE +#define BLDCFG_MEMORY_QUAD_RANK_CAPABLE TRUE +#define BLDCFG_MEMORY_QUADRANK_TYPE QUADRANK_UNBUFFERED +#define BLDCFG_MEMORY_RDIMM_CAPABLE FALSE +#define BLDCFG_MEMORY_UDIMM_CAPABLE TRUE +#define BLDCFG_MEMORY_SODIMM_CAPABLE FALSE +#define BLDCFG_MEMORY_ENABLE_BANK_INTERLEAVING TRUE +#define BLDCFG_MEMORY_ENABLE_NODE_INTERLEAVING FALSE +#define BLDCFG_MEMORY_CHANNEL_INTERLEAVING TRUE +#define BLDCFG_MEMORY_POWER_DOWN TRUE +#define BLDCFG_POWER_DOWN_MODE POWER_DOWN_BY_CHIP_SELECT +#define BLDCFG_ONLINE_SPARE FALSE +#define BLDCFG_BANK_SWIZZLE TRUE +#define BLDCFG_TIMING_MODE_SELECT TIMING_MODE_AUTO +#define BLDCFG_MEMORY_CLOCK_SELECT DDR1600_FREQUENCY +#define BLDCFG_DQS_TRAINING_CONTROL TRUE +#define BLDCFG_IGNORE_SPD_CHECKSUM FALSE +#define BLDCFG_USE_BURST_MODE FALSE +#define BLDCFG_MEMORY_ALL_CLOCKS_ON FALSE +#define BLDCFG_ENABLE_ECC_FEATURE FALSE +#define BLDCFG_ECC_REDIRECTION FALSE +#define BLDCFG_SCRUB_DRAM_RATE 0 +#define BLDCFG_SCRUB_L2_RATE 0 +#define BLDCFG_SCRUB_L3_RATE 0 +#define BLDCFG_SCRUB_IC_RATE 0 +#define BLDCFG_SCRUB_DC_RATE 0 +#define BLDCFG_ECC_SYMBOL_SIZE 4 +#define BLDCFG_HEAP_DRAM_ADDRESS 0xB0000 +#define BLDCFG_ECC_SYNC_FLOOD FALSE +#define BLDCFG_VRM_HIGH_SPEED_ENABLE TRUE +#define BLDCFG_1GB_ALIGN FALSE +#define BLDCFG_VRM_HIGH_SPEED_ENABLE TRUE +#define BLDCFG_PCIE_REFCLK_SPREAD_SPECTRUM 36 // PCIE Spread Spectrum default value 0.36% +#define BLDCFG_PLATFORM_CSTATE_IO_BASE_ADDRESS 0x1770 + +#define BLDOPT_REMOVE_ALIB FALSE +#define BLDCFG_PLATFORM_CPB_MODE CpbModeDisabled +#define BLDCFG_PROCESSOR_SCOPE_NAME0 'P' +#define BLDCFG_PROCESSOR_SCOPE_NAME1 '0' +#define BLDCFG_PLATFORM_CSTATE_MODE CStateModeC6 + +#define BLDCFG_CFG_LCD_BACK_LIGHT_CONTROL 200 +#define BLDCFG_CFG_ABM_SUPPORT 0 + +//#define BLDCFG_PLATFORM_CSTATE_OPDATA 0x1770 + +// Specify the default values for the VRM controlling the VDDNB plane. +// If not specified, the values used for the core VRM will be applied +//#define BLDCFG_VRM_NB_CURRENT_LIMIT 0 // Not currently used on Trinity +//#define BLDCFG_VRM_NB_LOW_POWER_THRESHOLD 1 // Zero - disable NBPSI_L, Non-zero - enable NBPSI_L +//#define BLDCFG_VRM_NB_SLEW_RATE 5000 // Used in calculating the VSRampSlamTime +//#define BLDCFG_VRM_NB_ADDITIONAL_DELAY 0 // Not currently used on Trinity +//#define BLDCFG_VRM_NB_HIGH_SPEED_ENABLE 0 // Not currently used on Trinity +//#define BLDCFG_VRM_NB_INRUSH_CURRENT_LIMIT 0 // Not currently used on Trinity + +#define BLDCFG_VRM_NB_CURRENT_LIMIT 60000 + +#define BLDCFG_LVDS_POWER_ON_SEQ_VARY_BL_TO_BLON 3 +#define BLDCFG_LVDS_POWER_ON_SEQ_BLON_TO_VARY_BL 3 + +#if CONFIG_GFXUMA +#define BLDCFG_UMA_ALIGNMENT UMA_4MB_ALIGNED +#define BLDCFG_UMA_ALLOCATION_MODE UMA_SPECIFIED +//#define BLDCFG_UMA_ALLOCATION_SIZE 0x1000//0x1800//0x1000 /* (1000 << 16) = 256M*/ +#define BLDCFG_UMA_ALLOCATION_SIZE 0x2000//512M +#define BLDCFG_UMA_ABOVE4G_SUPPORT FALSE +#endif + +#define BLDCFG_IOMMU_SUPPORT FALSE + +#define BLDCFG_CFG_GNB_HD_AUDIO TRUE +//#define BLDCFG_IGPU_SUBSYSTEM_ID OEM_IGPU_SSID +//#define BLDCFG_IGPU_HD_AUDIO_SUBSYSTEM_ID OEM_IGPU_HD_AUDIO_SSID +//#define BLFCFG_APU_PCIE_PORTS_SUBSYSTEM_ID OEM_APU_PCIE_PORTS_SSID + +/* Process the options... + * This file include MUST occur AFTER the user option selection settings + */ +#define AGESA_ENTRY_INIT_RESET TRUE +#define AGESA_ENTRY_INIT_RECOVERY FALSE +#define AGESA_ENTRY_INIT_EARLY TRUE +#define AGESA_ENTRY_INIT_POST TRUE +#define AGESA_ENTRY_INIT_ENV TRUE +#define AGESA_ENTRY_INIT_MID TRUE +#define AGESA_ENTRY_INIT_LATE TRUE +#define AGESA_ENTRY_INIT_S3SAVE TRUE +#define AGESA_ENTRY_INIT_RESUME TRUE //TRUE +#define AGESA_ENTRY_INIT_LATE_RESTORE TRUE +#define AGESA_ENTRY_INIT_GENERAL_SERVICES TRUE +/* + * Customized OEM build configurations for FCH component + */ +// #define BLDCFG_SMBUS0_BASE_ADDRESS 0xB00 +// #define BLDCFG_SMBUS1_BASE_ADDRESS 0xB20 +// #define BLDCFG_SIO_PME_BASE_ADDRESS 0xE00 +// #define BLDCFG_ACPI_PM1_EVT_BLOCK_ADDRESS 0x400 +// #define BLDCFG_ACPI_PM1_CNT_BLOCK_ADDRESS 0x404 +// #define BLDCFG_ACPI_PM_TMR_BLOCK_ADDRESS 0x408 +// #define BLDCFG_ACPI_CPU_CNT_BLOCK_ADDRESS 0x410 +// #define BLDCFG_ACPI_GPE0_BLOCK_ADDRESS 0x420 +// #define BLDCFG_SPI_BASE_ADDRESS 0xFEC10000 +// #define BLDCFG_WATCHDOG_TIMER_BASE 0xFEC00000 +// #define BLDCFG_HPET_BASE_ADDRESS 0xFED00000 +// #define BLDCFG_SMI_CMD_PORT_ADDRESS 0xB0 +// #define BLDCFG_ACPI_PMA_BLK_ADDRESS 0xFE00 +// #define BLDCFG_ROM_BASE_ADDRESS 0xFED61000 +// #define BLDCFG_AZALIA_SSID 0x780D1022 +// #define BLDCFG_SMBUS_SSID 0x780B1022 +// #define BLDCFG_IDE_SSID 0x780C1022 +// #define BLDCFG_SATA_AHCI_SSID 0x78011022 +// #define BLDCFG_SATA_IDE_SSID 0x78001022 +// #define BLDCFG_SATA_RAID5_SSID 0x78031022 +// #define BLDCFG_SATA_RAID_SSID 0x78021022 +// #define BLDCFG_EHCI_SSID 0x78081022 +// #define BLDCFG_OHCI_SSID 0x78071022 +// #define BLDCFG_LPC_SSID 0x780E1022 +// #define BLDCFG_SD_SSID 0x78061022 +// #define BLDCFG_XHCI_SSID 0x78121022 +// #define BLDCFG_FCH_PORT80_BEHIND_PCIB FALSE +// #define BLDCFG_FCH_ENABLE_ACPI_SLEEP_TRAP TRUE +// #define BLDCFG_FCH_GPP_LINK_CONFIG PortA4 +// #define BLDCFG_FCH_GPP_PORT0_PRESENT FALSE +// #define BLDCFG_FCH_GPP_PORT1_PRESENT FALSE +// #define BLDCFG_FCH_GPP_PORT2_PRESENT FALSE +// #define BLDCFG_FCH_GPP_PORT3_PRESENT FALSE +// #define BLDCFG_FCH_GPP_PORT0_HOTPLUG FALSE +// #define BLDCFG_FCH_GPP_PORT1_HOTPLUG FALSE +// #define BLDCFG_FCH_GPP_PORT2_HOTPLUG FALSE +// #define BLDCFG_FCH_GPP_PORT3_HOTPLUG FALSE + +CONST AP_MTRR_SETTINGS ROMDATA TrinityApMtrrSettingsList[] = +{ + { AMD_AP_MTRR_FIX64k_00000, 0x1E1E1E1E1E1E1E1E }, + { AMD_AP_MTRR_FIX16k_80000, 0x1E1E1E1E1E1E1E1E }, + { AMD_AP_MTRR_FIX16k_A0000, 0x0000000000000000 }, + { AMD_AP_MTRR_FIX4k_C0000, 0x0000000000000000 }, + { AMD_AP_MTRR_FIX4k_C8000, 0x0000000000000000 }, + { AMD_AP_MTRR_FIX4k_D0000, 0x0000000000000000 }, + { AMD_AP_MTRR_FIX4k_D8000, 0x0000000000000000 }, + { AMD_AP_MTRR_FIX4k_E0000, 0x1818181818181818 }, + { AMD_AP_MTRR_FIX4k_E8000, 0x1818181818181818 }, + { AMD_AP_MTRR_FIX4k_F0000, 0x1818181818181818 }, + { AMD_AP_MTRR_FIX4k_F8000, 0x1818181818181818 }, + { CPU_LIST_TERMINAL } +}; + +#define BLDCFG_AP_MTRR_SETTINGS_LIST &TrinityApMtrrSettingsList + +//#include "VirgoInstall.h" + +/* Include the files that instantiate the configuration definitions. */ +#include "cpuRegisters.h" +#include "cpuFamRegisters.h" +#include "cpuFamilyTranslation.h" +#include "AdvancedApi.h" +#include "heapManager.h" +#include "CreateStruct.h" +#include "cpuFeatures.h" +#include "Table.h" +#include "CommonReturns.h" +#include "cpuEarlyInit.h" +#include "cpuLateInit.h" +#include "GnbInterface.h" + + // This is the delivery package title, "BrazosPI" + // This string MUST be exactly 8 characters long +#define AGESA_PACKAGE_STRING {'c', 'b', '_', 'A', 'g', 'e', 's', 'a'} + + // This is the release version number of the AGESA component + // This string MUST be exactly 12 characters long +#define AGESA_VERSION_STRING {'V', '0', '.', '0', '.', '0', '.', '1', ' ', ' ', ' ', ' '} + +/* MEMORY_BUS_SPEED */ +#define DDR400_FREQUENCY 200 ///< DDR 400 +#define DDR533_FREQUENCY 266 ///< DDR 533 +#define DDR667_FREQUENCY 333 ///< DDR 667 +#define DDR800_FREQUENCY 400 ///< DDR 800 +#define DDR1066_FREQUENCY 533 ///< DDR 1066 +#define DDR1333_FREQUENCY 667 ///< DDR 1333 +#define DDR1600_FREQUENCY 800 ///< DDR 1600 +#define DDR1866_FREQUENCY 933 ///< DDR 1866 +#define DDR2100_FREQUENCY 1050 ///< DDR 2100 +#define DDR2133_FREQUENCY 1066 ///< DDR 2133 +#define DDR2400_FREQUENCY 1200 ///< DDR 2400 +#define UNSUPPORTED_DDR_FREQUENCY 1201 ///< Highest limit of DDR frequency + +/* QUANDRANK_TYPE*/ +#define QUADRANK_REGISTERED 0 ///< Quadrank registered DIMM +#define QUADRANK_UNBUFFERED 1 ///< Quadrank unbuffered DIMM + +/* USER_MEMORY_TIMING_MODE */ +#define TIMING_MODE_AUTO 0 ///< Use best rate possible +#define TIMING_MODE_LIMITED 1 ///< Set user top limit +#define TIMING_MODE_SPECIFIC 2 ///< Set user specified speed + +/* POWER_DOWN_MODE */ +#define POWER_DOWN_BY_CHANNEL 0 ///< Channel power down mode +#define POWER_DOWN_BY_CHIP_SELECT 1 ///< Chip select power down mode + +/* + * Agesa optional capabilities selection. + * Uncomment and mark FALSE those features you wish to include in the build. + * Comment out or mark TRUE those features you want to REMOVE from the build. + */ + +#define DFLT_SMBUS0_BASE_ADDRESS 0xB00 +#define DFLT_SMBUS1_BASE_ADDRESS 0xB20 +#define DFLT_SIO_PME_BASE_ADDRESS 0xE00 +#define DFLT_ACPI_PM1_EVT_BLOCK_ADDRESS 0x800 +#define DFLT_ACPI_PM1_CNT_BLOCK_ADDRESS 0x804 +#define DFLT_ACPI_PM_TMR_BLOCK_ADDRESS 0x808 +#define DFLT_ACPI_CPU_CNT_BLOCK_ADDRESS 0x810 +#define DFLT_ACPI_GPE0_BLOCK_ADDRESS 0x820 +#define DFLT_SPI_BASE_ADDRESS 0xFEC10000 +#define DFLT_WATCHDOG_TIMER_BASE_ADDRESS 0xFEC000F0 +#define DFLT_HPET_BASE_ADDRESS 0xFED00000 +#define DFLT_SMI_CMD_PORT 0xB0 +#define DFLT_ACPI_PMA_CNT_BLK_ADDRESS 0xFE00 +#define DFLT_GEC_BASE_ADDRESS 0xFED61000 +#define DFLT_AZALIA_SSID 0x780D1022 +#define DFLT_SMBUS_SSID 0x780B1022 +#define DFLT_IDE_SSID 0x780C1022 +#define DFLT_SATA_AHCI_SSID 0x78011022 +#define DFLT_SATA_IDE_SSID 0x78001022 +#define DFLT_SATA_RAID5_SSID 0x78031022 +#define DFLT_SATA_RAID_SSID 0x78021022 +#define DFLT_EHCI_SSID 0x78081022 +#define DFLT_OHCI_SSID 0x78071022 +#define DFLT_LPC_SSID 0x780E1022 +#define DFLT_SD_SSID 0x78061022 +#define DFLT_XHCI_SSID 0x78121022 +#define DFLT_FCH_PORT80_BEHIND_PCIB FALSE +#define DFLT_FCH_ENABLE_ACPI_SLEEP_TRAP TRUE +#define DFLT_FCH_GPP_LINK_CONFIG PortA1B1C1D1 +#define DFLT_FCH_GPP_PORT0_PRESENT TRUE +#define DFLT_FCH_GPP_PORT1_PRESENT TRUE +#define DFLT_FCH_GPP_PORT2_PRESENT FALSE +#define DFLT_FCH_GPP_PORT3_PRESENT FALSE +#define DFLT_FCH_GPP_PORT0_HOTPLUG FALSE +#define DFLT_FCH_GPP_PORT1_HOTPLUG FALSE +#define DFLT_FCH_GPP_PORT2_HOTPLUG FALSE +#define DFLT_FCH_GPP_PORT3_HOTPLUG FALSE +//#define BLDCFG_IR_PIN_CONTROL 0x33 +//#define FCH_NO_XHCI_SUPPORT FALSE +GPIO_CONTROL f2a85_m_gpio[] = { +// {183, Function1, PullUpB}, + {-1} +}; +#define BLDCFG_FCH_GPIO_CONTROL_LIST (&f2a85_m_gpio[0]) + +// The following definitions specify the default values for various parameters in which there are +// no clearly defined defaults to be used in the common file. The values below are based on product +// and BKDG content, please consult the AGESA Memory team for consultation. +#define DFLT_SCRUB_DRAM_RATE (0) +#define DFLT_SCRUB_L2_RATE (0) +#define DFLT_SCRUB_L3_RATE (0) +#define DFLT_SCRUB_IC_RATE (0) +#define DFLT_SCRUB_DC_RATE (0) +#define DFLT_MEMORY_QUADRANK_TYPE QUADRANK_UNBUFFERED +#define DFLT_VRM_SLEW_RATE (5000) + +#include "PlatformInstall.h" + +/*---------------------------------------------------------------------------------------- + * CUSTOMER OVERIDES MEMORY TABLE + *---------------------------------------------------------------------------------------- + */ + +/* + * Platform Specific Overriding Table allows IBV/OEM to pass in platform information to AGESA + * (e.g. MemClk routing, the number of DIMM slots per channel,...). If PlatformSpecificTable + * is populated, AGESA will base its settings on the data from the table. Otherwise, it will + * use its default conservative settings. + */ +CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = { + // + // The following macros are supported (use comma to separate macros): + // + // MEMCLK_DIS_MAP(SocketID, ChannelID, MemClkDisBit0CSMap,..., MemClkDisBit7CSMap) + // The MemClk pins are identified based on BKDG definition of Fn2x88[MemClkDis] bitmap. + // AGESA will base on this value to disable unused MemClk to save power. + // Example: + // BKDG definition of Fn2x88[MemClkDis] bitmap for AM3 package is like below: + // Bit AM3/S1g3 pin name + // 0 M[B,A]_CLK_H/L[0] + // 1 M[B,A]_CLK_H/L[1] + // 2 M[B,A]_CLK_H/L[2] + // 3 M[B,A]_CLK_H/L[3] + // 4 M[B,A]_CLK_H/L[4] + // 5 M[B,A]_CLK_H/L[5] + // 6 M[B,A]_CLK_H/L[6] + // 7 M[B,A]_CLK_H/L[7] + // And platform has the following routing: + // CS0 M[B,A]_CLK_H/L[4] + // CS1 M[B,A]_CLK_H/L[2] + // CS2 M[B,A]_CLK_H/L[3] + // CS3 M[B,A]_CLK_H/L[5] + // Then platform can specify the following macro: + // MEMCLK_DIS_MAP(ANY_SOCKET, ANY_CHANNEL, 0x00, 0x00, 0x02, 0x04, 0x01, 0x08, 0x00, 0x00) + // + // CKE_TRI_MAP(SocketID, ChannelID, CKETriBit0CSMap, CKETriBit1CSMap) + // The CKE pins are identified based on BKDG definition of Fn2x9C_0C[CKETri] bitmap. + // AGESA will base on this value to tristate unused CKE to save power. + // + // ODT_TRI_MAP(SocketID, ChannelID, ODTTriBit0CSMap,..., ODTTriBit3CSMap) + // The ODT pins are identified based on BKDG definition of Fn2x9C_0C[ODTTri] bitmap. + // AGESA will base on this value to tristate unused ODT pins to save power. + // + // CS_TRI_MAP(SocketID, ChannelID, CSTriBit0CSMap,..., CSTriBit7CSMap) + // The Chip select pins are identified based on BKDG definition of Fn2x9C_0C[ChipSelTri] bitmap. + // AGESA will base on this value to tristate unused Chip select to save power. + // + // NUMBER_OF_DIMMS_SUPPORTED(SocketID, ChannelID, NumberOfDimmSlotsPerChannel) + // Specifies the number of DIMM slots per channel. + // + // NUMBER_OF_CHIP_SELECTS_SUPPORTED(SocketID, ChannelID, NumberOfChipSelectsPerChannel) + // Specifies the number of Chip selects per channel. + // + // NUMBER_OF_CHANNELS_SUPPORTED(SocketID, NumberOfChannelsPerSocket) + // Specifies the number of channels per socket. + // + // OVERRIDE_DDR_BUS_SPEED(SocketID, ChannelID, USER_MEMORY_TIMING_MODE, MEMORY_BUS_SPEED) + // Specifies DDR bus speed of channel ChannelID on socket SocketID. + // + // DRAM_TECHNOLOGY(SocketID, TECHNOLOGY_TYPE) + // Specifies the DRAM technology type of socket SocketID (DDR2, DDR3,...) + // + // WRITE_LEVELING_SEED(SocketID, ChannelID, DimmID, Byte0Seed, Byte1Seed, Byte2Seed, Byte3Seed, Byte4Seed, Byte5Seed, + // Byte6Seed, Byte7Seed, ByteEccSeed) + // Specifies the write leveling seed for a channel of a socket. + // + // HW_RXEN_SEED(SocketID, ChannelID, DimmID, Byte0Seed, Byte1Seed, Byte2Seed, Byte3Seed, Byte4Seed, Byte5Seed, + // Byte6Seed, Byte7Seed, ByteEccSeed) + // Speicifes the HW RXEN training seed for a channel of a socket + // + + NUMBER_OF_DIMMS_SUPPORTED (ANY_SOCKET, ANY_CHANNEL, 2), + NUMBER_OF_CHANNELS_SUPPORTED (ANY_SOCKET, 2), +/* + TODO: is this OK for DDR3 socket FM2? + MEMCLK_DIS_MAP (ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00), + CKE_TRI_MAP (ANY_SOCKET, ANY_CHANNEL, 0x05, 0x0A), + ODT_TRI_MAP (ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x00, 0x00), + CS_TRI_MAP (ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00), + */ + PSO_END +}; + +/* + * These tables are optional and may be used to adjust memory timing settings + */ +#include "mm.h" +#include "mn.h" + +// Customer table +UINT8 AGESA_MEM_TABLE_TN[][sizeof (MEM_TABLE_ALIAS)] = +{ + // Hardcoded Memory Training Values + + // The following macro should be used to override training values for your platform + // + // DQSACCESS(MTAfterDqsRwPosTrn, MTNodes, MTDcts, MTDIMMs, BFRdDqsDly, MTOverride, 0x00, 0x04, 0x08, 0x0c, 0x10, 0x14, 0x18, 0x1c, 0x20), + // + // NOTE: + // The following training hardcode values are example values that were taken from a tilapia motherboard + // with a particular DIMM configuration. To hardcode your own values, uncomment the appropriate line in + // the table and replace the byte lane values with your own. + // + // ------------------ BYTE LANES ---------------------- + // BL0 BL1 BL2 BL3 BL4 BL5 BL6 Bl7 ECC + // Write Data Timing + // DQSACCESS(MTAfterHwWLTrnP2, MTNode0, MTDct0, MTDIMM0, BFWrDatDly, MTOverride, 0x1D, 0x20, 0x26, 0x2B, 0x37, 0x3A, 0x3e, 0x3F, 0x30),// DCT0, DIMM0 + // DQSACCESS(MTAfterHwWLTrnP2, MTNode0, MTDct0, MTDIMM1, BFWrDatDly, MTOverride, 0x1D, 0x00, 0x06, 0x0B, 0x17, 0x1A, 0x1E, 0x1F, 0x10),// DCT0, DIMM1 + // DQSACCESS(MTAfterHwWLTrnP2, MTNode0, MTDct1, MTDIMM0, BFWrDatDly, MTOverride, 0x18, 0x1D, 0x27, 0x2B, 0x3B, 0x3B, 0x3E, 0x3E, 0x30),// DCT1, DIMM0 + // DQSACCESS(MTAfterHwWLTrnP2, MTNode0, MTDct1, MTDIMM1, BFWrDatDly, MTOverride, 0x18, 0x1D, 0x1C, 0x0B, 0x17, 0x1A, 0x1D, 0x1C, 0x10),// DCT1, DIMM1 + + // DQS Receiver Enable + // DQSACCESS(MTAfterSwRxEnTrn, MTNode0, MTDct0, MTDIMM0, BFRcvEnDly, MTOverride, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00),// DCT0, DIMM0 + // DQSACCESS(MTAfterSwRxEnTrn, MTNode0, MTDct0, MTDIMM1, BFRcvEnDly, MTOverride, 0x7C, 0x7D, 0x7E, 0x81, 0x88, 0x8F, 0x96, 0x9F, 0x84),// DCT0, DIMM1 + // DQSACCESS(MTAfterSwRxEnTrn, MTNode0, MTDct1, MTDIMM0, BFRcvEnDly, MTOverride, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00),// DCT1, DIMM0 + // DQSACCESS(MTAfterSwRxEnTrn, MTNode0, MTDct1, MTDIMM1, BFRcvEnDly, MTOverride, 0x1C, 0x1D, 0x1E, 0x01, 0x08, 0x0F, 0x16, 0x1F, 0x04),// DCT1, DIMM1 + + // Write DQS Delays + // DQSACCESS(MTAfterDqsRwPosTrn, MTNode0, MTDct0, MTDIMM0, BFWrDqsDly, MTOverride, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00),// DCT0, DIMM0 + // DQSACCESS(MTAfterDqsRwPosTrn, MTNode0, MTDct0, MTDIMM1, BFWrDqsDly, MTOverride, 0x06, 0x0D, 0x12, 0x1A, 0x25, 0x28, 0x2C, 0x2C, 0x44),// DCT0, DIMM1 + // DQSACCESS(MTAfterDqsRwPosTrn, MTNode0, MTDct1, MTDIMM0, BFWrDqsDly, MTOverride, 0x07, 0x0E, 0x14, 0x1B, 0x24, 0x29, 0x2B, 0x2C, 0x1F),// DCT1, DIMM0 + // DQSACCESS(MTAfterDqsRwPosTrn, MTNode0, MTDct1, MTDIMM1, BFWrDqsDly, MTOverride, 0x07, 0x0C, 0x14, 0x19, 0x25, 0x28, 0x2B, 0x2B, 0x1A),// DCT1, DIMM1 + + // Read DQS Delays + // DQSACCESS(MTAfterDqsRwPosTrn, MTNode0, MTDct0, MTDIMM0, BFRdDqsDly, MTOverride, 0x10, 0x10, 0x0E, 0x10, 0x10, 0x10, 0x10, 0x0E, 0x10),// DCT0, DIMM0 + // DQSACCESS(MTAfterDqsRwPosTrn, MTNode0, MTDct0, MTDIMM1, BFRdDqsDly, MTOverride, 0x10, 0x10, 0x0E, 0x10, 0x10, 0x10, 0x10, 0x1E, 0x10),// DCT0, DIMM1 + // DQSACCESS(MTAfterDqsRwPosTrn, MTNode0, MTDct1, MTDIMM0, BFRdDqsDly, MTOverride, 0x10, 0x10, 0x0E, 0x10, 0x10, 0x10, 0x10, 0x1E, 0x10),// DCT1, DIMM0 + // DQSACCESS(MTAfterDqsRwPosTrn, MTNode0, MTDct1, MTDIMM1, BFRdDqsDly, MTOverride, 0x10, 0x10, 0x0E, 0x10, 0x10, 0x10, 0x10, 0x1E, 0x10),// DCT1, DIMM1 + //-------------------------------------------------------------------------------------------------------------------------------------------------- + // TABLE END + NBACCESS (MTEnd, 0, 0, 0, 0, 0), // End of Table +}; +UINT8 SizeOfTableTN = sizeof (AGESA_MEM_TABLE_TN) / sizeof (AGESA_MEM_TABLE_TN[0]); + +/* *************************************************************************** + * Optional User code to be included into the AGESA build + * These may be 32-bit call-out routines... + */ +//AGESA_STATUS +//AgesaReadSpd ( +// IN UINTN FcnData, +// IN OUT AGESA_READ_SPD_PARAMS *ReadSpd +// ) +//{ +// /* platform code to read an SPD... */ +// return Status; +//} diff --git a/src/mainboard/asus/f2a85-m/cmos.layout b/src/mainboard/asus/f2a85-m/cmos.layout new file mode 100644 index 0000000..5520564 --- /dev/null +++ b/src/mainboard/asus/f2a85-m/cmos.layout @@ -0,0 +1,114 @@ +#***************************************************************************** +# +# This file is part of the coreboot project. +# +# Copyright (C) 2012 Advanced Micro Devices, Inc. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +#***************************************************************************** + +entries + +#start-bit length config config-ID name +#0 8 r 0 seconds +#8 8 r 0 alarm_seconds +#16 8 r 0 minutes +#24 8 r 0 alarm_minutes +#32 8 r 0 hours +#40 8 r 0 alarm_hours +#48 8 r 0 day_of_week +#56 8 r 0 day_of_month +#64 8 r 0 month +#72 8 r 0 year +#80 4 r 0 rate_select +#84 3 r 0 REF_Clock +#87 1 r 0 UIP +#88 1 r 0 auto_switch_DST +#89 1 r 0 24_hour_mode +#90 1 r 0 binary_values_enable +#91 1 r 0 square-wave_out_enable +#92 1 r 0 update_finished_enable +#93 1 r 0 alarm_interrupt_enable +#94 1 r 0 periodic_interrupt_enable +#95 1 r 0 disable_clock_updates +#96 288 r 0 temporary_filler +0 384 r 0 reserved_memory +384 1 e 4 boot_option +385 1 e 4 last_boot +386 1 e 1 ECC_memory +388 4 r 0 reboot_bits +392 3 e 5 baud_rate +395 1 e 1 hw_scrubber +396 1 e 1 interleave_chip_selects +397 2 e 8 max_mem_clock +399 1 e 2 multi_core +400 1 e 1 power_on_after_fail +412 4 e 6 debug_level +416 4 e 7 boot_first +420 4 e 7 boot_second +424 4 e 7 boot_third +428 4 h 0 boot_index +432 8 h 0 boot_countdown +440 4 e 9 slow_cpu +444 1 e 1 nmi +445 1 e 1 iommu +728 256 h 0 user_data +984 16 h 0 check_sum +# Reserve the extended AMD configuration registers +1000 24 r 0 amd_reserved + +enumerations + +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +5 0 115200 +5 1 57600 +5 2 38400 +5 3 19200 +5 4 9600 +5 5 4800 +5 6 2400 +5 7 1200 +6 6 Notice +6 7 Info +6 8 Debug +6 9 Spew +7 0 Network +7 1 HDD +7 2 Floppy +7 8 Fallback_Network +7 9 Fallback_HDD +7 10 Fallback_Floppy +#7 3 ROM +8 0 400Mhz +8 1 333Mhz +8 2 266Mhz +8 3 200Mhz +9 0 off +9 1 87.5% +9 2 75.0% +9 3 62.5% +9 4 50.0% +9 5 37.5% +9 6 25.0% +9 7 12.5% + +checksums + +checksum 392 983 984 diff --git a/src/mainboard/asus/f2a85-m/devicetree.cb b/src/mainboard/asus/f2a85-m/devicetree.cb new file mode 100644 index 0000000..8272964 --- /dev/null +++ b/src/mainboard/asus/f2a85-m/devicetree.cb @@ -0,0 +1,130 @@ +# +# This file is part of the coreboot project. +# +# Copyright (C) 2012 Advanced Micro Devices, Inc. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +# +chip northbridge/amd/agesa/family15tn/root_complex + + device cpu_cluster 0 on + chip cpu/amd/agesa/family15tn + device lapic 10 on end + end + end + + device domain 0 on + subsystemid 0x1022 0x1410 inherit + chip northbridge/amd/agesa/family15tn # CPU side of HT root complex + + chip northbridge/amd/agesa/family15tn # PCI side of HT root complex + device pci 0.0 on end # Root Complex + device pci 1.0 on end # Internal Graphics P2P bridge 0x99XX + device pci 1.1 on end # Internal Multimedia + device pci 2.0 on end # PCIE SLOT0 x16 blue + device pci 3.0 off end # unused? + device pci 4.0 on end # PCIE 4x black + device pci 5.0 off end # unused? + device pci 6.0 off end # unused? + device pci 7.0 off end # LAN + device pci 8.0 off end # NB/SB Link P2P bridge + end #chip northbridge/amd/agesa/family15tn # PCI side of HT root complex + + chip southbridge/amd/agesa/hudson # it is under NB/SB Link, but on the same pci bus + device pci 10.0 on end # XHCI HC0 + device pci 10.1 on end # XHCI HC1 + device pci 11.0 on end # SATA + device pci 12.0 on end # USB + device pci 12.2 on end # USB + device pci 13.0 on end # USB + device pci 13.2 on end # USB + device pci 14.0 on # SMBUS + chip drivers/generic/generic #dimm 0 + device i2c 50 on end # 7-bit SPD address + end + chip drivers/generic/generic #dimm 1 + device i2c 51 on end # 7-bit SPD address + end + end # SM + device pci 14.1 off end # IDE 0x439c + device pci 14.2 on end # HDA 0x4383 + device pci 14.3 on # LPC 0x439d + chip superio/ite/it8712f + device pnp 2e.0 off # Floppy + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 + end + device pnp 2e.1 on # Com1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.2 off # Com2 + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 2e.3 off # Parallel Port + io 0x60 = 0x378 + irq 0x70 = 7 + end + device pnp 2e.4 off end # EC + device pnp 2e.5 on # Keyboard + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 + end + device pnp 2e.6 off # Mouse + irq 0x70 = 12 + end + device pnp 2e.7 off # GPIO, must be closed for unresolved reason. + end + device pnp 2e.8 off # MIDI + io 0x60 = 0x300 + irq 0x70 = 9 + end + device pnp 2e.9 off # GAME + io 0x60 = 0x220 + end + device pnp 2e.a off end # CIR + end #superio/ite/it8712f + end #device pci 14.3 # LPC + device pci 14.4 on end # PCI 0x4384 # PCI-b conflict with GPIO. + device pci 14.5 on end # USB 2 + device pci 14.6 off end # Gec + device pci 14.7 off end + device pci 15.0 on end # PCIe 0 - onboard PCIe 1x + device pci 15.1 on end # PCIe 1 onboard gigabit + device pci 15.2 off end # unused + device pci 15.3 off end # unused + + register "boot_switch_sata_ide" = "0" # 0: boot from SATA. 1: IDE + register "gpp_configuration" = "4" + end #chip southbridge/amd/hudson + + device pci 18.0 on end + device pci 18.1 on end + device pci 18.2 on end + device pci 18.3 on end + device pci 18.4 on end + device pci 18.5 on end + + register "spdAddrLookup" = " + { + { {0xA0, 0xA4}, {0xA2, 0xA6}, }, // socket 0 - Channel 0 & 1 - 8-bit SPD addresses + { {0x00, 0x00}, {0x00, 0x00}, }, // socket 1 - Channel 0 & 1 - 8-bit SPD addresses + }" + + end #chip northbridge/amd/agesa/family15tn # CPU side of HT root complex + end #domain +end #chip northbridge/amd/agesa/family15tn/root_complex diff --git a/src/mainboard/asus/f2a85-m/dsdt.asl b/src/mainboard/asus/f2a85-m/dsdt.asl new file mode 100644 index 0000000..d9f8fa4 --- /dev/null +++ b/src/mainboard/asus/f2a85-m/dsdt.asl @@ -0,0 +1,1411 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* DefinitionBlock Statement */ +DefinitionBlock ( + "DSDT.AML", /* Output filename */ + "DSDT", /* Signature */ + 0x02, /* DSDT Revision, needs to be 2 for 64bit */ + "ASUS ", /* OEMID */ + "COREBOOT", /* TABLE ID */ + 0x00010001 /* OEM Revision */ + ) +{ /* Start of ASL file */ + /* #include "../../../arch/x86/acpi/debug.asl" */ /* Include global debug methods if needed */ + + /* Data to be patched by the BIOS during POST */ + /* FIXME the patching is not done yet! */ + /* Memory related values */ + Name(LOMH, 0x0) /* Start of unused memory in C0000-E0000 range */ + Name(PBAD, 0x0) /* Address of BIOS area (If TOM2 != 0, Addr >> 16) */ + Name(PBLN, 0x0) /* Length of BIOS area */ + + Name(PCBA, CONFIG_MMCONF_BASE_ADDRESS) /* Base address of PCIe config space */ + Name(PCLN, Multiply(0x100000, CONFIG_MMCONF_BUS_NUMBER)) /* Length of PCIe config space, 1MB each bus */ + Name(HPBA, 0xFED00000) /* Base address of HPET table */ + + Name(SSFG, 0x0D) /* S1 support: bit 0, S2 Support: bit 1, etc. S0 & S5 assumed */ + + /* USB overcurrent mapping pins. */ + Name(UOM0, 0) + Name(UOM1, 2) + Name(UOM2, 0) + Name(UOM3, 7) + Name(UOM4, 2) + Name(UOM5, 2) + Name(UOM6, 6) + Name(UOM7, 2) + Name(UOM8, 6) + Name(UOM9, 6) + + /* Some global data */ + Name(OSTP, 3) /* Assume nothing. WinXp = 1, Vista = 2, Linux = 3, WinCE = 4 */ + Name(OSV, Ones) /* Assume nothing */ + Name(PMOD, One) /* Assume APIC */ + + /* + * Processor Object + * + */ + Scope (\_PR) { /* define processor scope */ + Processor( + P000, /* name space name */ + 0, /* Unique number for this processor */ + 0x810, /* PBLK system I/O address !hardcoded! */ + 0x06 /* PBLKLEN for boot processor */ + ) { + } + + Processor( + P001, /* name space name */ + 1, /* Unique number for this processor */ + 0x0810, /* PBLK system I/O address !hardcoded! */ + 0x06 /* PBLKLEN for boot processor */ + ) { + } + Processor( + P002, /* name space name */ + 2, /* Unique number for this processor */ + 0x0810, /* PBLK system I/O address !hardcoded! */ + 0x06 /* PBLKLEN for boot processor */ + ) { + } + Processor( + P003, /* name space name */ + 3, /* Unique number for this processor */ + 0x0810, /* PBLK system I/O address !hardcoded! */ + 0x06 /* PBLKLEN for boot processor */ + ) { + } + Processor( + P004, /* name space name */ + 4, /* Unique number for this processor */ + 0x0810, /* PBLK system I/O address !hardcoded! */ + 0x06 /* PBLKLEN for boot processor */ + ) { + } + Processor( + P005, /* name space name */ + 5, /* Unique number for this processor */ + 0x0810, /* PBLK system I/O address !hardcoded! */ + 0x06 /* PBLKLEN for boot processor */ + ) { + } + Processor( + P006, /* name space name */ + 6, /* Unique number for this processor */ + 0x0810, /* PBLK system I/O address !hardcoded! */ + 0x06 /* PBLKLEN for boot processor */ + ) { + } + Processor( + P007, /* name space name */ + 7, /* Unique number for this processor */ + 0x0810, /* PBLK system I/O address !hardcoded! */ + 0x06 /* PBLKLEN for boot processor */ + ) { + } + } /* End _PR scope */ + + /* PIC IRQ mapping registers, C00h-C01h. */ + OperationRegion(PRQM, SystemIO, 0x00000C00, 0x00000002) + Field(PRQM, ByteAcc, NoLock, Preserve) { + PRQI, 0x00000008, + PRQD, 0x00000008, /* Offset: 1h */ + } + IndexField(PRQI, PRQD, ByteAcc, NoLock, Preserve) { + PIRA, 0x00000008, /* Index 0 */ + PIRB, 0x00000008, /* Index 1 */ + PIRC, 0x00000008, /* Index 2 */ + PIRD, 0x00000008, /* Index 3 */ + PIRE, 0x00000008, /* Index 4 */ + PIRF, 0x00000008, /* Index 5 */ + PIRG, 0x00000008, /* Index 6 */ + PIRH, 0x00000008, /* Index 7 */ + } + + /* PCI Error control register */ + OperationRegion(PERC, SystemIO, 0x00000C14, 0x00000001) + Field(PERC, ByteAcc, NoLock, Preserve) { + SENS, 0x00000001, + PENS, 0x00000001, + SENE, 0x00000001, + PENE, 0x00000001, + } + + /* Client Management index/data registers */ + OperationRegion(CMT, SystemIO, 0x00000C50, 0x00000002) + Field(CMT, ByteAcc, NoLock, Preserve) { + CMTI, 8, + /* Client Management Data register */ + G64E, 1, + G64O, 1, + G32O, 2, + , 2, + GPSL, 2, + } + + /* GPM Port register */ + OperationRegion(GPT, SystemIO, 0x00000C52, 0x00000001) + Field(GPT, ByteAcc, NoLock, Preserve) { + GPB0,1, + GPB1,1, + GPB2,1, + GPB3,1, + GPB4,1, + GPB5,1, + GPB6,1, + GPB7,1, + } + + /* Flash ROM program enable register */ + OperationRegion(FRE, SystemIO, 0x00000C6F, 0x00000001) + Field(FRE, ByteAcc, NoLock, Preserve) { + , 0x00000006, + FLRE, 0x00000001, + } + + /* PM2 index/data registers */ + OperationRegion(PM2R, SystemIO, 0x00000CD0, 0x00000002) + Field(PM2R, ByteAcc, NoLock, Preserve) { + PM2I, 0x00000008, + PM2D, 0x00000008, + } + + /* Power Management I/O registers. */ + OperationRegion(PIOR, SystemIO, 0x00000CD6, 0x00000002) + Field(PIOR, ByteAcc, NoLock, Preserve) { + PIOI, 0x00000008, + PIOD, 0x00000008, + } + IndexField (PIOI, PIOD, ByteAcc, NoLock, Preserve) { + Offset(0xEE), + UPWS, 3, + } + + /* PM1 Event Block + * First word is PM1_Status, Second word is PM1_Enable + */ + Scope(\_SB) { + /* PCIe Configuration Space for CONFIG_MMCONF_BUS_NUMBER busses */ + OperationRegion(PCFG, SystemMemory, PCBA, PCLN) + Field(PCFG, ByteAcc, NoLock, Preserve) { + /* Byte offsets are computed using the following technique: + * ((bus number + 1) * ((device number * 8) * 4096)) + register offset + * The 8 comes from 8 functions per device, and 4096 bytes per function config space + */ + Offset(0x00088024), /* Byte offset to SATA register 24h - Bus 0, Device 17, Function 0 */ + STB5, 32, + Offset(0x00098042), /* Byte offset to OHCI0 register 42h - Bus 0, Device 19, Function 0 */ + PT0D, 1, + PT1D, 1, + PT2D, 1, + PT3D, 1, + PT4D, 1, + PT5D, 1, + PT6D, 1, + PT7D, 1, + PT8D, 1, + PT9D, 1, + Offset(0x000A0004), /* Byte offset to SMBUS register 4h - Bus 0, Device 20, Function 0 */ + SBIE, 1, + SBME, 1, + Offset(0x000A0008), /* Byte offset to SMBUS register 8h - Bus 0, Device 20, Function 0 */ + SBRI, 8, + Offset(0x000A0014), /* Byte offset to SMBUS register 14h - Bus 0, Device 20, Function 0 */ + SBB1, 32, + Offset(0x000A0078), /* Byte offset to SMBUS register 78h - Bus 0, Device 20, Function 0 */ + ,14, + P92E, 1, /* Port92 decode enable */ + } + + OperationRegion(SB5, SystemMemory, STB5, 0x1000) + Field(SB5, AnyAcc, NoLock, Preserve){ + /* Port 0 */ + Offset(0x120), /* Port 0 Task file status */ + P0ER, 1, + , 2, + P0DQ, 1, + , 3, + P0BY, 1, + Offset(0x128), /* Port 0 Serial ATA status */ + P0DD, 4, + , 4, + P0IS, 4, + Offset(0x12C), /* Port 0 Serial ATA control */ + P0DI, 4, + Offset(0x130), /* Port 0 Serial ATA error */ + , 16, + P0PR, 1, + + /* Port 1 */ + offset(0x1A0), /* Port 1 Task file status */ + P1ER, 1, + , 2, + P1DQ, 1, + , 3, + P1BY, 1, + Offset(0x1A8), /* Port 1 Serial ATA status */ + P1DD, 4, + , 4, + P1IS, 4, + Offset(0x1AC), /* Port 1 Serial ATA control */ + P1DI, 4, + Offset(0x1B0), /* Port 1 Serial ATA error */ + , 16, + P1PR, 1, + + /* Port 2 */ + Offset(0x220), /* Port 2 Task file status */ + P2ER, 1, + , 2, + P2DQ, 1, + , 3, + P2BY, 1, + Offset(0x228), /* Port 2 Serial ATA status */ + P2DD, 4, + , 4, + P2IS, 4, + Offset(0x22C), /* Port 2 Serial ATA control */ + P2DI, 4, + Offset(0x230), /* Port 2 Serial ATA error */ + , 16, + P2PR, 1, + + /* Port 3 */ + Offset(0x2A0), /* Port 3 Task file status */ + P3ER, 1, + , 2, + P3DQ, 1, + , 3, + P3BY, 1, + Offset(0x2A8), /* Port 3 Serial ATA status */ + P3DD, 4, + , 4, + P3IS, 4, + Offset(0x2AC), /* Port 3 Serial ATA control */ + P3DI, 4, + Offset(0x2B0), /* Port 3 Serial ATA error */ + , 16, + P3PR, 1, + } + } + + #include "acpi/routing.asl" + + Scope(\_SB) { + + Method(CkOT, 0){ + + if(LNotEqual(OSTP, Ones)) {Return(OSTP)} /* OS version was already detected */ + + if(CondRefOf(\_OSI,Local1)) + { + Store(1, OSTP) /* Assume some form of XP */ + if (\_OSI("Windows 2006")) /* Vista */ + { + Store(2, OSTP) + } + } else { + If(WCMP(\_OS,"Linux")) { + Store(3, OSTP) /* Linux */ + } Else { + Store(4, OSTP) /* Gotta be WinCE */ + } + } + Return(OSTP) + } + + Method(_PIC, 0x01, NotSerialized) + { + If (Arg0) + { + \_SB.CIRQ() + } + Store(Arg0, PMOD) + } + Method(CIRQ, 0x00, NotSerialized){ + //Store(0, PIRA) + //Store(0, PIRB) + //Store(0, PIRC) + //Store(0, PIRD) + //Store(0, PIRE) + //Store(0, PIRF) + //Store(0, PIRG) + //Store(0, PIRH) + } + + Name(IRQB, ResourceTemplate(){ + IRQ(Level,ActiveLow,Shared){15} + }) + + Name(IRQP, ResourceTemplate(){ + IRQ(Level,ActiveLow,Exclusive){3, 4, 5, 7, 10, 11, 12, 15} + }) + + Name(PITF, ResourceTemplate(){ + IRQ(Level,ActiveLow,Exclusive){9} + }) + + Device(INTA) { + Name(_HID, EISAID("PNP0C0F")) + Name(_UID, 1) + + Method(_STA, 0) { + if (PIRA) { + Return(0x0B) /* sata is invisible */ + } else { + Return(0x09) /* sata is disabled */ + } + } /* End Method(_SB.INTA._STA) */ + + Method(_DIS ,0) { + /* DBGO("\\_SB\\LNKA\\_DIS\n") */ + //Store(0x1F, PIRA) + } /* End Method(_SB.INTA._DIS) */ + + Method(_PRS ,0) { + /* DBGO("\\_SB\\LNKA\\_PRS\n") */ + Return(IRQP) + } /* Method(_SB.INTA._PRS) */ + + Method(_CRS ,0) { + /* DBGO("\\_SB\\LNKA\\_CRS\n") */ + CreateWordField(IRQB, 0x1, IRQN) + ShiftLeft(1, PIRA, IRQN) + Return(IRQB) + } /* Method(_SB.INTA._CRS) */ + + Method(_SRS, 1) { + /* DBGO("\\_SB\\LNKA\\_CRS\n") */ + CreateWordField(ARG0, 1, IRQM) + + /* Use lowest available IRQ */ + FindSetRightBit(IRQM, Local0) + if (Local0) { + Decrement(Local0) + } + //Store(Local0, PIRA) + } /* End Method(_SB.INTA._SRS) */ + } /* End Device(INTA) */ + + Device(INTB) { + Name(_HID, EISAID("PNP0C0F")) + Name(_UID, 2) + + Method(_STA, 0) { + if (PIRB) { + Return(0x0B) /* sata is invisible */ + } else { + Return(0x09) /* sata is disabled */ + } + } /* End Method(_SB.INTB._STA) */ + + Method(_DIS ,0) { + /* DBGO("\\_SB\\LNKB\\_DIS\n") */ + //Store(0, PIRB) + } /* End Method(_SB.INTB._DIS) */ + + Method(_PRS ,0) { + /* DBGO("\\_SB\\LNKB\\_PRS\n") */ + Return(IRQP) + } /* Method(_SB.INTB._PRS) */ + + Method(_CRS ,0) { + /* DBGO("\\_SB\\LNKB\\_CRS\n") */ + CreateWordField(IRQB, 0x1, IRQN) + ShiftLeft(1, PIRB, IRQN) + Return(IRQB) + } /* Method(_SB.INTB._CRS) */ + + Method(_SRS, 1) { + /* DBGO("\\_SB\\LNKB\\_CRS\n") */ + CreateWordField(ARG0, 1, IRQM) + + /* Use lowest available IRQ */ + FindSetRightBit(IRQM, Local0) + if (Local0) { + Decrement(Local0) + } + Store(Local0, PIRB) + } /* End Method(_SB.INTB._SRS) */ + } /* End Device(INTB) */ + + Device(INTC) { + Name(_HID, EISAID("PNP0C0F")) + Name(_UID, 3) + + Method(_STA, 0) { + if (PIRC) { + Return(0x0B) /* sata is invisible */ + } else { + Return(0x09) /* sata is disabled */ + } + } /* End Method(_SB.INTC._STA) */ + + Method(_DIS ,0) { + /* DBGO("\\_SB\\LNKC\\_DIS\n") */ + //Store(0, PIRC) + } /* End Method(_SB.INTC._DIS) */ + + Method(_PRS ,0) { + /* DBGO("\\_SB\\LNKC\\_PRS\n") */ + Return(IRQP) + } /* Method(_SB.INTC._PRS) */ + + Method(_CRS ,0) { + /* DBGO("\\_SB\\LNKC\\_CRS\n") */ + CreateWordField(IRQB, 0x1, IRQN) + ShiftLeft(1, PIRC, IRQN) + Return(IRQB) + } /* Method(_SB.INTC._CRS) */ + + Method(_SRS, 1) { + /* DBGO("\\_SB\\LNKC\\_CRS\n") */ + CreateWordField(ARG0, 1, IRQM) + + /* Use lowest available IRQ */ + FindSetRightBit(IRQM, Local0) + if (Local0) { + Decrement(Local0) + } + Store(Local0, PIRC) + } /* End Method(_SB.INTC._SRS) */ + } /* End Device(INTC) */ + + Device(INTD) { + Name(_HID, EISAID("PNP0C0F")) + Name(_UID, 4) + + Method(_STA, 0) { + if (PIRD) { + Return(0x0B) /* sata is invisible */ + } else { + Return(0x09) /* sata is disabled */ + } + } /* End Method(_SB.INTD._STA) */ + + Method(_DIS ,0) { + /* DBGO("\\_SB\\LNKD\\_DIS\n") */ + //Store(0, PIRD) + } /* End Method(_SB.INTD._DIS) */ + + Method(_PRS ,0) { + /* DBGO("\\_SB\\LNKD\\_PRS\n") */ + Return(IRQP) + } /* Method(_SB.INTD._PRS) */ + + Method(_CRS ,0) { + /* DBGO("\\_SB\\LNKD\\_CRS\n") */ + CreateWordField(IRQB, 0x1, IRQN) + ShiftLeft(1, PIRD, IRQN) + Return(IRQB) + } /* Method(_SB.INTD._CRS) */ + + Method(_SRS, 1) { + /* DBGO("\\_SB\\LNKD\\_CRS\n") */ + CreateWordField(ARG0, 1, IRQM) + + /* Use lowest available IRQ */ + FindSetRightBit(IRQM, Local0) + if (Local0) { + Decrement(Local0) + } + Store(Local0, PIRD) + } /* End Method(_SB.INTD._SRS) */ + } /* End Device(INTD) */ + + Device(INTE) { + Name(_HID, EISAID("PNP0C0F")) + Name(_UID, 5) + + Method(_STA, 0) { + if (PIRE) { + Return(0x0B) /* sata is invisible */ + } else { + Return(0x09) /* sata is disabled */ + } + } /* End Method(_SB.INTE._STA) */ + + Method(_DIS ,0) { + /* DBGO("\\_SB\\LNKE\\_DIS\n") */ + //Store(0, PIRE) + } /* End Method(_SB.INTE._DIS) */ + + Method(_PRS ,0) { + /* DBGO("\\_SB\\LNKE\\_PRS\n") */ + Return(IRQP) + } /* Method(_SB.INTE._PRS) */ + + Method(_CRS ,0) { + /* DBGO("\\_SB\\LNKE\\_CRS\n") */ + CreateWordField(IRQB, 0x1, IRQN) + ShiftLeft(1, PIRE, IRQN) + Return(IRQB) + } /* Method(_SB.INTE._CRS) */ + + Method(_SRS, 1) { + /* DBGO("\\_SB\\LNKE\\_CRS\n") */ + CreateWordField(ARG0, 1, IRQM) + + /* Use lowest available IRQ */ + FindSetRightBit(IRQM, Local0) + if (Local0) { + Decrement(Local0) + } + Store(Local0, PIRE) + } /* End Method(_SB.INTE._SRS) */ + } /* End Device(INTE) */ + + Device(INTF) { + Name(_HID, EISAID("PNP0C0F")) + Name(_UID, 6) + + Method(_STA, 0) { + if (PIRF) { + Return(0x0B) /* sata is invisible */ + } else { + Return(0x09) /* sata is disabled */ + } + } /* End Method(_SB.INTF._STA) */ + + Method(_DIS ,0) { + /* DBGO("\\_SB\\LNKF\\_DIS\n") */ + //Store(0, PIRF) + } /* End Method(_SB.INTF._DIS) */ + + Method(_PRS ,0) { + /* DBGO("\\_SB\\LNKF\\_PRS\n") */ + Return(PITF) + } /* Method(_SB.INTF._PRS) */ + + Method(_CRS ,0) { + /* DBGO("\\_SB\\LNKF\\_CRS\n") */ + CreateWordField(IRQB, 0x1, IRQN) + ShiftLeft(1, PIRF, IRQN) + Return(IRQB) + } /* Method(_SB.INTF._CRS) */ + + Method(_SRS, 1) { + /* DBGO("\\_SB\\LNKF\\_CRS\n") */ + CreateWordField(ARG0, 1, IRQM) + + /* Use lowest available IRQ */ + FindSetRightBit(IRQM, Local0) + if (Local0) { + Decrement(Local0) + } + Store(Local0, PIRF) + } /* End Method(_SB.INTF._SRS) */ + } /* End Device(INTF) */ + + Device(INTG) { + Name(_HID, EISAID("PNP0C0F")) + Name(_UID, 7) + + Method(_STA, 0) { + if (PIRG) { + Return(0x0B) /* sata is invisible */ + } else { + Return(0x09) /* sata is disabled */ + } + } /* End Method(_SB.INTG._STA) */ + + Method(_DIS ,0) { + /* DBGO("\\_SB\\LNKG\\_DIS\n") */ + //Store(0, PIRG) + } /* End Method(_SB.INTG._DIS) */ + + Method(_PRS ,0) { + /* DBGO("\\_SB\\LNKG\\_PRS\n") */ + Return(IRQP) + } /* Method(_SB.INTG._CRS) */ + + Method(_CRS ,0) { + /* DBGO("\\_SB\\LNKG\\_CRS\n") */ + CreateWordField(IRQB, 0x1, IRQN) + ShiftLeft(1, PIRG, IRQN) + Return(IRQB) + } /* Method(_SB.INTG._CRS) */ + + Method(_SRS, 1) { + /* DBGO("\\_SB\\LNKG\\_CRS\n") */ + CreateWordField(ARG0, 1, IRQM) + + /* Use lowest available IRQ */ + FindSetRightBit(IRQM, Local0) + if (Local0) { + Decrement(Local0) + } + Store(Local0, PIRG) + } /* End Method(_SB.INTG._SRS) */ + } /* End Device(INTG) */ + + Device(INTH) { + Name(_HID, EISAID("PNP0C0F")) + Name(_UID, 8) + + Method(_STA, 0) { + if (PIRH) { + Return(0x0B) /* sata is invisible */ + } else { + Return(0x09) /* sata is disabled */ + } + } /* End Method(_SB.INTH._STA) */ + + Method(_DIS ,0) { + /* DBGO("\\_SB\\LNKH\\_DIS\n") */ + //Store(0, PIRH) + } /* End Method(_SB.INTH._DIS) */ + + Method(_PRS ,0) { + /* DBGO("\\_SB\\LNKH\\_PRS\n") */ + Return(IRQP) + } /* Method(_SB.INTH._CRS) */ + + Method(_CRS ,0) { + /* DBGO("\\_SB\\LNKH\\_CRS\n") */ + CreateWordField(IRQB, 0x1, IRQN) + ShiftLeft(1, PIRH, IRQN) + Return(IRQB) + } /* Method(_SB.INTH._CRS) */ + + Method(_SRS, 1) { + /* DBGO("\\_SB\\LNKH\\_CRS\n") */ + CreateWordField(ARG0, 1, IRQM) + + /* Use lowest available IRQ */ + FindSetRightBit(IRQM, Local0) + if (Local0) { + Decrement(Local0) + } + //Store(Local0, PIRH) + } /* End Method(_SB.INTH._SRS) */ + } /* End Device(INTH) */ + + } /* End Scope(_SB) */ + + /* Supported sleep states: */ + Name(\_S0, Package () {0x00, 0x00, 0x00, 0x00} ) /* (S0) - working state */ + + If (LAnd(SSFG, 0x01)) { + Name(\_S1, Package () {0x01, 0x01, 0x00, 0x00} ) /* (S1) - sleeping w/CPU context */ + } + If (LAnd(SSFG, 0x02)) { + Name(\_S2, Package () {0x02, 0x02, 0x00, 0x00} ) /* (S2) - "light" Suspend to RAM */ + } + If (LAnd(SSFG, 0x04)) { + Name(\_S3, Package () {0x03, 0x03, 0x00, 0x00} ) /* (S3) - Suspend to RAM */ + } + If (LAnd(SSFG, 0x08)) { + Name(\_S4, Package () {0x04, 0x04, 0x00, 0x00} ) /* (S4) - Suspend to Disk */ + } + + Name(\_S5, Package () {0x05, 0x05, 0x00, 0x00} ) /* (S5) - Soft Off */ + + Name(\_SB.CSPS ,0) /* Current Sleep State (S0, S1, S2, S3, S4, S5) */ + Name(CSMS, 0) /* Current System State */ + + /* Wake status package */ + Name(WKST,Package(){Zero, Zero}) + + /* + * \_PTS - Prepare to Sleep method + * + * Entry: + * Arg0=The value of the sleeping state S1=1, S2=2, etc + * + * Exit: + * -none- + * + * The _PTS control method is executed at the beginning of the sleep process + * for S1-S5. The sleeping value is passed to the _PTS control method. This + * control method may be executed a relatively long time before entering the + * sleep state and the OS may abort the operation without notification to + * the ACPI driver. This method cannot modify the configuration or power + * state of any device in the system. + */ + Method(_PTS, 1) { + /* DBGO("\\_PTS\n") */ + /* DBGO("From S0 to S") */ + /* DBGO(Arg0) */ + /* DBGO("\n") */ + + /* Don't allow PCIRST# to reset USB */ + //if (LEqual(Arg0,3)){ + // Store(0,URRE) + //} + + /* Clear sleep SMI status flag and enable sleep SMI trap. */ + /*Store(One, CSSM) + Store(One, SSEN)*/ + + /* On older chips, clear PciExpWakeDisEn */ + /*if (LLessEqual(\_SB.SBRI, 0x13)) { + * Store(0,\_SB.PWDE) + *} + */ + + /* Clear wake status structure. */ + Store(0, Index(WKST,0)) + Store(0, Index(WKST,1)) + Store(7, UPWS) + } /* End Method(\_PTS) */ + + /* + * The following method results in a "not a valid reserved NameSeg" + * warning so I have commented it out for the duration. It isn't + * used, so it could be removed. + * + * + * \_GTS OEM Going To Sleep method + * + * Entry: + * Arg0=The value of the sleeping state S1=1, S2=2 + * + * Exit: + * -none- + * + * Method(\_GTS, 1) { + * DBGO("\\_GTS\n") + * DBGO("From S0 to S") + * DBGO(Arg0) + * DBGO("\n") + * } + */ + + /* + * \_BFS OEM Back From Sleep method + * + * Entry: + * Arg0=The value of the sleeping state S1=1, S2=2 + * + * Exit: + * -none- + */ + Method(\_BFS, 1) { + /* DBGO("\\_BFS\n") */ + /* DBGO("From S") */ + /* DBGO(Arg0) */ + /* DBGO(" to S0\n") */ + } + + /* + * \_WAK System Wake method + * + * Entry: + * Arg0=The value of the sleeping state S1=1, S2=2 + * + * Exit: + * Return package of 2 DWords + * Dword 1 - Status + * 0x00000000 wake succeeded + * 0x00000001 Wake was signaled but failed due to lack of power + * 0x00000002 Wake was signaled but failed due to thermal condition + * Dword 2 - Power Supply state + * if non-zero the effective S-state the power supply entered + */ + Method(\_WAK, 1) { + /* DBGO("\\_WAK\n") */ + /* DBGO("From S") */ + /* DBGO(Arg0) */ + /* DBGO(" to S0\n") */ + + /* Re-enable HPET */ + //Store(1,HPDE) + + /* Restore PCIRST# so it resets USB */ + //if (LEqual(Arg0,3)){ + // Store(1,URRE) + //} + + /* Arbitrarily clear PciExpWakeStatus */ + //Store(PWST, PWST) + + /* if(DeRefOf(Index(WKST,0))) { + * Store(0, Index(WKST,1)) + * } else { + * Store(Arg0, Index(WKST,1)) + * } + */ + Return(WKST) + } /* End Method(\_WAK) */ + + Scope(\_GPE) { /* Start Scope GPE */ + /* General event 0 */ + /* Method(_L00) { + * DBGO("\\_GPE\\_L00\n") + * } + */ + + /* General event 1 */ + /* Method(_L01) { + * DBGO("\\_GPE\\_L00\n") + * } + */ + + /* General event 2 */ + /* Method(_L02) { + * DBGO("\\_GPE\\_L00\n") + * } + */ + + /* General event 3 */ + Method(_L03) { + /* DBGO("\\_GPE\\_L00\n") */ + Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ + } + + /* General event 4 */ + /* Method(_L04) { + * DBGO("\\_GPE\\_L00\n") + * } + */ + + /* General event 5 */ + /* Method(_L05) { + * DBGO("\\_GPE\\_L00\n") + * } + */ + + /* General event 6 - Used for GPM6, moved to USB.asl */ + /* Method(_L06) { + * DBGO("\\_GPE\\_L00\n") + * } + */ + + /* General event 7 - Used for GPM7, moved to USB.asl */ + /* Method(_L07) { + * DBGO("\\_GPE\\_L07\n") + * } + */ + + /* Legacy PM event */ + Method(_L08) { + /* DBGO("\\_GPE\\_L08\n") */ + } + + /* Temp warning (TWarn) event */ + Method(_L09) { + /* DBGO("\\_GPE\\_L09\n") */ + /* Notify (\_TZ.TZ00, 0x80) */ + } + + /* Reserved */ + /* Method(_L0A) { + * DBGO("\\_GPE\\_L0A\n") + * } + */ + + /* USB controller PME# */ + Method(_L0B) { + /* DBGO("\\_GPE\\_L0B\n") */ + Notify(\_SB.PCI0.UOH1, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PCI0.UOH2, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PCI0.UOH3, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PCI0.UOH4, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PCI0.UOH5, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PCI0.UOH6, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PCI0.UEH1, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ + } + + /* AC97 controller PME# */ + /* Method(_L0C) { + * DBGO("\\_GPE\\_L0C\n") + * } + */ + + /* OtherTherm PME# */ + /* Method(_L0D) { + * DBGO("\\_GPE\\_L0D\n") + * } + */ + + /* GPM9 SCI event - Moved to USB.asl */ + /* Method(_L0E) { + * DBGO("\\_GPE\\_L0E\n") + * } + */ + + /* PCIe HotPlug event */ + /* Method(_L0F) { + * DBGO("\\_GPE\\_L0F\n") + * } + */ + + /* ExtEvent0 SCI event */ + Method(_L10) { + /* DBGO("\\_GPE\\_L10\n") */ + } + + /* ExtEvent1 SCI event */ + Method(_L11) { + /* DBGO("\\_GPE\\_L11\n") */ + } + + /* PCIe PME# event */ + /* Method(_L12) { + * DBGO("\\_GPE\\_L12\n") + * } + */ + + /* GPM0 SCI event - Moved to USB.asl */ + /* Method(_L13) { + * DBGO("\\_GPE\\_L13\n") + * } + */ + + /* GPM1 SCI event - Moved to USB.asl */ + /* Method(_L14) { + * DBGO("\\_GPE\\_L14\n") + * } + */ + + /* GPM2 SCI event - Moved to USB.asl */ + /* Method(_L15) { + * DBGO("\\_GPE\\_L15\n") + * } + */ + + /* GPM3 SCI event - Moved to USB.asl */ + /* Method(_L16) { + * DBGO("\\_GPE\\_L16\n") + * } + */ + + /* GPM8 SCI event - Moved to USB.asl */ + /* Method(_L17) { + * DBGO("\\_GPE\\_L17\n") + * } + */ + + /* GPIO0 or GEvent8 event */ + Method(_L18) { + /* DBGO("\\_GPE\\_L18\n") */ + Notify(\_SB.PCI0.PBR4, 0x02) /* NOTIFY_DEVICE_WAKE */ +#if 0 + Notify(\_SB.PCI0.PBR5, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PCI0.PBR6, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PCI0.PBR7, 0x02) /* NOTIFY_DEVICE_WAKE */ +#endif + Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ + } + + /* GPM4 SCI event - Moved to USB.asl */ + /* Method(_L19) { + * DBGO("\\_GPE\\_L19\n") + * } + */ + + /* GPM5 SCI event - Moved to USB.asl */ + /* Method(_L1A) { + * DBGO("\\_GPE\\_L1A\n") + * } + */ + + /* Azalia SCI event */ + Method(_L1B) { + /* DBGO("\\_GPE\\_L1B\n") */ + Notify(\_SB.PCI0.AZHD, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ + } + + /* GPM6 SCI event - Reassigned to _L06 */ + /* Method(_L1C) { + * DBGO("\\_GPE\\_L1C\n") + * } + */ + + /* GPM7 SCI event - Reassigned to _L07 */ + /* Method(_L1D) { + * DBGO("\\_GPE\\_L1D\n") + * } + */ + + /* GPIO2 or GPIO66 SCI event */ + /* Method(_L1E) { + * DBGO("\\_GPE\\_L1E\n") + * } + */ + + /* SATA SCI event - Moved to sata.asl */ + /* Method(_L1F) { + * DBGO("\\_GPE\\_L1F\n") + * } + */ + + } /* End Scope GPE */ + + //#include "acpi/usb.asl" + + /* System Bus */ + Scope(\_SB) { /* Start \_SB scope */ + #include "../../../arch/x86/acpi/globutil.asl" /* global utility methods expected within the \_SB scope */ + + /* _SB.PCI0 */ + /* Note: Only need HID on Primary Bus */ + Device(PCI0) { + External (TOM1) + External (TOM2) + Name(_HID, EISAID("PNP0A03")) + Name(_ADR, 0x00180000) /* Dev# = BSP Dev#, Func# = 0 */ + Method(_BBN, 0) { /* Bus number = 0 */ + Return(0) + } + Method(_STA, 0) { + /* DBGO("\\_SB\\PCI0\\_STA\n") */ + Return(0x0B) /* Status is visible */ + } + + Method(_PRT,0) { + If(PMOD){ Return(APR0) } /* APIC mode */ + Return (PR0) /* PIC Mode */ + } /* end _PRT */ + + /* Describe the Northbridge devices Dev0 ,Func0*/ + Device(AMRT) { + Name(_ADR, 0x00000000) + } /* end AMRT */ + + /* Dev2 is also an external GFX bridge */ + Device(PBR2) { + Name(_ADR, 0x00020000) + Name(_PRW, Package() {0x18, 4}) + Method(_PRT,0) { + If(PMOD){ Return(APS2) } /* APIC mode */ + Return (PS2) /* PIC Mode */ + } /* end _PRT */ + } /* end PBR2 */ + + Device(PBR4) { + Name(_ADR, 0x00040000) + Name(_PRW, Package() {0x18, 4}) + Method(_PRT,0) { + If(PMOD){ Return(APS4) } /* APIC mode */ + Return (PS4) /* PIC Mode */ + } /* end _PRT */ + } /* end PBR4 */ + + /* PCI slot 1, 2, 3 */ + Device(PIBR) { + Name(_ADR, 0x00140004) + Name(_PRW, Package() {0x18, 4}) + /* TODO: non APIC rounting */ + Method(_PRT,0) { + Return (PCIB) + } + } + + /* Describe the Southbridge devices */ + /* PCIe 1x SB */ + Device(SBR0) { + Name(_ADR, 0x00150000) + Name(_PRW, Package() {0x18, 4}) + Method(_PRT,0) { + If(PMOD){ Return(ABR0) } /* APIC mode */ + Return (PBR0) /* PIC Mode */ + } /* end _PRT */ + } /* end SBR0 */ + + + /* Onboard network */ + Device(SBR1) { + Name(_ADR, 0x00150001) + Name(_PRW, Package() {0x18, 4}) + Method(_PRT, 0) { + If(PMOD){ Return(ABR1) } /* APIC mode */ + Return (PBR1) /* PIC Mode */ + } /* end _PRT */ + } /* end SBR1 */ + + Device(STCR) { + Name(_ADR, 0x00110000) + //#include "acpi/sata.asl" + } /* end STCR */ + + Device(UOH1) { + Name(_ADR, 0x00120000) + Name(_PRW, Package() {0x0B, 3}) + } /* end UOH1 */ + + Device(UOH2) { + Name(_ADR, 0x00120002) + Name(_PRW, Package() {0x0B, 3}) + } /* end UOH2 */ + + Device(UOH3) { + Name(_ADR, 0x00130000) + Name(_PRW, Package() {0x0B, 3}) + } /* end UOH3 */ + + Device(UOH4) { + Name(_ADR, 0x00130002) + Name(_PRW, Package() {0x0B, 3}) + } /* end UOH4 */ + + Device(UOH5) { + Name(_ADR, 0x00160000) + Name(_PRW, Package() {0x0B, 3}) + } /* end UOH5 */ + + Device(UOH6) { + Name(_ADR, 0x00160002) + Name(_PRW, Package() {0x0B, 3}) + } /* end UOH5 */ + + Device(UEH1) { + Name(_ADR, 0x00140005) + Name(_PRW, Package() {0x0B, 3}) + } /* end UEH1 */ + + Device(XHC0) { + Name(_ADR, 0x00100000) + Name(_PRW, Package() {0x0B, 4}) + } /* end XHC0 */ + Device(XHC1) { + Name(_ADR, 0x00100001) + Name(_PRW, Package() {0x0B, 4}) + } /* end XHC1 */ + + Device(SBUS) { + Name(_ADR, 0x00140000) + } /* end SBUS */ + + /* Primary (and only) IDE channel */ + Device(IDEC) { + Name(_ADR, 0x00140001) + //#include "acpi/ide.asl" + } /* end IDEC */ + + Device(AZHD) { + Name(_ADR, 0x00140002) + OperationRegion(AZPD, PCI_Config, 0x00, 0x100) + Field(AZPD, AnyAcc, NoLock, Preserve) { + offset (0x42), + NSDI, 1, + NSDO, 1, + NSEN, 1, + offset (0x44), + IPCR, 4, + offset (0x54), + PWST, 2, + , 6, + PMEB, 1, + , 6, + PMST, 1, + offset (0x62), + MMCR, 1, + offset (0x64), + MMLA, 32, + offset (0x68), + MMHA, 32, + offset (0x6C), + MMDT, 16, + } + + Method(_INI) { + If(LEqual(OSTP,3)){ /* If we are running Linux */ + Store(zero, NSEN) + Store(one, NSDO) + Store(one, NSDI) + } + } + } /* end AZHD */ + + Device(LIBR) { + Name(_ADR, 0x00140003) + /* Method(_INI) { + * DBGO("\\_SB\\PCI0\\LpcIsaBr\\_INI\n") + } */ /* End Method(_SB.SBRDG._INI) */ + + /* Real Time Clock Device */ + Device(RTC0) { + Name(_HID, EISAID("PNP0B00")) /* AT Real Time Clock (not PIIX4 compatible) */ + Name(_CRS, ResourceTemplate() { + IRQNoFlags(){8} + IO(Decode16,0x0070, 0x0070, 0, 2) + /* IO(Decode16,0x0070, 0x0070, 0, 4) */ + }) + } /* End Device(_SB.PCI0.LpcIsaBr.RTC0) */ + + Device(TMR) { /* Timer */ + Name(_HID,EISAID("PNP0100")) /* System Timer */ + Name(_CRS, ResourceTemplate() { + IRQNoFlags(){0} + IO(Decode16, 0x0040, 0x0040, 0, 4) + /* IO(Decode16, 0x0048, 0x0048, 0, 4) */ + }) + } /* End Device(_SB.PCI0.LpcIsaBr.TMR) */ + + Device(SPKR) { /* Speaker */ + Name(_HID,EISAID("PNP0800")) /* AT style speaker */ + Name(_CRS, ResourceTemplate() { + IO(Decode16, 0x0061, 0x0061, 0, 1) + }) + } /* End Device(_SB.PCI0.LpcIsaBr.SPKR) */ + + Device(PIC) { + Name(_HID,EISAID("PNP0000")) /* AT Interrupt Controller */ + Name(_CRS, ResourceTemplate() { + IRQNoFlags(){2} + IO(Decode16,0x0020, 0x0020, 0, 2) + IO(Decode16,0x00A0, 0x00A0, 0, 2) + /* IO(Decode16, 0x00D0, 0x00D0, 0x10, 0x02) */ + /* IO(Decode16, 0x04D0, 0x04D0, 0x10, 0x02) */ + }) + } /* End Device(_SB.PCI0.LpcIsaBr.PIC) */ + + Device(MAD) { /* 8257 DMA */ + Name(_HID,EISAID("PNP0200")) /* Hardware Device ID */ + Name(_CRS, ResourceTemplate() { + DMA(Compatibility,BusMaster,Transfer8){4} + IO(Decode16, 0x0000, 0x0000, 0x10, 0x10) + IO(Decode16, 0x0081, 0x0081, 0x01, 0x03) + IO(Decode16, 0x0087, 0x0087, 0x01, 0x01) + IO(Decode16, 0x0089, 0x0089, 0x01, 0x03) + IO(Decode16, 0x008F, 0x008F, 0x01, 0x01) + IO(Decode16, 0x00C0, 0x00C0, 0x10, 0x20) + }) /* End Name(_SB.PCI0.LpcIsaBr.MAD._CRS) */ + } /* End Device(_SB.PCI0.LpcIsaBr.MAD) */ + + Device(COPR) { + Name(_HID,EISAID("PNP0C04")) /* Math Coprocessor */ + Name(_CRS, ResourceTemplate() { + IO(Decode16, 0x00F0, 0x00F0, 0, 0x10) + IRQNoFlags(){13} + }) + } /* End Device(_SB.PCI0.LpcIsaBr.COPR) */ + } /* end LIBR */ + + Device(HPBR) { + Name(_ADR, 0x00140004) + } /* end HostPciBr */ + + Device(ACAD) { + Name(_ADR, 0x00140005) + } /* end Ac97audio */ + + Device(ACMD) { + Name(_ADR, 0x00140006) + } /* end Ac97modem */ + + Name(CRES, ResourceTemplate() { + IO(Decode16, 0x0CF8, 0x0CF8, 1, 8) + + WORDIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, + 0x0000, /* address granularity */ + 0x0000, /* range minimum */ + 0x0CF7, /* range maximum */ + 0x0000, /* translation */ + 0x0CF8 /* length */ + ) + WORDIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, + 0x0000, /* address granularity */ + 0x03B0, /* range minimum */ + 0x03DF, /* range maximum */ + 0x0000, /* translation */ + 0x0030 /* length */ + ) + + WORDIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, + 0x0000, /* address granularity */ + 0x0D00, /* range minimum */ + 0xFFFF, /* range maximum */ + 0x0000, /* translation */ + 0xF300 /* length */ + ) + + Memory32Fixed(READONLY, 0x000A0000, 0x00020000, VGAM) /* VGA memory space */ + Memory32Fixed(READONLY, 0x000C0000, 0x00020000, EMM1) /* Assume C0000-E0000 empty */ + /* memory space for PCI BARs below 4GB */ + Memory32Fixed(ReadOnly, 0x00000000, 0x00000000, MMIO) + }) /* End Name(_SB.PCI0.CRES) */ + + Method(_CRS, 0) { + /* DBGO("\\_SB\\PCI0\\_CRS\n") */ + CreateDWordField(CRES, ^MMIO._BAS, MM1B) + CreateDWordField(CRES, ^MMIO._LEN, MM1L) + /* + * Declare memory between TOM1 and 4GB as available + * for PCI MMIO. + * Use ShiftLeft to avoid 64bit constant (for XP). + * This will work even if the OS does 32bit arithmetic, as + * 32bit (0x00000000 - TOM1) will wrap and give the same + * result as 64bit (0x100000000 - TOM1). + */ + Store(TOM1, MM1B) + ShiftLeft(0x10000000, 4, Local0) + Subtract(Local0, TOM1, Local0) + Store(Local0, MM1L) + + Return(CRES) /* note to change the Name buffer */ + } /* end of Method(_SB.PCI0._CRS) */ + + /* + * + * FIRST METHOD CALLED UPON BOOT + * + * 1. If debugging, print current OS and ACPI interpreter. + * 2. Get PCI Interrupt routing from ACPI VSM, this + * value is based on user choice in BIOS setup. + */ + Method(_INI, 0) { + /* DBGO("\\_SB\\_INI\n") */ + /* DBGO(" DSDT.ASL code from ") */ + /* DBGO(__DATE__) */ + /* DBGO(" ") */ + /* DBGO(__TIME__) */ + /* DBGO("\n Sleep states supported: ") */ + /* DBGO("\n") */ + /* DBGO(" \\_OS=") */ + /* DBGO(\_OS) */ + /* DBGO("\n \\_REV=") */ + /* DBGO(\_REV) */ + /* DBGO("\n") */ + + /* Determine the OS we're running on */ + CkOT() + + /* On older chips, clear PciExpWakeDisEn */ + /*if (LLessEqual(\SBRI, 0x13)) { + * Store(0,\PWDE) + * } + */ + } /* End Method(_SB._INI) */ + } /* End Device(PCI0) */ + + Device(PWRB) { /* Start Power button device */ + Name(_HID, EISAID("PNP0C0C")) + Name(_UID, 0xAA) + Name(_PRW, Package () {3, 0x04}) /* wake from S1-S4 */ + Name(_STA, 0x0B) /* sata is invisible */ + } + } /* End \_SB scope */ + + Scope(\_SI) { + Method(_SST, 1) { + /* DBGO("\\_SI\\_SST\n") */ + /* DBGO(" New Indicator state: ") */ + /* DBGO(Arg0) */ + /* DBGO("\n") */ + } + } /* End Scope SI */ +} +/* End of ASL file */ diff --git a/src/mainboard/asus/f2a85-m/get_bus_conf.c b/src/mainboard/asus/f2a85-m/get_bus_conf.c new file mode 100644 index 0000000..3ae4c18 --- /dev/null +++ b/src/mainboard/asus/f2a85-m/get_bus_conf.c @@ -0,0 +1,139 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <console/console.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include <string.h> +#include <stdint.h> +#include <stdlib.h> +#include <cpu/amd/amdfam14.h> +#include "agesawrapper.h" + +/* Global variables for MB layouts and these will be shared by irqtable mptable + * and acpi_tables busnum is default. + */ +u8 bus_isa; +u8 bus_hudson[3]; +u32 apicid_hudson; + +/* + * Here you only need to set value in pci1234 for HT-IO that could be installed or not + * You may need to preset pci1234 for HTIO board, + * please refer to src/northbridge/amd/amdk8/get_sblk_pci1234.c for detail + */ +u32 pci1234x[] = { + 0x0000ff0, +}; + +u32 bus_type[256]; +u32 sbdn_hudson; + +static u32 get_bus_conf_done = 0; + +#if CONFIG_HAVE_ACPI_RESUME +extern u8 acpi_slp_type; +#endif +void get_bus_conf(void) +{ + u32 apicid_base; + u32 status; + + device_t dev; + int i, j; + + if (get_bus_conf_done == 1) + return; /* do it only once */ + + get_bus_conf_done = 1; + + /* + * This is the call to AmdInitLate. It is really in the wrong place, conceptually, + * but functionally within the coreboot model, this is the best place to make the + * call. The logically correct place to call AmdInitLate is after PCI scan is done, + * after the decision about S3 resume is made, and before the system tables are + * written into RAM. The routine that is responsible for writing the tables is + * "write_tables", called near the end of "hardwaremain". There is no platform + * specific entry point between the S3 resume decision point and the call to + * "write_tables", and the next platform specific entry points are the calls to + * the ACPI table write functions. The first of ose would seem to be the right + * place, but other table write functions, e.g. the PIRQ table write function, are + * called before the ACPI tables are written. This routine is called at the beginning + * of each of the write functions called prior to the ACPI write functions, so this + * becomes the best place for this call. + */ +#if CONFIG_HAVE_ACPI_RESUME + if (acpi_slp_type != 3) { + status = agesawrapper_amdinitlate(); + if(status) { + printk(BIOS_DEBUG, "agesawrapper_amdinitlate failed: %x \n", status); + } + status = agesawrapper_amdS3Save(); + if (status) { + printk(BIOS_DEBUG, "agesawrapper_amds3save failed: %x \n", status); + } + } +#else + status = agesawrapper_amdinitlate(); + if (status) + printk(BIOS_DEBUG, "agesawrapper_amdinitlate failed: %x \n", status); +#endif + + sbdn_hudson = 0; + + for (i = 0; i < 3; i++) { + bus_hudson[i] = 0; + } + + for (i = 0; i < 256; i++) { + bus_type[i] = 0; /* default ISA bus. */ + } + + bus_type[0] = 1; /* pci */ + + bus_hudson[0] = (pci1234x[0] >> 16) & 0xff; + + /* Hudson */ + dev = dev_find_slot(bus_hudson[0], PCI_DEVFN(sbdn_hudson + 0x14, 4)); + + if (dev) { + bus_hudson[1] = pci_read_config8(dev, PCI_SECONDARY_BUS); + + bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS); + bus_isa++; + for (j = bus_hudson[1]; j < bus_isa; j++) + bus_type[j] = 1; + } + + for (i = 0; i < 4; i++) { + dev = dev_find_slot(bus_hudson[0], PCI_DEVFN(sbdn_hudson + 0x14, i)); + if (dev) { + bus_hudson[2 + i] = pci_read_config8(dev, PCI_SECONDARY_BUS); + bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS); + bus_isa++; + } + } + for (j = bus_hudson[2]; j < bus_isa; j++) + bus_type[j] = 1; + + /* I/O APICs: APIC ID Version State Address */ + bus_isa = 10; + apicid_base = CONFIG_MAX_CPUS; + apicid_hudson = apicid_base; +} diff --git a/src/mainboard/asus/f2a85-m/irq_tables.c b/src/mainboard/asus/f2a85-m/irq_tables.c new file mode 100644 index 0000000..d7e223b --- /dev/null +++ b/src/mainboard/asus/f2a85-m/irq_tables.c @@ -0,0 +1,112 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <console/console.h> +#include <device/pci.h> +#include <string.h> +#include <stdint.h> +#include <arch/pirq_routing.h> +#include <cpu/amd/amdfam15.h> + +static void write_pirq_info(struct irq_info *pirq_info, u8 bus, u8 devfn, + u8 link0, u16 bitmap0, u8 link1, u16 bitmap1, + u8 link2, u16 bitmap2, u8 link3, u16 bitmap3, + u8 slot, u8 rfu) +{ + pirq_info->bus = bus; + pirq_info->devfn = devfn; + pirq_info->irq[0].link = link0; + pirq_info->irq[0].bitmap = bitmap0; + pirq_info->irq[1].link = link1; + pirq_info->irq[1].bitmap = bitmap1; + pirq_info->irq[2].link = link2; + pirq_info->irq[2].bitmap = bitmap2; + pirq_info->irq[3].link = link3; + pirq_info->irq[3].bitmap = bitmap3; + pirq_info->slot = slot; + pirq_info->rfu = rfu; +} + +extern u8 bus_isa; +extern u8 bus_hudson[2]; +extern unsigned long sbdn_hudson; + +unsigned long write_pirq_routing_table(unsigned long addr) +{ + struct irq_routing_table *pirq; + struct irq_info *pirq_info; + u32 slot_num; + u8 *v; + + u8 sum = 0; + int i; + + get_bus_conf(); /* it will find out all bus num and apic that share with mptable.c and mptable.c and acpi_tables.c */ + + /* Align the table to be 16 byte aligned. */ + addr += 15; + addr &= ~15; + + /* This table must be betweeen 0xf0000 & 0x100000 */ + printk(BIOS_INFO, "Writing IRQ routing tables to 0x%lx...", addr); + + pirq = (void *)(addr); + v = (u8 *) (addr); + + pirq->signature = PIRQ_SIGNATURE; + pirq->version = PIRQ_VERSION; + + pirq->rtr_bus = bus_hudson[0]; + pirq->rtr_devfn = ((sbdn_hudson + 0x14) << 3) | 4; + + pirq->exclusive_irqs = 0; + + pirq->rtr_vendor = 0x1002; + pirq->rtr_device = 0x4384; + + pirq->miniport_data = 0; + + memset(pirq->rfu, 0, sizeof(pirq->rfu)); + + pirq_info = (void *)(&pirq->checksum + 1); + slot_num = 0; + + /* pci bridge */ + write_pirq_info(pirq_info, bus_hudson[0], ((sbdn_hudson + 0x14) << 3) | 4, + 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, + 0); + pirq_info++; + + slot_num++; + + pirq->size = 32 + 16 * slot_num; + + for (i = 0; i < pirq->size; i++) + sum += v[i]; + + sum = pirq->checksum - sum; + + if (sum != pirq->checksum) { + pirq->checksum = sum; + } + + printk(BIOS_INFO, "write_pirq_routing_table done.\n"); + + return (unsigned long)pirq_info; +} diff --git a/src/mainboard/asus/f2a85-m/mainboard.c b/src/mainboard/asus/f2a85-m/mainboard.c new file mode 100644 index 0000000..266c813 --- /dev/null +++ b/src/mainboard/asus/f2a85-m/mainboard.c @@ -0,0 +1,68 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <console/console.h> +#include <device/device.h> +#include <device/pci.h> +#include <arch/io.h> +#include <cpu/x86/msr.h> +#include "BiosCallOuts.h" +#include <cpu/amd/mtrr.h> +#include <device/pci_def.h> +#include <arch/acpi.h> +#include <cpu/amd/agesa/s3_resume.h> +#include "agesawrapper.h" + +/************************************************* + * enable the dedicated function in thatcher board. + *************************************************/ +static void mainboard_enable(device_t dev) +{ + msr_t msr; + + printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n"); + + msr = rdmsr(0xC0011020); + msr.lo &= ~(1 << 28); + wrmsr(0xC0011020, msr); + + msr = rdmsr(0xC0011022); + msr.lo &= ~(1 << 4); + msr.lo &= ~(1 << 13); + wrmsr(0xC0011022, msr); + + msr = rdmsr(0xC0011023); + msr.lo &= ~(1 << 23); + wrmsr(0xC0011023, msr); + + /* + * The mainboard is the first place that we get control in ramstage. Check + * for S3 resume and call the approriate AGESA/CIMx resume functions. + */ +#if CONFIG_HAVE_ACPI_RESUME + acpi_slp_type = acpi_get_sleep_type(); + if (acpi_slp_type == 3) + agesawrapper_fchs3earlyrestore(); + +#endif +} + +struct chip_operations mainboard_ops = { + .enable_dev = mainboard_enable, +}; diff --git a/src/mainboard/asus/f2a85-m/mptable.c b/src/mainboard/asus/f2a85-m/mptable.c new file mode 100644 index 0000000..5b6136c --- /dev/null +++ b/src/mainboard/asus/f2a85-m/mptable.c @@ -0,0 +1,195 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <console/console.h> +#include <arch/smp/mpspec.h> +#include <device/pci.h> +#include <arch/io.h> +#include <string.h> +#include <stdint.h> +#include <cpu/amd/amdfam15.h> +#include <arch/cpu.h> +#include <cpu/x86/lapic.h> +#include "southbridge/amd/agesa/hudson/hudson.h" + + +//-#define IO_APIC_ID CONFIG_MAX_PHYSICAL_CPUS + 1 +#define IO_APIC_ID CONFIG_MAX_CPUS +extern u8 bus_hudson[3]; + +extern u32 bus_type[256]; +extern u32 sbdn_hudson; +extern u32 apicid_hudson; + +u8 picr_data[] = { + 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x0A,0xF1,0x00,0x00,0x1F,0x1F,0x1F,0x1F, + 0x09,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x1F,0x1F,0x1F,0x1F +}; +u8 intr_data[0x54] = { + 0x10,0x11,0x12,0x13,0x14,0x15,0x16,0x17,0x00,0x00,0x00,0x00,0x1F,0x1F,0x1F,0x1F, + 0x09,0x1F,0x1F,0x10,0x1F,0x10,0x1F,0x10,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x05,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x12,0x11,0x12,0x11,0x12,0x11,0x12,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x11,0x13,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x10,0x11,0x12,0x13 +}; + +static void smp_add_mpc_entry(struct mp_config_table *mc, unsigned length) +{ + mc->mpc_length += length; + mc->mpc_entry_count++; +} + +static void my_smp_write_bus(struct mp_config_table *mc, + unsigned char id, const char *bustype) +{ + struct mpc_config_bus *mpc; + mpc = smp_next_mpc_entry(mc); + memset(mpc, '\0', sizeof(*mpc)); + mpc->mpc_type = MP_BUS; + mpc->mpc_busid = id; + memcpy(mpc->mpc_bustype, bustype, sizeof(mpc->mpc_bustype)); + smp_add_mpc_entry(mc, sizeof(*mpc)); +} + +static void *smp_write_config_table(void *v) +{ + struct mp_config_table *mc; + int bus_isa; + u32 dword; + u8 byte; + + mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); + + mptable_init(mc, LOCAL_APIC_ADDR); + memcpy(mc->mpc_oem, "AMD ", 8); + + smp_write_processors(mc); + + get_bus_conf(); + + //mptable_write_buses(mc, NULL, &bus_isa); + my_smp_write_bus(mc, 0, "PCI "); + my_smp_write_bus(mc, 1, "PCI "); + bus_isa = 0x02; + my_smp_write_bus(mc, bus_isa, "ISA "); + + /* I/O APICs: APIC ID Version State Address */ + + dword = 0; + dword = pm_ioread(0x34) & 0xF0; + dword |= (pm_ioread(0x35) & 0xFF) << 8; + dword |= (pm_ioread(0x36) & 0xFF) << 16; + dword |= (pm_ioread(0x37) & 0xFF) << 24; + /* Set IO APIC ID onto IO_APIC_ID */ + write32 (dword, 0x00); + write32 (dword + 0x10, IO_APIC_ID << 24); + apicid_hudson = IO_APIC_ID; + smp_write_ioapic(mc, apicid_hudson, 0x21, dword); + + /* PIC IRQ routine */ + for (byte = 0x0; byte < sizeof(picr_data); byte ++) { + outb(byte, 0xC00); + outb(picr_data[byte], 0xC01); + } + + /* APIC IRQ routine */ + for (byte = 0x0; byte < sizeof(intr_data); byte ++) { + outb(byte | 0x80, 0xC00); + outb(intr_data[byte], 0xC01); + } + + /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ +#define IO_LOCAL_INT(type, intr, apicid, pin) \ + smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin)); + mptable_add_isa_interrupts(mc, bus_isa, apicid_hudson, 0); + + /* PCI interrupts are level triggered, and are + * associated with a specific bus/device/function tuple. + */ +#define PCI_INT(bus, dev, int_sign, pin) \ + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(int_sign)), apicid_hudson, (pin)) + + /* Internal VGA */ + PCI_INT(0x0, 0x01, 0x0, intr_data[0x02]); + PCI_INT(0x0, 0x01, 0x1, intr_data[0x03]); + + /* SMBUS */ + PCI_INT(0x0, 0x14, 0x0, 0x10); + + /* HD Audio */ + PCI_INT(0x0, 0x14, 0x0, intr_data[0x13]); + + /* USB */ + PCI_INT(0x0, 0x12, 0x0, intr_data[0x30]); + PCI_INT(0x0, 0x12, 0x1, intr_data[0x31]); + PCI_INT(0x0, 0x13, 0x0, intr_data[0x32]); + PCI_INT(0x0, 0x13, 0x1, intr_data[0x33]); + PCI_INT(0x0, 0x16, 0x0, intr_data[0x34]); + PCI_INT(0x0, 0x16, 0x1, intr_data[0x35]); + PCI_INT(0x0, 0x14, 0x2, intr_data[0x36]); + + /* sata */ + PCI_INT(0x0, 0x11, 0x0, intr_data[0x40]); + PCI_INT(0x0, 0x11, 0x0, intr_data[0x41]); + + /* on board NIC & Slot PCIE. */ + + /* PCI slots */ + /* PCI_SLOT 0. */ + PCI_INT(bus_hudson[1], 0x5, 0x0, 0x14); + PCI_INT(bus_hudson[1], 0x5, 0x1, 0x15); + PCI_INT(bus_hudson[1], 0x5, 0x2, 0x16); + PCI_INT(bus_hudson[1], 0x5, 0x3, 0x17); + + PCI_INT(bus_hudson[2], 0x0, 0x0, 0x12); + PCI_INT(bus_hudson[2], 0x0, 0x1, 0x13); + PCI_INT(bus_hudson[2], 0x0, 0x2, 0x14); + + /* PCIe Lan*/ + PCI_INT(0x0, 0x06, 0x0, 0x13); + + /* FCH PCIe PortA */ + PCI_INT(0x0, 0x15, 0x0, 0x10); + /* FCH PCIe PortB */ + PCI_INT(0x0, 0x15, 0x1, 0x11); + /* FCH PCIe PortC */ + PCI_INT(0x0, 0x15, 0x2, 0x12); + /* FCH PCIe PortD */ + PCI_INT(0x0, 0x15, 0x3, 0x13); + + /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ + IO_LOCAL_INT(mp_ExtINT, 0, MP_APIC_ALL, 0x0); + IO_LOCAL_INT(mp_NMI, 0, MP_APIC_ALL, 0x1); + /* There is no extension information... */ + + /* Compute the checksums */ + return mptable_finalize(mc); +} + +unsigned long write_smp_table(unsigned long addr) +{ + void *v; + v = smp_write_floating_table(addr, 0); + return (unsigned long)smp_write_config_table(v); +} diff --git a/src/mainboard/asus/f2a85-m/pmio.h b/src/mainboard/asus/f2a85-m/pmio.h new file mode 100644 index 0000000..35751f5 --- /dev/null +++ b/src/mainboard/asus/f2a85-m/pmio.h @@ -0,0 +1,33 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef _PMIO_H_ +#define _PMIO_H_ + +#define PM_INDEX 0xCD6 +#define PM_DATA 0xCD7 +#define PM2_INDEX 0xCD0 +#define PM2_DATA 0xCD1 + +void pm_iowrite(u8 reg, u8 value); +u8 pm_ioread(u8 reg); +void pm2_iowrite(u8 reg, u8 value); +u8 pm2_ioread(u8 reg); + +#endif diff --git a/src/mainboard/asus/f2a85-m/romstage.c b/src/mainboard/asus/f2a85-m/romstage.c new file mode 100644 index 0000000..8d35f8d --- /dev/null +++ b/src/mainboard/asus/f2a85-m/romstage.c @@ -0,0 +1,206 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * Copyright (C) 2012 Rudolf Marek <r.marek(a)assembler.cz> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <stdint.h> +#include <string.h> +#include <device/pci_def.h> +#include <device/pci_ids.h> +#include <arch/io.h> +#include <arch/stages.h> +#include <device/pnp_def.h> +#include <arch/romcc_io.h> +#include <arch/cpu.h> +#include <cpu/x86/lapic.h> +#include <console/console.h> +#include <console/loglevel.h> +#include "agesawrapper.h" +#include "cpu/x86/bist.h" +#include "cpu/x86/lapic/boot_cpu.c" +#include "southbridge/amd/agesa/hudson/hudson.h" +#include "southbridge/amd/agesa/hudson/smbus.h" +#include "superio/ite/it8712f/early_serial.c" +#include "cpu/amd/agesa/s3_resume.h" +#include "src/drivers/pc80/i8254.c" +#include "src/drivers/pc80/i8259.c" +#include "cbmem.h" + +void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx); +void disable_cache_as_ram(void); + +#define MMIO_NON_POSTED_START 0xfed00000 +#define MMIO_NON_POSTED_END 0xfedfffff +#define SB_MMIO 0xFED80000 +#define SB_MMIO_MISC32(x) *(volatile u32 *)(SB_MMIO + 0xE00 + (x)) + +static void sbxxx_enable_48mhzout(void) +{ + /* most likely programming to 48MHz out signal */ + u32 reg32; + reg32 = SB_MMIO_MISC32(0x28); + reg32 &= 0xffc7ffff; + reg32 |= 0x00100000; + SB_MMIO_MISC32(0x28) = reg32; + + reg32 = SB_MMIO_MISC32(0x40); + reg32 &= ~0x80u; + SB_MMIO_MISC32(0x40) = reg32; +} + +void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) +{ + u32 val; + u8 byte; + device_t dev; +#if CONFIG_HAVE_ACPI_RESUME + void *resume_backup_memory; +#endif + val = agesawrapper_amdinitmmio(); + + if (!cpu_init_detectedx && boot_cpu()) { + + /* enable SIO decode */ + dev = PCI_DEV(0, 0x14, 3); + byte = pci_read_config8(dev, 0x48); + byte |= 3; /* 2e, 2f */ + pci_write_config8(dev, 0x48, byte); + + post_code(0x30); + + /* enable SB MMIO space */ + outb(0x24, 0xcd6); + outb(0x1, 0xcd7); + + /* enable SIO clock */ + sbxxx_enable_48mhzout(); + it8712f_kill_watchdog(); + it8712f_enable_serial(0, CONFIG_TTYS0_BASE); + console_init(); + + /* turn on secondary smbus at b20 */ + outb(0x28, 0xcd6); + byte = inb(0xcd7); + byte |= 1; + outb(byte, 0xcd7); + + /* set DDR3 voltage */ + byte = CONFIG_BOARD_ASUS_F2A85_M_DDR3_VOLT_VAL; + + if (!byte) + do_smbus_write_byte(0xb20, 0x15, 0x3, byte); + } + + /* Halt if there was a built in self test failure */ + post_code(0x34); + report_bist_failure(bist); + + /* Load MPB */ + val = cpuid_eax(1); + printk(BIOS_DEBUG, "BSP Family_Model: %08x \n", val); + printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx \n", cpu_init_detectedx); + + post_code(0x37); + printk(BIOS_DEBUG, "agesawrapper_amdinitreset "); + val = agesawrapper_amdinitreset(); + if(val) { + printk(BIOS_DEBUG, "agesawrapper_amdinitreset failed: %x \n", val); + } + + post_code(0x39); + + val = agesawrapper_amdinitearly (); + if(val) { + printk(BIOS_DEBUG, "agesawrapper_amdinitearly failed: %x \n", val); + } + printk(BIOS_DEBUG, "Got past agesawrapper_amdinitearly\n"); + +#if CONFIG_HAVE_ACPI_RESUME + if (!acpi_is_wakeup_early()) { /* Check for S3 resume */ +#endif + post_code(0x40); + val = agesawrapper_amdinitpost (); + if(val) { + printk(BIOS_DEBUG, "agesawrapper_amdinitpost failed: %x \n", val); + } + printk(BIOS_DEBUG, "Got past agesawrapper_amdinitpost\n"); + + post_code(0x41); + val = agesawrapper_amdinitenv (); + if(val) { + printk(BIOS_DEBUG, "agesawrapper_amdinitenv failed: %x \n", val); + } + printk(BIOS_DEBUG, "Got past agesawrapper_amdinitenv\n"); + disable_cache_as_ram(); +#if CONFIG_HAVE_ACPI_RESUME + } else { /* S3 detect */ + printk(BIOS_INFO, "S3 detected\n"); + + post_code(0x60); + printk(BIOS_DEBUG, "agesawrapper_amdinitresume "); + val = agesawrapper_amdinitresume(); + if (val) + printk(BIOS_DEBUG, "error level: %x \n", val); + else + printk(BIOS_DEBUG, "passed.\n"); + + printk(BIOS_DEBUG, "agesawrapper_amds3laterestore "); + val = agesawrapper_amds3laterestore (); + if (val) + printk(BIOS_DEBUG, "error level: %x \n", val); + else + printk(BIOS_DEBUG, "passed.\n"); + + post_code(0x61); + printk(BIOS_DEBUG, "Find resume memory location\n"); + resume_backup_memory = (void *)backup_resume(); + + post_code(0x62); + printk(BIOS_DEBUG, "Move CAR stack.\n"); + move_stack_high_mem(); + printk(BIOS_DEBUG, "stack moved to: 0x%x\n", (u32) (resume_backup_memory + HIGH_MEMORY_SAVE)); + + post_code(0x63); + disable_cache_as_ram(); + printk(BIOS_DEBUG, "CAR disabled.\n"); + set_resume_cache(); + + /* + * Copy the system memory that is in the ramstage area to the + * reserved area. + */ + if (resume_backup_memory) + memcpy(resume_backup_memory, (void *)(CONFIG_RAMBASE), HIGH_MEMORY_SAVE); + + printk(BIOS_DEBUG, "System memory saved. OK to load ramstage.\n"); + } +#endif + + /* Initialize i8259 pic */ + post_code(0x41); + setup_i8259 (); + + /* Initialize i8254 timers */ + post_code(0x42); + setup_i8254 (); + + post_code(0x50); + copy_and_run(0); + + post_code(0x54); /* Should never see this post code. */ +}

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Patch merged into coreboot/master: cddcc80 coreboot: introduce romstage_handoff structure
by gerrit＠coreboot.org March 21, 2013

March 21, 2013

the following patch was just integrated into master: commit cddcc80048ab963f96d13575a3f63070cf6d7c14 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Fri Feb 8 17:15:53 2013 -0600 coreboot: introduce romstage_handoff structure The romstage_handoff structure is intended to be a way for romstage and ramstage to communicate with one another instead of using sideband signals such as stuffing magic values in pci config or memory scratch space. Initially this structure just contains a single region that indicates to ramstage that it should reserve a memory region used by the romstage. Ramstage looks for a romstage_handoff structure in cbmem with an id of CBMEM_ID_ROMSTAGE_INFO. If found, it will honor reserving the region defined in the romstage_handoff structure. Change-Id: I9274ea5124e9bd6584f6977d8280b7e9292251f0 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: http://review.coreboot.org/2791 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich(a)gmail.com> Build-Tested: build bot (Jenkins) at Tue Mar 19 04:34:43 2013, giving +1 Reviewed-By: Ronald G. Minnich <rminnich(a)gmail.com> at Thu Mar 21 18:04:56 2013, giving +2 See http://review.coreboot.org/2791 for details. -gerrit

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