coreboot-gerrit March 2013

coreboot-gerrit@coreboot.org

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Patch set updated for coreboot: 0c6d067 rmodule: add ability to calculate module placement
by Stefan Reinauer 21 Mar '13

21 Mar '13

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2788 -gerrit commit 0c6d067913068103eb56e4d0b6fd62cd7c3510ee Author: Aaron Durbin <adurbin(a)chromium.org> Date: Fri Feb 8 17:05:36 2013 -0600 rmodule: add ability to calculate module placement There is a need to calculate the proper placement for an rmodule in memory. e.g. loading a compressed rmodule from flash into ram can be an issue. Determining the placement is hard since the header is not readable until it is decompressed so choosing the wrong location may require a memmove() after decompression. This patch provides a function to perform this calculation by finding region below a given address while making an assumption on the size of the rmodule header.. Change-Id: I2703438f58ae847ed6e80b58063ff820fbcfcbc0 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/include/rmodule.h | 8 ++++++++ src/lib/rmodule.c | 51 +++++++++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 59 insertions(+) diff --git a/src/include/rmodule.h b/src/include/rmodule.h index 5300c63..2d8fc0f 100644 --- a/src/include/rmodule.h +++ b/src/include/rmodule.h @@ -20,6 +20,7 @@ #define RMODULE_H #include <stdint.h> +#include <stddef.h> #define RMODULE_MAGIC 0xf8fe #define RMODULE_VERSION_1 1 @@ -40,6 +41,13 @@ int rmodule_entry_offset(const struct rmodule *m); int rmodule_memory_size(const struct rmodule *m); int rmodule_load(void *loc, struct rmodule *m); int rmodule_load_alignment(const struct rmodule *m); +/* Returns the an aligned pointer that reflects a region used below addr + * based on the rmodule_size. i.e. the returned pointer up to addr is memory + * that may be utilized by the rmodule. program_start and rmodule_start + * are pointers updated to reflect where the rmodule program starts and where + * the rmodule (including header) should be placed respectively. */ +void *rmodule_find_region_below(void *addr, size_t rmodule_size, + void **program_start, void **rmodule_start); #define FIELD_ENTRY(x_) ((u32)&x_) #define RMODULE_HEADER(entry_, type_) \ diff --git a/src/lib/rmodule.c b/src/lib/rmodule.c index 56d7c6d..81e9ef1 100644 --- a/src/lib/rmodule.c +++ b/src/lib/rmodule.c @@ -17,6 +17,7 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ #include <stdint.h> +#include <stdlib.h> #include <string.h> #include <console/console.h> #include <rmodule.h> @@ -165,6 +166,12 @@ static void rmodule_copy_payload(const struct rmodule *module) "filesize: 0x%x memsize: 0x%x\n", module->location, rmodule_entry(module), module->payload_size, rmodule_memory_size(module)); + + /* No need to copy the payload if the load location and the + * payload location are the same. */ + if (module->location == module->payload) + return; + memcpy(module->location, module->payload, module->payload_size); } @@ -243,3 +250,47 @@ int rmodule_load(void *base, struct rmodule *module) return rmodule_relocate(module); } +void *rmodule_find_region_below(void *addr, size_t rmodule_size, + void **program_start, void **rmodule_start) +{ + unsigned long ceiling; + unsigned long program_base; + unsigned long placement_loc; + unsigned long program_begin; + + ceiling = (unsigned long)addr; + /* Place the rmodule just under the ceiling. The rmodule files + * themselves are packed as a header and a payload, however the rmodule + * itself is linked along with the header. The header starts at address + * 0. Immediately following the header in the file is the program, + * however its starting address is determined by the rmodule linker + * script. In short, sizeof(struct rmodule_header) can be less than + * or equal to the linked address of the program. Therefore we want + * to place the rmodule so that the program falls on the aligned + * address with the header just before it. Therefore, we need at least + * a page to account for the size of the header. */ + program_base = ALIGN((ceiling - (rmodule_size + 4096)), 4096); + /* The program starts immediately after the header. However, + * it needs to be aligned to a 4KiB boundary. Therefore, adjust the + * program location so that the program lands on a page boundary. The + * layout looks like the following: + * + * +--------------------------------+ ceiling + * | >= 0 bytes from alignment | + * +--------------------------------+ program end (4KiB aligned) + * | program size | + * +--------------------------------+ program_begin (4KiB aligned) + * | sizeof(struct rmodule_header) | + * +--------------------------------+ rmodule header start + * | >= 0 bytes from alignment | + * +--------------------------------+ program_base (4KiB aligned) + */ + placement_loc = ALIGN(program_base + sizeof(struct rmodule_header), + 4096) - sizeof(struct rmodule_header); + program_begin = placement_loc + sizeof(struct rmodule_header); + + *program_start = (void *)program_begin; + *rmodule_start = (void *)placement_loc; + + return (void *)program_base; +}

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Patch set updated for coreboot: dfd605b samsung/exynos5: add resource functions for the display port
by Ronald G. Minnich 20 Mar '13

20 Mar '13

Ronald G. Minnich (rminnich(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2615 -gerrit commit dfd605b9b6691caf3f52e311630b7f03eb22321f Author: Ronald G. Minnich <rminnich(a)gmail.com> Date: Mon Mar 18 09:49:54 2013 -0700 samsung/exynos5: add resource functions for the display port NOT WORKING. We're still not getting our ops set -- seems the enable function is not being called, sigh. Simplified devicetree.cb however. Not working, seemingly, but we need to add a 4M resource for memory, and it seems it needs to be fixed at the address shown. This address was chosen from current hardware. The pnp device in the displayport is really hokey. We're going to have to create a new kind of device, maybe called 'hardwired', or something, to allow us to wire down devices we know are there without probing. Discussion on IRC implies this is the direction we need to go. Change-Id: Ied65a554f833566be817540702f79a02e7b6cb6e Signed-off-by: Ronald G. Minnich <rminnich(a)gmail.com> --- src/cpu/samsung/exynos5-common/displayport/Kconfig | 2 - .../exynos5-common/displayport/Makefile.inc | 2 - src/cpu/samsung/exynos5-common/displayport/chip.h | 40 -------- .../exynos5-common/displayport/displayport.c | 107 --------------------- src/cpu/samsung/exynos5250/chip.h | 42 ++++++++ src/cpu/samsung/exynos5250/cpu.c | 70 ++++++++++++++ src/mainboard/google/snow/devicetree.cb | 33 +++---- src/vendorcode/google/chromeos/build-snow | 4 +- 8 files changed, 127 insertions(+), 173 deletions(-) diff --git a/src/cpu/samsung/exynos5-common/displayport/Kconfig b/src/cpu/samsung/exynos5-common/displayport/Kconfig deleted file mode 100644 index 26d1422..0000000 --- a/src/cpu/samsung/exynos5-common/displayport/Kconfig +++ /dev/null @@ -1,2 +0,0 @@ -config EXYNOS_DISPLAYPORT - bool diff --git a/src/cpu/samsung/exynos5-common/displayport/Makefile.inc b/src/cpu/samsung/exynos5-common/displayport/Makefile.inc deleted file mode 100644 index 7c52eaf..0000000 --- a/src/cpu/samsung/exynos5-common/displayport/Makefile.inc +++ /dev/null @@ -1,2 +0,0 @@ -ramstage-$(CONFIG_EXYNOS_DISPLAYPORT) += displayport.c - diff --git a/src/cpu/samsung/exynos5-common/displayport/chip.h b/src/cpu/samsung/exynos5-common/displayport/chip.h deleted file mode 100644 index 53b7836..0000000 --- a/src/cpu/samsung/exynos5-common/displayport/chip.h +++ /dev/null @@ -1,40 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2013 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#ifndef CPU_SAMSUNG_EXYNOS5_COMMON_DISPLAYPORT_H -#define CPU_SAMSUNG_EXYNOS5_COMMON_DISPLAYPORT_H - -struct cpu_samsung_exynos5_common_displayport_config { - /* special magic numbers! */ - int clkval_f; - int upper_margin; - int lower_margin; - int vsync; - int left_margin; - int right_margin; - int hsync; - - int xres; - int yres; - int bpp; - - u32 lcdbase; -}; - -#endif /* CPU_SAMSUNG_EXYNOS5-COMMON_DISPLAYPORT_H */ diff --git a/src/cpu/samsung/exynos5-common/displayport/displayport.c b/src/cpu/samsung/exynos5-common/displayport/displayport.c deleted file mode 100644 index 1c08bc7..0000000 --- a/src/cpu/samsung/exynos5-common/displayport/displayport.c +++ /dev/null @@ -1,107 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2013 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include <stdlib.h> -#include <string.h> -#include <delay.h> -#include <arch/io.h> -#include <device/device.h> - -/* we distinguish a display port device from a raw graphics device because there are - * dramatic differences in startup depending on graphics usage. To make startup fast - * and easier to understand and debug we explicitly name this common case. The alternate - * approach, involving lots of machine and callbacks, is hard to debug and verify. - */ -static void exynos_displayport_init(void) -{ - struct cpu_samsung_exynos5_common_displayport_config *conf = dev->chip_info; - /* put these on the stack. If, at some point, we want to move this code to a - * pre-ram stage, it will be much easier. - */ - vidinfo_t vi; - struct exynos5_fimd_panel panel; - void *lcdbase; - - memset(vi, 0, sizeof(vi)); - memset(panel, 0, sizeof(panel)); - - panel.is_dp = 1; /* Display I/F is eDP */ - /* while it is true that we did a memset to zero, - * we leave some 'set to zero' entries here to make - * it clear what's going on. Graphics is confusing. - */ - panel.is_mipi = 0; - panel.fixvclk = 0; - panel.ivclk = 0; - panel.clkval_f = conf->clkval_f; - panel.upper_margin = conf->upper_margin; - panel.lower_margin = conf->lower_margin; - panel.vsync = conf->vsync; - panel.left_margin = conf->left_margin; - panel.right_margin = conf->right_margin; - panel.hsync = conf->hsync; - - vi->vl_col = conf->xres; - vi->fl_row = conf->yres; - vi->vl_bpix = conf->bpp; - vi->cmap = cbmem_reserve(64*1024); /* The size is a magic number from hardware. */ - - lcdbase = conf->lcdbase; - printk(BIOS_DEBUG, "Initializing exynos VGA\n"); - ret = lcd_ctrl_init(&vi, &panel, lcdbase); -#if 0 - ret = board_dp_lcd_vdd(blob, &wait_ms); - ret = board_dp_bridge_setup(blob, &wait_ms); - while (tries < 5) { - ret = board_dp_bridge_init(blob, &wait_ms); - ret = board_dp_hotplug(blob, &wait_ms); - if (ret) { - ret = board_dp_bridge_reset(blob, &wait_ms); - continue; - } - ret = dp_controller_init(blob, &wait_ms); - ret = board_dp_backlight_vdd(blob, &wait_ms); - ret = board_dp_backlight_pwm(blob, &wait_ms); - ret = board_dp_backlight_en(blob, &wait_ms); - } -#endif -} - -static void exynos_displayport_noop(device_t dummy) -{ -} - -static struct device_operations exynos_displayport_operations = { - .read_resources = exynos_displayport_noop, - .set_resources = exynos_displayport_noop, - .enable_resources = exynos_displayport_noop, - .init = exynos_displayport_init, - .scan_bus = exynos_displayport_noop, -}; - -static void exynos_displayport_enable(struct device *dev) -{ - if (dev->link_list != NULL) - dev->ops = &exynos_displayport_operations; -} - -struct chip_operations drivers_i2c_exynos_displayport_ops = { - CHIP_NAME("exynos displayport") - .enable_dev = exynos_displayport_enable; -}; diff --git a/src/cpu/samsung/exynos5250/chip.h b/src/cpu/samsung/exynos5250/chip.h new file mode 100644 index 0000000..306d374 --- /dev/null +++ b/src/cpu/samsung/exynos5250/chip.h @@ -0,0 +1,42 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2013 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef CPU_SAMSUNG_EXYNOS5250_H +#define CPU_SAMSUNG_EXYNOS55250_H +#include <cpu/samsung/exynos5250/fimd.h> +#include <cpu/samsung/exynos5-common/s5p-dp-core.h> + +struct cpu_samsung_exynos5250_config { + /* special magic numbers! */ + int clkval_f; + int upper_margin; + int lower_margin; + int vsync; + int left_margin; + int right_margin; + int hsync; + + int xres; + int yres; + int bpp; + + u32 lcdbase; +}; + +#endif /* CPU_SAMSUNG_EXYNOS5250_H */ diff --git a/src/cpu/samsung/exynos5250/cpu.c b/src/cpu/samsung/exynos5250/cpu.c index bcf4d22..e9fc383 100644 --- a/src/cpu/samsung/exynos5250/cpu.c +++ b/src/cpu/samsung/exynos5250/cpu.c @@ -1,5 +1,12 @@ +#include <stdlib.h> +#include <string.h> +#include <stddef.h> +#include <delay.h> #include <console/console.h> +#include <arch/io.h> #include <device/device.h> +#include <cbmem.h> +#include "chip.h" #define RAM_BASE_KB (CONFIG_SYS_SDRAM_BASE >> 10) #define RAM_SIZE_KB (CONFIG_DRAM_SIZE_MB << 10UL) @@ -28,8 +35,71 @@ static struct device_operations domain_ops = { .scan_bus = domain_scan_bus, }; +/* we distinguish a display port device from a raw graphics device because there are + * dramatic differences in startup depending on graphics usage. To make startup fast + * and easier to understand and debug we explicitly name this common case. The alternate + * approach, involving lots of machine and callbacks, is hard to debug and verify. + */ +static void exynos_displayport_init(device_t dev) +{ + int ret; + struct cpu_samsung_exynos5250_config *conf = dev->chip_info; + /* put these on the stack. If, at some point, we want to move this code to a + * pre-ram stage, it will be much easier. + */ + vidinfo_t vi; + struct exynos5_fimd_panel panel; + void *lcdbase; + + memset(&vi, 0, sizeof(vi)); + memset(&panel, 0, sizeof(panel)); + + panel.is_dp = 1; /* Display I/F is eDP */ + /* while it is true that we did a memset to zero, + * we leave some 'set to zero' entries here to make + * it clear what's going on. Graphics is confusing. + */ + panel.is_mipi = 0; + panel.fixvclk = 0; + panel.ivclk = 0; + panel.clkval_f = conf->clkval_f; + panel.upper_margin = conf->upper_margin; + panel.lower_margin = conf->lower_margin; + panel.vsync = conf->vsync; + panel.left_margin = conf->left_margin; + panel.right_margin = conf->right_margin; + panel.hsync = conf->hsync; + + vi.vl_col = conf->xres; + vi.vl_row = conf->yres; + vi.vl_bpix = conf->bpp; + /* The size is a magic number from hardware. */ + vi.cmap = cbmem_add(CBMEM_ID_CONSOLE, 64*1024); + + lcdbase = (void *)conf->lcdbase; + printk(BIOS_DEBUG, "Initializing exynos VGA\n"); + ret = lcd_ctrl_init(&vi, &panel, lcdbase); +#if 0 + ret = board_dp_lcd_vdd(blob, &wait_ms); + ret = board_dp_bridge_setup(blob, &wait_ms); + while (tries < 5) { + ret = board_dp_bridge_init(blob, &wait_ms); + ret = board_dp_hotplug(blob, &wait_ms); + if (ret) { + ret = board_dp_bridge_reset(blob, &wait_ms); + continue; + } + ret = dp_controller_init(blob, &wait_ms); + ret = board_dp_backlight_vdd(blob, &wait_ms); + ret = board_dp_backlight_pwm(blob, &wait_ms); + ret = board_dp_backlight_en(blob, &wait_ms); + } +#endif +} + static void cpu_init(device_t dev) { + exynos_displayport_init(dev); } static void cpu_noop(device_t dev) diff --git a/src/mainboard/google/snow/devicetree.cb b/src/mainboard/google/snow/devicetree.cb index 5ad786e..f252c75 100644 --- a/src/mainboard/google/snow/devicetree.cb +++ b/src/mainboard/google/snow/devicetree.cb @@ -17,30 +17,23 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -# FIXME: this is just a stub for now chip cpu/samsung/exynos5250 + device pnp 1.1 on end + register "xres" = "1366" + register "yres" = "768" + register "bpp" = "16" + # complex magic timing! + register "clkval_f" = "2" + register "upper_margin" = "14" + register "lower_margin" = "3" + register "vsync" = "5" + register "left_margin" = "80" + register "right_margin" = "48" + register "hsync" = "32" + register "lcdbase" = "0x10000000" -device cpu_cluster 0 on -end - -device domain 0 on chip drivers/generic/generic # I2C0 controller device i2c 6 on end # ? device i2c 9 on end # ? end - chip cpu/samsung/exynos5-common/displayport - register "xres" = "1366" - register "yres" = "768" - register "bpp" = "16" - # complex magic timing! - register "clkval_f" = "2" - register "upper_margin" = "14" - register "lower_margin" = "3" - register "vsync" = "5" - register "left_margin" = "80" - register "right_margin" = "48" - register "hsync" = "32" - register "lcdbase" = "0x10000000" - end -end end diff --git a/src/vendorcode/google/chromeos/build-snow b/src/vendorcode/google/chromeos/build-snow index a749ba5..9cdba75 100755 --- a/src/vendorcode/google/chromeos/build-snow +++ b/src/vendorcode/google/chromeos/build-snow @@ -70,8 +70,8 @@ main() { create_diff_192k "$OUTPUT" "$TMP_DIFF" echo "OK: Generated image (with BL1) in $OUTPUT" if is_servod_ready; then - echo "servod detected - flashing into device." - fast_flash_image "$OUTPUT" "$TMP_DIFF" + echo "servod detected - NOT flashing into device." + echo fast_flash_image "$OUTPUT" "$TMP_DIFF" echo "OK: Generated and flashed 128k of image into device via servo." else echo "(servod is not running, flashing into device is skipped)"

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Patch set updated for coreboot: 0d1f519 Unify coreboot table generation
by Stefan Reinauer 20 Mar '13

20 Mar '13

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2863 -gerrit commit 0d1f5197032845c16b038ec8247401f9e1f759f6 Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Wed Mar 20 14:08:04 2013 -0700 Unify coreboot table generation coreboot tables are, unlike general system tables, a platform independent concept. Hence, use the same code for coreboot table generation on all platforms. lib/coreboot_tables.c is based on the x86 version of the file, because some important fixes were missed on the ARMv7 version lately. Change-Id: Icc38baf609f10536a320d21ac64408bef44bb77d Signed-off-by: Stefan Reinauer <reinauer(a)coreboot.org> --- src/arch/armv7/boot/Makefile.inc | 1 - src/arch/armv7/boot/coreboot_table.c | 675 ------------------------ src/arch/armv7/boot/tables.c | 35 +- src/arch/armv7/include/arch/coreboot_tables.h | 31 -- src/arch/x86/boot/Makefile.inc | 1 - src/arch/x86/boot/coreboot_table.c | 730 -------------------------- src/arch/x86/boot/multiboot.c | 1 - src/arch/x86/boot/tables.c | 3 +- src/arch/x86/include/arch/coreboot_tables.h | 21 - src/include/boot/coreboot_tables.h | 16 + src/include/boot/tables.h | 1 - src/lib/Makefile.inc | 1 + src/lib/coreboot_table.c | 725 +++++++++++++++++++++++++ src/mainboard/google/butterfly/chromeos.c | 1 - src/mainboard/google/butterfly/mainboard.c | 2 +- src/mainboard/google/link/chromeos.c | 1 - src/mainboard/google/link/i915.c | 2 +- src/mainboard/google/link/mainboard.c | 2 +- src/mainboard/google/parrot/chromeos.c | 1 - src/mainboard/google/parrot/mainboard.c | 2 +- src/mainboard/google/snow/chromeos.c | 1 - src/mainboard/google/stout/chromeos.c | 1 - src/mainboard/google/stout/i915.c | 2 +- src/mainboard/google/stout/mainboard.c | 2 +- src/mainboard/intel/baskingridge/chromeos.c | 1 - src/mainboard/intel/baskingridge/mainboard.c | 2 +- src/mainboard/intel/emeraldlake2/chromeos.c | 2 +- src/mainboard/intel/emeraldlake2/mainboard.c | 2 +- src/mainboard/intel/wtm1/chromeos.c | 1 - src/mainboard/intel/wtm1/mainboard.c | 2 +- src/mainboard/intel/wtm2/chromeos.c | 1 - src/mainboard/intel/wtm2/mainboard.c | 2 +- src/mainboard/samsung/lumpy/chromeos.c | 2 +- src/mainboard/samsung/lumpy/mainboard.c | 2 +- src/mainboard/samsung/stumpy/chromeos.c | 2 +- src/mainboard/samsung/stumpy/mainboard.c | 2 +- src/vendorcode/google/chromeos/Kconfig | 2 + src/vendorcode/google/chromeos/chromeos.c | 2 +- 38 files changed, 780 insertions(+), 1503 deletions(-) diff --git a/src/arch/armv7/boot/Makefile.inc b/src/arch/armv7/boot/Makefile.inc index a0752d6..8d24fae 100644 --- a/src/arch/armv7/boot/Makefile.inc +++ b/src/arch/armv7/boot/Makefile.inc @@ -1,5 +1,4 @@ ramstage-y += boot.c -ramstage-y += coreboot_table.c #ramstage-$(CONFIG_MULTIBOOT) += multiboot.c ramstage-y += tables.c #ramstage-$(CONFIG_GENERATE_ACPI_TABLES) += acpi.c diff --git a/src/arch/armv7/boot/coreboot_table.c b/src/arch/armv7/boot/coreboot_table.c deleted file mode 100644 index e5aa6ed..0000000 --- a/src/arch/armv7/boot/coreboot_table.c +++ /dev/null @@ -1,675 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2003-2004 Eric Biederman - * Copyright (C) 2005-2010 coresystems GmbH - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, - * MA 02110-1301 USA - */ - -#include <console/console.h> -#include <ip_checksum.h> -#include <boot/tables.h> -#include <arch/coreboot_tables.h> -#include <string.h> -#include <version.h> -#include <device/device.h> -#include <stdlib.h> -#include <cbfs.h> -#include <cbmem.h> -#if CONFIG_USE_OPTION_TABLE -#include <option_table.h> -#endif -#if CONFIG_CHROMEOS -//#include <arch/acpi.h> -#include <vendorcode/google/chromeos/gnvs.h> -#endif - -static struct lb_header *lb_table_init(unsigned long addr) -{ - struct lb_header *header; - - /* 16 byte align the address */ - addr += 15; - addr &= ~15; - - header = (void *)addr; - header->signature[0] = 'L'; - header->signature[1] = 'B'; - header->signature[2] = 'I'; - header->signature[3] = 'O'; - header->header_bytes = sizeof(*header); - header->header_checksum = 0; - header->table_bytes = 0; - header->table_checksum = 0; - header->table_entries = 0; - return header; -} - -static struct lb_record *lb_first_record(struct lb_header *header) -{ - struct lb_record *rec; - rec = (void *)(((char *)header) + sizeof(*header)); - return rec; -} - -static struct lb_record *lb_last_record(struct lb_header *header) -{ - struct lb_record *rec; - rec = (void *)(((char *)header) + sizeof(*header) + header->table_bytes); - return rec; -} - -#if 0 -static struct lb_record *lb_next_record(struct lb_record *rec) -{ - rec = (void *)(((char *)rec) + rec->size); - return rec; -} -#endif - -static struct lb_record *lb_new_record(struct lb_header *header) -{ - struct lb_record *rec; - rec = lb_last_record(header); - if (header->table_entries) { - header->table_bytes += rec->size; - } - rec = lb_last_record(header); - header->table_entries++; - rec->tag = LB_TAG_UNUSED; - rec->size = sizeof(*rec); - return rec; -} - - -static struct lb_memory *lb_memory(struct lb_header *header) -{ - struct lb_record *rec; - struct lb_memory *mem; - rec = lb_new_record(header); - mem = (struct lb_memory *)rec; - mem->tag = LB_TAG_MEMORY; - mem->size = sizeof(*mem); - return mem; -} - -static struct lb_serial *lb_serial(struct lb_header *header) -{ -#if CONFIG_CONSOLE_SERIAL - if (uartmem_getbaseaddr()) { - struct lb_record *rec; - struct lb_serial *serial; - rec = lb_new_record(header); - serial = (struct lb_serial *)rec; - serial->tag = LB_TAG_SERIAL; - serial->size = sizeof(*serial); - serial->type = LB_SERIAL_TYPE_MEMORY_MAPPED; - serial->baseaddr = uartmem_getbaseaddr(); - serial->baud = CONFIG_TTYS0_BAUD; - return serial; - } else { - return NULL; - } -#else - return NULL; -#endif -} - -#if CONFIG_CONSOLE_SERIAL8250 || CONFIG_CONSOLE_SERIAL8250MEM || \ - CONFIG_CONSOLE_LOGBUF || CONFIG_USBDEBUG -static void add_console(struct lb_header *header, u16 consoletype) -{ - struct lb_console *console; - - console = (struct lb_console *)lb_new_record(header); - console->tag = LB_TAG_CONSOLE; - console->size = sizeof(*console); - console->type = consoletype; -} -#endif - -static void lb_console(struct lb_header *header) -{ -#if CONFIG_CONSOLE_SERIAL8250 - add_console(header, LB_TAG_CONSOLE_SERIAL8250); -#endif -#if CONFIG_CONSOLE_SERIAL8250MEM - add_console(header, LB_TAG_CONSOLE_SERIAL8250MEM); -#endif -#if CONFIG_CONSOLE_LOGBUF - add_console(header, LB_TAG_CONSOLE_LOGBUF); -#endif -#if CONFIG_USBDEBUG - add_console(header, LB_TAG_CONSOLE_EHCI); -#endif -} - -static void lb_framebuffer(struct lb_header *header) -{ -#if CONFIG_FRAMEBUFFER_KEEP_VESA_MODE - void fill_lb_framebuffer(struct lb_framebuffer *framebuffer); - int vbe_mode_info_valid(void); - - // If there isn't any mode info to put in the table, don't ask for it - // to be filled with junk. - if (!vbe_mode_info_valid()) - return; - struct lb_framebuffer *framebuffer; - framebuffer = (struct lb_framebuffer *)lb_new_record(header); - framebuffer->tag = LB_TAG_FRAMEBUFFER; - framebuffer->size = sizeof(*framebuffer); - fill_lb_framebuffer(framebuffer); -#endif -} - -#if CONFIG_CHROMEOS -static void lb_gpios(struct lb_header *header) -{ - struct lb_gpios *gpios; - gpios = (struct lb_gpios *)lb_new_record(header); - gpios->tag = LB_TAG_GPIO; - fill_lb_gpios(gpios); -} - -#if 0 -static void lb_vdat(struct lb_header *header) -{ - struct lb_vdat* vdat; - - vdat = (struct lb_vdat *)lb_new_record(header); - vdat->tag = LB_TAG_VDAT; - vdat->size = sizeof(*vdat); - acpi_get_vdat_info(&vdat->vdat_addr, &vdat->vdat_size); -} - -static void lb_vbnv(struct lb_header *header) -{ - struct lb_vbnv* vbnv; - - vbnv = (struct lb_vbnv *)lb_new_record(header); - vbnv->tag = LB_TAG_VBNV; - vbnv->size = sizeof(*vbnv); - vbnv->vbnv_start = CONFIG_VBNV_OFFSET + 14; - vbnv->vbnv_size = CONFIG_VBNV_SIZE; -} -#endif -#endif - -static void add_cbmem_pointers(struct lb_header *header) -{ - /* - * These CBMEM sections' addresses are included in the coreboot table - * with the appropriate tags. - */ - const struct section_id { - int cbmem_id; - int table_tag; - } section_ids[] = { - {CBMEM_ID_TIMESTAMP, LB_TAG_TIMESTAMPS}, - {CBMEM_ID_CONSOLE, LB_TAG_CBMEM_CONSOLE} - }; - int i; - - for (i = 0; i < ARRAY_SIZE(section_ids); i++) { - const struct section_id *sid = section_ids + i; - struct lb_cbmem_ref *cbmem_ref; - void *cbmem_addr = cbmem_find(sid->cbmem_id); - - if (!cbmem_addr) - continue; /* This section is not present */ - - cbmem_ref = (struct lb_cbmem_ref *)lb_new_record(header); - if (!cbmem_ref) { - printk(BIOS_ERR, "No more room in coreboot table!\n"); - break; - } - cbmem_ref->tag = sid->table_tag; - cbmem_ref->size = sizeof(*cbmem_ref); - cbmem_ref->cbmem_addr = (unsigned long)cbmem_addr; - } -} - -static struct lb_mainboard *lb_mainboard(struct lb_header *header) -{ - struct lb_record *rec; - struct lb_mainboard *mainboard; - rec = lb_new_record(header); - mainboard = (struct lb_mainboard *)rec; - mainboard->tag = LB_TAG_MAINBOARD; - - mainboard->size = (sizeof(*mainboard) + - strlen(mainboard_vendor) + 1 + - strlen(mainboard_part_number) + 1 + - 3) & ~3; - - mainboard->vendor_idx = 0; - mainboard->part_number_idx = strlen(mainboard_vendor) + 1; - - memcpy(mainboard->strings + mainboard->vendor_idx, - mainboard_vendor, strlen(mainboard_vendor) + 1); - memcpy(mainboard->strings + mainboard->part_number_idx, - mainboard_part_number, strlen(mainboard_part_number) + 1); - - return mainboard; -} - -#if CONFIG_USE_OPTION_TABLE -static struct cmos_checksum *lb_cmos_checksum(struct lb_header *header) -{ - struct lb_record *rec; - struct cmos_checksum *cmos_checksum; - rec = lb_new_record(header); - cmos_checksum = (struct cmos_checksum *)rec; - cmos_checksum->tag = LB_TAG_OPTION_CHECKSUM; - - cmos_checksum->size = (sizeof(*cmos_checksum)); - - cmos_checksum->range_start = LB_CKS_RANGE_START * 8; - cmos_checksum->range_end = ( LB_CKS_RANGE_END * 8 ) + 7; - cmos_checksum->location = LB_CKS_LOC * 8; - cmos_checksum->type = CHECKSUM_PCBIOS; - - return cmos_checksum; -} -#endif - -static void lb_strings(struct lb_header *header) -{ - static const struct { - uint32_t tag; - const char *string; - } strings[] = { - { LB_TAG_VERSION, coreboot_version, }, - { LB_TAG_EXTRA_VERSION, coreboot_extra_version, }, - { LB_TAG_BUILD, coreboot_build, }, - { LB_TAG_COMPILE_TIME, coreboot_compile_time, }, - { LB_TAG_COMPILE_BY, coreboot_compile_by, }, - { LB_TAG_COMPILE_HOST, coreboot_compile_host, }, - { LB_TAG_COMPILE_DOMAIN, coreboot_compile_domain, }, - { LB_TAG_COMPILER, coreboot_compiler, }, - { LB_TAG_LINKER, coreboot_linker, }, - { LB_TAG_ASSEMBLER, coreboot_assembler, }, - }; - unsigned int i; - for(i = 0; i < ARRAY_SIZE(strings); i++) { - struct lb_string *rec; - size_t len; - rec = (struct lb_string *)lb_new_record(header); - len = strlen(strings[i].string); - rec->tag = strings[i].tag; - rec->size = (sizeof(*rec) + len + 1 + 3) & ~3; - memcpy(rec->string, strings[i].string, len+1); - } - -} - -/* FIXME(dhendrix): used to be static void lb_memory_range(), but compiler - started complaining since it shares a name with a non-static struct. ugh. */ -static void new_lb_memory_range(struct lb_memory *mem, - uint32_t type, uint64_t start, uint64_t size) -{ - int entries; - entries = (mem->size - sizeof(*mem))/sizeof(mem->map[0]); - mem->map[entries].start = pack_lb64(start); - mem->map[entries].size = pack_lb64(size); - mem->map[entries].type = type; - mem->size += sizeof(mem->map[0]); -} - -static void lb_reserve_table_memory(struct lb_header *head) -{ - struct lb_record *last_rec; - struct lb_memory *mem; - uint64_t start; - uint64_t end; - int i, entries; - - last_rec = lb_last_record(head); - mem = get_lb_mem(); - start = (unsigned long)head; - end = (unsigned long)last_rec; - entries = (mem->size - sizeof(*mem))/sizeof(mem->map[0]); - /* Resize the right two memory areas so this table is in - * a reserved area of memory. Everything has been carefully - * setup so that is all we need to do. - */ - for(i = 0; i < entries; i++ ) { - uint64_t map_start = unpack_lb64(mem->map[i].start); - uint64_t map_end = map_start + unpack_lb64(mem->map[i].size); - /* Does this area need to be expanded? */ - if (map_end == start) { - mem->map[i].size = pack_lb64(end - map_start); - } - /* Does this area need to be contracted? */ - else if (map_start == start) { - mem->map[i].start = pack_lb64(end); - mem->map[i].size = pack_lb64(map_end - end); - } - } -} - -static unsigned long lb_table_fini(struct lb_header *head, int fixup) -{ - struct lb_record *rec, *first_rec; - rec = lb_last_record(head); - if (head->table_entries) { - head->table_bytes += rec->size; - } - - if (fixup) - lb_reserve_table_memory(head); - - first_rec = lb_first_record(head); - head->table_checksum = compute_ip_checksum(first_rec, head->table_bytes); - head->header_checksum = 0; - head->header_checksum = compute_ip_checksum(head, sizeof(*head)); - printk(BIOS_DEBUG, - "Wrote coreboot table at: %p, 0x%x bytes, checksum %x\n", - head, head->table_bytes, head->table_checksum); - return (unsigned long)rec + rec->size; -} - -static void lb_cleanup_memory_ranges(struct lb_memory *mem) -{ - int entries; - int i, j; - entries = (mem->size - sizeof(*mem))/sizeof(mem->map[0]); - - /* Sort the lb memory ranges */ - for(i = 0; i < entries; i++) { - uint64_t entry_start = unpack_lb64(mem->map[i].start); - for(j = i; j < entries; j++) { - uint64_t temp_start = unpack_lb64(mem->map[j].start); - if (temp_start < entry_start) { - struct lb_memory_range tmp; - tmp = mem->map[i]; - mem->map[i] = mem->map[j]; - mem->map[j] = tmp; - } - } - } - - /* Merge adjacent entries */ - for(i = 0; (i + 1) < entries; i++) { - uint64_t start, end, nstart, nend; - if (mem->map[i].type != mem->map[i + 1].type) { - continue; - } - start = unpack_lb64(mem->map[i].start); - end = start + unpack_lb64(mem->map[i].size); - nstart = unpack_lb64(mem->map[i + 1].start); - nend = nstart + unpack_lb64(mem->map[i + 1].size); - if ((start <= nstart) && (end > nstart)) { - if (start > nstart) { - start = nstart; - } - if (end < nend) { - end = nend; - } - /* Record the new region size */ - mem->map[i].start = pack_lb64(start); - mem->map[i].size = pack_lb64(end - start); - - /* Delete the entry I have merged with */ - memmove(&mem->map[i + 1], &mem->map[i + 2], - ((entries - i - 2) * sizeof(mem->map[0]))); - mem->size -= sizeof(mem->map[0]); - entries -= 1; - /* See if I can merge with the next entry as well */ - i -= 1; - } - } -} - -static void lb_remove_memory_range(struct lb_memory *mem, - uint64_t start, uint64_t size) -{ - uint64_t end; - int entries; - int i; - - end = start + size; - entries = (mem->size - sizeof(*mem))/sizeof(mem->map[0]); - - /* Remove a reserved area from the memory map */ - for(i = 0; i < entries; i++) { - uint64_t map_start = unpack_lb64(mem->map[i].start); - uint64_t map_end = map_start + unpack_lb64(mem->map[i].size); - if ((start <= map_start) && (end >= map_end)) { - /* Remove the completely covered range */ - memmove(&mem->map[i], &mem->map[i + 1], - ((entries - i - 1) * sizeof(mem->map[0]))); - mem->size -= sizeof(mem->map[0]); - entries -= 1; - /* Since the index will disappear revisit what will appear here */ - i -= 1; - } - else if ((start > map_start) && (end < map_end)) { - /* Split the memory range */ - memmove(&mem->map[i + 1], &mem->map[i], - ((entries - i) * sizeof(mem->map[0]))); - mem->size += sizeof(mem->map[0]); - entries += 1; - /* Update the first map entry */ - mem->map[i].size = pack_lb64(start - map_start); - /* Update the second map entry */ - mem->map[i + 1].start = pack_lb64(end); - mem->map[i + 1].size = pack_lb64(map_end - end); - /* Don't bother with this map entry again */ - i += 1; - } - else if ((start <= map_start) && (end > map_start)) { - /* Shrink the start of the memory range */ - mem->map[i].start = pack_lb64(end); - mem->map[i].size = pack_lb64(map_end - end); - } - else if ((start < map_end) && (start > map_start)) { - /* Shrink the end of the memory range */ - mem->map[i].size = pack_lb64(start - map_start); - } - } -} - -void lb_add_memory_range(struct lb_memory *mem, - uint32_t type, uint64_t start, uint64_t size) -{ - lb_remove_memory_range(mem, start, size); - new_lb_memory_range(mem, type, start, size); - lb_cleanup_memory_ranges(mem); -} - -static void lb_dump_memory_ranges(struct lb_memory *mem) -{ - int entries; - int i; - entries = (mem->size - sizeof(*mem))/sizeof(mem->map[0]); - - printk(BIOS_DEBUG, "coreboot memory table:\n"); - for(i = 0; i < entries; i++) { - uint64_t entry_start = unpack_lb64(mem->map[i].start); - uint64_t entry_size = unpack_lb64(mem->map[i].size); - const char *entry_type; - - switch (mem->map[i].type) { - case LB_MEM_RAM: entry_type="RAM"; break; - case LB_MEM_RESERVED: entry_type="RESERVED"; break; - case LB_MEM_ACPI: entry_type="ACPI"; break; - case LB_MEM_NVS: entry_type="NVS"; break; - case LB_MEM_UNUSABLE: entry_type="UNUSABLE"; break; - case LB_MEM_VENDOR_RSVD: entry_type="VENDOR RESERVED"; break; - case LB_MEM_TABLE: entry_type="CONFIGURATION TABLES"; break; - default: entry_type="UNKNOWN!"; break; - } - - printk(BIOS_DEBUG, "%2d. %016llx-%016llx: %s\n", - i, entry_start, entry_start+entry_size-1, entry_type); - - } -} - - -/* Routines to extract part so the coreboot table or - * information from the coreboot table after we have written it. - * Currently get_lb_mem relies on a global we can change the - * implementaiton. - */ -static struct lb_memory *mem_ranges = 0; -struct lb_memory *get_lb_mem(void) -{ - return mem_ranges; -} - -static void build_lb_mem_range(void *gp, struct device *dev, struct resource *res) -{ - struct lb_memory *mem = gp; - new_lb_memory_range(mem, LB_MEM_RAM, res->base, res->size); -} - -static struct lb_memory *build_lb_mem(struct lb_header *head) -{ - struct lb_memory *mem; - - /* Record where the lb memory ranges will live */ - mem = lb_memory(head); - mem_ranges = mem; - - /* FIXME: implement this */ - /* Build the raw table of memory */ - search_global_resources( - IORESOURCE_MEM | IORESOURCE_CACHEABLE, IORESOURCE_MEM | IORESOURCE_CACHEABLE, - build_lb_mem_range, mem); - /* FIXME: things die in cleanup_memory_ranges(), skip for now */ -// lb_cleanup_memory_ranges(mem); - return mem; -} - -static void lb_add_rsvd_range(void *gp, struct device *dev, struct resource *res) -{ - struct lb_memory *mem = gp; - lb_add_memory_range(mem, LB_MEM_RESERVED, res->base, res->size); -} - -static void add_lb_reserved(struct lb_memory *mem) -{ - /* Add reserved ranges */ - search_global_resources( - IORESOURCE_MEM | IORESOURCE_RESERVE, IORESOURCE_MEM | IORESOURCE_RESERVE, - lb_add_rsvd_range, mem); -} - -unsigned long write_coreboot_table( - unsigned long table_start, unsigned long table_end) -{ - struct lb_header *head; - struct lb_memory *mem; - unsigned long fini; - - printk(BIOS_DEBUG, "table_start: 0x%lx, table_end: 0x%lx\n", - table_start, table_end); - head = lb_table_init(table_start); - - table_end = (unsigned long) head + head->table_bytes; - - /* FIXME(dhendrix): do we need this? */ - printk(BIOS_DEBUG, "Adjust table_end from 0x%08lx to ", table_end); - table_end += 0xfff; // 4K aligned - table_end &= ~0xfff; - printk(BIOS_DEBUG, "0x%08lx \n", table_end); - -#if CONFIG_USE_OPTION_TABLE - { - struct cmos_option_table *option_table = cbfs_get_file_content( - CBFS_DEFAULT_MEDIA, "cmos_layout.bin", - CBFS_COMPONENT_CMOS_LAYOUT); - if (option_table) { - struct lb_record *rec_dest = lb_new_record(head); - /* Copy the option config table, it's already a lb_record... */ - memcpy(rec_dest, option_table, option_table->size); - /* Create cmos checksum entry in coreboot table */ - lb_cmos_checksum(head); - } else { - printk(BIOS_ERR, "cmos_layout.bin could not be found!\n"); - } - } -#endif - /* Record where RAM is located */ - /* FIXME(dhendrix): add global resources */ - printk(BIOS_DEBUG, "%s: head: 0x%p\n", __func__, head); - mem = build_lb_mem(head); - /* FIXME: we seem to get a bogus return value */ - printk(BIOS_DEBUG, "%s: mem: 0x%p\n", __func__, mem); - if ((unsigned long)mem < CONFIG_RAMBASE) { - printk(BIOS_DEBUG, "%s: mem < CONFIG_RAMBASE\n" , __func__); - while (1); - } - - /* Record the mptable and the the lb_table (This will be adjusted later) */ - lb_add_memory_range(mem, LB_MEM_TABLE, - table_start, table_end - table_start); - - /* Record the pirq table, acpi tables, and maybe the mptable */ - lb_add_memory_range(mem, LB_MEM_TABLE, - table_start, table_end - table_start); - - printk(BIOS_DEBUG, "Adding high table area\n"); - // should this be LB_MEM_ACPI? - lb_add_memory_range(mem, LB_MEM_TABLE, - table_start, table_end - table_start); - - /* Add reserved regions */ - add_lb_reserved(mem); - - lb_dump_memory_ranges(mem); - - /* Note: - * I assume that there is always memory at immediately after - * the table_end. This means that after I setup the coreboot table. - * I can trivially fixup the reserved memory ranges to hold the correct - * size of the coreboot table. - */ - - /* FIXME(dhendrix): Most of these do nothing at the moment */ - /* Record our motherboard */ - lb_mainboard(head); - /* Record the serial port, if present */ - lb_serial(head); - /* Record our console setup */ - lb_console(head); - /* Record our various random string information */ - lb_strings(head); - /* Record our framebuffer */ - lb_framebuffer(head); -#if CONFIG_CHROMEOS - /* Record our GPIO settings (ChromeOS specific) */ - lb_gpios(head); - -#if 0 - /* pass along the VDAT buffer adress */ - lb_vdat(head); - - /* pass along VBNV offsets in CMOS */ - lb_vbnv(head); -#endif -#endif - add_cbmem_pointers(head); - - /* Remember where my valid memory ranges are */ - fini = lb_table_fini(head, 1); - printk(BIOS_DEBUG, "%s: DONE: fini is 0x%lx\n", __func__, fini); - return fini; - -} diff --git a/src/arch/armv7/boot/tables.c b/src/arch/armv7/boot/tables.c index e9fb6ab..0fc7399 100644 --- a/src/arch/armv7/boot/tables.c +++ b/src/arch/armv7/boot/tables.c @@ -23,11 +23,12 @@ #include <cpu/cpu.h> #include <boot/tables.h> #include <boot/coreboot_tables.h> -#include <arch/coreboot_tables.h> #include <string.h> #include <cbmem.h> #include <lib.h> +#define MAX_COREBOOT_TABLE_SIZE (8 * 1024) + /* * TODO: "High" tables are a convention used on x86. Maybe we can * clean up that naming at some point. @@ -41,12 +42,10 @@ void cbmem_arch_init(void) struct lb_memory *write_tables(void) { - unsigned long table_pointer; + unsigned long table_pointer, new_table_pointer; if (!high_tables_base) { - printk(BIOS_ERR, "ERROR: coreboot_tables_base is not set.\n"); - // Are there any boards without? - // Stepan thinks we should die() here! + printk(BIOS_ERR, "ERROR: high_tables_base is not set.\n"); } printk(BIOS_DEBUG, "high_tables_base: %llx.\n", high_tables_base); @@ -55,21 +54,25 @@ struct lb_memory *write_tables(void) table_pointer = (unsigned long)cbmem_add(CBMEM_ID_CBTABLE, MAX_COREBOOT_TABLE_SIZE); - if (table_pointer) { - unsigned long new_table_pointer; - new_table_pointer = write_coreboot_table(table_pointer, - high_tables_size); - if (table_pointer > (table_pointer + MAX_COREBOOT_TABLE_SIZE)) { - printk(BIOS_ERR, "%s: coreboot table didn't fit (%lx)\n", - __func__, new_table_pointer - table_pointer); - } - printk(BIOS_DEBUG, "coreboot table: %ld bytes.\n", - new_table_pointer - table_pointer); + if (!table_pointer) { + printk(BIOS_ERR, "Could not add CBMEM for coreboot table.\n"); + return NULL; } + new_table_pointer = write_coreboot_table(0UL, 0UL, + table_pointer, table_pointer); + + if (new_table_pointer > (table_pointer + MAX_COREBOOT_TABLE_SIZE)) { + printk(BIOS_ERR, "coreboot table didn't fit (%lx/%x bytes)\n", + new_table_pointer - table_pointer, MAX_COREBOOT_TABLE_SIZE); + } + + printk(BIOS_DEBUG, "coreboot table: %ld bytes.\n", + new_table_pointer - table_pointer); + post_code(0x9e); - // Remove before sending upstream + /* Print CBMEM sections */ cbmem_list(); return get_lb_mem(); diff --git a/src/arch/armv7/include/arch/coreboot_tables.h b/src/arch/armv7/include/arch/coreboot_tables.h deleted file mode 100644 index c5eacf8..0000000 --- a/src/arch/armv7/include/arch/coreboot_tables.h +++ /dev/null @@ -1,31 +0,0 @@ -#ifndef COREBOOT_TABLE_H -#define COREBOOT_TABLE_H - -#include <boot/coreboot_tables.h> - -#define MAX_COREBOOT_TABLE_SIZE (8 * 1024) - -/* This file holds function prototypes for building the coreboot table. */ -unsigned long write_coreboot_table( - unsigned long table_start, unsigned long table_end); - -void lb_memory_range(struct lb_memory *mem, - uint32_t type, uint64_t start, uint64_t size); - -void lb_add_memory_range(struct lb_memory *mem, - uint32_t type, uint64_t start, uint64_t size); - -void fill_lb_gpios(struct lb_gpios *gpios); - -/* Routines to extract part so the coreboot table or information - * from the coreboot table. - */ -struct lb_memory *get_lb_mem(void); - -extern struct cmos_option_table option_table; - -/* defined by mainboard.c if the mainboard requires extra resources */ -int add_mainboard_resources(struct lb_memory *mem); -int add_northbridge_resources(struct lb_memory *mem); - -#endif /* COREBOOT_TABLE_H */ diff --git a/src/arch/x86/boot/Makefile.inc b/src/arch/x86/boot/Makefile.inc index 9c18043..7b67e49 100644 --- a/src/arch/x86/boot/Makefile.inc +++ b/src/arch/x86/boot/Makefile.inc @@ -1,5 +1,4 @@ ramstage-y += boot.c -ramstage-y += coreboot_table.c ramstage-$(CONFIG_MULTIBOOT) += multiboot.c ramstage-y += gdt.c ramstage-y += tables.c diff --git a/src/arch/x86/boot/coreboot_table.c b/src/arch/x86/boot/coreboot_table.c deleted file mode 100644 index a456484..0000000 --- a/src/arch/x86/boot/coreboot_table.c +++ /dev/null @@ -1,730 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2003-2004 Eric Biederman - * Copyright (C) 2005-2010 coresystems GmbH - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, - * MA 02110-1301 USA - */ - -#include <console/console.h> -#include <ip_checksum.h> -#include <boot/tables.h> -#include <boot/coreboot_tables.h> -#include <arch/coreboot_tables.h> -#include <string.h> -#include <version.h> -#include <device/device.h> -#include <stdlib.h> -#include <cbfs.h> -#include <cbmem.h> -#if CONFIG_USE_OPTION_TABLE -#include <option_table.h> -#endif -#if CONFIG_CHROMEOS -#include <arch/acpi.h> -#include <vendorcode/google/chromeos/chromeos.h> -#include <vendorcode/google/chromeos/gnvs.h> -#endif - -static struct lb_header *lb_table_init(unsigned long addr) -{ - struct lb_header *header; - - /* 16 byte align the address */ - addr += 15; - addr &= ~15; - - header = (void *)addr; - header->signature[0] = 'L'; - header->signature[1] = 'B'; - header->signature[2] = 'I'; - header->signature[3] = 'O'; - header->header_bytes = sizeof(*header); - header->header_checksum = 0; - header->table_bytes = 0; - header->table_checksum = 0; - header->table_entries = 0; - return header; -} - -static struct lb_record *lb_first_record(struct lb_header *header) -{ - struct lb_record *rec; - rec = (void *)(((char *)header) + sizeof(*header)); - return rec; -} - -static struct lb_record *lb_last_record(struct lb_header *header) -{ - struct lb_record *rec; - rec = (void *)(((char *)header) + sizeof(*header) + header->table_bytes); - return rec; -} - -#if 0 -static struct lb_record *lb_next_record(struct lb_record *rec) -{ - rec = (void *)(((char *)rec) + rec->size); - return rec; -} -#endif - -static struct lb_record *lb_new_record(struct lb_header *header) -{ - struct lb_record *rec; - rec = lb_last_record(header); - if (header->table_entries) { - header->table_bytes += rec->size; - } - rec = lb_last_record(header); - header->table_entries++; - rec->tag = LB_TAG_UNUSED; - rec->size = sizeof(*rec); - return rec; -} - - -static struct lb_memory *lb_memory(struct lb_header *header) -{ - struct lb_record *rec; - struct lb_memory *mem; - rec = lb_new_record(header); - mem = (struct lb_memory *)rec; - mem->tag = LB_TAG_MEMORY; - mem->size = sizeof(*mem); - return mem; -} - -static struct lb_serial *lb_serial(struct lb_header *header) -{ -#if CONFIG_CONSOLE_SERIAL8250 - struct lb_record *rec; - struct lb_serial *serial; - rec = lb_new_record(header); - serial = (struct lb_serial *)rec; - serial->tag = LB_TAG_SERIAL; - serial->size = sizeof(*serial); - serial->type = LB_SERIAL_TYPE_IO_MAPPED; - serial->baseaddr = CONFIG_TTYS0_BASE; - serial->baud = CONFIG_TTYS0_BAUD; - return serial; -#elif CONFIG_CONSOLE_SERIAL8250MEM - if (uartmem_getbaseaddr()) { - struct lb_record *rec; - struct lb_serial *serial; - rec = lb_new_record(header); - serial = (struct lb_serial *)rec; - serial->tag = LB_TAG_SERIAL; - serial->size = sizeof(*serial); - serial->type = LB_SERIAL_TYPE_MEMORY_MAPPED; - serial->baseaddr = uartmem_getbaseaddr(); - serial->baud = CONFIG_TTYS0_BAUD; - return serial; - } else { - return NULL; - } -#else - return NULL; -#endif -} - -#if CONFIG_CONSOLE_SERIAL8250 || CONFIG_CONSOLE_SERIAL8250MEM || \ - CONFIG_CONSOLE_LOGBUF || CONFIG_USBDEBUG -static void add_console(struct lb_header *header, u16 consoletype) -{ - struct lb_console *console; - - console = (struct lb_console *)lb_new_record(header); - console->tag = LB_TAG_CONSOLE; - console->size = sizeof(*console); - console->type = consoletype; -} -#endif - -static void lb_console(struct lb_header *header) -{ -#if CONFIG_CONSOLE_SERIAL8250 - add_console(header, LB_TAG_CONSOLE_SERIAL8250); -#endif -#if CONFIG_CONSOLE_SERIAL8250MEM - add_console(header, LB_TAG_CONSOLE_SERIAL8250MEM); -#endif -#if CONFIG_CONSOLE_LOGBUF - add_console(header, LB_TAG_CONSOLE_LOGBUF); -#endif -#if CONFIG_USBDEBUG - add_console(header, LB_TAG_CONSOLE_EHCI); -#endif -} - -static void lb_framebuffer(struct lb_header *header) -{ -#if CONFIG_FRAMEBUFFER_KEEP_VESA_MODE || CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT - void fill_lb_framebuffer(struct lb_framebuffer *framebuffer); - int vbe_mode_info_valid(void); - - // If there isn't any mode info to put in the table, don't ask for it - // to be filled with junk. - if (!vbe_mode_info_valid()) - return; - struct lb_framebuffer *framebuffer; - framebuffer = (struct lb_framebuffer *)lb_new_record(header); - framebuffer->tag = LB_TAG_FRAMEBUFFER; - framebuffer->size = sizeof(*framebuffer); - fill_lb_framebuffer(framebuffer); -#endif -} - -#if CONFIG_CHROMEOS -static void lb_gpios(struct lb_header *header) -{ - struct lb_gpios *gpios; - gpios = (struct lb_gpios *)lb_new_record(header); - gpios->tag = LB_TAG_GPIO; - gpios->size = sizeof(*gpios); - gpios->count = 0; - fill_lb_gpios(gpios); -} - -static void lb_vdat(struct lb_header *header) -{ - struct lb_vdat* vdat; - - vdat = (struct lb_vdat *)lb_new_record(header); - vdat->tag = LB_TAG_VDAT; - vdat->size = sizeof(*vdat); - acpi_get_vdat_info(&vdat->vdat_addr, &vdat->vdat_size); -} - -static void lb_vbnv(struct lb_header *header) -{ - struct lb_vbnv* vbnv; - - vbnv = (struct lb_vbnv *)lb_new_record(header); - vbnv->tag = LB_TAG_VBNV; - vbnv->size = sizeof(*vbnv); - vbnv->vbnv_start = CONFIG_VBNV_OFFSET + 14; - vbnv->vbnv_size = CONFIG_VBNV_SIZE; -} - -#if CONFIG_VBOOT_VERIFY_FIRMWARE -static void lb_vboot_handoff(struct lb_header *header) -{ - void *addr; - uint32_t size; - struct lb_vboot_handoff* vbho; - - if (vboot_get_handoff_info(&addr, &size)) - return; - - vbho = (struct lb_vboot_handoff *)lb_new_record(header); - vbho->tag = LB_TAB_VBOOT_HANDOFF; - vbho->size = sizeof(*vbho); - vbho->vboot_handoff_addr = addr; - vbho->vboot_handoff_size = size; -} -#else -static inline void lb_vboot_handoff(struct lb_header *header) {} -#endif /* CONFIG_VBOOT_VERIFY_FIRMWARE */ -#endif /* CONFIG_CHROMEOS */ - -static void add_cbmem_pointers(struct lb_header *header) -{ - /* - * These CBMEM sections' addresses are included in the coreboot table - * with the appropriate tags. - */ - const struct section_id { - int cbmem_id; - int table_tag; - } section_ids[] = { - {CBMEM_ID_TIMESTAMP, LB_TAG_TIMESTAMPS}, - {CBMEM_ID_CONSOLE, LB_TAG_CBMEM_CONSOLE} - }; - int i; - - for (i = 0; i < ARRAY_SIZE(section_ids); i++) { - const struct section_id *sid = section_ids + i; - struct lb_cbmem_ref *cbmem_ref; - void *cbmem_addr = cbmem_find(sid->cbmem_id); - - if (!cbmem_addr) - continue; /* This section is not present */ - - cbmem_ref = (struct lb_cbmem_ref *)lb_new_record(header); - if (!cbmem_ref) { - printk(BIOS_ERR, "No more room in coreboot table!\n"); - break; - } - cbmem_ref->tag = sid->table_tag; - cbmem_ref->size = sizeof(*cbmem_ref); - cbmem_ref->cbmem_addr = (unsigned long)cbmem_addr; - } -} - -static struct lb_mainboard *lb_mainboard(struct lb_header *header) -{ - struct lb_record *rec; - struct lb_mainboard *mainboard; - rec = lb_new_record(header); - mainboard = (struct lb_mainboard *)rec; - mainboard->tag = LB_TAG_MAINBOARD; - - mainboard->size = (sizeof(*mainboard) + - strlen(mainboard_vendor) + 1 + - strlen(mainboard_part_number) + 1 + - 3) & ~3; - - mainboard->vendor_idx = 0; - mainboard->part_number_idx = strlen(mainboard_vendor) + 1; - - memcpy(mainboard->strings + mainboard->vendor_idx, - mainboard_vendor, strlen(mainboard_vendor) + 1); - memcpy(mainboard->strings + mainboard->part_number_idx, - mainboard_part_number, strlen(mainboard_part_number) + 1); - - return mainboard; -} - -#if CONFIG_USE_OPTION_TABLE -static struct cmos_checksum *lb_cmos_checksum(struct lb_header *header) -{ - struct lb_record *rec; - struct cmos_checksum *cmos_checksum; - rec = lb_new_record(header); - cmos_checksum = (struct cmos_checksum *)rec; - cmos_checksum->tag = LB_TAG_OPTION_CHECKSUM; - - cmos_checksum->size = (sizeof(*cmos_checksum)); - - cmos_checksum->range_start = LB_CKS_RANGE_START * 8; - cmos_checksum->range_end = ( LB_CKS_RANGE_END * 8 ) + 7; - cmos_checksum->location = LB_CKS_LOC * 8; - cmos_checksum->type = CHECKSUM_PCBIOS; - - return cmos_checksum; -} -#endif - -static void lb_strings(struct lb_header *header) -{ - static const struct { - uint32_t tag; - const char *string; - } strings[] = { - { LB_TAG_VERSION, coreboot_version, }, - { LB_TAG_EXTRA_VERSION, coreboot_extra_version, }, - { LB_TAG_BUILD, coreboot_build, }, - { LB_TAG_COMPILE_TIME, coreboot_compile_time, }, - { LB_TAG_COMPILE_BY, coreboot_compile_by, }, - { LB_TAG_COMPILE_HOST, coreboot_compile_host, }, - { LB_TAG_COMPILE_DOMAIN, coreboot_compile_domain, }, - { LB_TAG_COMPILER, coreboot_compiler, }, - { LB_TAG_LINKER, coreboot_linker, }, - { LB_TAG_ASSEMBLER, coreboot_assembler, }, - }; - unsigned int i; - for(i = 0; i < ARRAY_SIZE(strings); i++) { - struct lb_string *rec; - size_t len; - rec = (struct lb_string *)lb_new_record(header); - len = strlen(strings[i].string); - rec->tag = strings[i].tag; - rec->size = (sizeof(*rec) + len + 1 + 3) & ~3; - memcpy(rec->string, strings[i].string, len+1); - } - -} - -static struct lb_forward *lb_forward(struct lb_header *header, struct lb_header *next_header) -{ - struct lb_record *rec; - struct lb_forward *forward; - rec = lb_new_record(header); - forward = (struct lb_forward *)rec; - forward->tag = LB_TAG_FORWARD; - forward->size = sizeof(*forward); - forward->forward = (uint64_t)(unsigned long)next_header; - return forward; -} - -static void lb_memory_range(struct lb_memory *mem, - uint32_t type, uint64_t start, uint64_t size) -{ - int entries; - entries = (mem->size - sizeof(*mem))/sizeof(mem->map[0]); - mem->map[entries].start = pack_lb64(start); - mem->map[entries].size = pack_lb64(size); - mem->map[entries].type = type; - mem->size += sizeof(mem->map[0]); -} - -static void lb_reserve_table_memory(struct lb_header *head) -{ -/* Dynamic cbmem has already reserved the memory where the coreboot tables - * reside. Therefore, there is nothing to fix up. */ -#if !CONFIG_DYNAMIC_CBMEM - struct lb_record *last_rec; - struct lb_memory *mem; - uint64_t start; - uint64_t end; - int i, entries; - - last_rec = lb_last_record(head); - mem = get_lb_mem(); - start = (unsigned long)head; - end = (unsigned long)last_rec; - entries = (mem->size - sizeof(*mem))/sizeof(mem->map[0]); - /* Resize the right two memory areas so this table is in - * a reserved area of memory. Everything has been carefully - * setup so that is all we need to do. - */ - for(i = 0; i < entries; i++ ) { - uint64_t map_start = unpack_lb64(mem->map[i].start); - uint64_t map_end = map_start + unpack_lb64(mem->map[i].size); - /* Does this area need to be expanded? */ - if (map_end == start) { - mem->map[i].size = pack_lb64(end - map_start); - } - /* Does this area need to be contracted? */ - else if (map_start == start) { - mem->map[i].start = pack_lb64(end); - mem->map[i].size = pack_lb64(map_end - end); - } - } -#endif -} - -static unsigned long lb_table_fini(struct lb_header *head, int fixup) -{ - struct lb_record *rec, *first_rec; - rec = lb_last_record(head); - if (head->table_entries) { - head->table_bytes += rec->size; - } - - if (fixup) - lb_reserve_table_memory(head); - - first_rec = lb_first_record(head); - head->table_checksum = compute_ip_checksum(first_rec, head->table_bytes); - head->header_checksum = 0; - head->header_checksum = compute_ip_checksum(head, sizeof(*head)); - printk(BIOS_DEBUG, - "Wrote coreboot table at: %p, 0x%x bytes, checksum %x\n", - head, head->table_bytes, head->table_checksum); - return (unsigned long)rec + rec->size; -} - -static void lb_cleanup_memory_ranges(struct lb_memory *mem) -{ - int entries; - int i, j; - entries = (mem->size - sizeof(*mem))/sizeof(mem->map[0]); - - /* Sort the lb memory ranges */ - for(i = 0; i < entries; i++) { - uint64_t entry_start = unpack_lb64(mem->map[i].start); - for(j = i + 1; j < entries; j++) { - uint64_t temp_start = unpack_lb64(mem->map[j].start); - if (temp_start < entry_start) { - struct lb_memory_range tmp; - tmp = mem->map[i]; - mem->map[i] = mem->map[j]; - mem->map[j] = tmp; - } - } - } - - /* Merge adjacent entries */ - for(i = 0; (i + 1) < entries; i++) { - uint64_t start, end, nstart, nend; - if (mem->map[i].type != mem->map[i + 1].type) { - continue; - } - start = unpack_lb64(mem->map[i].start); - end = start + unpack_lb64(mem->map[i].size); - nstart = unpack_lb64(mem->map[i + 1].start); - nend = nstart + unpack_lb64(mem->map[i + 1].size); - if ((start <= nstart) && (end >= nstart)) { - if (start > nstart) { - start = nstart; - } - if (end < nend) { - end = nend; - } - /* Record the new region size */ - mem->map[i].start = pack_lb64(start); - mem->map[i].size = pack_lb64(end - start); - - /* Delete the entry I have merged with */ - memmove(&mem->map[i + 1], &mem->map[i + 2], - ((entries - i - 2) * sizeof(mem->map[0]))); - mem->size -= sizeof(mem->map[0]); - entries -= 1; - /* See if I can merge with the next entry as well */ - i -= 1; - } - } -} - -static void lb_remove_memory_range(struct lb_memory *mem, - uint64_t start, uint64_t size) -{ - uint64_t end; - int entries; - int i; - - end = start + size; - entries = (mem->size - sizeof(*mem))/sizeof(mem->map[0]); - - /* Remove a reserved area from the memory map */ - for(i = 0; i < entries; i++) { - uint64_t map_start = unpack_lb64(mem->map[i].start); - uint64_t map_end = map_start + unpack_lb64(mem->map[i].size); - if ((start <= map_start) && (end >= map_end)) { - /* Remove the completely covered range */ - memmove(&mem->map[i], &mem->map[i + 1], - ((entries - i - 1) * sizeof(mem->map[0]))); - mem->size -= sizeof(mem->map[0]); - entries -= 1; - /* Since the index will disappear revisit what will appear here */ - i -= 1; - } - else if ((start > map_start) && (end < map_end)) { - /* Split the memory range */ - memmove(&mem->map[i + 1], &mem->map[i], - ((entries - i) * sizeof(mem->map[0]))); - mem->size += sizeof(mem->map[0]); - entries += 1; - /* Update the first map entry */ - mem->map[i].size = pack_lb64(start - map_start); - /* Update the second map entry */ - mem->map[i + 1].start = pack_lb64(end); - mem->map[i + 1].size = pack_lb64(map_end - end); - /* Don't bother with this map entry again */ - i += 1; - } - else if ((start <= map_start) && (end > map_start)) { - /* Shrink the start of the memory range */ - mem->map[i].start = pack_lb64(end); - mem->map[i].size = pack_lb64(map_end - end); - } - else if ((start < map_end) && (start > map_start)) { - /* Shrink the end of the memory range */ - mem->map[i].size = pack_lb64(start - map_start); - } - } -} - -void lb_add_memory_range(struct lb_memory *mem, - uint32_t type, uint64_t start, uint64_t size) -{ - lb_remove_memory_range(mem, start, size); - lb_memory_range(mem, type, start, size); - lb_cleanup_memory_ranges(mem); -} - -static void lb_dump_memory_ranges(struct lb_memory *mem) -{ - int entries; - int i; - entries = (mem->size - sizeof(*mem))/sizeof(mem->map[0]); - - printk(BIOS_DEBUG, "coreboot memory table:\n"); - for(i = 0; i < entries; i++) { - uint64_t entry_start = unpack_lb64(mem->map[i].start); - uint64_t entry_size = unpack_lb64(mem->map[i].size); - const char *entry_type; - - switch (mem->map[i].type) { - case LB_MEM_RAM: entry_type="RAM"; break; - case LB_MEM_RESERVED: entry_type="RESERVED"; break; - case LB_MEM_ACPI: entry_type="ACPI"; break; - case LB_MEM_NVS: entry_type="NVS"; break; - case LB_MEM_UNUSABLE: entry_type="UNUSABLE"; break; - case LB_MEM_VENDOR_RSVD: entry_type="VENDOR RESERVED"; break; - case LB_MEM_TABLE: entry_type="CONFIGURATION TABLES"; break; - default: entry_type="UNKNOWN!"; break; - } - - printk(BIOS_DEBUG, "%2d. %016llx-%016llx: %s\n", - i, entry_start, entry_start+entry_size-1, entry_type); - - } -} - - -/* Routines to extract part so the coreboot table or - * information from the coreboot table after we have written it. - * Currently get_lb_mem relies on a global we can change the - * implementaiton. - */ -static struct lb_memory *mem_ranges = 0; -struct lb_memory *get_lb_mem(void) -{ - return mem_ranges; -} - -static void build_lb_mem_range(void *gp, struct device *dev, struct resource *res) -{ - struct lb_memory *mem = gp; - lb_memory_range(mem, LB_MEM_RAM, res->base, res->size); -} - -static struct lb_memory *build_lb_mem(struct lb_header *head) -{ - struct lb_memory *mem; - - /* Record where the lb memory ranges will live */ - mem = lb_memory(head); - mem_ranges = mem; - - /* Build the raw table of memory */ - search_global_resources( - IORESOURCE_MEM | IORESOURCE_CACHEABLE, IORESOURCE_MEM | IORESOURCE_CACHEABLE, - build_lb_mem_range, mem); - lb_cleanup_memory_ranges(mem); - return mem; -} - -static void lb_add_rsvd_range(void *gp, struct device *dev, struct resource *res) -{ - struct lb_memory *mem = gp; - lb_add_memory_range(mem, LB_MEM_RESERVED, res->base, res->size); -} - -static void add_lb_reserved(struct lb_memory *mem) -{ - /* Add reserved ranges */ - search_global_resources( - IORESOURCE_MEM | IORESOURCE_RESERVE, IORESOURCE_MEM | IORESOURCE_RESERVE, - lb_add_rsvd_range, mem); -} - -unsigned long write_coreboot_table( - unsigned long low_table_start, unsigned long low_table_end, - unsigned long rom_table_start, unsigned long rom_table_end) -{ - struct lb_header *head; - struct lb_memory *mem; - - printk(BIOS_DEBUG, "Writing high table forward entry at 0x%08lx\n", - low_table_end); - head = lb_table_init(low_table_end); - lb_forward(head, (struct lb_header*)rom_table_end); - - low_table_end = (unsigned long) lb_table_fini(head, 0); - printk(BIOS_DEBUG, "New low_table_end: 0x%08lx\n", low_table_end); - printk(BIOS_DEBUG, "Now going to write high coreboot table at 0x%08lx\n", - rom_table_end); - - head = lb_table_init(rom_table_end); - rom_table_end = (unsigned long)head; - printk(BIOS_DEBUG, "rom_table_end = 0x%08lx\n", rom_table_end); - - printk(BIOS_DEBUG, "Adjust low_table_end from 0x%08lx to ", low_table_end); - low_table_end += 0xfff; // 4K aligned - low_table_end &= ~0xfff; - printk(BIOS_DEBUG, "0x%08lx \n", low_table_end); - - /* The Linux kernel assumes this region is reserved */ - printk(BIOS_DEBUG, "Adjust rom_table_end from 0x%08lx to ", rom_table_end); - rom_table_end += 0xffff; // 64K align - rom_table_end &= ~0xffff; - printk(BIOS_DEBUG, "0x%08lx \n", rom_table_end); - -#if CONFIG_USE_OPTION_TABLE - { - struct cmos_option_table *option_table = cbfs_get_file_content( - CBFS_DEFAULT_MEDIA, "cmos_layout.bin", - CBFS_COMPONENT_CMOS_LAYOUT); - if (option_table) { - struct lb_record *rec_dest = lb_new_record(head); - /* Copy the option config table, it's already a lb_record... */ - memcpy(rec_dest, option_table, option_table->size); - /* Create cmos checksum entry in coreboot table */ - lb_cmos_checksum(head); - } else { - printk(BIOS_ERR, "cmos_layout.bin could not be found!\n"); - } - } -#endif - /* Record where RAM is located */ - mem = build_lb_mem(head); - - /* Record the mptable and the the lb_table (This will be adjusted later) */ - lb_add_memory_range(mem, LB_MEM_TABLE, - low_table_start, low_table_end - low_table_start); - - /* Record the pirq table, acpi tables, and maybe the mptable. However, - * these only need to be added when the rom_table is sitting below - * 1MiB. If it isn't that means high tables are being written. - * The code below handles high tables correctly. */ - if (rom_table_end <= (1 << 20)) - lb_add_memory_range(mem, LB_MEM_TABLE, - rom_table_start, rom_table_end-rom_table_start); - -#if CONFIG_DYNAMIC_CBMEM - cbmem_add_lb_mem(mem); -#else /* CONFIG_DYNAMIC_CBMEM */ - lb_add_memory_range(mem, LB_MEM_TABLE, - high_tables_base, high_tables_size); -#endif /* CONFIG_DYNAMIC_CBMEM */ - - /* Add reserved regions */ - add_lb_reserved(mem); - - lb_dump_memory_ranges(mem); - - /* Note: - * I assume that there is always memory at immediately after - * the low_table_end. This means that after I setup the coreboot table. - * I can trivially fixup the reserved memory ranges to hold the correct - * size of the coreboot table. - */ - - /* Record our motherboard */ - lb_mainboard(head); - /* Record the serial port, if present */ - lb_serial(head); - /* Record our console setup */ - lb_console(head); - /* Record our various random string information */ - lb_strings(head); - /* Record our framebuffer */ - lb_framebuffer(head); - -#if CONFIG_CHROMEOS - /* Record our GPIO settings (ChromeOS specific) */ - lb_gpios(head); - - /* pass along the VDAT buffer adress */ - lb_vdat(head); - - /* pass along VBNV offsets in CMOS */ - lb_vbnv(head); - - /* pass along the vboot_handoff address. */ - lb_vboot_handoff(head); -#endif - add_cbmem_pointers(head); - - /* Remember where my valid memory ranges are */ - return lb_table_fini(head, 1); - -} diff --git a/src/arch/x86/boot/multiboot.c b/src/arch/x86/boot/multiboot.c index 4059f27..a043e60 100644 --- a/src/arch/x86/boot/multiboot.c +++ b/src/arch/x86/boot/multiboot.c @@ -23,7 +23,6 @@ #include <device/resource.h> #include <console/console.h> #include <boot/coreboot_tables.h> -#include <arch/coreboot_tables.h> struct multiboot_info *mbi = NULL; diff --git a/src/arch/x86/boot/tables.c b/src/arch/x86/boot/tables.c index d842e73..4448333 100644 --- a/src/arch/x86/boot/tables.c +++ b/src/arch/x86/boot/tables.c @@ -23,7 +23,6 @@ #include <cpu/cpu.h> #include <boot/tables.h> #include <boot/coreboot_tables.h> -#include <arch/coreboot_tables.h> #include <arch/pirq_routing.h> #include <arch/smp/mpspec.h> #include <arch/acpi.h> @@ -254,7 +253,7 @@ struct lb_memory *write_tables(void) write_multiboot_info(rom_table_end); #endif - // Remove before sending upstream + /* Print CBMEM sections */ cbmem_list(); return get_lb_mem(); diff --git a/src/arch/x86/include/arch/coreboot_tables.h b/src/arch/x86/include/arch/coreboot_tables.h deleted file mode 100644 index a8deeed..0000000 --- a/src/arch/x86/include/arch/coreboot_tables.h +++ /dev/null @@ -1,21 +0,0 @@ -#ifndef COREBOOT_TABLE_H -#define COREBOOT_TABLE_H - -#include <boot/coreboot_tables.h> - -/* This file holds function prototypes for building the coreboot table. */ -unsigned long write_coreboot_table( - unsigned long low_table_start, unsigned long low_table_end, - unsigned long rom_table_start, unsigned long rom_table_end); - -void lb_add_memory_range(struct lb_memory *mem, - uint32_t type, uint64_t start, uint64_t size); - -/* Routines to extract part so the coreboot table or information - * from the coreboot table. - */ -struct lb_memory *get_lb_mem(void); - -void fill_lb_gpios(struct lb_gpios *gpios); - -#endif /* COREBOOT_TABLE_H */ diff --git a/src/include/boot/coreboot_tables.h b/src/include/boot/coreboot_tables.h index 71ad3f0..f624ac1 100644 --- a/src/include/boot/coreboot_tables.h +++ b/src/include/boot/coreboot_tables.h @@ -323,4 +323,20 @@ struct cmos_checksum { #define CHECKSUM_PCBIOS 1 }; +/* function prototypes for building the coreboot table */ + +unsigned long write_coreboot_table( + unsigned long low_table_start, unsigned long low_table_end, + unsigned long rom_table_start, unsigned long rom_table_end); + +void lb_add_memory_range(struct lb_memory *mem, + uint32_t type, uint64_t start, uint64_t size); + +/* Routines to extract part so the coreboot table or information + * from the coreboot table. + */ +struct lb_memory *get_lb_mem(void); + +void fill_lb_gpios(struct lb_gpios *gpios); + #endif /* COREBOOT_TABLES_H */ diff --git a/src/include/boot/tables.h b/src/include/boot/tables.h index 869da26..f9e91a4 100644 --- a/src/include/boot/tables.h +++ b/src/include/boot/tables.h @@ -2,7 +2,6 @@ #define BOOT_TABLES_H #include <boot/coreboot_tables.h> -#include <arch/coreboot_tables.h> struct lb_memory *write_tables(void); diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc index c0372c5..8eff2a4 100644 --- a/src/lib/Makefile.inc +++ b/src/lib/Makefile.inc @@ -54,6 +54,7 @@ romstage-$(CONFIG_ARCH_X86) += gcc.c ramstage-y += hardwaremain.c ramstage-y += selfboot.c +ramstage-y += coreboot_table.c ifneq ($(CONFIG_HAVE_ARCH_MEMSET),y) ramstage-y += memset.c endif diff --git a/src/lib/coreboot_table.c b/src/lib/coreboot_table.c new file mode 100644 index 0000000..84eb5a6 --- /dev/null +++ b/src/lib/coreboot_table.c @@ -0,0 +1,725 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2003-2004 Eric Biederman + * Copyright (C) 2005-2010 coresystems GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#include <console/console.h> +#include <ip_checksum.h> +#include <boot/coreboot_tables.h> +#include <string.h> +#include <version.h> +#include <device/device.h> +#include <stdlib.h> +#include <cbfs.h> +#include <cbmem.h> +#if CONFIG_USE_OPTION_TABLE +#include <option_table.h> +#endif +#if CONFIG_CHROMEOS +#if CONFIG_GENERATE_ACPI_TABLES +#include <arch/acpi.h> +#endif +#include <vendorcode/google/chromeos/chromeos.h> +#include <vendorcode/google/chromeos/gnvs.h> +#endif + +static struct lb_header *lb_table_init(unsigned long addr) +{ + struct lb_header *header; + + /* 16 byte align the address */ + addr += 15; + addr &= ~15; + + header = (void *)addr; + header->signature[0] = 'L'; + header->signature[1] = 'B'; + header->signature[2] = 'I'; + header->signature[3] = 'O'; + header->header_bytes = sizeof(*header); + header->header_checksum = 0; + header->table_bytes = 0; + header->table_checksum = 0; + header->table_entries = 0; + return header; +} + +static struct lb_record *lb_first_record(struct lb_header *header) +{ + struct lb_record *rec; + rec = (void *)(((char *)header) + sizeof(*header)); + return rec; +} + +static struct lb_record *lb_last_record(struct lb_header *header) +{ + struct lb_record *rec; + rec = (void *)(((char *)header) + sizeof(*header) + header->table_bytes); + return rec; +} + +static struct lb_record *lb_new_record(struct lb_header *header) +{ + struct lb_record *rec; + rec = lb_last_record(header); + if (header->table_entries) { + header->table_bytes += rec->size; + } + rec = lb_last_record(header); + header->table_entries++; + rec->tag = LB_TAG_UNUSED; + rec->size = sizeof(*rec); + return rec; +} + +static struct lb_memory *lb_memory(struct lb_header *header) +{ + struct lb_record *rec; + struct lb_memory *mem; + rec = lb_new_record(header); + mem = (struct lb_memory *)rec; + mem->tag = LB_TAG_MEMORY; + mem->size = sizeof(*mem); + return mem; +} + +static struct lb_serial *lb_serial(struct lb_header *header) +{ +#if CONFIG_CONSOLE_SERIAL8250 + struct lb_record *rec; + struct lb_serial *serial; + rec = lb_new_record(header); + serial = (struct lb_serial *)rec; + serial->tag = LB_TAG_SERIAL; + serial->size = sizeof(*serial); + serial->type = LB_SERIAL_TYPE_IO_MAPPED; + serial->baseaddr = CONFIG_TTYS0_BASE; + serial->baud = CONFIG_TTYS0_BAUD; + return serial; +#elif CONFIG_CONSOLE_SERIAL8250MEM || CONFIG_CONSOLE_SERIAL_UART + if (uartmem_getbaseaddr()) { + struct lb_record *rec; + struct lb_serial *serial; + rec = lb_new_record(header); + serial = (struct lb_serial *)rec; + serial->tag = LB_TAG_SERIAL; + serial->size = sizeof(*serial); + serial->type = LB_SERIAL_TYPE_MEMORY_MAPPED; + serial->baseaddr = uartmem_getbaseaddr(); + serial->baud = CONFIG_TTYS0_BAUD; + return serial; + } else { + return NULL; + } +#else + return NULL; +#endif +} + +#if CONFIG_CONSOLE_SERIAL || CONFIG_CONSOLE_LOGBUF || CONFIG_USBDEBUG +static void add_console(struct lb_header *header, u16 consoletype) +{ + struct lb_console *console; + + console = (struct lb_console *)lb_new_record(header); + console->tag = LB_TAG_CONSOLE; + console->size = sizeof(*console); + console->type = consoletype; +} +#endif + +static void lb_console(struct lb_header *header) +{ +#if CONFIG_CONSOLE_SERIAL8250 + add_console(header, LB_TAG_CONSOLE_SERIAL8250); +#endif +#if CONFIG_CONSOLE_SERIAL8250MEM || CONFIG_CONSOLE_SERIAL_UART + add_console(header, LB_TAG_CONSOLE_SERIAL8250MEM); +#endif +#if CONFIG_CONSOLE_LOGBUF + add_console(header, LB_TAG_CONSOLE_LOGBUF); +#endif +#if CONFIG_USBDEBUG + add_console(header, LB_TAG_CONSOLE_EHCI); +#endif +} + +static void lb_framebuffer(struct lb_header *header) +{ +#if CONFIG_FRAMEBUFFER_KEEP_VESA_MODE || CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT + void fill_lb_framebuffer(struct lb_framebuffer *framebuffer); + int vbe_mode_info_valid(void); + + // If there isn't any mode info to put in the table, don't ask for it + // to be filled with junk. + if (!vbe_mode_info_valid()) + return; + struct lb_framebuffer *framebuffer; + framebuffer = (struct lb_framebuffer *)lb_new_record(header); + framebuffer->tag = LB_TAG_FRAMEBUFFER; + framebuffer->size = sizeof(*framebuffer); + fill_lb_framebuffer(framebuffer); +#endif +} + +#if CONFIG_CHROMEOS +static void lb_gpios(struct lb_header *header) +{ + struct lb_gpios *gpios; + gpios = (struct lb_gpios *)lb_new_record(header); + gpios->tag = LB_TAG_GPIO; + gpios->size = sizeof(*gpios); + gpios->count = 0; + fill_lb_gpios(gpios); +} + +static void lb_vdat(struct lb_header *header) +{ +#if CONFIG_GENERATE_ACPI_TABLES + struct lb_vdat* vdat; + + vdat = (struct lb_vdat *)lb_new_record(header); + vdat->tag = LB_TAG_VDAT; + vdat->size = sizeof(*vdat); + acpi_get_vdat_info(&vdat->vdat_addr, &vdat->vdat_size); +#endif +} + +static void lb_vbnv(struct lb_header *header) +{ +#if CONFIG_PC80_SYSTEM + struct lb_vbnv* vbnv; + + vbnv = (struct lb_vbnv *)lb_new_record(header); + vbnv->tag = LB_TAG_VBNV; + vbnv->size = sizeof(*vbnv); + vbnv->vbnv_start = CONFIG_VBNV_OFFSET + 14; + vbnv->vbnv_size = CONFIG_VBNV_SIZE; +#endif +} + +#if CONFIG_VBOOT_VERIFY_FIRMWARE +static void lb_vboot_handoff(struct lb_header *header) +{ + void *addr; + uint32_t size; + struct lb_vboot_handoff* vbho; + + if (vboot_get_handoff_info(&addr, &size)) + return; + + vbho = (struct lb_vboot_handoff *)lb_new_record(header); + vbho->tag = LB_TAB_VBOOT_HANDOFF; + vbho->size = sizeof(*vbho); + vbho->vboot_handoff_addr = addr; + vbho->vboot_handoff_size = size; +} +#else +static inline void lb_vboot_handoff(struct lb_header *header) {} +#endif /* CONFIG_VBOOT_VERIFY_FIRMWARE */ +#endif /* CONFIG_CHROMEOS */ + +static void add_cbmem_pointers(struct lb_header *header) +{ + /* + * These CBMEM sections' addresses are included in the coreboot table + * with the appropriate tags. + */ + const struct section_id { + int cbmem_id; + int table_tag; + } section_ids[] = { + {CBMEM_ID_TIMESTAMP, LB_TAG_TIMESTAMPS}, + {CBMEM_ID_CONSOLE, LB_TAG_CBMEM_CONSOLE} + }; + int i; + + for (i = 0; i < ARRAY_SIZE(section_ids); i++) { + const struct section_id *sid = section_ids + i; + struct lb_cbmem_ref *cbmem_ref; + void *cbmem_addr = cbmem_find(sid->cbmem_id); + + if (!cbmem_addr) + continue; /* This section is not present */ + + cbmem_ref = (struct lb_cbmem_ref *)lb_new_record(header); + if (!cbmem_ref) { + printk(BIOS_ERR, "No more room in coreboot table!\n"); + break; + } + cbmem_ref->tag = sid->table_tag; + cbmem_ref->size = sizeof(*cbmem_ref); + cbmem_ref->cbmem_addr = (unsigned long)cbmem_addr; + } +} + +static struct lb_mainboard *lb_mainboard(struct lb_header *header) +{ + struct lb_record *rec; + struct lb_mainboard *mainboard; + rec = lb_new_record(header); + mainboard = (struct lb_mainboard *)rec; + mainboard->tag = LB_TAG_MAINBOARD; + + mainboard->size = (sizeof(*mainboard) + + strlen(mainboard_vendor) + 1 + + strlen(mainboard_part_number) + 1 + + 3) & ~3; + + mainboard->vendor_idx = 0; + mainboard->part_number_idx = strlen(mainboard_vendor) + 1; + + memcpy(mainboard->strings + mainboard->vendor_idx, + mainboard_vendor, strlen(mainboard_vendor) + 1); + memcpy(mainboard->strings + mainboard->part_number_idx, + mainboard_part_number, strlen(mainboard_part_number) + 1); + + return mainboard; +} + +#if CONFIG_USE_OPTION_TABLE +static struct cmos_checksum *lb_cmos_checksum(struct lb_header *header) +{ + struct lb_record *rec; + struct cmos_checksum *cmos_checksum; + rec = lb_new_record(header); + cmos_checksum = (struct cmos_checksum *)rec; + cmos_checksum->tag = LB_TAG_OPTION_CHECKSUM; + + cmos_checksum->size = (sizeof(*cmos_checksum)); + + cmos_checksum->range_start = LB_CKS_RANGE_START * 8; + cmos_checksum->range_end = ( LB_CKS_RANGE_END * 8 ) + 7; + cmos_checksum->location = LB_CKS_LOC * 8; + cmos_checksum->type = CHECKSUM_PCBIOS; + + return cmos_checksum; +} +#endif + +static void lb_strings(struct lb_header *header) +{ + static const struct { + uint32_t tag; + const char *string; + } strings[] = { + { LB_TAG_VERSION, coreboot_version, }, + { LB_TAG_EXTRA_VERSION, coreboot_extra_version, }, + { LB_TAG_BUILD, coreboot_build, }, + { LB_TAG_COMPILE_TIME, coreboot_compile_time, }, + { LB_TAG_COMPILE_BY, coreboot_compile_by, }, + { LB_TAG_COMPILE_HOST, coreboot_compile_host, }, + { LB_TAG_COMPILE_DOMAIN, coreboot_compile_domain, }, + { LB_TAG_COMPILER, coreboot_compiler, }, + { LB_TAG_LINKER, coreboot_linker, }, + { LB_TAG_ASSEMBLER, coreboot_assembler, }, + }; + unsigned int i; + for(i = 0; i < ARRAY_SIZE(strings); i++) { + struct lb_string *rec; + size_t len; + rec = (struct lb_string *)lb_new_record(header); + len = strlen(strings[i].string); + rec->tag = strings[i].tag; + rec->size = (sizeof(*rec) + len + 1 + 3) & ~3; + memcpy(rec->string, strings[i].string, len+1); + } + +} + +static struct lb_forward *lb_forward(struct lb_header *header, struct lb_header *next_header) +{ + struct lb_record *rec; + struct lb_forward *forward; + rec = lb_new_record(header); + forward = (struct lb_forward *)rec; + forward->tag = LB_TAG_FORWARD; + forward->size = sizeof(*forward); + forward->forward = (uint64_t)(unsigned long)next_header; + return forward; +} + +static void lb_memory_range(struct lb_memory *mem, + uint32_t type, uint64_t start, uint64_t size) +{ + int entries; + entries = (mem->size - sizeof(*mem))/sizeof(mem->map[0]); + mem->map[entries].start = pack_lb64(start); + mem->map[entries].size = pack_lb64(size); + mem->map[entries].type = type; + mem->size += sizeof(mem->map[0]); +} + +static void lb_reserve_table_memory(struct lb_header *head) +{ +/* Dynamic cbmem has already reserved the memory where the coreboot tables + * reside. Therefore, there is nothing to fix up. */ +#if !CONFIG_DYNAMIC_CBMEM + struct lb_record *last_rec; + struct lb_memory *mem; + uint64_t start; + uint64_t end; + int i, entries; + + last_rec = lb_last_record(head); + mem = get_lb_mem(); + start = (unsigned long)head; + end = (unsigned long)last_rec; + entries = (mem->size - sizeof(*mem))/sizeof(mem->map[0]); + /* Resize the right two memory areas so this table is in + * a reserved area of memory. Everything has been carefully + * setup so that is all we need to do. + */ + for(i = 0; i < entries; i++ ) { + uint64_t map_start = unpack_lb64(mem->map[i].start); + uint64_t map_end = map_start + unpack_lb64(mem->map[i].size); + /* Does this area need to be expanded? */ + if (map_end == start) { + mem->map[i].size = pack_lb64(end - map_start); + } + /* Does this area need to be contracted? */ + else if (map_start == start) { + mem->map[i].start = pack_lb64(end); + mem->map[i].size = pack_lb64(map_end - end); + } + } +#endif +} + +static unsigned long lb_table_fini(struct lb_header *head, int fixup) +{ + struct lb_record *rec, *first_rec; + rec = lb_last_record(head); + if (head->table_entries) { + head->table_bytes += rec->size; + } + + if (fixup) + lb_reserve_table_memory(head); + + first_rec = lb_first_record(head); + head->table_checksum = compute_ip_checksum(first_rec, head->table_bytes); + head->header_checksum = 0; + head->header_checksum = compute_ip_checksum(head, sizeof(*head)); + printk(BIOS_DEBUG, + "Wrote coreboot table at: %p, 0x%x bytes, checksum %x\n", + head, head->table_bytes, head->table_checksum); + return (unsigned long)rec + rec->size; +} + +static void lb_cleanup_memory_ranges(struct lb_memory *mem) +{ + int entries; + int i, j; + entries = (mem->size - sizeof(*mem))/sizeof(mem->map[0]); + + /* Sort the lb memory ranges */ + for(i = 0; i < entries; i++) { + uint64_t entry_start = unpack_lb64(mem->map[i].start); + for(j = i + 1; j < entries; j++) { + uint64_t temp_start = unpack_lb64(mem->map[j].start); + if (temp_start < entry_start) { + struct lb_memory_range tmp; + tmp = mem->map[i]; + mem->map[i] = mem->map[j]; + mem->map[j] = tmp; + } + } + } + + /* Merge adjacent entries */ + for(i = 0; (i + 1) < entries; i++) { + uint64_t start, end, nstart, nend; + if (mem->map[i].type != mem->map[i + 1].type) { + continue; + } + start = unpack_lb64(mem->map[i].start); + end = start + unpack_lb64(mem->map[i].size); + nstart = unpack_lb64(mem->map[i + 1].start); + nend = nstart + unpack_lb64(mem->map[i + 1].size); + if ((start <= nstart) && (end >= nstart)) { + if (start > nstart) { + start = nstart; + } + if (end < nend) { + end = nend; + } + /* Record the new region size */ + mem->map[i].start = pack_lb64(start); + mem->map[i].size = pack_lb64(end - start); + + /* Delete the entry I have merged with */ + memmove(&mem->map[i + 1], &mem->map[i + 2], + ((entries - i - 2) * sizeof(mem->map[0]))); + mem->size -= sizeof(mem->map[0]); + entries -= 1; + /* See if I can merge with the next entry as well */ + i -= 1; + } + } +} + +static void lb_remove_memory_range(struct lb_memory *mem, + uint64_t start, uint64_t size) +{ + uint64_t end; + int entries; + int i; + + end = start + size; + entries = (mem->size - sizeof(*mem))/sizeof(mem->map[0]); + + /* Remove a reserved area from the memory map */ + for(i = 0; i < entries; i++) { + uint64_t map_start = unpack_lb64(mem->map[i].start); + uint64_t map_end = map_start + unpack_lb64(mem->map[i].size); + if ((start <= map_start) && (end >= map_end)) { + /* Remove the completely covered range */ + memmove(&mem->map[i], &mem->map[i + 1], + ((entries - i - 1) * sizeof(mem->map[0]))); + mem->size -= sizeof(mem->map[0]); + entries -= 1; + /* Since the index will disappear revisit what will appear here */ + i -= 1; + } + else if ((start > map_start) && (end < map_end)) { + /* Split the memory range */ + memmove(&mem->map[i + 1], &mem->map[i], + ((entries - i) * sizeof(mem->map[0]))); + mem->size += sizeof(mem->map[0]); + entries += 1; + /* Update the first map entry */ + mem->map[i].size = pack_lb64(start - map_start); + /* Update the second map entry */ + mem->map[i + 1].start = pack_lb64(end); + mem->map[i + 1].size = pack_lb64(map_end - end); + /* Don't bother with this map entry again */ + i += 1; + } + else if ((start <= map_start) && (end > map_start)) { + /* Shrink the start of the memory range */ + mem->map[i].start = pack_lb64(end); + mem->map[i].size = pack_lb64(map_end - end); + } + else if ((start < map_end) && (start > map_start)) { + /* Shrink the end of the memory range */ + mem->map[i].size = pack_lb64(start - map_start); + } + } +} + +void lb_add_memory_range(struct lb_memory *mem, + uint32_t type, uint64_t start, uint64_t size) +{ + lb_remove_memory_range(mem, start, size); + lb_memory_range(mem, type, start, size); + lb_cleanup_memory_ranges(mem); +} + +static void lb_dump_memory_ranges(struct lb_memory *mem) +{ + int entries; + int i; + entries = (mem->size - sizeof(*mem))/sizeof(mem->map[0]); + + printk(BIOS_DEBUG, "coreboot memory table:\n"); + for(i = 0; i < entries; i++) { + uint64_t entry_start = unpack_lb64(mem->map[i].start); + uint64_t entry_size = unpack_lb64(mem->map[i].size); + const char *entry_type; + + switch (mem->map[i].type) { + case LB_MEM_RAM: entry_type="RAM"; break; + case LB_MEM_RESERVED: entry_type="RESERVED"; break; + case LB_MEM_ACPI: entry_type="ACPI"; break; + case LB_MEM_NVS: entry_type="NVS"; break; + case LB_MEM_UNUSABLE: entry_type="UNUSABLE"; break; + case LB_MEM_VENDOR_RSVD: entry_type="VENDOR RESERVED"; break; + case LB_MEM_TABLE: entry_type="CONFIGURATION TABLES"; break; + default: entry_type="UNKNOWN!"; break; + } + + printk(BIOS_DEBUG, "%2d. %016llx-%016llx: %s\n", + i, entry_start, entry_start+entry_size-1, entry_type); + + } +} + +/* Routines to extract part so the coreboot table or + * information from the coreboot table after we have written it. + * Currently get_lb_mem relies on a global we can change the + * implementaiton. + */ +static struct lb_memory *mem_ranges = NULL; + +struct lb_memory *get_lb_mem(void) +{ + return mem_ranges; +} + +static void build_lb_mem_range(void *gp, struct device *dev, struct resource *res) +{ + struct lb_memory *mem = gp; + lb_memory_range(mem, LB_MEM_RAM, res->base, res->size); +} + +static struct lb_memory *build_lb_mem(struct lb_header *head) +{ + struct lb_memory *mem; + + /* Record where the lb memory ranges will live */ + mem = lb_memory(head); + mem_ranges = mem; + + /* Build the raw table of memory */ + search_global_resources( + IORESOURCE_MEM | IORESOURCE_CACHEABLE, IORESOURCE_MEM | IORESOURCE_CACHEABLE, + build_lb_mem_range, mem); + lb_cleanup_memory_ranges(mem); + return mem; +} + +static void lb_add_rsvd_range(void *gp, struct device *dev, struct resource *res) +{ + struct lb_memory *mem = gp; + lb_add_memory_range(mem, LB_MEM_RESERVED, res->base, res->size); +} + +static void add_lb_reserved(struct lb_memory *mem) +{ + /* Add reserved ranges */ + search_global_resources( + IORESOURCE_MEM | IORESOURCE_RESERVE, IORESOURCE_MEM | IORESOURCE_RESERVE, + lb_add_rsvd_range, mem); +} + +unsigned long write_coreboot_table( + unsigned long low_table_start, unsigned long low_table_end, + unsigned long rom_table_start, unsigned long rom_table_end) +{ + struct lb_header *head; + struct lb_memory *mem; + + if (low_table_start || low_table_end) { + printk(BIOS_DEBUG, "Writing table forward entry at 0x%08lx\n", + low_table_end); + head = lb_table_init(low_table_end); + lb_forward(head, (struct lb_header*)rom_table_end); + + low_table_end = (unsigned long) lb_table_fini(head, 0); + printk(BIOS_DEBUG, "Table forward entry ends at 0x%08lx.\n", + low_table_end); + low_table_end = ALIGN(low_table_end, 4096); + printk(BIOS_DEBUG, "... aligned to 0x%08lx\n", low_table_end); + } + + printk(BIOS_DEBUG, "Writing coreboot table at 0x%08lx\n", + rom_table_end); + + head = lb_table_init(rom_table_end); + rom_table_end = (unsigned long)head; + printk(BIOS_DEBUG, "rom_table_end = 0x%08lx\n", rom_table_end); + rom_table_end = ALIGN(rom_table_end, (64 * 1024)); + printk(BIOS_DEBUG, "... aligned to 0x%08lx\n", rom_table_end); + +#if CONFIG_USE_OPTION_TABLE + { + struct cmos_option_table *option_table = cbfs_get_file_content( + CBFS_DEFAULT_MEDIA, "cmos_layout.bin", + CBFS_COMPONENT_CMOS_LAYOUT); + if (option_table) { + struct lb_record *rec_dest = lb_new_record(head); + /* Copy the option config table, it's already a lb_record... */ + memcpy(rec_dest, option_table, option_table->size); + /* Create cmos checksum entry in coreboot table */ + lb_cmos_checksum(head); + } else { + printk(BIOS_ERR, "cmos_layout.bin could not be found!\n"); + } + } +#endif + + /* The Linux kernel assumes this region is reserved */ + /* Record where RAM is located */ + mem = build_lb_mem(head); + + if (low_table_start || low_table_end) { + /* Record the mptable and the the lb_table. + * (This will be adjusted later) */ + lb_add_memory_range(mem, LB_MEM_TABLE, + low_table_start, low_table_end - low_table_start); + } + + /* Record the pirq table, acpi tables, and maybe the mptable. However, + * these only need to be added when the rom_table is sitting below + * 1MiB. If it isn't that means high tables are being written. + * The code below handles high tables correctly. */ + if (rom_table_end <= (1 << 20)) + lb_add_memory_range(mem, LB_MEM_TABLE, + rom_table_start, rom_table_end - rom_table_start); + +#if CONFIG_DYNAMIC_CBMEM + cbmem_add_lb_mem(mem); +#else /* CONFIG_DYNAMIC_CBMEM */ + lb_add_memory_range(mem, LB_MEM_TABLE, + high_tables_base, high_tables_size); +#endif /* CONFIG_DYNAMIC_CBMEM */ + + /* Add reserved regions */ + add_lb_reserved(mem); + + lb_dump_memory_ranges(mem); + + /* Note: + * I assume that there is always memory at immediately after + * the low_table_end. This means that after I setup the coreboot table. + * I can trivially fixup the reserved memory ranges to hold the correct + * size of the coreboot table. + */ + + /* Record our motherboard */ + lb_mainboard(head); + /* Record the serial port, if present */ + lb_serial(head); + /* Record our console setup */ + lb_console(head); + /* Record our various random string information */ + lb_strings(head); + /* Record our framebuffer */ + lb_framebuffer(head); + +#if CONFIG_CHROMEOS + /* Record our GPIO settings (ChromeOS specific) */ + lb_gpios(head); + + /* pass along the VDAT buffer adress */ + lb_vdat(head); + + /* pass along VBNV offsets in CMOS */ + lb_vbnv(head); + + /* pass along the vboot_handoff address. */ + lb_vboot_handoff(head); +#endif + add_cbmem_pointers(head); + + /* Remember where my valid memory ranges are */ + return lb_table_fini(head, 1); +} diff --git a/src/mainboard/google/butterfly/chromeos.c b/src/mainboard/google/butterfly/chromeos.c index 41abd95..6be7b8e 100644 --- a/src/mainboard/google/butterfly/chromeos.c +++ b/src/mainboard/google/butterfly/chromeos.c @@ -44,7 +44,6 @@ int get_pch_gpio(unsigned char gpio_num); #ifndef __PRE_RAM__ #include <boot/coreboot_tables.h> -#include <arch/coreboot_tables.h> #define GPIO_COUNT 6 diff --git a/src/mainboard/google/butterfly/mainboard.c b/src/mainboard/google/butterfly/mainboard.c index beda107..a1d9126 100644 --- a/src/mainboard/google/butterfly/mainboard.c +++ b/src/mainboard/google/butterfly/mainboard.c @@ -31,7 +31,7 @@ #include <arch/acpi.h> #include <arch/io.h> #include <arch/interrupt.h> -#include <arch/coreboot_tables.h> +#include <boot/coreboot_tables.h> #include "hda_verb.h" #include "onboard.h" #include "ec.h" diff --git a/src/mainboard/google/link/chromeos.c b/src/mainboard/google/link/chromeos.c index 04f68a9..32a6930 100644 --- a/src/mainboard/google/link/chromeos.c +++ b/src/mainboard/google/link/chromeos.c @@ -32,7 +32,6 @@ #ifndef __PRE_RAM__ #include <boot/coreboot_tables.h> -#include <arch/coreboot_tables.h> #define GPIO_COUNT 6 #define ACTIVE_LOW 0 diff --git a/src/mainboard/google/link/i915.c b/src/mainboard/google/link/i915.c index de7c306..4158fa2 100644 --- a/src/mainboard/google/link/i915.c +++ b/src/mainboard/google/link/i915.c @@ -29,7 +29,7 @@ #include <arch/acpi.h> #include <arch/io.h> #include <arch/interrupt.h> -#include <arch/coreboot_tables.h> +#include <boot/coreboot_tables.h> #include "hda_verb.h" #include "onboard.h" #include "ec.h" diff --git a/src/mainboard/google/link/mainboard.c b/src/mainboard/google/link/mainboard.c index e40ce52..f0afd81 100644 --- a/src/mainboard/google/link/mainboard.c +++ b/src/mainboard/google/link/mainboard.c @@ -32,7 +32,7 @@ #include <arch/acpi.h> #include <arch/io.h> #include <arch/interrupt.h> -#include <arch/coreboot_tables.h> +#include <boot/coreboot_tables.h> #include "hda_verb.h" #include "onboard.h" #include "ec.h" diff --git a/src/mainboard/google/parrot/chromeos.c b/src/mainboard/google/parrot/chromeos.c index d4054ef..ed3b7de 100644 --- a/src/mainboard/google/parrot/chromeos.c +++ b/src/mainboard/google/parrot/chromeos.c @@ -38,7 +38,6 @@ #ifndef __PRE_RAM__ #include <boot/coreboot_tables.h> -#include <arch/coreboot_tables.h> #define GPIO_COUNT 6 diff --git a/src/mainboard/google/parrot/mainboard.c b/src/mainboard/google/parrot/mainboard.c index 4c2618d..3822723 100644 --- a/src/mainboard/google/parrot/mainboard.c +++ b/src/mainboard/google/parrot/mainboard.c @@ -31,7 +31,7 @@ #include <arch/acpi.h> #include <arch/io.h> #include <arch/interrupt.h> -#include <arch/coreboot_tables.h> +#include <boot/coreboot_tables.h> #include "hda_verb.h" #include "onboard.h" #include "ec.h" diff --git a/src/mainboard/google/snow/chromeos.c b/src/mainboard/google/snow/chromeos.c index 14da49c..58836fe 100644 --- a/src/mainboard/google/snow/chromeos.c +++ b/src/mainboard/google/snow/chromeos.c @@ -38,7 +38,6 @@ #define POWER_BUTTON 3 #include <boot/coreboot_tables.h> -#include <arch/coreboot_tables.h> #define GPIO_COUNT 6 diff --git a/src/mainboard/google/stout/chromeos.c b/src/mainboard/google/stout/chromeos.c index db94cb7..f30d498 100644 --- a/src/mainboard/google/stout/chromeos.c +++ b/src/mainboard/google/stout/chromeos.c @@ -34,7 +34,6 @@ #ifndef __PRE_RAM__ #include <boot/coreboot_tables.h> -#include <arch/coreboot_tables.h> #define GPIO_COUNT 7 #define ACTIVE_LOW 0 diff --git a/src/mainboard/google/stout/i915.c b/src/mainboard/google/stout/i915.c index 309d18c..89a8594 100644 --- a/src/mainboard/google/stout/i915.c +++ b/src/mainboard/google/stout/i915.c @@ -13,7 +13,7 @@ #include <arch/acpi.h> #include <arch/io.h> #include <arch/interrupt.h> -#include <arch/coreboot_tables.h> +#include <boot/coreboot_tables.h> #include "hda_verb.h" #include "onboard.h" #include "ec.h" diff --git a/src/mainboard/google/stout/mainboard.c b/src/mainboard/google/stout/mainboard.c index f28c920..4af0ff5 100644 --- a/src/mainboard/google/stout/mainboard.c +++ b/src/mainboard/google/stout/mainboard.c @@ -31,7 +31,7 @@ #include <arch/acpi.h> #include <arch/io.h> #include <arch/interrupt.h> -#include <arch/coreboot_tables.h> +#include <boot/coreboot_tables.h> #include "hda_verb.h" #include "onboard.h" #include "ec.h" diff --git a/src/mainboard/intel/baskingridge/chromeos.c b/src/mainboard/intel/baskingridge/chromeos.c index 677f177..86a47b7 100644 --- a/src/mainboard/intel/baskingridge/chromeos.c +++ b/src/mainboard/intel/baskingridge/chromeos.c @@ -31,7 +31,6 @@ #ifndef __PRE_RAM__ #include <boot/coreboot_tables.h> -#include <arch/coreboot_tables.h> #define GPIO_COUNT 6 #define ACTIVE_LOW 0 diff --git a/src/mainboard/intel/baskingridge/mainboard.c b/src/mainboard/intel/baskingridge/mainboard.c index 5bd9aec..c7b0ee0 100644 --- a/src/mainboard/intel/baskingridge/mainboard.c +++ b/src/mainboard/intel/baskingridge/mainboard.c @@ -32,7 +32,7 @@ #include <arch/acpi.h> #include <arch/io.h> #include <arch/interrupt.h> -#include <arch/coreboot_tables.h> +#include <boot/coreboot_tables.h> #include "hda_verb.h" #include <southbridge/intel/lynxpoint/pch.h> diff --git a/src/mainboard/intel/emeraldlake2/chromeos.c b/src/mainboard/intel/emeraldlake2/chromeos.c index 1c5913a..a89e59c 100644 --- a/src/mainboard/intel/emeraldlake2/chromeos.c +++ b/src/mainboard/intel/emeraldlake2/chromeos.c @@ -29,7 +29,7 @@ #include <southbridge/intel/bd82x6x/pch.h> #ifndef __PRE_RAM__ -#include <arch/coreboot_tables.h> +#include <boot/coreboot_tables.h> #define GPIO_COUNT 6 #define ACTIVE_LOW 0 diff --git a/src/mainboard/intel/emeraldlake2/mainboard.c b/src/mainboard/intel/emeraldlake2/mainboard.c index 5d9e96a..92704c9 100644 --- a/src/mainboard/intel/emeraldlake2/mainboard.c +++ b/src/mainboard/intel/emeraldlake2/mainboard.c @@ -32,7 +32,7 @@ #include <arch/acpi.h> #include <arch/io.h> #include <arch/interrupt.h> -#include <arch/coreboot_tables.h> +#include <boot/coreboot_tables.h> #include "hda_verb.h" #include <southbridge/intel/bd82x6x/pch.h> diff --git a/src/mainboard/intel/wtm1/chromeos.c b/src/mainboard/intel/wtm1/chromeos.c index c2386a8..14857f5 100644 --- a/src/mainboard/intel/wtm1/chromeos.c +++ b/src/mainboard/intel/wtm1/chromeos.c @@ -30,7 +30,6 @@ #ifndef __PRE_RAM__ #include <boot/coreboot_tables.h> -#include <arch/coreboot_tables.h> #define GPIO_COUNT 6 #define ACTIVE_LOW 0 diff --git a/src/mainboard/intel/wtm1/mainboard.c b/src/mainboard/intel/wtm1/mainboard.c index e84b16e..f5b0054 100644 --- a/src/mainboard/intel/wtm1/mainboard.c +++ b/src/mainboard/intel/wtm1/mainboard.c @@ -32,7 +32,7 @@ #include <arch/acpi.h> #include <arch/io.h> #include <arch/interrupt.h> -#include <arch/coreboot_tables.h> +#include <boot/coreboot_tables.h> #include "hda_verb.h" #include <southbridge/intel/lynxpoint/pch.h> diff --git a/src/mainboard/intel/wtm2/chromeos.c b/src/mainboard/intel/wtm2/chromeos.c index 7ef7458..77a2ab5 100644 --- a/src/mainboard/intel/wtm2/chromeos.c +++ b/src/mainboard/intel/wtm2/chromeos.c @@ -34,7 +34,6 @@ #ifndef __PRE_RAM__ #include <boot/coreboot_tables.h> -#include <arch/coreboot_tables.h> #define GPIO_COUNT 6 #define ACTIVE_LOW 0 diff --git a/src/mainboard/intel/wtm2/mainboard.c b/src/mainboard/intel/wtm2/mainboard.c index e84b16e..f5b0054 100644 --- a/src/mainboard/intel/wtm2/mainboard.c +++ b/src/mainboard/intel/wtm2/mainboard.c @@ -32,7 +32,7 @@ #include <arch/acpi.h> #include <arch/io.h> #include <arch/interrupt.h> -#include <arch/coreboot_tables.h> +#include <boot/coreboot_tables.h> #include "hda_verb.h" #include <southbridge/intel/lynxpoint/pch.h> diff --git a/src/mainboard/samsung/lumpy/chromeos.c b/src/mainboard/samsung/lumpy/chromeos.c index 67a79f0..d27ab58 100644 --- a/src/mainboard/samsung/lumpy/chromeos.c +++ b/src/mainboard/samsung/lumpy/chromeos.c @@ -38,7 +38,7 @@ #define FLAG_DEV_MODE 2 #ifndef __PRE_RAM__ -#include <arch/coreboot_tables.h> +#include <boot/coreboot_tables.h> #include "ec.h" #include <ec/smsc/mec1308/ec.h> diff --git a/src/mainboard/samsung/lumpy/mainboard.c b/src/mainboard/samsung/lumpy/mainboard.c index d111181..be9a046 100644 --- a/src/mainboard/samsung/lumpy/mainboard.c +++ b/src/mainboard/samsung/lumpy/mainboard.c @@ -31,7 +31,7 @@ #include <arch/acpi.h> #include <arch/io.h> #include <arch/interrupt.h> -#include <arch/coreboot_tables.h> +#include <boot/coreboot_tables.h> #include <ec/smsc/mec1308/ec.h> #include "hda_verb.h" #include "ec.h" diff --git a/src/mainboard/samsung/stumpy/chromeos.c b/src/mainboard/samsung/stumpy/chromeos.c index 4222735..81f4a07 100644 --- a/src/mainboard/samsung/stumpy/chromeos.c +++ b/src/mainboard/samsung/stumpy/chromeos.c @@ -37,7 +37,7 @@ #define FLAG_DEV_MODE 2 #ifndef __PRE_RAM__ -#include <arch/coreboot_tables.h> +#include <boot/coreboot_tables.h> #define GPIO_COUNT 6 #define ACTIVE_LOW 0 diff --git a/src/mainboard/samsung/stumpy/mainboard.c b/src/mainboard/samsung/stumpy/mainboard.c index a465bb2..cbf5af7 100644 --- a/src/mainboard/samsung/stumpy/mainboard.c +++ b/src/mainboard/samsung/stumpy/mainboard.c @@ -32,7 +32,7 @@ #include <arch/acpi.h> #include <arch/io.h> #include <arch/interrupt.h> -#include <arch/coreboot_tables.h> +#include <boot/coreboot_tables.h> #include "hda_verb.h" #include <southbridge/intel/bd82x6x/pch.h> diff --git a/src/vendorcode/google/chromeos/Kconfig b/src/vendorcode/google/chromeos/Kconfig index 06ed7d3..e99e2c8 100644 --- a/src/vendorcode/google/chromeos/Kconfig +++ b/src/vendorcode/google/chromeos/Kconfig @@ -32,6 +32,7 @@ menu "ChromeOS" config VBNV_OFFSET hex default 0x26 + depends on PC80_SYSTEM help CMOS offset for VbNv data. This value must match cmos.layout in the mainboard directory, minus 14 bytes for the RTC. @@ -39,6 +40,7 @@ config VBNV_OFFSET config VBNV_SIZE hex default 0x10 + depends on PC80_SYSTEM help CMOS storage size for VbNv data. This value must match cmos.layout in the mainboard directory. diff --git a/src/vendorcode/google/chromeos/chromeos.c b/src/vendorcode/google/chromeos/chromeos.c index abe7104..658694d 100644 --- a/src/vendorcode/google/chromeos/chromeos.c +++ b/src/vendorcode/google/chromeos/chromeos.c @@ -21,7 +21,7 @@ #if CONFIG_VBOOT_VERIFY_FIRMWARE #include "vboot_handoff.h" #endif -#include <arch/coreboot_tables.h> +#include <boot/coreboot_tables.h> #include <cbmem.h> #include <console/console.h>

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Patch set updated for coreboot: e05228c samsung/exynos5: add resource functions for the display port
by Ronald G. Minnich 20 Mar '13

20 Mar '13

Ronald G. Minnich (rminnich(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2615 -gerrit commit e05228c2a7acb2200b13df8fdf6a9bd7210ab6ab Author: Ronald G. Minnich <rminnich(a)gmail.com> Date: Mon Mar 18 09:49:54 2013 -0700 samsung/exynos5: add resource functions for the display port NOT WORKING. We're still not getting our ops set -- seems the enable function is not being called, sigh. Simplified devicetree.cb however. Not working, seemingly, but we need to add a 4M resource for memory, and it seems it needs to be fixed at the address shown. This address was chosen from current hardware. The pnp device in the displayport is really hokey. We're going to have to create a new kind of device, maybe called 'hardwired', or something, to allow us to wire down devices we know are there without probing. Discussion on IRC implies this is the direction we need to go. Change-Id: Ied65a554f833566be817540702f79a02e7b6cb6e Signed-off-by: Ronald G. Minnich <rminnich(a)gmail.com> --- .../exynos5-common/displayport/displayport.c | 44 ++++++++++++++++++---- src/mainboard/google/snow/devicetree.cb | 7 +--- 2 files changed, 38 insertions(+), 13 deletions(-) diff --git a/src/cpu/samsung/exynos5-common/displayport/displayport.c b/src/cpu/samsung/exynos5-common/displayport/displayport.c index 1c08bc7..8609828 100644 --- a/src/cpu/samsung/exynos5-common/displayport/displayport.c +++ b/src/cpu/samsung/exynos5-common/displayport/displayport.c @@ -19,6 +19,7 @@ #include <stdlib.h> #include <string.h> +#include <stddef.h> #include <delay.h> #include <arch/io.h> #include <device/device.h> @@ -28,7 +29,7 @@ * and easier to understand and debug we explicitly name this common case. The alternate * approach, involving lots of machine and callbacks, is hard to debug and verify. */ -static void exynos_displayport_init(void) +static void exynos_displayport_init(device_t dev) { struct cpu_samsung_exynos5_common_displayport_config *conf = dev->chip_info; /* put these on the stack. If, at some point, we want to move this code to a @@ -83,22 +84,51 @@ static void exynos_displayport_init(void) #endif } -static void exynos_displayport_noop(device_t dummy) +static void exynos_displayport_read_resources(device_t dev) { + struct cpu_samsung_exynos5_common_displayport_config *conf = dev->chip_info; + struct resource *resource; + printk(BIOS_SPEW, "%s: dev %p\n", __func__, dev); + exynos_displayport_init(dev); + /* claim a resource for the UMA graphics. + * Follow the current convention of starting at 24M + * from the start. + */ + resource = new_resource(dev, 0); + /* this is a hardcode for now. There's some real confusion about what it + * needs to be, docs are not helping, and hardware on real systems + * has settings we don't understand. FIXME. + */ + resource->base = 0x20000000 + 24*MiB; + resource->size = conf->xres * conf->yres * 4; /* 4 bytes per pixel for RGB */ + resource->flags = IORESOURCE_MEM | IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED; + printk(BIOS_DEBUG, "Adding graphics at %p, size %08lx\n", (void *)resource->base, resource->size); +} + +static void exynos_displayport_set_resources(device_t dev) +{ + printk(BIOS_SPEW, "%s: dev %p\n", __function__, dev); +} + +static void exynos_displayport_enable_resources(device_t dev) +{ + printk(BIOS_SPEW, "%s: dev %p\n", __function__, dev); } static struct device_operations exynos_displayport_operations = { - .read_resources = exynos_displayport_noop, - .set_resources = exynos_displayport_noop, - .enable_resources = exynos_displayport_noop, + .read_resources = exynos_displayport_read_resources, + .set_resources = exynos_displayport_set_resources, + .enable_resources = exynos_displayport_enable_resources, .init = exynos_displayport_init, .scan_bus = exynos_displayport_noop, }; static void exynos_displayport_enable(struct device *dev) { - if (dev->link_list != NULL) - dev->ops = &exynos_displayport_operations; + printk(BIOS_SPEW, "%s: ", __function__); + printk(BIOS_SPEW, "set ops"); + dev->ops = &exynos_displayport_operations; + printk(BIOS_SPEW, "\n"); } struct chip_operations drivers_i2c_exynos_displayport_ops = { diff --git a/src/mainboard/google/snow/devicetree.cb b/src/mainboard/google/snow/devicetree.cb index 5ad786e..9c3d206 100644 --- a/src/mainboard/google/snow/devicetree.cb +++ b/src/mainboard/google/snow/devicetree.cb @@ -17,18 +17,14 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -# FIXME: this is just a stub for now chip cpu/samsung/exynos5250 -device cpu_cluster 0 on -end - -device domain 0 on chip drivers/generic/generic # I2C0 controller device i2c 6 on end # ? device i2c 9 on end # ? end chip cpu/samsung/exynos5-common/displayport + device pnp 1.1 on end register "xres" = "1366" register "yres" = "768" register "bpp" = "16" @@ -43,4 +39,3 @@ device domain 0 on register "lcdbase" = "0x10000000" end end -end

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New patch to review for coreboot: 1e8dbed armv7: add function for dcache_clean_by_mva()
by David Hendricks 20 Mar '13

20 Mar '13

David Hendricks (dhendrix(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2871 -gerrit commit 1e8dbed7718d2810ec01169526591d6982be35e0 Author: David Hendricks <dhendrix(a)chromium.org> Date: Tue Mar 19 18:38:48 2013 -0700 armv7: add function for dcache_clean_by_mva() This adds a function for using the DCCMVAC instruction (dcache clean by MVA at point of coherency (main memory)). We already have the inline defined, it's just not used by anything. Change-Id: Ia0641566a8881335bed8da2963e1db8321d74267 Signed-off-by: David Hendricks <dhendrix(a)chromium.org> --- src/arch/armv7/include/arch/cache.h | 3 +++ src/arch/armv7/lib/cache.c | 6 ++++++ 2 files changed, 9 insertions(+) diff --git a/src/arch/armv7/include/arch/cache.h b/src/arch/armv7/include/arch/cache.h index 31ed345..c003256 100644 --- a/src/arch/armv7/include/arch/cache.h +++ b/src/arch/armv7/include/arch/cache.h @@ -215,6 +215,9 @@ static inline void write_sctlr(unsigned int val) /* dcache clean and invalidate all (on current level given by CCSELR) */ void dcache_clean_invalidate_all(void); +/* dcache clean by modified virtual address to PoC */ +void dcache_clean_by_mva(unsigned long addr, unsigned long len); + /* dcache clean and invalidate by modified virtual address to PoC */ void dcache_clean_invalidate_by_mva(unsigned long addr, unsigned long len); diff --git a/src/arch/armv7/lib/cache.c b/src/arch/armv7/lib/cache.c index 8fb238a..63e406c 100644 --- a/src/arch/armv7/lib/cache.c +++ b/src/arch/armv7/lib/cache.c @@ -79,6 +79,7 @@ enum dcache_op { OP_DCCISW, OP_DCISW, OP_DCCIMVAC, + OP_DCCMVAC, }; /* @@ -193,6 +194,11 @@ static void dcache_op_mva(unsigned long addr, } } +void dcache_clean_by_mva(unsigned long addr, unsigned long len) +{ + dcache_op_mva(addr, len, OP_DCCMVAC); +} + void dcache_clean_invalidate_by_mva(unsigned long addr, unsigned long len) { dcache_op_mva(addr, len, OP_DCCIMVAC);

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New patch to review for coreboot: 55d9fba armv7: add a helper function for dcache ops by MVA
by David Hendricks 20 Mar '13

20 Mar '13

David Hendricks (dhendrix(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2870 -gerrit commit 55d9fba217938da3a2b22583c3cc223ae4828295 Author: David Hendricks <dhendrix(a)chromium.org> Date: Tue Mar 19 17:57:59 2013 -0700 armv7: add a helper function for dcache ops by MVA This adds a helper function for dcache ops by MVA which will perform the specified operation on a given memory range. This will make it more trivial to add other data cache maintenance routines. Change-Id: I01d746d5fd2f4138257ca9cab9e9d738e73f8633 Signed-off-by: David Hendricks <dhendrix(a)chromium.org> --- src/arch/armv7/lib/cache.c | 28 ++++++++++++++++++++++++---- 1 file changed, 24 insertions(+), 4 deletions(-) diff --git a/src/arch/armv7/lib/cache.c b/src/arch/armv7/lib/cache.c index d413bc4..8fb238a 100644 --- a/src/arch/armv7/lib/cache.c +++ b/src/arch/armv7/lib/cache.c @@ -77,7 +77,8 @@ void icache_invalidate_all(void) enum dcache_op { OP_DCCISW, - OP_DCISW + OP_DCISW, + OP_DCCIMVAC, }; /* @@ -169,13 +170,32 @@ static unsigned int line_bytes(void) return size; } -void dcache_clean_invalidate_by_mva(unsigned long addr, unsigned long len) +/* + * Do a dcache operation by modified virtual address. This is useful for + * maintaining coherency in drivers which do DMA transfers and only need to + * perform cache maintenance on a particular memory range rather than the + * entire cache. + */ +static void dcache_op_mva(unsigned long addr, + unsigned long len, enum dcache_op op) { unsigned long line, i; line = line_bytes(); - for (i = addr & ~(line - 1); i < addr + len - 1; i += line) - dccimvac(addr); + for (i = addr & ~(line - 1); i < addr + len - 1; i += line) { + switch(op) { + case OP_DCCIMVAC: + dccimvac(addr); + break; + default: + break; + } + } +} + +void dcache_clean_invalidate_by_mva(unsigned long addr, unsigned long len) +{ + dcache_op_mva(addr, len, OP_DCCIMVAC); } void armv7_invalidate_caches(void)

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New patch to review for coreboot: 8f2ae9d armv7: cosmetic changes to new cache code
by David Hendricks 20 Mar '13

20 Mar '13

David Hendricks (dhendrix(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2869 -gerrit commit 8f2ae9d1cf45b606765acfd9a67f8a8da2fdd9e7 Author: David Hendricks <dhendrix(a)chromium.org> Date: Tue Mar 19 17:32:54 2013 -0700 armv7: cosmetic changes to new cache code This clarifies and/or fixes formatting of some comments and alphabetizes some function prototypes and inlines. It also corrects references to "modified virtual address" (MVA). Change-Id: Ibcdda4febf915cc4a1996a5bbb4ffecbcb50a324 Signed-off-by: David Hendricks <dhendrix(a)chromium.org> --- src/arch/armv7/include/arch/cache.h | 38 +++++++++++++++++++++---------------- src/arch/armv7/lib/cache.c | 18 +++++++++++++----- 2 files changed, 35 insertions(+), 21 deletions(-) diff --git a/src/arch/armv7/include/arch/cache.h b/src/arch/armv7/include/arch/cache.h index 643da7c..31ed345 100644 --- a/src/arch/armv7/include/arch/cache.h +++ b/src/arch/armv7/include/arch/cache.h @@ -25,6 +25,8 @@ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. + * + * cache.h: Cache maintenance API for ARMv7 */ #ifndef ARMV7_CACHE_H @@ -128,12 +130,6 @@ static inline void dccisw(uint32_t val) asm volatile ("mcr p15, 0, %0, c7, c14, 2" : : "r" (val)); } -/* data cache invalidate by set/way */ -static inline void dcisw(uint32_t val) -{ - asm volatile ("mcr p15, 0, %0, c7, c6, 2" : : "r" (val)); -} - /* data cache clean by MVA to PoC */ static inline void dccmvac(unsigned long mva) { @@ -146,6 +142,12 @@ static inline void dcimvac(unsigned long mva) asm volatile ("mcr p15, 0, %0, c7, c6, 1" : : "r" (mva)); } +/* data cache invalidate by set/way */ +static inline void dcisw(uint32_t val) +{ + asm volatile ("mcr p15, 0, %0, c7, c6, 2" : : "r" (val)); +} + /* instruction cache invalidate all by PoU */ static inline void iciallu(void) { @@ -210,25 +212,29 @@ static inline void write_sctlr(unsigned int val) * Cache maintenance API */ -/* invalidate all TLBs */ -void tlb_invalidate_all(void); - -/* clean and invalidate entire dcache on current level (given by CCSELR) */ +/* dcache clean and invalidate all (on current level given by CCSELR) */ void dcache_clean_invalidate_all(void); -/* invalidate entire dcache on current level (given by CCSELR) */ -void dcache_invalidate_all(void); - -/* invalidate and clean dcache by machine virtual address to PoC */ +/* dcache clean and invalidate by modified virtual address to PoC */ void dcache_clean_invalidate_by_mva(unsigned long addr, unsigned long len); -/* invalidate entire icache on current level (given by CSSELR) */ +/* dcache invalidate all (on current level given by CCSELR) */ +void dcache_invalidate_all(void); + +/* icache invalidate all (on current level given by CSSELR) */ void icache_invalidate_all(void); +/* tlb invalidate all */ +void tlb_invalidate_all(void); + +/* + * Generalized setup/init functions + */ + /* invalidate all caches on ARMv7 */ void armv7_invalidate_caches(void); -/* MMU setup by machine virtual address */ +/* MMU setup by modified virtual address */ void mmu_setup_by_mva(unsigned long start, unsigned long size); #endif /* ARMV7_CACHE_H */ diff --git a/src/arch/armv7/lib/cache.c b/src/arch/armv7/lib/cache.c index 45d3308..d413bc4 100644 --- a/src/arch/armv7/lib/cache.c +++ b/src/arch/armv7/lib/cache.c @@ -26,7 +26,9 @@ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * - * cache.c: Low-level cache operations for ARMv7 + * cache.c: Cache maintenance routines for ARMv7-A and ARMv7-R + * + * Reference: ARM Architecture Reference Manual, ARMv7-A and ARMv7-R edition */ #include <types.h> @@ -52,8 +54,8 @@ void tlb_invalidate_all(void) { /* * FIXME: ARMv7 Architecture Ref. Manual claims that the distinction - * instruction vs. data TLBs is deprecated in ARMv7. But that doesn't - * really seem true for Cortex-A15? + * instruction vs. data TLBs is deprecated in ARMv7, however this does + * not seem to be the case as of Cortex-A15. */ tlbiall(); dtlbiall(); @@ -64,7 +66,8 @@ void tlb_invalidate_all(void) void icache_invalidate_all(void) { - /* icache can be entirely invalidated with one operation. + /* + * icache can be entirely invalidated with one operation. * Note: If branch predictors are architecturally-visible, ICIALLU * also performs a BPIALL operation (B2-1283 in arch manual) */ @@ -77,7 +80,12 @@ enum dcache_op { OP_DCISW }; -/* do a dcache operation on entire cache by set/way */ +/* + * Do a dcache operation on entire cache by set/way. This is done for + * portability because mapping of memory address to cache location is + * implementation defined (See note on "Requirements for operations by + * set/way" in arch ref. manual). + */ static void dcache_op_set_way(enum dcache_op op) { uint32_t ccsidr;

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New patch to review for coreboot: 0c69374 armv7: remove old isb() and dsb() macros
by David Hendricks 20 Mar '13

20 Mar '13

David Hendricks (dhendrix(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2868 -gerrit commit 0c69374f0b2b0db89e1ba7bb1d859c808cef4be0 Author: David Hendricks <dhendrix(a)chromium.org> Date: Tue Mar 19 17:12:46 2013 -0700 armv7: remove old isb() and dsb() macros This removes some old macros that we no longer use. Change-Id: I9d87beb5c2deca228cdf89a98e54b2779be0f0ea Signed-off-by: David Hendricks <dhendrix(a)chromium.org> --- src/arch/armv7/include/arch/io.h | 1 - src/arch/armv7/include/system.h | 3 --- 2 files changed, 4 deletions(-) diff --git a/src/arch/armv7/include/arch/io.h b/src/arch/armv7/include/arch/io.h index 623c305..b99e014 100644 --- a/src/arch/armv7/include/arch/io.h +++ b/src/arch/armv7/include/arch/io.h @@ -97,7 +97,6 @@ extern inline void __raw_readsl(unsigned int addr, void *data, int longlen) * TODO: The kernel offers some more advanced versions of barriers, it might * have some advantages to use them instead of the simple one here. */ -//#define dmb() __asm__ __volatile__ ("" : : : "memory") #define __iormb() dmb() #define __iowmb() dmb() diff --git a/src/arch/armv7/include/system.h b/src/arch/armv7/include/system.h index f3e9b6b..eda0bc1 100644 --- a/src/arch/armv7/include/system.h +++ b/src/arch/armv7/include/system.h @@ -43,9 +43,6 @@ */ #define __asmeq(x, y) ".ifnc " x "," y " ; .err ; .endif\n\t" -/* FIXME: conflicts with new implementation in cache.c */ -//#define isb() __asm__ __volatile__ ("" : : : "memory") - #define nop() __asm__ __volatile__("mov\tr0,r0\t@ nop\n\t"); #define arch_align_stack(x) (x)

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New patch to review for coreboot: 1fd276d armv7: move armv7_invalidate_caches() to cache.c
by David Hendricks 20 Mar '13

20 Mar '13

David Hendricks (dhendrix(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2867 -gerrit commit 1fd276d5ca3638f8f3bf8fcb9bdc899e748a5b8a Author: David Hendricks <dhendrix(a)chromium.org> Date: Tue Mar 19 17:11:31 2013 -0700 armv7: move armv7_invalidate_caches() to cache.c This just moves cache maintenance stuff from the armv7 bootblock code to cache.c Change-Id: I0b3ab58a1d8a3fe3d9568e02e156a36b6f33ca0b Signed-off-by: David Hendricks <dhendrix(a)chromium.org> --- src/arch/armv7/bootblock_simple.c | 52 ------------------------------------- src/arch/armv7/include/arch/cache.h | 3 +++ src/arch/armv7/lib/cache.c | 49 ++++++++++++++++++++++++++++++++++ 3 files changed, 52 insertions(+), 52 deletions(-) diff --git a/src/arch/armv7/bootblock_simple.c b/src/arch/armv7/bootblock_simple.c index 7012e17..ad25b41 100644 --- a/src/arch/armv7/bootblock_simple.c +++ b/src/arch/armv7/bootblock_simple.c @@ -28,58 +28,6 @@ #include "stages.c" -static void armv7_invalidate_caches(void) -{ - uint32_t clidr; - int level; - - /* Invalidate branch predictor */ - bpiall(); - - /* Iterate thru each cache identified in CLIDR and invalidate */ - clidr = read_clidr(); - for (level = 0; level < 7; level++) { - unsigned int ctype = (clidr >> (level * 3)) & 0x7; - uint32_t csselr; - - switch(ctype) { - case 0x0: - /* no cache */ - break; - case 0x1: - /* icache only */ - csselr = (level << 1) | 1; - write_csselr(csselr); - icache_invalidate_all(); - break; - case 0x2: - case 0x4: - /* dcache only or unified cache */ - dcache_invalidate_all(); - break; - case 0x3: - /* separate icache and dcache */ - csselr = (level << 1) | 1; - write_csselr(csselr); - icache_invalidate_all(); - - csselr = level < 1; - write_csselr(csselr); - dcache_invalidate_all(); - break; - default: - /* reserved */ - break; - } - } - - /* Invalidate TLB */ - /* FIXME: ARMv7 Architecture Ref. Manual claims that the distinction - * instruction vs. data TLBs is deprecated in ARMv7. But that doesn't - * really seem true for Cortex-A15? */ - tlb_invalidate_all(); -} - static int boot_cpu(void) { /* diff --git a/src/arch/armv7/include/arch/cache.h b/src/arch/armv7/include/arch/cache.h index 5125b8c..643da7c 100644 --- a/src/arch/armv7/include/arch/cache.h +++ b/src/arch/armv7/include/arch/cache.h @@ -225,6 +225,9 @@ void dcache_clean_invalidate_by_mva(unsigned long addr, unsigned long len); /* invalidate entire icache on current level (given by CSSELR) */ void icache_invalidate_all(void); +/* invalidate all caches on ARMv7 */ +void armv7_invalidate_caches(void); + /* MMU setup by machine virtual address */ void mmu_setup_by_mva(unsigned long start, unsigned long size); diff --git a/src/arch/armv7/lib/cache.c b/src/arch/armv7/lib/cache.c index 62ae755..45d3308 100644 --- a/src/arch/armv7/lib/cache.c +++ b/src/arch/armv7/lib/cache.c @@ -170,6 +170,55 @@ void dcache_clean_invalidate_by_mva(unsigned long addr, unsigned long len) dccimvac(addr); } +void armv7_invalidate_caches(void) +{ + uint32_t clidr; + int level; + + /* Invalidate branch predictor */ + bpiall(); + + /* Iterate thru each cache identified in CLIDR and invalidate */ + clidr = read_clidr(); + for (level = 0; level < 7; level++) { + unsigned int ctype = (clidr >> (level * 3)) & 0x7; + uint32_t csselr; + + switch(ctype) { + case 0x0: + /* no cache */ + break; + case 0x1: + /* icache only */ + csselr = (level << 1) | 1; + write_csselr(csselr); + icache_invalidate_all(); + break; + case 0x2: + case 0x4: + /* dcache only or unified cache */ + dcache_invalidate_all(); + break; + case 0x3: + /* separate icache and dcache */ + csselr = (level << 1) | 1; + write_csselr(csselr); + icache_invalidate_all(); + + csselr = level < 1; + write_csselr(csselr); + dcache_invalidate_all(); + break; + default: + /* reserved */ + break; + } + } + + /* Invalidate TLB */ + tlb_invalidate_all(); +} + /* FIXME: wrapper around imported mmu_setup() for now */ extern void mmu_setup(unsigned long start, unsigned long size); void mmu_setup_by_mva(unsigned long start, unsigned long size)

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Patch set updated for coreboot: cc051db samsung/exynos5: add resource functions for the display port
by Ronald G. Minnich 20 Mar '13

20 Mar '13

Ronald G. Minnich (rminnich(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2615 -gerrit commit cc051dbda22b9a05756b5830df3c680d13a4ea4e Author: Ronald G. Minnich <rminnich(a)gmail.com> Date: Mon Mar 18 09:49:54 2013 -0700 samsung/exynos5: add resource functions for the display port Not working, seemingly, but we need to add a 4M resource for memory, and it seems it needs to be fixed at the address shown. This address was chosen from current hardware. The pnp device in the displayport is really hokey. We're going to have to create a new kind of device, maybe called 'hardwired', or something, to allow us to wire down devices we know are there without probing. Discussion on IRC implies this is the direction we need to go. Change-Id: Ied65a554f833566be817540702f79a02e7b6cb6e Signed-off-by: Ronald G. Minnich <rminnich(a)gmail.com> --- .../exynos5-common/displayport/displayport.c | 44 ++++++++++++++++++--- src/mainboard/google/snow/devicetree.cb | 45 ++++++++++++---------- 2 files changed, 62 insertions(+), 27 deletions(-) diff --git a/src/cpu/samsung/exynos5-common/displayport/displayport.c b/src/cpu/samsung/exynos5-common/displayport/displayport.c index 1c08bc7..2dde860 100644 --- a/src/cpu/samsung/exynos5-common/displayport/displayport.c +++ b/src/cpu/samsung/exynos5-common/displayport/displayport.c @@ -19,6 +19,7 @@ #include <stdlib.h> #include <string.h> +#include <stddef.h> #include <delay.h> #include <arch/io.h> #include <device/device.h> @@ -28,7 +29,7 @@ * and easier to understand and debug we explicitly name this common case. The alternate * approach, involving lots of machine and callbacks, is hard to debug and verify. */ -static void exynos_displayport_init(void) +static void exynos_displayport_init(device_t dev) { struct cpu_samsung_exynos5_common_displayport_config *conf = dev->chip_info; /* put these on the stack. If, at some point, we want to move this code to a @@ -83,22 +84,53 @@ static void exynos_displayport_init(void) #endif } -static void exynos_displayport_noop(device_t dummy) +static void exynos_displayport_read_resources(device_t dev) { + struct cpu_samsung_exynos5_common_displayport_config *conf = dev->chip_info; + struct resource *resource; + printk(BIOS_SPEW, "%s: dev %p\n", __func__, dev); + exynos_displayport_init(dev); + /* claim a resource for the UMA graphics. + * Follow the current convention of starting at 24M + * from the start. + */ + resource = new_resource(dev, 0); + /* this is a hardcode for now. There's some real confusion about what it + * needs to be, docs are not helping, and hardware on real systems + * has settings we don't understand. FIXME. + */ + resource->base = 0x20000000 + 24*MiB; + resource->size = conf->xres * conf->yres * 4; /* 4 bytes per pixel for RGB */ + resource->flags = IORESOURCE_MEM | IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED; + printk(BIOS_DEBUG, "Adding graphics at %p, size %08lx\n", (void *)resource->base, resource->size); +} + +static void exynos_displayport_set_resources(device_t dev) +{ + printk(BIOS_SPEW, "%s: dev %p\n", __function__, dev); +} + +static void exynos_displayport_enable_resources(device_t dev) +{ + printk(BIOS_SPEW, "%s: dev %p\n", __function__, dev); } static struct device_operations exynos_displayport_operations = { - .read_resources = exynos_displayport_noop, - .set_resources = exynos_displayport_noop, - .enable_resources = exynos_displayport_noop, + .read_resources = exynos_displayport_read_resources, + .set_resources = exynos_displayport_set_resources, + .enable_resources = exynos_displayport_enable_resources, .init = exynos_displayport_init, .scan_bus = exynos_displayport_noop, }; static void exynos_displayport_enable(struct device *dev) { - if (dev->link_list != NULL) + printk(BIOS_SPEW, "%s: ", __function__); + if (dev->link_list != NULL){ + printk(BIOS_SPEW, "set ops"); dev->ops = &exynos_displayport_operations; + } + printk(BIOS_SPEW, "\n"); } struct chip_operations drivers_i2c_exynos_displayport_ops = { diff --git a/src/mainboard/google/snow/devicetree.cb b/src/mainboard/google/snow/devicetree.cb index 5ad786e..b48ae97 100644 --- a/src/mainboard/google/snow/devicetree.cb +++ b/src/mainboard/google/snow/devicetree.cb @@ -20,27 +20,30 @@ # FIXME: this is just a stub for now chip cpu/samsung/exynos5250 -device cpu_cluster 0 on -end + device cpu_cluster 0 on + + device domain 0 on + chip drivers/generic/generic # I2C0 controller + device i2c 6 on end # ? + device i2c 9 on end # ? + end + chip cpu/samsung/exynos5-common/displayport + device pnp 0 on end + register "xres" = "1366" + register "yres" = "768" + register "bpp" = "16" + # complex magic timing! + register "clkval_f" = "2" + register "upper_margin" = "14" + register "lower_margin" = "3" + register "vsync" = "5" + register "left_margin" = "80" + register "right_margin" = "48" + register "hsync" = "32" + register "lcdbase" = "0x10000000" + end + end -device domain 0 on - chip drivers/generic/generic # I2C0 controller - device i2c 6 on end # ? - device i2c 9 on end # ? - end - chip cpu/samsung/exynos5-common/displayport - register "xres" = "1366" - register "yres" = "768" - register "bpp" = "16" - # complex magic timing! - register "clkval_f" = "2" - register "upper_margin" = "14" - register "lower_margin" = "3" - register "vsync" = "5" - register "left_margin" = "80" - register "right_margin" = "48" - register "hsync" = "32" - register "lcdbase" = "0x10000000" end -end + end

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coreboot-gerrit March 2013