coreboot-gerrit March 2013

coreboot-gerrit@coreboot.org

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Patch merged into coreboot/master: d5c79f9 libpayload: Fix unused function warning in EHCI stack
by gerrit＠coreboot.org 26 Mar '13

26 Mar '13

the following patch was just integrated into master: commit d5c79f9cc897ef74ee7c376553572c67ed532662 Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Mon Mar 25 15:56:08 2013 -0700 libpayload: Fix unused function warning in EHCI stack The function dump_qh() was added a while back but never used. Hide it behind USB_DEBUG so it doesn't cause warnings when not debugging the USB stack. Change-Id: Idb3c7bb214895ef82676d181836a578bf161e8e0 Signed-off-by: Stefan Reinauer <reinauer(a)google.com> Reviewed-on: http://review.coreboot.org/2909 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martin.roth(a)se-eng.com> Build-Tested: build bot (Jenkins) at Tue Mar 26 01:16:09 2013, giving +1 See http://review.coreboot.org/2909 for details. -gerrit

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Patch merged into coreboot/master: cf4a3f4 Revert "coreboot table: use memrange library"
by gerrit＠coreboot.org 26 Mar '13

26 Mar '13

the following patch was just integrated into master: commit cf4a3f4a9781dab1e08aa2d0c937d4bd196e02f6 Author: Aaron Durbin <adurbin(a)google.com> Date: Tue Mar 26 18:07:32 2013 +0100 Revert "coreboot table: use memrange library" This reverts commit 56075eaefcd7ef51464206166b24a0a47a59147f Change-Id: I8a37ce1f5ce36e4a120941ec264140abc9447ff5 Reviewed-on: http://review.coreboot.org/2915 Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Tested-by: build bot (Jenkins) Build-Tested: build bot (Jenkins) at Tue Mar 26 18:20:17 2013, giving +1 Reviewed-By: Stefan Reinauer <stefan.reinauer(a)coreboot.org> at Tue Mar 26 18:12:21 2013, giving +2 See http://review.coreboot.org/2915 for details. -gerrit

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New patch to review for coreboot: a880fe0 Revert "coreboot table: use memrange library"
by Aaron Durbin 26 Mar '13

26 Mar '13

Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2915 -gerrit commit a880fe0408697f535beef47ad23b8bb4238362c5 Author: Aaron Durbin <adurbin(a)google.com> Date: Tue Mar 26 18:07:32 2013 +0100 Revert "coreboot table: use memrange library" This reverts commit 56075eaefcd7ef51464206166b24a0a47a59147f Change-Id: I8a37ce1f5ce36e4a120941ec264140abc9447ff5 --- src/lib/coreboot_table.c | 271 ++++++++++++++++++++++++++++++++++++++--------- 1 file changed, 218 insertions(+), 53 deletions(-) diff --git a/src/lib/coreboot_table.c b/src/lib/coreboot_table.c index 840470b..84eb5a6 100644 --- a/src/lib/coreboot_table.c +++ b/src/lib/coreboot_table.c @@ -29,7 +29,6 @@ #include <stdlib.h> #include <cbfs.h> #include <cbmem.h> -#include <memrange.h> #if CONFIG_USE_OPTION_TABLE #include <option_table.h> #endif @@ -357,7 +356,54 @@ static struct lb_forward *lb_forward(struct lb_header *header, struct lb_header return forward; } -static unsigned long lb_table_fini(struct lb_header *head) +static void lb_memory_range(struct lb_memory *mem, + uint32_t type, uint64_t start, uint64_t size) +{ + int entries; + entries = (mem->size - sizeof(*mem))/sizeof(mem->map[0]); + mem->map[entries].start = pack_lb64(start); + mem->map[entries].size = pack_lb64(size); + mem->map[entries].type = type; + mem->size += sizeof(mem->map[0]); +} + +static void lb_reserve_table_memory(struct lb_header *head) +{ +/* Dynamic cbmem has already reserved the memory where the coreboot tables + * reside. Therefore, there is nothing to fix up. */ +#if !CONFIG_DYNAMIC_CBMEM + struct lb_record *last_rec; + struct lb_memory *mem; + uint64_t start; + uint64_t end; + int i, entries; + + last_rec = lb_last_record(head); + mem = get_lb_mem(); + start = (unsigned long)head; + end = (unsigned long)last_rec; + entries = (mem->size - sizeof(*mem))/sizeof(mem->map[0]); + /* Resize the right two memory areas so this table is in + * a reserved area of memory. Everything has been carefully + * setup so that is all we need to do. + */ + for(i = 0; i < entries; i++ ) { + uint64_t map_start = unpack_lb64(mem->map[i].start); + uint64_t map_end = map_start + unpack_lb64(mem->map[i].size); + /* Does this area need to be expanded? */ + if (map_end == start) { + mem->map[i].size = pack_lb64(end - map_start); + } + /* Does this area need to be contracted? */ + else if (map_start == start) { + mem->map[i].start = pack_lb64(end); + mem->map[i].size = pack_lb64(map_end - end); + } + } +#endif +} + +static unsigned long lb_table_fini(struct lb_header *head, int fixup) { struct lb_record *rec, *first_rec; rec = lb_last_record(head); @@ -365,6 +411,9 @@ static unsigned long lb_table_fini(struct lb_header *head) head->table_bytes += rec->size; } + if (fixup) + lb_reserve_table_memory(head); + first_rec = lb_first_record(head); head->table_checksum = compute_ip_checksum(first_rec, head->table_bytes); head->header_checksum = 0; @@ -375,53 +424,128 @@ static unsigned long lb_table_fini(struct lb_header *head) return (unsigned long)rec + rec->size; } -/* Routines to extract part so the coreboot table or - * information from the coreboot table after we have written it. - * Currently get_lb_mem relies on a global we can change the - * implementaiton. - */ -static struct lb_memory *mem_ranges = NULL; - -struct lb_memory *get_lb_mem(void) +static void lb_cleanup_memory_ranges(struct lb_memory *mem) { - return mem_ranges; -} + int entries; + int i, j; + entries = (mem->size - sizeof(*mem))/sizeof(mem->map[0]); + + /* Sort the lb memory ranges */ + for(i = 0; i < entries; i++) { + uint64_t entry_start = unpack_lb64(mem->map[i].start); + for(j = i + 1; j < entries; j++) { + uint64_t temp_start = unpack_lb64(mem->map[j].start); + if (temp_start < entry_start) { + struct lb_memory_range tmp; + tmp = mem->map[i]; + mem->map[i] = mem->map[j]; + mem->map[j] = tmp; + } + } + } -/* This structure keeps track of the coreboot table memory ranges. */ -static struct memory_ranges lb_ranges; + /* Merge adjacent entries */ + for(i = 0; (i + 1) < entries; i++) { + uint64_t start, end, nstart, nend; + if (mem->map[i].type != mem->map[i + 1].type) { + continue; + } + start = unpack_lb64(mem->map[i].start); + end = start + unpack_lb64(mem->map[i].size); + nstart = unpack_lb64(mem->map[i + 1].start); + nend = nstart + unpack_lb64(mem->map[i + 1].size); + if ((start <= nstart) && (end >= nstart)) { + if (start > nstart) { + start = nstart; + } + if (end < nend) { + end = nend; + } + /* Record the new region size */ + mem->map[i].start = pack_lb64(start); + mem->map[i].size = pack_lb64(end - start); + + /* Delete the entry I have merged with */ + memmove(&mem->map[i + 1], &mem->map[i + 2], + ((entries - i - 2) * sizeof(mem->map[0]))); + mem->size -= sizeof(mem->map[0]); + entries -= 1; + /* See if I can merge with the next entry as well */ + i -= 1; + } + } +} -static struct lb_memory *build_lb_mem(struct lb_header *head) +static void lb_remove_memory_range(struct lb_memory *mem, + uint64_t start, uint64_t size) { - struct lb_memory *mem; - - /* Record where the lb memory ranges will live */ - mem = lb_memory(head); - mem_ranges = mem; + uint64_t end; + int entries; + int i; - /* Fill the memory map out. The order of operations is important in - * that each overlapping range will take over the next. Therefore, - * add cacheable resources as RAM then add the reserved resources. */ - memory_ranges_init(&lb_ranges, IORESOURCE_CACHEABLE, - IORESOURCE_CACHEABLE, LB_MEM_RAM); - memory_ranges_add_resources(&lb_ranges, IORESOURCE_RESERVE, - IORESOURCE_RESERVE, LB_MEM_RESERVED); + end = start + size; + entries = (mem->size - sizeof(*mem))/sizeof(mem->map[0]); + + /* Remove a reserved area from the memory map */ + for(i = 0; i < entries; i++) { + uint64_t map_start = unpack_lb64(mem->map[i].start); + uint64_t map_end = map_start + unpack_lb64(mem->map[i].size); + if ((start <= map_start) && (end >= map_end)) { + /* Remove the completely covered range */ + memmove(&mem->map[i], &mem->map[i + 1], + ((entries - i - 1) * sizeof(mem->map[0]))); + mem->size -= sizeof(mem->map[0]); + entries -= 1; + /* Since the index will disappear revisit what will appear here */ + i -= 1; + } + else if ((start > map_start) && (end < map_end)) { + /* Split the memory range */ + memmove(&mem->map[i + 1], &mem->map[i], + ((entries - i) * sizeof(mem->map[0]))); + mem->size += sizeof(mem->map[0]); + entries += 1; + /* Update the first map entry */ + mem->map[i].size = pack_lb64(start - map_start); + /* Update the second map entry */ + mem->map[i + 1].start = pack_lb64(end); + mem->map[i + 1].size = pack_lb64(map_end - end); + /* Don't bother with this map entry again */ + i += 1; + } + else if ((start <= map_start) && (end > map_start)) { + /* Shrink the start of the memory range */ + mem->map[i].start = pack_lb64(end); + mem->map[i].size = pack_lb64(map_end - end); + } + else if ((start < map_end) && (start > map_start)) { + /* Shrink the end of the memory range */ + mem->map[i].size = pack_lb64(start - map_start); + } + } +} - return mem; +void lb_add_memory_range(struct lb_memory *mem, + uint32_t type, uint64_t start, uint64_t size) +{ + lb_remove_memory_range(mem, start, size); + lb_memory_range(mem, type, start, size); + lb_cleanup_memory_ranges(mem); } -static void commit_lb_memory(struct lb_memory *mem) +static void lb_dump_memory_ranges(struct lb_memory *mem) { - struct memory_range *r; - struct lb_memory_range *lb_r; + int entries; int i; + entries = (mem->size - sizeof(*mem))/sizeof(mem->map[0]); - lb_r = &mem->map[0]; - i = 0; - - memory_ranges_each_entry(r, &lb_ranges) { + printk(BIOS_DEBUG, "coreboot memory table:\n"); + for(i = 0; i < entries; i++) { + uint64_t entry_start = unpack_lb64(mem->map[i].start); + uint64_t entry_size = unpack_lb64(mem->map[i].size); const char *entry_type; - switch (memory_range_tag(r)) { + switch (mem->map[i].type) { case LB_MEM_RAM: entry_type="RAM"; break; case LB_MEM_RESERVED: entry_type="RESERVED"; break; case LB_MEM_ACPI: entry_type="ACPI"; break; @@ -433,25 +557,58 @@ static void commit_lb_memory(struct lb_memory *mem) } printk(BIOS_DEBUG, "%2d. %016llx-%016llx: %s\n", - i, memory_range_base(r), memory_range_end(r)-1, - entry_type); - - lb_r->start = pack_lb64(memory_range_base(r)); - lb_r->size = pack_lb64(memory_range_size(r)); - lb_r->type = memory_range_tag(r); + i, entry_start, entry_start+entry_size-1, entry_type); - i++; - lb_r++; - mem->size += sizeof(struct lb_memory_range); } } -void lb_add_memory_range(struct lb_memory *mem, - uint32_t type, uint64_t start, uint64_t size) +/* Routines to extract part so the coreboot table or + * information from the coreboot table after we have written it. + * Currently get_lb_mem relies on a global we can change the + * implementaiton. + */ +static struct lb_memory *mem_ranges = NULL; + +struct lb_memory *get_lb_mem(void) { - insert_memory_range(&lb_ranges, start, size, type); + return mem_ranges; } +static void build_lb_mem_range(void *gp, struct device *dev, struct resource *res) +{ + struct lb_memory *mem = gp; + lb_memory_range(mem, LB_MEM_RAM, res->base, res->size); +} + +static struct lb_memory *build_lb_mem(struct lb_header *head) +{ + struct lb_memory *mem; + + /* Record where the lb memory ranges will live */ + mem = lb_memory(head); + mem_ranges = mem; + + /* Build the raw table of memory */ + search_global_resources( + IORESOURCE_MEM | IORESOURCE_CACHEABLE, IORESOURCE_MEM | IORESOURCE_CACHEABLE, + build_lb_mem_range, mem); + lb_cleanup_memory_ranges(mem); + return mem; +} + +static void lb_add_rsvd_range(void *gp, struct device *dev, struct resource *res) +{ + struct lb_memory *mem = gp; + lb_add_memory_range(mem, LB_MEM_RESERVED, res->base, res->size); +} + +static void add_lb_reserved(struct lb_memory *mem) +{ + /* Add reserved ranges */ + search_global_resources( + IORESOURCE_MEM | IORESOURCE_RESERVE, IORESOURCE_MEM | IORESOURCE_RESERVE, + lb_add_rsvd_range, mem); +} unsigned long write_coreboot_table( unsigned long low_table_start, unsigned long low_table_end, @@ -466,7 +623,7 @@ unsigned long write_coreboot_table( head = lb_table_init(low_table_end); lb_forward(head, (struct lb_header*)rom_table_end); - low_table_end = (unsigned long) lb_table_fini(head); + low_table_end = (unsigned long) lb_table_fini(head, 0); printk(BIOS_DEBUG, "Table forward entry ends at 0x%08lx.\n", low_table_end); low_table_end = ALIGN(low_table_end, 4096); @@ -525,9 +682,17 @@ unsigned long write_coreboot_table( high_tables_base, high_tables_size); #endif /* CONFIG_DYNAMIC_CBMEM */ - /* No other memory areas can be added after the memory table has been - * committed as the entries won't show up in the serialize mem table. */ - commit_lb_memory(mem); + /* Add reserved regions */ + add_lb_reserved(mem); + + lb_dump_memory_ranges(mem); + + /* Note: + * I assume that there is always memory at immediately after + * the low_table_end. This means that after I setup the coreboot table. + * I can trivially fixup the reserved memory ranges to hold the correct + * size of the coreboot table. + */ /* Record our motherboard */ lb_mainboard(head); @@ -556,5 +721,5 @@ unsigned long write_coreboot_table( add_cbmem_pointers(head); /* Remember where my valid memory ranges are */ - return lb_table_fini(head); + return lb_table_fini(head, 1); }

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Patch merged into coreboot/master: 5a767fd x86: dynamic cbmem: fix acpi reservations
by gerrit＠coreboot.org 26 Mar '13

26 Mar '13

the following patch was just integrated into master: commit 5a767fdfcb08f0c23f6a9763a8f90a282de49326 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Sat Mar 23 00:12:19 2013 -0500 x86: dynamic cbmem: fix acpi reservations If a configuration was not using RELOCTABLE_RAMSTAGE, but it was using HAVE_ACPI_RESUME then the ACPI memory was not being marked as reserved to the OS. The reason is that memory is marked as reserved during write_coreboot_table(). These reservations were being added to cbmem after the call to write_coreboot_table(). In the non-dynamic cbmem case this sequence is fine because cbmem area is a fixed size and is already reserved. For the dynamic cbmem case that no longer holds by the nature of the dynamic cbmem. Change-Id: I9aa44205205bfef75a9e7d9f02cf5c93d7c457b2 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: http://review.coreboot.org/2897 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Build-Tested: build bot (Jenkins) at Sat Mar 23 09:29:52 2013, giving +1 Reviewed-By: Stefan Reinauer <stefan.reinauer(a)coreboot.org> at Mon Mar 25 22:52:46 2013, giving +2 See http://review.coreboot.org/2897 for details. -gerrit

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Patch merged into coreboot/master: 56075ea coreboot table: use memrange library
by gerrit＠coreboot.org 26 Mar '13

26 Mar '13

the following patch was just integrated into master: commit 56075eaefcd7ef51464206166b24a0a47a59147f Author: Aaron Durbin <adurbin(a)chromium.org> Date: Sat Mar 23 00:06:36 2013 -0500 coreboot table: use memrange library Use the memrange library for keeping track of the address space region types. The memrange library is built to do just that for both the MTRR code and the coreboot memtable code. Change-Id: Ic667df444586c2b5b5f2ee531370bb790d683a42 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: http://review.coreboot.org/2896 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Build-Tested: build bot (Jenkins) at Sat Mar 23 09:16:49 2013, giving +1 Reviewed-By: Stefan Reinauer <stefan.reinauer(a)coreboot.org> at Mon Mar 25 22:49:06 2013, giving +2 See http://review.coreboot.org/2896 for details. -gerrit

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Patch set updated for coreboot: 0781831 armv7: fixes for dcache_op_by_mva()
by David Hendricks 26 Mar '13

26 Mar '13

David Hendricks (dhendrix(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2913 -gerrit commit 078183143549f1af6bd0b97d718f336e500aeeea Author: David Hendricks <dhendrix(a)chromium.org> Date: Mon Mar 25 19:50:11 2013 -0700 armv7: fixes for dcache_op_by_mva() This fixes a couple issues with dcache_op_by_mva(): - Add missing data and instruction sync barriers. - Removes unneded -1 from loop terminating condition. Change-Id: I098388614397c1e53079c017d56b1cf3ef273676 Signed-off-by: David Hendricks <dhendrix(a)chromium.org> --- src/arch/armv7/lib/cache.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/src/arch/armv7/lib/cache.c b/src/arch/armv7/lib/cache.c index 2686db7..c93da36 100644 --- a/src/arch/armv7/lib/cache.c +++ b/src/arch/armv7/lib/cache.c @@ -183,7 +183,9 @@ static void dcache_op_mva(unsigned long addr, unsigned long line, i; line = line_bytes(); - for (i = addr & ~(line - 1); i < addr + len - 1; i += line) { + + dsb(); + for (i = addr & ~(line - 1); i < addr + len; i += line) { switch(op) { case OP_DCCIMVAC: dccimvac(addr); @@ -192,6 +194,7 @@ static void dcache_op_mva(unsigned long addr, break; } } + isb(); } void dcache_clean_by_mva(unsigned long addr, unsigned long len)

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Patch merged into coreboot/master: 0175587 Revert "samsung/exynos5: add resource functions for the display port"
by gerrit＠coreboot.org 26 Mar '13

26 Mar '13

the following patch was just integrated into master: commit 0175587c5ea1db0ef76b3000db027e353b383de9 Author: David Hendricks <dhendrix(a)chromium.org> Date: Tue Mar 26 04:25:46 2013 +0100 Revert "samsung/exynos5: add resource functions for the display port" This reverts commit 9427ca151e44644238b1b52138894195a9f5175f Looks like we were a bit too anxious to see this one get in. The devicetree.cb change seems to have broken things. coreboot memory table: 0. 0000000050000000-000000005000ffff: RESERVED 1. 00000000bff00000-00000000bfffffff: CONFIGURATION TABLES 2. 0000014004000000-00000140044007ff: RESERVED Before this patch: coreboot memory table: 0. 0000000040000000-00000000bfefffff: RAM 1. 00000000bff00000-00000000bfffffff: CONFIGURATION TABLES Change-Id: I618e4f1976265d56cfd6a61d0c5736c55a0f3cec Reviewed-on: http://review.coreboot.org/2914 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix(a)chromium.org> Build-Tested: build bot (Jenkins) at Tue Mar 26 04:38:40 2013, giving +1 Reviewed-By: David Hendricks <dhendrix(a)chromium.org> at Tue Mar 26 04:39:53 2013, giving +2 See http://review.coreboot.org/2914 for details. -gerrit

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New patch to review for coreboot: 01a6e6f Revert "samsung/exynos5: add resource functions for the display port"
by David Hendricks 26 Mar '13

26 Mar '13

David Hendricks (dhendrix(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2914 -gerrit commit 01a6e6f0322fc4739780ad7b9cd83a8392748956 Author: David Hendricks <dhendrix(a)chromium.org> Date: Tue Mar 26 04:25:46 2013 +0100 Revert "samsung/exynos5: add resource functions for the display port" This reverts commit 9427ca151e44644238b1b52138894195a9f5175f Looks like we were a bit too anxious to see this one get in. The devicetree.cb change seems to have broken things. coreboot memory table: 0. 0000000050000000-000000005000ffff: RESERVED 1. 00000000bff00000-00000000bfffffff: CONFIGURATION TABLES 2. 0000014004000000-00000140044007ff: RESERVED Before this patch: coreboot memory table: 0. 0000000040000000-00000000bfefffff: RAM 1. 00000000bff00000-00000000bfffffff: CONFIGURATION TABLES Change-Id: I618e4f1976265d56cfd6a61d0c5736c55a0f3cec --- src/cpu/samsung/exynos5-common/displayport/Kconfig | 2 + .../exynos5-common/displayport/Makefile.inc | 2 + src/cpu/samsung/exynos5-common/displayport/chip.h | 40 ++++++++ .../exynos5-common/displayport/displayport.c | 107 +++++++++++++++++++++ src/cpu/samsung/exynos5-common/exynos-fb.c | 4 +- src/cpu/samsung/exynos5250/chip.h | 40 -------- src/cpu/samsung/exynos5250/cpu.c | 84 +--------------- src/mainboard/google/snow/devicetree.cb | 38 +++++--- 8 files changed, 179 insertions(+), 138 deletions(-) diff --git a/src/cpu/samsung/exynos5-common/displayport/Kconfig b/src/cpu/samsung/exynos5-common/displayport/Kconfig new file mode 100644 index 0000000..26d1422 --- /dev/null +++ b/src/cpu/samsung/exynos5-common/displayport/Kconfig @@ -0,0 +1,2 @@ +config EXYNOS_DISPLAYPORT + bool diff --git a/src/cpu/samsung/exynos5-common/displayport/Makefile.inc b/src/cpu/samsung/exynos5-common/displayport/Makefile.inc new file mode 100644 index 0000000..7c52eaf --- /dev/null +++ b/src/cpu/samsung/exynos5-common/displayport/Makefile.inc @@ -0,0 +1,2 @@ +ramstage-$(CONFIG_EXYNOS_DISPLAYPORT) += displayport.c + diff --git a/src/cpu/samsung/exynos5-common/displayport/chip.h b/src/cpu/samsung/exynos5-common/displayport/chip.h new file mode 100644 index 0000000..53b7836 --- /dev/null +++ b/src/cpu/samsung/exynos5-common/displayport/chip.h @@ -0,0 +1,40 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2013 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef CPU_SAMSUNG_EXYNOS5_COMMON_DISPLAYPORT_H +#define CPU_SAMSUNG_EXYNOS5_COMMON_DISPLAYPORT_H + +struct cpu_samsung_exynos5_common_displayport_config { + /* special magic numbers! */ + int clkval_f; + int upper_margin; + int lower_margin; + int vsync; + int left_margin; + int right_margin; + int hsync; + + int xres; + int yres; + int bpp; + + u32 lcdbase; +}; + +#endif /* CPU_SAMSUNG_EXYNOS5-COMMON_DISPLAYPORT_H */ diff --git a/src/cpu/samsung/exynos5-common/displayport/displayport.c b/src/cpu/samsung/exynos5-common/displayport/displayport.c new file mode 100644 index 0000000..1c08bc7 --- /dev/null +++ b/src/cpu/samsung/exynos5-common/displayport/displayport.c @@ -0,0 +1,107 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2013 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <stdlib.h> +#include <string.h> +#include <delay.h> +#include <arch/io.h> +#include <device/device.h> + +/* we distinguish a display port device from a raw graphics device because there are + * dramatic differences in startup depending on graphics usage. To make startup fast + * and easier to understand and debug we explicitly name this common case. The alternate + * approach, involving lots of machine and callbacks, is hard to debug and verify. + */ +static void exynos_displayport_init(void) +{ + struct cpu_samsung_exynos5_common_displayport_config *conf = dev->chip_info; + /* put these on the stack. If, at some point, we want to move this code to a + * pre-ram stage, it will be much easier. + */ + vidinfo_t vi; + struct exynos5_fimd_panel panel; + void *lcdbase; + + memset(vi, 0, sizeof(vi)); + memset(panel, 0, sizeof(panel)); + + panel.is_dp = 1; /* Display I/F is eDP */ + /* while it is true that we did a memset to zero, + * we leave some 'set to zero' entries here to make + * it clear what's going on. Graphics is confusing. + */ + panel.is_mipi = 0; + panel.fixvclk = 0; + panel.ivclk = 0; + panel.clkval_f = conf->clkval_f; + panel.upper_margin = conf->upper_margin; + panel.lower_margin = conf->lower_margin; + panel.vsync = conf->vsync; + panel.left_margin = conf->left_margin; + panel.right_margin = conf->right_margin; + panel.hsync = conf->hsync; + + vi->vl_col = conf->xres; + vi->fl_row = conf->yres; + vi->vl_bpix = conf->bpp; + vi->cmap = cbmem_reserve(64*1024); /* The size is a magic number from hardware. */ + + lcdbase = conf->lcdbase; + printk(BIOS_DEBUG, "Initializing exynos VGA\n"); + ret = lcd_ctrl_init(&vi, &panel, lcdbase); +#if 0 + ret = board_dp_lcd_vdd(blob, &wait_ms); + ret = board_dp_bridge_setup(blob, &wait_ms); + while (tries < 5) { + ret = board_dp_bridge_init(blob, &wait_ms); + ret = board_dp_hotplug(blob, &wait_ms); + if (ret) { + ret = board_dp_bridge_reset(blob, &wait_ms); + continue; + } + ret = dp_controller_init(blob, &wait_ms); + ret = board_dp_backlight_vdd(blob, &wait_ms); + ret = board_dp_backlight_pwm(blob, &wait_ms); + ret = board_dp_backlight_en(blob, &wait_ms); + } +#endif +} + +static void exynos_displayport_noop(device_t dummy) +{ +} + +static struct device_operations exynos_displayport_operations = { + .read_resources = exynos_displayport_noop, + .set_resources = exynos_displayport_noop, + .enable_resources = exynos_displayport_noop, + .init = exynos_displayport_init, + .scan_bus = exynos_displayport_noop, +}; + +static void exynos_displayport_enable(struct device *dev) +{ + if (dev->link_list != NULL) + dev->ops = &exynos_displayport_operations; +} + +struct chip_operations drivers_i2c_exynos_displayport_ops = { + CHIP_NAME("exynos displayport") + .enable_dev = exynos_displayport_enable; +}; diff --git a/src/cpu/samsung/exynos5-common/exynos-fb.c b/src/cpu/samsung/exynos5-common/exynos-fb.c index 990a313..30d0767 100644 --- a/src/cpu/samsung/exynos5-common/exynos-fb.c +++ b/src/cpu/samsung/exynos5-common/exynos-fb.c @@ -100,7 +100,7 @@ static void fimd_bypass(void) { struct exynos5_sysreg *sysreg = samsung_get_base_sysreg(); - setbits_le32(&sysreg->disp1blk_cfg, FIMDBYPASS_DISP1); + /*setbits_le32(&sysreg->disp1blk_cfg, FIMDBYPASS_DISP1);*/ sysreg->disp1blk_cfg &= ~FIMDBYPASS_DISP1; } @@ -586,9 +586,7 @@ int lcd_ctrl_init(vidinfo_t *panel_info, struct exynos5_fimd_panel *panel_data, //vi->yres = panel_info->vl_row; fimd_bypass(); - printk(BIOS_SPEW, "fimd_bypass\n"); fb_init(panel_info, lcdbase, panel_data); - printk(BIOS_SPEW, "fb_init(%p, %p, %p\n",panel_info, lcdbase, panel_data); /* Enable flushing after LCD writes if requested */ // forget it. lcd_set_flush_dcache(1); diff --git a/src/cpu/samsung/exynos5250/chip.h b/src/cpu/samsung/exynos5250/chip.h deleted file mode 100644 index 798cd26..0000000 --- a/src/cpu/samsung/exynos5250/chip.h +++ /dev/null @@ -1,40 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2013 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#ifndef CPU_SAMSUNG_EXYNOS5250_H -#define CPU_SAMSUNG_EXYNOS5250_H - -struct cpu_samsung_exynos5250_config { - /* special magic numbers! */ - int clkval_f; - int upper_margin; - int lower_margin; - int vsync; - int left_margin; - int right_margin; - int hsync; - - int xres; - int yres; - int bpp; - - u32 lcdbase; -}; - -#endif /* CPU_SAMSUNG_EXYNOS5250_H */ diff --git a/src/cpu/samsung/exynos5250/cpu.c b/src/cpu/samsung/exynos5250/cpu.c index 114d691..bcf4d22 100644 --- a/src/cpu/samsung/exynos5250/cpu.c +++ b/src/cpu/samsung/exynos5250/cpu.c @@ -1,14 +1,5 @@ -#include <stdlib.h> -#include <string.h> -#include <stddef.h> -#include <delay.h> #include <console/console.h> -#include <arch/io.h> #include <device/device.h> -#include <cbmem.h> -#include <cpu/samsung/exynos5250/fimd.h> -#include <cpu/samsung/exynos5-common/s5p-dp-core.h> -#include "chip.h" #define RAM_BASE_KB (CONFIG_SYS_SDRAM_BASE >> 10) #define RAM_SIZE_KB (CONFIG_DRAM_SIZE_MB << 10UL) @@ -37,76 +28,8 @@ static struct device_operations domain_ops = { .scan_bus = domain_scan_bus, }; -/* we distinguish a display port device from a raw graphics device because there are - * dramatic differences in startup depending on graphics usage. To make startup fast - * and easier to understand and debug we explicitly name this common case. The alternate - * approach, involving lots of machine and callbacks, is hard to debug and verify. - */ -static void exynos_displayport_init(device_t dev) -{ - int ret; - struct cpu_samsung_exynos5250_config *conf = dev->chip_info; - /* put these on the stack. If, at some point, we want to move this code to a - * pre-ram stage, it will be much easier. - */ - vidinfo_t vi; - struct exynos5_fimd_panel panel; - u32 lcdbase; - - printk(BIOS_SPEW, "%s: dev %p, conf %p\n", __func__, dev, conf); - memset(&vi, 0, sizeof(vi)); - memset(&panel, 0, sizeof(panel)); - - panel.is_dp = 1; /* Display I/F is eDP */ - /* while it is true that we did a memset to zero, - * we leave some 'set to zero' entries here to make - * it clear what's going on. Graphics is confusing. - */ - panel.is_mipi = 0; - panel.fixvclk = 0; - panel.ivclk = 0; - panel.clkval_f = conf->clkval_f; - panel.upper_margin = conf->upper_margin; - panel.lower_margin = conf->lower_margin; - panel.vsync = conf->vsync; - panel.left_margin = conf->left_margin; - panel.right_margin = conf->right_margin; - panel.hsync = conf->hsync; - - vi.vl_col = conf->xres; - vi.vl_row = conf->yres; - vi.vl_bpix = conf->bpp; - printk(BIOS_SPEW, "lcd base is %p\n", (void *)(conf->lcdbase)); - /* The size is a magic number from hardware. */ - mmio_resource(dev, 0, conf->lcdbase/KiB, 64); - vi.cmap = (void *)conf->lcdbase; - lcdbase = conf->lcdbase + 64*KiB; - - mmio_resource(dev, 1, lcdbase, (conf->xres*conf->yres*4 + (KiB-1))/KiB); - printk(BIOS_DEBUG, "Initializing exynos VGA, base %p\n",(void *)lcdbase); - ret = lcd_ctrl_init(&vi, &panel, (void *)lcdbase); -#if 0 - ret = board_dp_lcd_vdd(blob, &wait_ms); - ret = board_dp_bridge_setup(blob, &wait_ms); - while (tries < 5) { - ret = board_dp_bridge_init(blob, &wait_ms); - ret = board_dp_hotplug(blob, &wait_ms); - if (ret) { - ret = board_dp_bridge_reset(blob, &wait_ms); - continue; - } - ret = dp_controller_init(blob, &wait_ms); - ret = board_dp_backlight_vdd(blob, &wait_ms); - ret = board_dp_backlight_pwm(blob, &wait_ms); - ret = board_dp_backlight_en(blob, &wait_ms); - } -#endif -} - static void cpu_init(device_t dev) { - printk(BIOS_SPEW, "%s\n", __func__); - exynos_displayport_init(dev); } static void cpu_noop(device_t dev) @@ -121,20 +44,17 @@ static struct device_operations cpu_ops = { .scan_bus = 0, }; -static void enable_exynos5250_dev(device_t dev) +static void enable_dev(device_t dev) { /* Set the operations if it is a special bus type */ if (dev->path.type == DEVICE_PATH_DOMAIN) { - printk(BIOS_SPEW, "%s: DOMAIN\n", __func__); dev->ops = &domain_ops; } else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER) { - printk(BIOS_SPEW, "%s: CPU_CLUSTER\n", __func__); dev->ops = &cpu_ops; } - printk(BIOS_SPEW, "%s: done\n", __func__); } struct chip_operations cpu_samsung_exynos5250_ops = { CHIP_NAME("CPU Samsung Exynos 5250") - .enable_dev = enable_exynos5250_dev, + .enable_dev = enable_dev, }; diff --git a/src/mainboard/google/snow/devicetree.cb b/src/mainboard/google/snow/devicetree.cb index cfe5cf1..5ad786e 100644 --- a/src/mainboard/google/snow/devicetree.cb +++ b/src/mainboard/google/snow/devicetree.cb @@ -17,18 +17,30 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## +# FIXME: this is just a stub for now chip cpu/samsung/exynos5250 - device cpu_cluster 0 on end - register "xres" = "1366" - register "yres" = "768" - register "bpp" = "16" - # complex magic timing! - register "clkval_f" = "2" - register "upper_margin" = "14" - register "lower_margin" = "3" - register "vsync" = "5" - register "left_margin" = "80" - register "right_margin" = "48" - register "hsync" = "32" - register "lcdbase" = "0x50000000" + +device cpu_cluster 0 on +end + +device domain 0 on + chip drivers/generic/generic # I2C0 controller + device i2c 6 on end # ? + device i2c 9 on end # ? + end + chip cpu/samsung/exynos5-common/displayport + register "xres" = "1366" + register "yres" = "768" + register "bpp" = "16" + # complex magic timing! + register "clkval_f" = "2" + register "upper_margin" = "14" + register "lower_margin" = "3" + register "vsync" = "5" + register "left_margin" = "80" + register "right_margin" = "48" + register "hsync" = "32" + register "lcdbase" = "0x10000000" + end +end end

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New patch to review for coreboot: 51a2844 armv7: fixes for dcache_op_by_mva()
by David Hendricks 26 Mar '13

26 Mar '13

David Hendricks (dhendrix(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2913 -gerrit commit 51a2844d0c29f31875058e90720c6222ccea264a Author: David Hendricks <dhendrix(a)chromium.org> Date: Mon Mar 25 19:50:11 2013 -0700 armv7: fixes for dcache_op_by_mva() This fixes a couple issues with dcache_op_by_mva(): - Adds missing DSB at the end - Removes unneded -1 from loop terminating condition. Change-Id: I098388614397c1e53079c017d56b1cf3ef273676 Signed-off-by: David Hendricks <dhendrix(a)chromium.org> --- src/arch/armv7/lib/cache.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/src/arch/armv7/lib/cache.c b/src/arch/armv7/lib/cache.c index 2686db7..33b857d 100644 --- a/src/arch/armv7/lib/cache.c +++ b/src/arch/armv7/lib/cache.c @@ -183,7 +183,7 @@ static void dcache_op_mva(unsigned long addr, unsigned long line, i; line = line_bytes(); - for (i = addr & ~(line - 1); i < addr + len - 1; i += line) { + for (i = addr & ~(line - 1); i < addr + len; i += line) { switch(op) { case OP_DCCIMVAC: dccimvac(addr); @@ -192,6 +192,8 @@ static void dcache_op_mva(unsigned long addr, break; } } + + dsb(); } void dcache_clean_by_mva(unsigned long addr, unsigned long len)

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Patch merged into coreboot/master: 7f86c05 ARMv7: Drop XIP relocation code for romstage
by gerrit＠coreboot.org 26 Mar '13

26 Mar '13

the following patch was just integrated into master: commit 7f86c0586add7836b8c44805b6ef9eaa59fac787 Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Mon Mar 25 17:50:17 2013 -0700 ARMv7: Drop XIP relocation code for romstage It was never used, because we pushed romstage_null into the CBFS instead of romstage_xip. It's not surprising this worked, but it was a crude hack. Get rid of all the intermediate objects that are not needed. This could probably be further simplified to use the default cbfs mechanism in our build system instead of having a specific rule for romstage, but that's for another day. Change-Id: I492ca2015ec81e13499fcd8dd331371f46a31c78 Signed-off-by: Stefan Reinauer <reinauer(a)google.com> Reviewed-on: http://review.coreboot.org/2912 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix(a)chromium.org> Build-Tested: build bot (Jenkins) at Tue Mar 26 02:07:08 2013, giving +1 Reviewed-By: David Hendricks <dhendrix(a)chromium.org> at Tue Mar 26 03:12:35 2013, giving +2 See http://review.coreboot.org/2912 for details. -gerrit

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coreboot-gerrit March 2013