Change in ...coreboot[master]: nb/intel/sandybridge: Fill common MRC settings in northbridge code
Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32069
Change subject: nb/intel/sandybridge: Fill common MRC settings in northbridge code ......................................................................
nb/intel/sandybridge: Fill common MRC settings in northbridge code
Fill northbridge and southbridge BARs in raminit code. Allows to drop duplicated code from mainboard directories.
Change-Id: Ic6d9f0fd6a2b792ac693d6016ed9ce44945c900c Signed-off-by: Patrick Rudolph patrick.rudolph@9elements.com --- M src/northbridge/intel/sandybridge/raminit_mrc.c 1 file changed, 19 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/32069/1
diff --git a/src/northbridge/intel/sandybridge/raminit_mrc.c b/src/northbridge/intel/sandybridge/raminit_mrc.c index 852da7a..c544a74 100644 --- a/src/northbridge/intel/sandybridge/raminit_mrc.c +++ b/src/northbridge/intel/sandybridge/raminit_mrc.c @@ -275,6 +275,24 @@ u32 reserved[4]; } __packed;
+static void northbridge_fill_pei_data(struct pei_data *pei_data) +{ + pei_data->mchbar = (uintptr_t)DEFAULT_MCHBAR; + pei_data->dmibar = (uintptr_t)DEFAULT_DMIBAR; + pei_data->epbar = DEFAULT_EPBAR; + pei_data->pciexbar = CONFIG_MMCONF_BASE_ADDRESS; + pei_data->smbusbar = SMBUS_IO_BASE; + pei_data->wdbbar = 0x4000000; + pei_data->wdbsize = 0x1000; + pei_data->hpet_address = CONFIG_HPET_ADDRESS; + pei_data->rcba = (uintptr_t)DEFAULT_RCBABASE; + pei_data->pmbase = DEFAULT_PMBASE; + pei_data->gpiobase = DEFAULT_GPIOBASE; + pei_data->thermalbase = 0xfed08000; + pei_data->system_type = get_platform_type() == PLATFORM_MOBILE ? 0 : 1; + pei_data->tseg_size = CONFIG_SMM_TSEG_SIZE; +} + void perform_raminit(int s3resume) { int cbmem_was_initted; @@ -286,6 +304,7 @@ enable_usb_bar();
mainboard_fill_pei_data(&pei_data); + northbridge_fill_pei_data(&pei_data);
post_code(0x3a); pei_data.boot_mode = s3resume ? 2 : 0;
Hello Patrick Rudolph, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/32069
to look at the new patch set (#5).
Change subject: [WIP]nb/intel/sandybridge: Migrate MRC settings to devicetree ......................................................................
[WIP]nb/intel/sandybridge: Migrate MRC settings to devicetree
* Add more chip register to move PEI data to devicetree.cb. * Set northbridge/southbridge and runtime detectable settings. * Fill in values from devicetree.
This change is still a noop as the pei structure is overwritten with the mainboard pei structure.
The followup commit will migrate to devicetree.cb.
Signed-off-by: Patrick Rudolph patrick.rudolph@9elements.com Change-Id: Ic6d9f0fd6a2b792ac693d6016ed9ce44945c900c --- M src/northbridge/intel/sandybridge/chip.h M src/northbridge/intel/sandybridge/raminit_mrc.c 2 files changed, 131 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/32069/5
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32069 )
Change subject: [WIP]nb/intel/sandybridge: Migrate MRC settings to devicetree ......................................................................
Patch Set 5:
(4 comments)
https://review.coreboot.org/#/c/32069/5/src/northbridge/intel/sandybridge/ch... File src/northbridge/intel/sandybridge/chip.h:
https://review.coreboot.org/#/c/32069/5/src/northbridge/intel/sandybridge/ch... PS5, Line 65: * PCIe. Note: This should only be required if your system has Gen3 devices line over 80 characters
https://review.coreboot.org/#/c/32069/5/src/northbridge/intel/sandybridge/ch... PS5, Line 114: u8 mode : 2; // 0: Disable, 1: Enable, 2: Auto, 3: Smart Auto line over 80 characters
https://review.coreboot.org/#/c/32069/5/src/northbridge/intel/sandybridge/ch... PS5, Line 115: u8 hs_port_switch_mask : 4; // 4 bit mask, 1: switchable, 0: not switchable line over 80 characters
https://review.coreboot.org/#/c/32069/5/src/northbridge/intel/sandybridge/ch... PS5, Line 116: u8 preboot_support : 1; // 0: No xHCI preOS driver, 1: xHCI preOS driver line over 80 characters
Hello Patrick Rudolph, Arthur Heymans, build bot (Jenkins), Nico Huber,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/32069
to look at the new patch set (#6).
Change subject: nb/intel/sandybridge: Migrate MRC settings to devicetree ......................................................................
nb/intel/sandybridge: Migrate MRC settings to devicetree
* Add more chip register to move PEI data to devicetree.cb. * Set northbridge/southbridge and runtime detectable settings. * Fill in values from devicetree.
This change is still a noop as the pei structure is completely overwritten with the exsting mainboard pei structure.
The followup commit will migrate to devicetree.cb.
Tested on Lenovo T520, boots MRC path with the new devicetree settings.
Signed-off-by: Patrick Rudolph patrick.rudolph@9elements.com Change-Id: Ic6d9f0fd6a2b792ac693d6016ed9ce44945c900c --- M src/northbridge/intel/sandybridge/chip.h M src/northbridge/intel/sandybridge/raminit_mrc.c 2 files changed, 149 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/32069/6
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32069 )
Change subject: nb/intel/sandybridge: Migrate MRC settings to devicetree ......................................................................
Patch Set 6:
(5 comments)
https://review.coreboot.org/#/c/32069/6/src/northbridge/intel/sandybridge/ch... File src/northbridge/intel/sandybridge/chip.h:
https://review.coreboot.org/#/c/32069/6/src/northbridge/intel/sandybridge/ch... PS6, Line 65: * PCIe. Note: This should only be required if your system has Gen3 devices line over 80 characters
https://review.coreboot.org/#/c/32069/6/src/northbridge/intel/sandybridge/ch... PS6, Line 114: u8 mode : 2; // 0: Disable, 1: Enable, 2: Auto, 3: Smart Auto line over 80 characters
https://review.coreboot.org/#/c/32069/6/src/northbridge/intel/sandybridge/ch... PS6, Line 115: u8 hs_port_switch_mask : 4; // 4 bit mask, 1: switchable, 0: not switchable line over 80 characters
https://review.coreboot.org/#/c/32069/6/src/northbridge/intel/sandybridge/ch... PS6, Line 116: u8 preboot_support : 1; // 0: No xHCI preOS driver, 1: xHCI preOS driver line over 80 characters
https://review.coreboot.org/#/c/32069/6/src/northbridge/intel/sandybridge/ra... File src/northbridge/intel/sandybridge/raminit_mrc.c:
https://review.coreboot.org/#/c/32069/6/src/northbridge/intel/sandybridge/ra... PS6, Line 314: switch (cfg->max_mem_clock_mhz) { switch and case should be at the same indent
Hello Patrick Rudolph, Arthur Heymans, build bot (Jenkins), Nico Huber,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/32069
to look at the new patch set (#7).
Change subject: nb/intel/sandybridge: Migrate MRC settings to devicetree ......................................................................
nb/intel/sandybridge: Migrate MRC settings to devicetree
* Add more chip register to move PEI data to devicetree.cb. * Set northbridge/southbridge and runtime detectable settings. * Fill in values from devicetree.
This change is still a noop as the pei structure is completely overwritten with the exsting mainboard pei structure.
The followup commit will migrate to devicetree.cb.
Tested on Lenovo T520, boots MRC path with the new devicetree settings.
Signed-off-by: Patrick Rudolph patrick.rudolph@9elements.com Change-Id: Ic6d9f0fd6a2b792ac693d6016ed9ce44945c900c --- M src/northbridge/intel/sandybridge/chip.h M src/northbridge/intel/sandybridge/raminit_mrc.c 2 files changed, 153 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/32069/7
Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32069 )
Change subject: nb/intel/sandybridge: Migrate MRC settings to devicetree ......................................................................
Patch Set 7:
(10 comments)
https://review.coreboot.org/#/c/32069/7/src/northbridge/intel/sandybridge/ch... File src/northbridge/intel/sandybridge/chip.h:
PS7: When I see bit fields that are not part of an ABI or hardware interface, I always wonder if it doesn't increase code size more than what is saved by packing them. What do we gain here?
https://review.coreboot.org/#/c/32069/7/src/northbridge/intel/sandybridge/ch... PS7, Line 58: u8 spd_addresses[4]; These are not MRC specific, we could use the values for all DIMM configs.
https://review.coreboot.org/#/c/32069/7/src/northbridge/intel/sandybridge/ch... PS7, Line 68: u16 pcie_init : 2; Why 2 bits?
Can we derive it from PEG device on/off?
https://review.coreboot.org/#/c/32069/7/src/northbridge/intel/sandybridge/ch... PS7, Line 69: /* N mode functionality. Leave this setting at 0. Doesn't sound like we'd ever need it in a devicetree.
https://review.coreboot.org/#/c/32069/7/src/northbridge/intel/sandybridge/ch... PS7, Line 72: * 2 2N I prefer enums over such comments. Makes the devicetrees more readable without copying the comments all over. Doesn't even need a separate declaration:
enum { NMODE_AUTO, NMODE_1N, NMODE_2N, } nmode;
https://review.coreboot.org/#/c/32069/7/src/northbridge/intel/sandybridge/ch... PS7, Line 91: u16 dimm_channel1_disabled : 2; Can we derive this from `spd_addresses`?
https://review.coreboot.org/#/c/32069/7/src/northbridge/intel/sandybridge/ra... File src/northbridge/intel/sandybridge/raminit_mrc.c:
https://review.coreboot.org/#/c/32069/7/src/northbridge/intel/sandybridge/ra... PS7, Line 294: const struct device *dev = pcidev_path_on_root(PCI_DEVFN(0, 0x19)); that would be `pcidev_on_root(0, 0x19)`
https://review.coreboot.org/#/c/32069/7/src/northbridge/intel/sandybridge/ra... PS7, Line 307: = NULL initialization is overwritten
https://review.coreboot.org/#/c/32069/7/src/northbridge/intel/sandybridge/ra... PS7, Line 310: if (!dev) check `!dev->chip_info` too?
https://review.coreboot.org/#/c/32069/7/src/northbridge/intel/sandybridge/ra... PS7, Line 329: pei_data->max_ddr3_freq = 0; Fall back to 800, with a warning? 0 doesn't seem valid.
Hello Alexander Couzens, Evgeny Zinoviev, Patrick Rudolph, Felix Held, Nico Rikken, Arthur Heymans, Duncan Laurie, Bill XIE, build bot (Jenkins), Nico Huber, Jan Tatje,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/32069
to look at the new patch set (#8).
Change subject: nb/intel/sandybridge: Migrate MRC settings to devicetree ......................................................................
nb/intel/sandybridge: Migrate MRC settings to devicetree
* Add more chip register to move PEI data to devicetree.cb. * Set northbridge/southbridge and runtime detectable settings. * Fill in values from devicetree.
This change is still a noop as the pei structure is completely overwritten with the exsting mainboard pei structure.
The followup commit will migrate to devicetree.cb.
Tested on Lenovo T520, boots MRC path with the new devicetree settings.
Signed-off-by: Patrick Rudolph patrick.rudolph@9elements.com Change-Id: Ic6d9f0fd6a2b792ac693d6016ed9ce44945c900c --- M src/northbridge/intel/sandybridge/chip.h M src/northbridge/intel/sandybridge/raminit_mrc.c 2 files changed, 167 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/32069/8
Hello Alexander Couzens, Evgeny Zinoviev, Patrick Rudolph, Felix Held, Nico Rikken, Arthur Heymans, Duncan Laurie, Bill XIE, build bot (Jenkins), Nico Huber, Jan Tatje,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/32069
to look at the new patch set (#9).
Change subject: nb/intel/sandybridge: Migrate MRC settings to devicetree ......................................................................
nb/intel/sandybridge: Migrate MRC settings to devicetree
* Add more chip register to move PEI data to devicetree.cb. * Set northbridge/southbridge and runtime detectable settings. * Fill in values from devicetree.
This change is still a noop as the pei structure is completely overwritten with the exsting mainboard pei structure.
The followup commit will migrate to devicetree.cb.
Tested on Lenovo T520, boots MRC path with the new devicetree settings.
Signed-off-by: Patrick Rudolph patrick.rudolph@9elements.com Change-Id: Ic6d9f0fd6a2b792ac693d6016ed9ce44945c900c --- M src/northbridge/intel/sandybridge/chip.h M src/northbridge/intel/sandybridge/raminit_mrc.c 2 files changed, 167 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/32069/9
Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32069 )
Change subject: nb/intel/sandybridge: Migrate MRC settings to devicetree ......................................................................
Patch Set 9:
(1 comment)
https://review.coreboot.org/#/c/32069/9/src/northbridge/intel/sandybridge/ra... File src/northbridge/intel/sandybridge/raminit_mrc.c:
https://review.coreboot.org/#/c/32069/9/src/northbridge/intel/sandybridge/ra... PS9, Line 385: pei_data.dimm_channel0_disabled = this might not work on lumpy as the onboard spd config looks fishy. It uses spd_data[0] which should be spd_data[2] IMHO.
Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32069 )
Change subject: nb/intel/sandybridge: Migrate MRC settings to devicetree ......................................................................
Patch Set 9: Code-Review+2
(11 comments)
https://review.coreboot.org/#/c/32069/9/src/northbridge/intel/sandybridge/ch... File src/northbridge/intel/sandybridge/chip.h:
https://review.coreboot.org/#/c/32069/9/src/northbridge/intel/sandybridge/ch... PS9, Line 58: Use 8bit notation where BIT0 is always zero. Or shift by 1 when copying to `pei_data`?
https://review.coreboot.org/#/c/32069/7/src/northbridge/intel/sandybridge/ch... File src/northbridge/intel/sandybridge/chip.h:
PS7:
Haven't tested actual code size. Removed in favour of enums.
Ack
https://review.coreboot.org/#/c/32069/7/src/northbridge/intel/sandybridge/ch... PS7, Line 58: u8 spd_addresses[4];
Same for usb_port_config. Comments will be adjusted once native code makes use of them.
Ack
https://review.coreboot.org/#/c/32069/7/src/northbridge/intel/sandybridge/ch... PS7, Line 68: u16 pcie_init : 2;
Not sure. Removed and drived from PEG device on Ivybridge.
Ack
NB. There are only two boards that set it, and I think the Roda is wrong (might be copy-pasta on my side).
https://review.coreboot.org/#/c/32069/7/src/northbridge/intel/sandybridge/ch... PS7, Line 72: * 2 2N
I prefer enums over such comments. Makes the devicetrees more […]
Ack
https://review.coreboot.org/#/c/32069/7/src/northbridge/intel/sandybridge/ch... PS7, Line 91: u16 dimm_channel1_disabled : 2;
Yes. Done.
Ack
https://review.coreboot.org/#/c/32069/7/src/northbridge/intel/sandybridge/ra... File src/northbridge/intel/sandybridge/raminit_mrc.c:
https://review.coreboot.org/#/c/32069/7/src/northbridge/intel/sandybridge/ra... PS7, Line 294: const struct device *dev = pcidev_path_on_root(PCI_DEVFN(0, 0x19));
Done
Ack
https://review.coreboot.org/#/c/32069/7/src/northbridge/intel/sandybridge/ra... PS7, Line 307: = NULL
Done
Ack
https://review.coreboot.org/#/c/32069/7/src/northbridge/intel/sandybridge/ra... PS7, Line 310: if (!dev)
Done
Ack
https://review.coreboot.org/#/c/32069/7/src/northbridge/intel/sandybridge/ra... PS7, Line 329: pei_data->max_ddr3_freq = 0;
Done
Ack
https://review.coreboot.org/#/c/32069/9/src/northbridge/intel/sandybridge/ra... File src/northbridge/intel/sandybridge/raminit_mrc.c:
https://review.coreboot.org/#/c/32069/9/src/northbridge/intel/sandybridge/ra... PS9, Line 385: pei_data.dimm_channel0_disabled =
this might not work on lumpy as the onboard spd config looks fishy. […]
Probably worth to ask around if it uses the second channel.
Hello Alexander Couzens, Evgeny Zinoviev, Patrick Rudolph, Felix Held, Nico Rikken, Arthur Heymans, Duncan Laurie, build bot (Jenkins), Bill XIE, Nico Huber, Jan Tatje,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/32069
to look at the new patch set (#10).
Change subject: nb/intel/sandybridge: Migrate MRC settings to devicetree ......................................................................
nb/intel/sandybridge: Migrate MRC settings to devicetree
* Add more chip register to move PEI data to devicetree.cb. * Set northbridge/southbridge and runtime detectable settings. * Fill in values from devicetree.
This change is still a noop as the pei structure is completely overwritten with the exsting mainboard pei structure.
The followup commit will migrate to devicetree.cb.
Tested on Lenovo T520, boots MRC path with the new devicetree settings.
Signed-off-by: Patrick Rudolph patrick.rudolph@9elements.com Change-Id: Ic6d9f0fd6a2b792ac693d6016ed9ce44945c900c --- M src/northbridge/intel/sandybridge/chip.h M src/northbridge/intel/sandybridge/raminit_mrc.c 2 files changed, 166 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/32069/10
Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32069 )
Change subject: nb/intel/sandybridge: Migrate MRC settings to devicetree ......................................................................
Patch Set 10: Code-Review+2
(1 comment)
https://review.coreboot.org/#/c/32069/10/src/northbridge/intel/sandybridge/r... File src/northbridge/intel/sandybridge/raminit_mrc.c:
https://review.coreboot.org/#/c/32069/10/src/northbridge/intel/sandybridge/r... PS10, Line 402: } Might be easier to read if you'd put a
if (!pei_data.spd_data[i][0]) continue;
up front.
Patrick Georgi has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/32069 )
Change subject: nb/intel/sandybridge: Migrate MRC settings to devicetree ......................................................................
nb/intel/sandybridge: Migrate MRC settings to devicetree
* Add more chip register to move PEI data to devicetree.cb. * Set northbridge/southbridge and runtime detectable settings. * Fill in values from devicetree.
This change is still a noop as the pei structure is completely overwritten with the exsting mainboard pei structure.
The followup commit will migrate to devicetree.cb.
Tested on Lenovo T520, boots MRC path with the new devicetree settings.
Signed-off-by: Patrick Rudolph patrick.rudolph@9elements.com Change-Id: Ic6d9f0fd6a2b792ac693d6016ed9ce44945c900c Reviewed-on: https://review.coreboot.org/c/coreboot/+/32069 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Nico Huber nico.h@gmx.de --- M src/northbridge/intel/sandybridge/chip.h M src/northbridge/intel/sandybridge/raminit_mrc.c 2 files changed, 166 insertions(+), 0 deletions(-)
Approvals: build bot (Jenkins): Verified Nico Huber: Looks good to me, approved
diff --git a/src/northbridge/intel/sandybridge/chip.h b/src/northbridge/intel/sandybridge/chip.h index d002824..7dddb8a 100644 --- a/src/northbridge/intel/sandybridge/chip.h +++ b/src/northbridge/intel/sandybridge/chip.h @@ -52,6 +52,72 @@ * Maximum PCI mmio size in MiB. */ u16 pci_mmio_size; + + /* Data for RAM init */ + + /* DIMM SPD address. Use 8bit notation where BIT0 is always zero. */ + u8 spd_addresses[4]; + + /* PEI data for RAM init and early silicon init */ + u8 ts_addresses[4]; + + bool ec_present; + bool ddr3lv_support; + + /* N mode functionality. Leave this setting at 0. + * 0 Auto + * 1 1N + * 2 2N + */ + enum { + DDR_NMODE_AUTO = 0, + DDR_NMODE_1N, + DDR_NMODE_2N, + } nmode; + + /* DDR refresh rate config. JEDEC Standard No.21-C Annex K allows + * for DIMM SPD data to specify whether double-rate is required for + * extended operating temperature range. + * 0 Enable double rate based upon temperature thresholds + * 1 Normal rate + * 2 Always enable double rate + */ + enum { + DDR_REFRESH_RATE_TEMP_THRES = 0, + DDR_REFRESH_REATE_NORMAL, + DDR_REFRESH_RATE_DOUBLE, + } ddr_refresh_rate_config; + + /* + * USB Port Configuration: + * [0] = enable + * [1] = overcurrent pin + * [2] = length + * + * Ports 0-7 can be mapped to OC0-OC3 + * Ports 8-13 can be mapped to OC4-OC7 + * + * Port Length + * MOBILE: + * < 0x050 = Setting 1 (back panel, 1-5in, lowest tx amplitude) + * < 0x140 = Setting 2 (back panel, 5-14in, highest tx amplitude) + * DESKTOP: + * < 0x080 = Setting 1 (front/back panel, <8in, lowest tx amplitude) + * < 0x130 = Setting 2 (back panel, 8-13in, higher tx amplitude) + * < 0x150 = Setting 3 (back panel, 13-15in, highest tx amplitude) + */ + u16 usb_port_config[16][3]; + + struct { + /* 0: Disable, 1: Enable, 2: Auto, 3: Smart Auto */ + u8 mode : 2; + /* 4 bit mask, 1: switchable, 0: not switchable */ + u8 hs_port_switch_mask : 4; + /* 0: No xHCI preOS driver, 1: xHCI preOS driver */ + u8 preboot_support : 1; + /* 0: Disable, 1: Enable */ + u8 xhci_streams : 1; + } usb3; };
#endif /* NORTHBRIDGE_INTEL_SANDYBRIDGE_CHIP_H */ diff --git a/src/northbridge/intel/sandybridge/raminit_mrc.c b/src/northbridge/intel/sandybridge/raminit_mrc.c index 1c9e021..a35d9d8 100644 --- a/src/northbridge/intel/sandybridge/raminit_mrc.c +++ b/src/northbridge/intel/sandybridge/raminit_mrc.c @@ -20,6 +20,7 @@ #include <string.h> #include <arch/io.h> #include <device/pci_ops.h> +#include <arch/cpu.h> #include <cbmem.h> #include <arch/cbfs.h> #include <cbfs.h> @@ -32,6 +33,7 @@ #include "raminit.h" #include "pei_data.h" #include "sandybridge.h" +#include "chip.h" #include <security/vboot/vboot_common.h> #include <southbridge/intel/bd82x6x/pch.h>
@@ -275,6 +277,89 @@ u32 reserved[4]; } __packed;
+static void northbridge_fill_pei_data(struct pei_data *pei_data) +{ + pei_data->mchbar = (uintptr_t)DEFAULT_MCHBAR; + pei_data->dmibar = (uintptr_t)DEFAULT_DMIBAR; + pei_data->epbar = DEFAULT_EPBAR; + pei_data->pciexbar = CONFIG_MMCONF_BASE_ADDRESS; + pei_data->hpet_address = CONFIG_HPET_ADDRESS; + pei_data->thermalbase = 0xfed08000; + pei_data->system_type = get_platform_type() == PLATFORM_MOBILE ? 0 : 1; + pei_data->tseg_size = CONFIG_SMM_TSEG_SIZE; + + if ((cpu_get_cpuid() & 0xffff0) == 0x306a0) { + const struct device *dev = pcidev_on_root(1, 0); + pei_data->pcie_init = dev && dev->enabled; + } else { + pei_data->pcie_init = 0; + } +} + +static void southbridge_fill_pei_data(struct pei_data *pei_data) +{ + const struct device *dev = pcidev_on_root(0x19, 0); + + pei_data->smbusbar = SMBUS_IO_BASE; + pei_data->wdbbar = 0x4000000; + pei_data->wdbsize = 0x1000; + pei_data->rcba = (uintptr_t)DEFAULT_RCBABASE; + pei_data->pmbase = DEFAULT_PMBASE; + pei_data->gpiobase = DEFAULT_GPIOBASE; + pei_data->gbe_enable = dev && dev->enabled; +} + +static void devicetree_fill_pei_data(struct pei_data *pei_data) +{ + const struct northbridge_intel_sandybridge_config *cfg; + + const struct device *dev = pcidev_on_root(0, 0); + if (!dev || !dev->chip_info) + return; + + cfg = dev->chip_info; + + switch (cfg->max_mem_clock_mhz) { + /* MRC only supports fixed numbers of frequencies */ + default: + printk(BIOS_WARNING, "RAMINIT: Limiting DDR3 clock to 800 Mhz\n"); + /* fallthrough */ + case 400: + pei_data->max_ddr3_freq = 800; + break; + case 533: + pei_data->max_ddr3_freq = 1066; + break; + case 666: + pei_data->max_ddr3_freq = 1333; + break; + case 800: + pei_data->max_ddr3_freq = 1600; + break; + + } + + memcpy(pei_data->spd_addresses, cfg->spd_addresses, + sizeof(pei_data->spd_addresses)); + + memcpy(pei_data->ts_addresses, cfg->ts_addresses, + sizeof(pei_data->ts_addresses)); + + pei_data->ec_present = cfg->ec_present; + pei_data->ddr3lv_support = cfg->ddr3lv_support; + + pei_data->nmode = cfg->nmode; + pei_data->ddr_refresh_rate_config = cfg->ddr_refresh_rate_config; + + memcpy(pei_data->usb_port_config, cfg->usb_port_config, + sizeof(pei_data->usb_port_config)); + + pei_data->usb3.mode = cfg->usb3.mode; + pei_data->usb3.hs_port_switch_mask = cfg->usb3.hs_port_switch_mask; + pei_data->usb3.preboot_support = cfg->usb3.preboot_support; + pei_data->usb3.xhci_streams = cfg->usb3.xhci_streams; +} + void perform_raminit(int s3resume) { int cbmem_was_initted; @@ -285,10 +370,25 @@ if (!mainboard_should_reset_usb(s3resume)) enable_usb_bar();
+ memset(&pei_data, 0, sizeof(pei_data)); + pei_data.pei_version = PEI_VERSION, + + northbridge_fill_pei_data(&pei_data); + southbridge_fill_pei_data(&pei_data); + devicetree_fill_pei_data(&pei_data); mainboard_fill_pei_data(&pei_data);
post_code(0x3a);
+ /* Fill after mainboard_fill_pei_data as it might provide spd_data */ + pei_data.dimm_channel0_disabled = + (!pei_data.spd_addresses[0] && !pei_data.spd_data[0][0]) + + (!pei_data.spd_addresses[1] && !pei_data.spd_data[1][0]) * 2; + + pei_data.dimm_channel1_disabled = + (!pei_data.spd_addresses[2] && !pei_data.spd_data[2][0]) + + (!pei_data.spd_addresses[3] && !pei_data.spd_data[3][0]) * 2; + /* Fix spd_data. MRC only uses spd_data[0] and ignores the other */ for (size_t i = 1; i < ARRAY_SIZE(pei_data.spd_data); i++) { if (pei_data.spd_data[i][0] && !pei_data.spd_data[0][0]) {
Nico Rikken has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32069 )
Change subject: nb/intel/sandybridge: Migrate MRC settings to devicetree ......................................................................
Patch Set 11: Code-Review+1
Just checking in from my W520 with firmware based on commit 556cc26337bc3b36b20f139b5627de441eba88ef (Mon Nov 11 14:28:32 2019 +0100) from master. It seems to work flawlessly, so thanks for this work.
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build bot (Jenkins) (Code Review) -
Nico Huber (Code Review)
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Nico Rikken (Code Review)
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Patrick Georgi (Code Review)
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Patrick Rudolph (Code Review)