[coreboot-gerrit] Change in ...coreboot[master]: nb/intel/sandybridge: Fill common MRC settings in northbridge code

[Patrick Rudolph (Code Review)]

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32069

Change subject: nb/intel/sandybridge: Fill common MRC settings in northbridge code
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nb/intel/sandybridge: Fill common MRC settings in northbridge code

Fill northbridge and southbridge BARs in raminit code.
Allows to drop duplicated code from mainboard directories.

Change-Id: Ic6d9f0fd6a2b792ac693d6016ed9ce44945c900c
Signed-off-by: Patrick Rudolph 
---
M src/northbridge/intel/sandybridge/raminit_mrc.c
1 file changed, 19 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/32069/1

diff --git a/src/northbridge/intel/sandybridge/raminit_mrc.c b/src/northbridge/intel/sandybridge/raminit_mrc.c
index 852da7a..c544a74 100644
--- a/src/northbridge/intel/sandybridge/raminit_mrc.c
+++ b/src/northbridge/intel/sandybridge/raminit_mrc.c
@@ -275,6 +275,24 @@
    u32 reserved[4];
 } __packed;

+static void northbridge_fill_pei_data(struct pei_data *pei_data)
+{
+	pei_data->mchbar = (uintptr_t)DEFAULT_MCHBAR;
+	pei_data->dmibar = (uintptr_t)DEFAULT_DMIBAR;
+	pei_data->epbar = DEFAULT_EPBAR;
+	pei_data->pciexbar = CONFIG_MMCONF_BASE_ADDRESS;
+	pei_data->smbusbar = SMBUS_IO_BASE;
+	pei_data->wdbbar = 0x4000000;
+	pei_data->wdbsize = 0x1000;
+	pei_data->hpet_address = CONFIG_HPET_ADDRESS;
+	pei_data->rcba = (uintptr_t)DEFAULT_RCBABASE;
+	pei_data->pmbase = DEFAULT_PMBASE;
+	pei_data->gpiobase = DEFAULT_GPIOBASE;
+	pei_data->thermalbase = 0xfed08000;
+	pei_data->system_type = get_platform_type() == PLATFORM_MOBILE ? 0 : 1;
+	pei_data->tseg_size = CONFIG_SMM_TSEG_SIZE;
+}
+
 void perform_raminit(int s3resume)
 {
    int cbmem_was_initted;
@@ -286,6 +304,7 @@
    	enable_usb_bar();

mainboard_fill_pei_data(&pei_data);
+	northbridge_fill_pei_data(&pei_data);

post_code(0x3a);
    pei_data.boot_mode = s3resume ? 2 : 0;