Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46091 )
Change subject: mb/intel/adlrvp: Add ADL-P romstage mainboard code ......................................................................
mb/intel/adlrvp: Add ADL-P romstage mainboard code
List of changes: 1. Add DDR4 and LPDDR4 memory related code - SPD for LPDDR4 - DQ byte map - DQS CPU-DRAM map - Rcomp resistor - Rcomp target 2. Fill FSP-M related memory UPD parameters 3. Add devicetree.cb config parameters related to FSP-M UPD
TEST=Able to build and boot ADL-P RVP till ramstage early
Change-Id: Iffc5c17ed0725f61c8c274a80a1d27161ca6cebf Signed-off-by: Subrata Banik subrata.banik@intel.com --- M src/mainboard/intel/adlrvp/Makefile.inc A src/mainboard/intel/adlrvp/board_id.c A src/mainboard/intel/adlrvp/board_id.h A src/mainboard/intel/adlrvp/romstage_fsp_params.c A src/mainboard/intel/adlrvp/spd/Makefile.inc A src/mainboard/intel/adlrvp/spd/adlrvp_lp4.spd.hex A src/mainboard/intel/adlrvp/spd/empty.spd.hex A src/mainboard/intel/adlrvp/spd/spd.h M src/mainboard/intel/adlrvp/variants/adlrvp_p/Makefile.inc M src/mainboard/intel/adlrvp/variants/adlrvp_p/devicetree.cb A src/mainboard/intel/adlrvp/variants/adlrvp_p/memory.c M src/mainboard/intel/adlrvp/variants/baseboard/include/baseboard/variants.h 12 files changed, 341 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/91/46091/1
diff --git a/src/mainboard/intel/adlrvp/Makefile.inc b/src/mainboard/intel/adlrvp/Makefile.inc index 22f1abc..4064409 100644 --- a/src/mainboard/intel/adlrvp/Makefile.inc +++ b/src/mainboard/intel/adlrvp/Makefile.inc @@ -1,11 +1,15 @@ ## SPDX-License-Identifier: GPL-2.0-only
+subdirs-y += spd + bootblock-y += bootblock.c bootblock-$(CONFIG_CHROMEOS) += chromeos.c
verstage-$(CONFIG_CHROMEOS) += chromeos.c
romstage-$(CONFIG_CHROMEOS) += chromeos.c +romstage-y += romstage_fsp_params.c +romstage-y += board_id.c
ramstage-$(CONFIG_CHROMEOS) += chromeos.c
diff --git a/src/mainboard/intel/adlrvp/board_id.c b/src/mainboard/intel/adlrvp/board_id.c new file mode 100644 index 0000000..a6cad1c --- /dev/null +++ b/src/mainboard/intel/adlrvp/board_id.c @@ -0,0 +1,39 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <boardid.h> +#include <ec/acpi/ec.h> +#include <ec/google/chromeec/ec.h> +#include <stdint.h> + +#include "board_id.h" + +static uint32_t get_board_id_via_ext_ec(void) +{ + uint32_t id = BOARD_ID_INIT; + + if (google_chromeec_get_board_version(&id)) + id = BOARD_ID_UNKNOWN; + + return id; +} + +/* Get Board ID via EC I/O port write/read */ +int get_board_id(void) +{ + MAYBE_STATIC_NONZERO int id = -1; + + if (id < 0) { + if (CONFIG(EC_GOOGLE_CHROMEEC)) { + id = get_board_id_via_ext_ec(); + } else { + uint8_t buffer[2]; + uint8_t index; + if (send_ec_command(EC_FAB_ID_CMD) == 0) { + for (index = 0; index < sizeof(buffer); index++) + buffer[index] = recv_ec_data(); + id = (buffer[0] << 8) | buffer[1]; + } + } + } + return id; +} diff --git a/src/mainboard/intel/adlrvp/board_id.h b/src/mainboard/intel/adlrvp/board_id.h new file mode 100644 index 0000000..20483c8 --- /dev/null +++ b/src/mainboard/intel/adlrvp/board_id.h @@ -0,0 +1,17 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _MAINBOARD_COMMON_BOARD_ID_H_ +#define _MAINBOARD_COMMON_BOARD_ID_H_ + +#include <stdint.h> + +/* Board/FAB ID Command */ +#define EC_FAB_ID_CMD 0x0D + +/* + * Returns board information (board id[15:8] and + * Fab info[7:0]) on success and < 0 on error + */ +int get_board_id(void); + +#endif /* _MAINBOARD_COMMON_BOARD_ID_H_ */ diff --git a/src/mainboard/intel/adlrvp/romstage_fsp_params.c b/src/mainboard/intel/adlrvp/romstage_fsp_params.c new file mode 100644 index 0000000..56f2098 --- /dev/null +++ b/src/mainboard/intel/adlrvp/romstage_fsp_params.c @@ -0,0 +1,64 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +#include <assert.h> +#include <console/console.h> +#include <fsp/api.h> +#include <soc/romstage.h> +#include <spd_bin.h> +#include <string.h> +#include <soc/meminit.h> +#include <baseboard/variants.h> +#include <cbfs.h> +#include "board_id.h" +#include "spd/spd.h" + +static uintptr_t mainboard_get_spd_index(void) +{ + uint8_t board_id = (get_board_id() & 0x3F); + int spd_index; + + printk(BIOS_INFO, "board id is 0x%x\n", board_id); + + spd_index = (board_id & 0x1F) & 0x7; + + printk(BIOS_INFO, "SPD index is 0x%x\n", spd_index); + return spd_index; +} + +void mainboard_memory_init_params(FSPM_UPD *mupd) +{ + const struct mb_cfg *mem_config = variant_memory_params(); + int board_id = (get_board_id() & 0x3F); + + const struct spd_info lpddr4_spd_info = { + .read_type = READ_SPD_CBFS, + .spd_spec.spd_index = mainboard_get_spd_index(), + }; + + const struct spd_info ddr4_spd_info = { + .read_type = READ_SMBUS, + .spd_spec = + { .spd_smbus_address[0] = 0xA0, + .spd_smbus_address[1] = 0xA2, + .spd_smbus_address[8] = 0xA4, + .spd_smbus_address[9] = 0xA6 + } + }; + + bool half_populated = false; + + switch (board_id) { + case adl_p_ddr4_1: + case adl_p_ddr4_2: + mupd->FspmConfig.DqPinsInterleaved = 1; + memcfg_init(&mupd->FspmConfig, mem_config, &ddr4_spd_info, half_populated); + break; + case adl_p_lp4_1: + case adl_p_lp4_2: + mupd->FspmConfig.DqPinsInterleaved = 0; + memcfg_init(&mupd->FspmConfig, mem_config, &lpddr4_spd_info, half_populated); + break; + default: + die("Unknown board id = 0x%x\n", board_id); + break; + } +} diff --git a/src/mainboard/intel/adlrvp/spd/Makefile.inc b/src/mainboard/intel/adlrvp/spd/Makefile.inc new file mode 100644 index 0000000..aa9b294 --- /dev/null +++ b/src/mainboard/intel/adlrvp/spd/Makefile.inc @@ -0,0 +1,18 @@ +## SPDX-License-Identifier: GPL-2.0-only + +SPD_SOURCES = adlrvp_lp4 #0b000 +SPD_SOURCES += empty # 0b001 + +SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/spd/$(f).spd.hex) + +# Include spd ROM data +$(SPD_BIN): $(SPD_DEPS) + for f in $+; \ + do for c in $$(cat $$f | grep -v ^#); \ + do printf $$(printf '%o' 0x$$c); \ + done; \ + done > $@ + +cbfs-files-y += spd.bin +spd.bin-file := $(SPD_BIN) +spd.bin-type := spd diff --git a/src/mainboard/intel/adlrvp/spd/adlrvp_lp4.spd.hex b/src/mainboard/intel/adlrvp/spd/adlrvp_lp4.spd.hex new file mode 100644 index 0000000..17f270d --- /dev/null +++ b/src/mainboard/intel/adlrvp/spd/adlrvp_lp4.spd.hex @@ -0,0 +1,32 @@ +23 12 11 0E 15 21 B5 08 00 40 00 00 0A 01 00 00 +48 00 04 00 D2 54 01 00 87 40 90 A8 90 C0 08 60 +04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 E4 00 60 A1 AC +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 55 00 00 00 20 20 20 20 20 20 20 +20 20 20 20 20 20 20 20 20 20 20 20 20 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/intel/adlrvp/spd/empty.spd.hex b/src/mainboard/intel/adlrvp/spd/empty.spd.hex new file mode 100644 index 0000000..67b46cd --- /dev/null +++ b/src/mainboard/intel/adlrvp/spd/empty.spd.hex @@ -0,0 +1,32 @@ +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 80 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 80 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/intel/adlrvp/spd/spd.h b/src/mainboard/intel/adlrvp/spd/spd.h new file mode 100644 index 0000000..3429209 --- /dev/null +++ b/src/mainboard/intel/adlrvp/spd/spd.h @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef MAINBOARD_SPD_H +#define MAINBOARD_SPD_H + +void mainboard_fill_dq_map_ch0(void *dq_map_ptr); +void mainboard_fill_dq_map_ch1(void *dq_map_ptr); +void mainboard_fill_dqs_map_ch0(void *dqs_map_ptr); +void mainboard_fill_dqs_map_ch1(void *dqs_map_ptr); +void mainboard_fill_rcomp_res_data(void *rcomp_ptr); +void mainboard_fill_rcomp_strength_data(void *rcomp_strength_ptr); + +#endif diff --git a/src/mainboard/intel/adlrvp/variants/adlrvp_p/Makefile.inc b/src/mainboard/intel/adlrvp/variants/adlrvp_p/Makefile.inc index 9b21a1b..8c05721 100644 --- a/src/mainboard/intel/adlrvp/variants/adlrvp_p/Makefile.inc +++ b/src/mainboard/intel/adlrvp/variants/adlrvp_p/Makefile.inc @@ -1,3 +1,5 @@ ## SPDX-License-Identifier: GPL-2.0-only
bootblock-y += early_gpio.c + +romstage-y += memory.c diff --git a/src/mainboard/intel/adlrvp/variants/adlrvp_p/devicetree.cb b/src/mainboard/intel/adlrvp/variants/adlrvp_p/devicetree.cb index e16de65..9c7cb49 100644 --- a/src/mainboard/intel/adlrvp/variants/adlrvp_p/devicetree.cb +++ b/src/mainboard/intel/adlrvp/variants/adlrvp_p/devicetree.cb @@ -4,6 +4,8 @@ device lapic 0 on end end
+ # FSP configuration + register "SaGv" = "SaGv_Disabled" # EC host command ranges are in 0x800-0x8ff & 0x200-0x20f register "gen1_dec" = "0x00fc0801" register "gen2_dec" = "0x000c0201" @@ -11,6 +13,55 @@ register "gen3_dec" = "0x00fc0901" register "gen4_dec" = "0x000c0081"
+ register "PrmrrSize" = "0" + + register "PcieRpEnable[0]" = "1" + register "PcieRpEnable[1]" = "1" + register "PcieRpEnable[2]" = "1" + register "PcieRpEnable[3]" = "1" + register "PcieRpEnable[4]" = "1" + register "PcieRpEnable[5]" = "1" + register "PcieRpEnable[6]" = "1" + register "PcieRpEnable[7]" = "1" + register "PcieRpEnable[8]" = "1" + register "PcieRpEnable[9]" = "1" + register "PcieRpEnable[10]" = "1" + register "PcieRpEnable[11]" = "1" + + register "PcieClkSrcClkReq[0]" = "0" + register "PcieClkSrcClkReq[1]" = "1" + register "PcieClkSrcClkReq[2]" = "2" + register "PcieClkSrcClkReq[3]" = "3" + register "PcieClkSrcClkReq[4]" = "4" + register "PcieClkSrcClkReq[5]" = "5" + register "PcieClkSrcClkReq[6]" = "6" + register "PcieClkSrcClkReq[7]" = "7" + register "PcieClkSrcClkReq[8]" = "8" + register "PcieClkSrcClkReq[9]" = "9" + register "PcieClkSrcClkReq[10]" = "10" + register "PcieClkSrcClkReq[11]" = "11" + + register "PcieClkSrcUsage[0]" = "0x40" + register "PcieClkSrcUsage[1]" = "0x8" + register "PcieClkSrcUsage[2]" = "0x4" + register "PcieClkSrcUsage[3]" = "0x41" + register "PcieClkSrcUsage[4]" = "0x42" + register "PcieClkSrcUsage[5]" = "0x5" + register "PcieClkSrcUsage[6]" = "0x70" + + register "PcieRpClkReqDetect[0]" = "1" + register "PcieRpClkReqDetect[1]" = "1" + register "PcieRpClkReqDetect[2]" = "1" + register "PcieRpClkReqDetect[3]" = "1" + register "PcieRpClkReqDetect[4]" = "1" + register "PcieRpClkReqDetect[5]" = "1" + register "PcieRpClkReqDetect[6]" = "1" + register "PcieRpClkReqDetect[7]" = "1" + register "PcieRpClkReqDetect[8]" = "1" + register "PcieRpClkReqDetect[9]" = "1" + register "PcieRpClkReqDetect[10]" = "1" + register "PcieRpClkReqDetect[11]" = "1" + device domain 0 on device pci 00.0 on end # Host Bridge device pci 02.0 on end # Graphics diff --git a/src/mainboard/intel/adlrvp/variants/adlrvp_p/memory.c b/src/mainboard/intel/adlrvp/variants/adlrvp_p/memory.c new file mode 100644 index 0000000..cb0474b --- /dev/null +++ b/src/mainboard/intel/adlrvp/variants/adlrvp_p/memory.c @@ -0,0 +1,57 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <arch/cpu.h> +#include "../../board_id.h" +#include <baseboard/variants.h> +#include <soc/romstage.h> + +size_t __weak variant_memory_sku(void) +{ + return 0; +} + +static const struct mb_cfg mem_config = { + /* DQ byte map */ + .dq_map = { + { 0, 2, 3, 1, 6, 7, 5, 4, /* Byte 0 */ + 10, 8, 11, 9, 14, 12, 13, 15 }, /* Byte 1 */ + { 12, 8, 14, 10, 11, 13, 15, 9, /* Byte 2 */ + 5, 0, 7, 3, 6, 2, 1, 4 }, /* Byte 3 */ + { 3, 0, 2, 1, 6, 5, 4, 7, /* Byte 4 */ + 12, 13, 14, 15, 10, 9, 8, 11 }, /* Byte 5 */ + { 2, 6, 7, 1, 3, 4, 0, 5, /* Byte 6 */ + 9, 13, 8, 15, 14, 11, 12, 10 }, /* Byte 7 */ + { 3, 0, 1, 2, 7, 4, 6, 5, /* Byte 0 */ + 10, 8, 11, 9, 14, 13, 12, 15 }, /* Byte 1 */ + { 10, 12, 14, 8, 9, 13, 15, 11, /* Byte 2 */ + 3, 7, 6, 2, 0, 4, 5, 1 }, /* Byte 3 */ + { 12, 15, 14, 13, 9, 10, 11, 8, /* Byte 4 */ + 7, 4, 6, 5, 0, 1, 3, 2 }, /* Byte 5 */ + { 0, 2, 4, 3, 1, 6, 7, 5, /* Byte 6 */ + 13, 9, 10, 11, 8, 12, 14, 15 }, /* Byte 7 */ + }, + + /* DQS CPU<>DRAM map */ + .dqs_map = { + /* Ch 0 1 2 3 */ + { 0, 1 }, { 1, 0 }, { 0, 1 }, { 0, 1 }, + { 0, 1 }, { 1, 0 }, { 1, 0 }, { 0, 1 } + }, + + /* Baseboard uses 100, 100 and 100 rcomp resistors */ + .rcomp_resistor = {100, 100, 100}, + + /* + * Baseboard Rcomp target values. + */ + .rcomp_targets = {40, 30, 33, 33, 30}, + + .ect = true, /* Early Command Training */ + + .UserBd = BOARD_TYPE_MOBILE, +}; + +const struct mb_cfg *__weak variant_memory_params(void) +{ + return &mem_config; +} diff --git a/src/mainboard/intel/adlrvp/variants/baseboard/include/baseboard/variants.h b/src/mainboard/intel/adlrvp/variants/baseboard/include/baseboard/variants.h index 7a8f444..adbbe1e 100644 --- a/src/mainboard/intel/adlrvp/variants/baseboard/include/baseboard/variants.h +++ b/src/mainboard/intel/adlrvp/variants/baseboard/include/baseboard/variants.h @@ -4,13 +4,25 @@ #define __BASEBOARD_VARIANTS_H__
#include <soc/gpio.h> +#include <soc/meminit.h> #include <stdint.h> #include <vendorcode/google/chromeos/chromeos.h>
+enum adl_boardid { + /* ADL-P LPDDR4 RVPs */ + adl_p_lp4_1 = 0x10, + adl_p_lp4_2 = 0x11, + /* ADL-P DDR4 RVPs */ + adl_p_ddr4_1 = 0x14, + adl_p_ddr4_2 = 0x3F, +}; + /* The next set of functions return the gpio table and fill in the number of * entries for each table. */ const struct cros_gpio *variant_cros_gpios(size_t *num);
void variant_configure_early_gpio_pads(void);
+size_t variant_memory_sku(void); +const struct mb_cfg *variant_memory_params(void); #endif /*__BASEBOARD_VARIANTS_H__ */
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46091 )
Change subject: mb/intel/adlrvp: Add ADL-P romstage mainboard code ......................................................................
Patch Set 1:
(1 comment)
https://review.coreboot.org/c/coreboot/+/46091/1/src/mainboard/intel/adlrvp/... File src/mainboard/intel/adlrvp/romstage_fsp_params.c:
https://review.coreboot.org/c/coreboot/+/46091/1/src/mainboard/intel/adlrvp/... PS1, Line 40: { .spd_smbus_address[0] = 0xA0, that open brace { should be on the previous line
Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46091 )
Change subject: mb/intel/adlrvp: Add ADL-P romstage mainboard code ......................................................................
Patch Set 1:
(4 comments)
https://review.coreboot.org/c/coreboot/+/46091/1/src/mainboard/intel/adlrvp/... File src/mainboard/intel/adlrvp/board_id.c:
https://review.coreboot.org/c/coreboot/+/46091/1/src/mainboard/intel/adlrvp/... PS1, Line 30: uint8_t This should be `size_t` b/c that's what `sizeof` returns. Will also need #include <types.h>
https://review.coreboot.org/c/coreboot/+/46091/1/src/mainboard/intel/adlrvp/... File src/mainboard/intel/adlrvp/romstage_fsp_params.c:
https://review.coreboot.org/c/coreboot/+/46091/1/src/mainboard/intel/adlrvp/... PS1, Line 16: (get_board_id() & 0x3F); Should `get_board_id()` just always mask its return value with 0x3F in the function?
https://review.coreboot.org/c/coreboot/+/46091/1/src/mainboard/intel/adlrvp/... File src/mainboard/intel/adlrvp/variants/adlrvp_p/memory.c:
https://review.coreboot.org/c/coreboot/+/46091/1/src/mainboard/intel/adlrvp/... PS1, Line 15: .dq_map = { : { 0, 2, 3, 1, 6, 7, 5, 4, /* Byte 0 */ : 10, 8, 11, 9, 14, 12, 13, 15 }, /* Byte 1 */ : { 12, 8, 14, 10, 11, 13, 15, 9, /* Byte 2 */ : 5, 0, 7, 3, 6, 2, 1, 4 }, /* Byte 3 */ : { 3, 0, 2, 1, 6, 5, 4, 7, /* Byte 4 */ : 12, 13, 14, 15, 10, 9, 8, 11 }, /* Byte 5 */ : { 2, 6, 7, 1, 3, 4, 0, 5, /* Byte 6 */ : 9, 13, 8, 15, 14, 11, 12, 10 }, /* Byte 7 */ : { 3, 0, 1, 2, 7, 4, 6, 5, /* Byte 0 */ : 10, 8, 11, 9, 14, 13, 12, 15 }, /* Byte 1 */ : { 10, 12, 14, 8, 9, 13, 15, 11, /* Byte 2 */ : 3, 7, 6, 2, 0, 4, 5, 1 }, /* Byte 3 */ : { 12, 15, 14, 13, 9, 10, 11, 8, /* Byte 4 */ : 7, 4, 6, 5, 0, 1, 3, 2 }, /* Byte 5 */ : { 0, 2, 4, 3, 1, 6, 7, 5, /* Byte 6 */ : 13, 9, 10, 11, 8, 12, 14, 15 }, /* Byte 7 */ nit: line up the comments
https://review.coreboot.org/c/coreboot/+/46091/1/src/mainboard/intel/adlrvp/... PS1, Line 41: Baseboard uses 100, 100 and 100 rcomp resistors nit: maybe Baseboard uses only 100ohm Rcomp resistors
Hello build bot (Jenkins), Furquan Shaikh, Patrick Georgi, Martin Roth, Tim Wawrzynczak, Angel Pons,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/46091
to look at the new patch set (#2).
Change subject: mb/intel/adlrvp: Add ADL-P romstage mainboard code ......................................................................
mb/intel/adlrvp: Add ADL-P romstage mainboard code
List of changes: 1. Add DDR4 and LPDDR4 memory related code - SPD for LPDDR4 - DQ byte map - DQS CPU-DRAM map - Rcomp resistor - Rcomp target 2. Fill FSP-M related memory UPD parameters 3. Add devicetree.cb config parameters related to FSP-M UPD
TEST=Able to build and boot ADL-P RVP till ramstage early
Change-Id: Iffc5c17ed0725f61c8c274a80a1d27161ca6cebf Signed-off-by: Subrata Banik subrata.banik@intel.com --- M src/mainboard/intel/adlrvp/Makefile.inc A src/mainboard/intel/adlrvp/board_id.c A src/mainboard/intel/adlrvp/board_id.h A src/mainboard/intel/adlrvp/romstage_fsp_params.c A src/mainboard/intel/adlrvp/spd/Makefile.inc A src/mainboard/intel/adlrvp/spd/adlrvp_lp4.spd.hex A src/mainboard/intel/adlrvp/spd/empty.spd.hex A src/mainboard/intel/adlrvp/spd/spd.h M src/mainboard/intel/adlrvp/variants/adlrvp_p/Makefile.inc M src/mainboard/intel/adlrvp/variants/adlrvp_p/devicetree.cb A src/mainboard/intel/adlrvp/variants/adlrvp_p/memory.c M src/mainboard/intel/adlrvp/variants/baseboard/include/baseboard/variants.h 12 files changed, 342 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/91/46091/2
Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46091 )
Change subject: mb/intel/adlrvp: Add ADL-P romstage mainboard code ......................................................................
Patch Set 2:
(4 comments)
https://review.coreboot.org/c/coreboot/+/46091/1/src/mainboard/intel/adlrvp/... File src/mainboard/intel/adlrvp/board_id.c:
https://review.coreboot.org/c/coreboot/+/46091/1/src/mainboard/intel/adlrvp/... PS1, Line 30: uint8_t
This should be `size_t` b/c that's what `sizeof` returns. […]
Ack
https://review.coreboot.org/c/coreboot/+/46091/1/src/mainboard/intel/adlrvp/... File src/mainboard/intel/adlrvp/romstage_fsp_params.c:
https://review.coreboot.org/c/coreboot/+/46091/1/src/mainboard/intel/adlrvp/... PS1, Line 16: (get_board_id() & 0x3F);
Should `get_board_id()` just always mask its return value with 0x3F in the function?
Ack
https://review.coreboot.org/c/coreboot/+/46091/1/src/mainboard/intel/adlrvp/... File src/mainboard/intel/adlrvp/variants/adlrvp_p/memory.c:
https://review.coreboot.org/c/coreboot/+/46091/1/src/mainboard/intel/adlrvp/... PS1, Line 15: .dq_map = { : { 0, 2, 3, 1, 6, 7, 5, 4, /* Byte 0 */ : 10, 8, 11, 9, 14, 12, 13, 15 }, /* Byte 1 */ : { 12, 8, 14, 10, 11, 13, 15, 9, /* Byte 2 */ : 5, 0, 7, 3, 6, 2, 1, 4 }, /* Byte 3 */ : { 3, 0, 2, 1, 6, 5, 4, 7, /* Byte 4 */ : 12, 13, 14, 15, 10, 9, 8, 11 }, /* Byte 5 */ : { 2, 6, 7, 1, 3, 4, 0, 5, /* Byte 6 */ : 9, 13, 8, 15, 14, 11, 12, 10 }, /* Byte 7 */ : { 3, 0, 1, 2, 7, 4, 6, 5, /* Byte 0 */ : 10, 8, 11, 9, 14, 13, 12, 15 }, /* Byte 1 */ : { 10, 12, 14, 8, 9, 13, 15, 11, /* Byte 2 */ : 3, 7, 6, 2, 0, 4, 5, 1 }, /* Byte 3 */ : { 12, 15, 14, 13, 9, 10, 11, 8, /* Byte 4 */ : 7, 4, 6, 5, 0, 1, 3, 2 }, /* Byte 5 */ : { 0, 2, 4, 3, 1, 6, 7, 5, /* Byte 6 */ : 13, 9, 10, 11, 8, 12, 14, 15 }, /* Byte 7 */
nit: line up the comments
Ack
https://review.coreboot.org/c/coreboot/+/46091/1/src/mainboard/intel/adlrvp/... PS1, Line 41: Baseboard uses 100, 100 and 100 rcomp resistors
nit: maybe Baseboard uses only 100ohm Rcomp resistors
Ack
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46091 )
Change subject: mb/intel/adlrvp: Add ADL-P romstage mainboard code ......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/c/coreboot/+/46091/2/src/mainboard/intel/adlrvp/... File src/mainboard/intel/adlrvp/romstage_fsp_params.c:
https://review.coreboot.org/c/coreboot/+/46091/2/src/mainboard/intel/adlrvp/... PS2, Line 40: { .spd_smbus_address[0] = 0xA0, that open brace { should be on the previous line
Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46091 )
Change subject: mb/intel/adlrvp: Add ADL-P romstage mainboard code ......................................................................
Patch Set 2:
HI Angel, Tim, if you could take a look further if you have some free time.
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46091 )
Change subject: mb/intel/adlrvp: Add ADL-P romstage mainboard code ......................................................................
Patch Set 2:
(6 comments)
https://review.coreboot.org/c/coreboot/+/46091/2/src/mainboard/intel/adlrvp/... File src/mainboard/intel/adlrvp/romstage_fsp_params.c:
https://review.coreboot.org/c/coreboot/+/46091/2/src/mainboard/intel/adlrvp/... PS2, Line 40: { .spd_smbus_address[0] = 0xA0,
that open brace { should be on the previous line
I suggest formatting this struct as follows:
const struct spd_info ddr4_spd_info = { .read_type = READ_SMBUS, .spd_spec = { .spd_smbus_address = { .[0] = 0xa0, .[1] = 0xa2, .[8] = 0xa4, .[9] = 0xa6, }, }, };
https://review.coreboot.org/c/coreboot/+/46091/2/src/mainboard/intel/adlrvp/... File src/mainboard/intel/adlrvp/spd/Makefile.inc:
https://review.coreboot.org/c/coreboot/+/46091/2/src/mainboard/intel/adlrvp/... PS2, Line 6: SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/spd/$(f).spd.hex) : : # Include spd ROM data : $(SPD_BIN): $(SPD_DEPS) : for f in $+; \ : do for c in $$(cat $$f | grep -v ^#); \ : do printf $$(printf '%o' 0x$$c); \ : done; \ : done > $@ : : cbfs-files-y += spd.bin : spd.bin-file := $(SPD_BIN) : spd.bin-type := spd Most of this can be eliminated by using the HAVE_SPD_BIN_IN_CBFS Kconfig option
https://review.coreboot.org/c/coreboot/+/46091/2/src/mainboard/intel/adlrvp/... File src/mainboard/intel/adlrvp/spd/spd.h:
https://review.coreboot.org/c/coreboot/+/46091/2/src/mainboard/intel/adlrvp/... PS2, Line 6: void mainboard_fill_dq_map_ch0(void *dq_map_ptr); : void mainboard_fill_dq_map_ch1(void *dq_map_ptr); : void mainboard_fill_dqs_map_ch0(void *dqs_map_ptr); : void mainboard_fill_dqs_map_ch1(void *dqs_map_ptr); : void mainboard_fill_rcomp_res_data(void *rcomp_ptr); : void mainboard_fill_rcomp_strength_data(void *rcomp_strength_ptr); unused?
https://review.coreboot.org/c/coreboot/+/46091/2/src/mainboard/intel/adlrvp/... File src/mainboard/intel/adlrvp/variants/adlrvp_p/memory.c:
https://review.coreboot.org/c/coreboot/+/46091/2/src/mainboard/intel/adlrvp/... PS2, Line 8: __weak shouldn't be weak
https://review.coreboot.org/c/coreboot/+/46091/2/src/mainboard/intel/adlrvp/... PS2, Line 16: { 0, 2, 3, 1, 6, 7, 5, 4, /* Byte 0 */ : 10, 8, 11, 9, 14, 12, 13, 15 }, /* Byte 1 */ : { 12, 8, 14, 10, 11, 13, 15, 9, /* Byte 2 */ : 5, 0, 7, 3, 6, 2, 1, 4 }, /* Byte 3 */ : { 3, 0, 2, 1, 6, 5, 4, 7, /* Byte 4 */ : 12, 13, 14, 15, 10, 9, 8, 11 }, /* Byte 5 */ : { 2, 6, 7, 1, 3, 4, 0, 5, /* Byte 6 */ : 9, 13, 8, 15, 14, 11, 12, 10 }, /* Byte 7 */ : { 3, 0, 1, 2, 7, 4, 6, 5, /* Byte 0 */ : 10, 8, 11, 9, 14, 13, 12, 15 }, /* Byte 1 */ : { 10, 12, 14, 8, 9, 13, 15, 11, /* Byte 2 */ : 3, 7, 6, 2, 0, 4, 5, 1 }, /* Byte 3 */ : { 12, 15, 14, 13, 9, 10, 11, 8, /* Byte 4 */ : 7, 4, 6, 5, 0, 1, 3, 2 }, /* Byte 5 */ : { 0, 2, 4, 3, 1, 6, 7, 5, /* Byte 6 */ : 13, 9, 10, 11, 8, 12, 14, 15 }, nit: right-align the numbers to make this more readable:
{ 0, 2, 3, 1, 6, 7, 5, 4, 10, 8, 11, 9, 14, 12, 13, 15, },
https://review.coreboot.org/c/coreboot/+/46091/2/src/mainboard/intel/adlrvp/... PS2, Line 54: __weak This shouldn't be weak
Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46091 )
Change subject: mb/intel/adlrvp: Add ADL-P romstage mainboard code ......................................................................
Patch Set 2:
(6 comments)
ir
https://review.coreboot.org/c/coreboot/+/46091/2/src/mainboard/intel/adlrvp/... File src/mainboard/intel/adlrvp/romstage_fsp_params.c:
https://review.coreboot.org/c/coreboot/+/46091/2/src/mainboard/intel/adlrvp/... PS2, Line 40: { .spd_smbus_address[0] = 0xA0,
I suggest formatting this struct as follows: […]
Getting below error
src/mainboard/intel/adlrvp/romstage_fsp_params.c: In function 'mainboard_memory_init_params': src/mainboard/intel/adlrvp/romstage_fsp_params.c:41:6: error: expected identifier before '[' token .[0] = 0xa0, ^ src/mainboard/intel/adlrvp/romstage_fsp_params.c:42:5: error: expected '}' before '.' token .[1] = 0xa2, ^ src/mainboard/intel/adlrvp/romstage_fsp_params.c:40:25: note: to match this '{' .spd_smbus_address = { ^ src/mainboard/intel/adlrvp/romstage_fsp_params.c: At top level:
https://review.coreboot.org/c/coreboot/+/46091/2/src/mainboard/intel/adlrvp/... File src/mainboard/intel/adlrvp/spd/Makefile.inc:
https://review.coreboot.org/c/coreboot/+/46091/2/src/mainboard/intel/adlrvp/... PS2, Line 6: SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/spd/$(f).spd.hex) : : # Include spd ROM data : $(SPD_BIN): $(SPD_DEPS) : for f in $+; \ : do for c in $$(cat $$f | grep -v ^#); \ : do printf $$(printf '%o' 0x$$c); \ : done; \ : done > $@ : : cbfs-files-y += spd.bin : spd.bin-file := $(SPD_BIN) : spd.bin-type := spd
Most of this can be eliminated by using the HAVE_SPD_BIN_IN_CBFS Kconfig option
Ack
https://review.coreboot.org/c/coreboot/+/46091/2/src/mainboard/intel/adlrvp/... File src/mainboard/intel/adlrvp/spd/spd.h:
https://review.coreboot.org/c/coreboot/+/46091/2/src/mainboard/intel/adlrvp/... PS2, Line 6: void mainboard_fill_dq_map_ch0(void *dq_map_ptr); : void mainboard_fill_dq_map_ch1(void *dq_map_ptr); : void mainboard_fill_dqs_map_ch0(void *dqs_map_ptr); : void mainboard_fill_dqs_map_ch1(void *dqs_map_ptr); : void mainboard_fill_rcomp_res_data(void *rcomp_ptr); : void mainboard_fill_rcomp_strength_data(void *rcomp_strength_ptr);
unused?
my bad :(
https://review.coreboot.org/c/coreboot/+/46091/2/src/mainboard/intel/adlrvp/... File src/mainboard/intel/adlrvp/variants/adlrvp_p/memory.c:
https://review.coreboot.org/c/coreboot/+/46091/2/src/mainboard/intel/adlrvp/... PS2, Line 8: __weak
shouldn't be weak
Ack
https://review.coreboot.org/c/coreboot/+/46091/2/src/mainboard/intel/adlrvp/... PS2, Line 16: { 0, 2, 3, 1, 6, 7, 5, 4, /* Byte 0 */ : 10, 8, 11, 9, 14, 12, 13, 15 }, /* Byte 1 */ : { 12, 8, 14, 10, 11, 13, 15, 9, /* Byte 2 */ : 5, 0, 7, 3, 6, 2, 1, 4 }, /* Byte 3 */ : { 3, 0, 2, 1, 6, 5, 4, 7, /* Byte 4 */ : 12, 13, 14, 15, 10, 9, 8, 11 }, /* Byte 5 */ : { 2, 6, 7, 1, 3, 4, 0, 5, /* Byte 6 */ : 9, 13, 8, 15, 14, 11, 12, 10 }, /* Byte 7 */ : { 3, 0, 1, 2, 7, 4, 6, 5, /* Byte 0 */ : 10, 8, 11, 9, 14, 13, 12, 15 }, /* Byte 1 */ : { 10, 12, 14, 8, 9, 13, 15, 11, /* Byte 2 */ : 3, 7, 6, 2, 0, 4, 5, 1 }, /* Byte 3 */ : { 12, 15, 14, 13, 9, 10, 11, 8, /* Byte 4 */ : 7, 4, 6, 5, 0, 1, 3, 2 }, /* Byte 5 */ : { 0, 2, 4, 3, 1, 6, 7, 5, /* Byte 6 */ : 13, 9, 10, 11, 8, 12, 14, 15 },
nit: right-align the numbers to make this more readable: […]
Ack
https://review.coreboot.org/c/coreboot/+/46091/2/src/mainboard/intel/adlrvp/... PS2, Line 54: __weak
This shouldn't be weak
Ack
Hello build bot (Jenkins), Furquan Shaikh, Patrick Georgi, Martin Roth, Tim Wawrzynczak, Angel Pons,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/46091
to look at the new patch set (#3).
Change subject: mb/intel/adlrvp: Add ADL-P romstage mainboard code ......................................................................
mb/intel/adlrvp: Add ADL-P romstage mainboard code
List of changes: 1. Add DDR4 and LPDDR4 memory related code - SPD for LPDDR4 - DQ byte map - DQS CPU-DRAM map - Rcomp resistor - Rcomp target 2. Fill FSP-M related memory UPD parameters 3. Add devicetree.cb config parameters related to FSP-M UPD
TEST=Able to build and boot ADL-P RVP till ramstage early
Change-Id: Iffc5c17ed0725f61c8c274a80a1d27161ca6cebf Signed-off-by: Subrata Banik subrata.banik@intel.com --- M src/mainboard/intel/adlrvp/Kconfig M src/mainboard/intel/adlrvp/Makefile.inc A src/mainboard/intel/adlrvp/board_id.c A src/mainboard/intel/adlrvp/board_id.h A src/mainboard/intel/adlrvp/romstage_fsp_params.c A src/mainboard/intel/adlrvp/spd/Makefile.inc A src/mainboard/intel/adlrvp/spd/adlrvp_lp4.spd.hex A src/mainboard/intel/adlrvp/spd/empty.spd.hex M src/mainboard/intel/adlrvp/variants/adlrvp_p/Makefile.inc M src/mainboard/intel/adlrvp/variants/adlrvp_p/devicetree.cb A src/mainboard/intel/adlrvp/variants/adlrvp_p/memory.c M src/mainboard/intel/adlrvp/variants/baseboard/include/baseboard/variants.h 12 files changed, 310 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/91/46091/3
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46091 )
Change subject: mb/intel/adlrvp: Add ADL-P romstage mainboard code ......................................................................
Patch Set 3:
(1 comment)
https://review.coreboot.org/c/coreboot/+/46091/3/src/mainboard/intel/adlrvp/... File src/mainboard/intel/adlrvp/variants/adlrvp_p/memory.c:
https://review.coreboot.org/c/coreboot/+/46091/3/src/mainboard/intel/adlrvp/... PS3, Line 49: const struct mb_cfg * variant_memory_params(void) "foo * bar" should be "foo *bar"
Hello build bot (Jenkins), Furquan Shaikh, Patrick Georgi, Martin Roth, Tim Wawrzynczak, Angel Pons,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/46091
to look at the new patch set (#4).
Change subject: mb/intel/adlrvp: Add ADL-P romstage mainboard code ......................................................................
mb/intel/adlrvp: Add ADL-P romstage mainboard code
List of changes: 1. Add DDR4 and LPDDR4 memory related code - SPD for LPDDR4 - DQ byte map - DQS CPU-DRAM map - Rcomp resistor - Rcomp target 2. Fill FSP-M related memory UPD parameters 3. Add devicetree.cb config parameters related to FSP-M UPD
TEST=Able to build and boot ADL-P RVP till ramstage early
Change-Id: Iffc5c17ed0725f61c8c274a80a1d27161ca6cebf Signed-off-by: Subrata Banik subrata.banik@intel.com --- M src/mainboard/intel/adlrvp/Kconfig M src/mainboard/intel/adlrvp/Makefile.inc A src/mainboard/intel/adlrvp/board_id.c A src/mainboard/intel/adlrvp/board_id.h A src/mainboard/intel/adlrvp/romstage_fsp_params.c A src/mainboard/intel/adlrvp/spd/Makefile.inc A src/mainboard/intel/adlrvp/spd/adlrvp_lp4.spd.hex A src/mainboard/intel/adlrvp/spd/empty.spd.hex M src/mainboard/intel/adlrvp/variants/adlrvp_p/Makefile.inc M src/mainboard/intel/adlrvp/variants/adlrvp_p/devicetree.cb A src/mainboard/intel/adlrvp/variants/adlrvp_p/memory.c M src/mainboard/intel/adlrvp/variants/baseboard/include/baseboard/variants.h 12 files changed, 310 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/91/46091/4
Hello build bot (Jenkins), Furquan Shaikh, Patrick Georgi, Martin Roth, Tim Wawrzynczak, Angel Pons,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/46091
to look at the new patch set (#5).
Change subject: mb/intel/adlrvp: Add ADL-P romstage mainboard code ......................................................................
mb/intel/adlrvp: Add ADL-P romstage mainboard code
List of changes: 1. Add DDR4 and LPDDR4 memory related code - SPD for LPDDR4 - DQ byte map - DQS CPU-DRAM map - Rcomp resistor - Rcomp target 2. Fill FSP-M related UPD parameters 3. Add devicetree.cb config parameters related to FSP-M UPD
TEST=Able to build and boot ADL-P RVP till ramstage early
Change-Id: Iffc5c17ed0725f61c8c274a80a1d27161ca6cebf Signed-off-by: Subrata Banik subrata.banik@intel.com --- M src/mainboard/intel/adlrvp/Kconfig M src/mainboard/intel/adlrvp/Makefile.inc A src/mainboard/intel/adlrvp/board_id.c A src/mainboard/intel/adlrvp/board_id.h A src/mainboard/intel/adlrvp/romstage_fsp_params.c A src/mainboard/intel/adlrvp/spd/Makefile.inc A src/mainboard/intel/adlrvp/spd/adlrvp_lp4.spd.hex A src/mainboard/intel/adlrvp/spd/empty.spd.hex M src/mainboard/intel/adlrvp/variants/adlrvp_p/Makefile.inc M src/mainboard/intel/adlrvp/variants/adlrvp_p/devicetree.cb A src/mainboard/intel/adlrvp/variants/adlrvp_p/memory.c M src/mainboard/intel/adlrvp/variants/baseboard/include/baseboard/variants.h 12 files changed, 310 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/91/46091/5
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46091 )
Change subject: mb/intel/adlrvp: Add ADL-P romstage mainboard code ......................................................................
Patch Set 5:
(1 comment)
https://review.coreboot.org/c/coreboot/+/46091/2/src/mainboard/intel/adlrvp/... File src/mainboard/intel/adlrvp/romstage_fsp_params.c:
https://review.coreboot.org/c/coreboot/+/46091/2/src/mainboard/intel/adlrvp/... PS2, Line 40: { .spd_smbus_address[0] = 0xA0,
Getting below error […]
Oh, sorry. Remove the `.` before the array index specifiers, then it should work.
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46091 )
Change subject: mb/intel/adlrvp: Add ADL-P romstage mainboard code ......................................................................
Patch Set 5: Code-Review+1
(2 comments)
https://review.coreboot.org/c/coreboot/+/46091/5/src/mainboard/intel/adlrvp/... File src/mainboard/intel/adlrvp/variants/adlrvp_p/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/46091/5/src/mainboard/intel/adlrvp/... PS5, Line 29: register "PcieRpEnable[11]" = "1" I find it weird that all PCIe RPs are enabled. I would expect that not all PCH PCIe ports are x1.
https://review.coreboot.org/c/coreboot/+/46091/5/src/mainboard/intel/adlrvp/... PS5, Line 50: 0x70 This setting seems to be for use with Intel GbE, but its PCI device is disabled?
Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46091 )
Change subject: mb/intel/adlrvp: Add ADL-P romstage mainboard code ......................................................................
Patch Set 5:
(2 comments)
https://review.coreboot.org/c/coreboot/+/46091/5/src/mainboard/intel/adlrvp/... File src/mainboard/intel/adlrvp/variants/adlrvp_p/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/46091/5/src/mainboard/intel/adlrvp/... PS5, Line 29: register "PcieRpEnable[11]" = "1"
I find it weird that all PCIe RPs are enabled. I would expect that not all PCH PCIe ports are x1.
Ack
https://review.coreboot.org/c/coreboot/+/46091/5/src/mainboard/intel/adlrvp/... PS5, Line 50: 0x70
This setting seems to be for use with Intel GbE, but its PCI device is disabled?
Ack
Hello build bot (Jenkins), Furquan Shaikh, Patrick Georgi, Martin Roth, Tim Wawrzynczak, Angel Pons,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/46091
to look at the new patch set (#6).
Change subject: mb/intel/adlrvp: Add ADL-P romstage mainboard code ......................................................................
mb/intel/adlrvp: Add ADL-P romstage mainboard code
List of changes: 1. Add DDR4 and LPDDR4 memory related code - SPD for LPDDR4 - DQ byte map - DQS CPU-DRAM map - Rcomp resistor - Rcomp target 2. Fill FSP-M related UPD parameters 3. Add devicetree.cb config parameters related to FSP-M UPD
TEST=Able to build and boot ADL-P RVP till ramstage early
Change-Id: Iffc5c17ed0725f61c8c274a80a1d27161ca6cebf Signed-off-by: Subrata Banik subrata.banik@intel.com --- M src/mainboard/intel/adlrvp/Kconfig M src/mainboard/intel/adlrvp/Makefile.inc A src/mainboard/intel/adlrvp/board_id.c A src/mainboard/intel/adlrvp/board_id.h A src/mainboard/intel/adlrvp/romstage_fsp_params.c A src/mainboard/intel/adlrvp/spd/Makefile.inc A src/mainboard/intel/adlrvp/spd/adlrvp_lp4.spd.hex A src/mainboard/intel/adlrvp/spd/empty.spd.hex M src/mainboard/intel/adlrvp/variants/adlrvp_p/Makefile.inc M src/mainboard/intel/adlrvp/variants/adlrvp_p/devicetree.cb A src/mainboard/intel/adlrvp/variants/adlrvp_p/memory.c M src/mainboard/intel/adlrvp/variants/baseboard/include/baseboard/variants.h 12 files changed, 299 insertions(+), 8 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/91/46091/6
Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46091 )
Change subject: mb/intel/adlrvp: Add ADL-P romstage mainboard code ......................................................................
Patch Set 6:
(1 comment)
https://review.coreboot.org/c/coreboot/+/46091/2/src/mainboard/intel/adlrvp/... File src/mainboard/intel/adlrvp/romstage_fsp_params.c:
https://review.coreboot.org/c/coreboot/+/46091/2/src/mainboard/intel/adlrvp/... PS2, Line 40: { .spd_smbus_address[0] = 0xA0,
Oh, sorry. Remove the `.` before the array index specifiers, then it should work.
Ack
Hello build bot (Jenkins), Furquan Shaikh, Patrick Georgi, Martin Roth, Tim Wawrzynczak, Angel Pons,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/46091
to look at the new patch set (#7).
Change subject: mb/intel/adlrvp: Add ADL-P romstage mainboard code ......................................................................
mb/intel/adlrvp: Add ADL-P romstage mainboard code
List of changes: 1. Add DDR4 and LPDDR4 memory related code - SPD for LPDDR4 - DQ byte map - DQS CPU-DRAM map - Rcomp resistor - Rcomp target 2. Fill FSP-M related UPD parameters 3. Add devicetree.cb config parameters related to FSP-M UPD
TEST=Able to build and boot ADL-P RVP till ramstage early
Change-Id: Iffc5c17ed0725f61c8c274a80a1d27161ca6cebf Signed-off-by: Subrata Banik subrata.banik@intel.com --- M src/mainboard/intel/adlrvp/Kconfig M src/mainboard/intel/adlrvp/Makefile.inc A src/mainboard/intel/adlrvp/board_id.c A src/mainboard/intel/adlrvp/board_id.h A src/mainboard/intel/adlrvp/romstage_fsp_params.c A src/mainboard/intel/adlrvp/spd/Makefile.inc A src/mainboard/intel/adlrvp/spd/adlrvp_lp4.spd.hex A src/mainboard/intel/adlrvp/spd/empty.spd.hex M src/mainboard/intel/adlrvp/variants/adlrvp_p/Makefile.inc M src/mainboard/intel/adlrvp/variants/adlrvp_p/devicetree.cb A src/mainboard/intel/adlrvp/variants/adlrvp_p/memory.c M src/mainboard/intel/adlrvp/variants/baseboard/include/baseboard/variants.h 12 files changed, 301 insertions(+), 8 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/91/46091/7
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46091 )
Change subject: mb/intel/adlrvp: Add ADL-P romstage mainboard code ......................................................................
Patch Set 7: Code-Review+1
(1 comment)
LGTM, but I'd like to have Tim's opinion on this as well.
https://review.coreboot.org/c/coreboot/+/46091/5/src/mainboard/intel/adlrvp/... File src/mainboard/intel/adlrvp/variants/adlrvp_p/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/46091/5/src/mainboard/intel/adlrvp/... PS5, Line 29: register "PcieRpEnable[11]" = "1"
Ack
Much better. Thank you!
Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46091 )
Change subject: mb/intel/adlrvp: Add ADL-P romstage mainboard code ......................................................................
Patch Set 7:
(9 comments)
https://review.coreboot.org/c/coreboot/+/46091/7/src/mainboard/intel/adlrvp/... File src/mainboard/intel/adlrvp/board_id.h:
https://review.coreboot.org/c/coreboot/+/46091/7/src/mainboard/intel/adlrvp/... PS7, Line 6: #include <stdint.h> not required
https://review.coreboot.org/c/coreboot/+/46091/7/src/mainboard/intel/adlrvp/... File src/mainboard/intel/adlrvp/board_id.c:
https://review.coreboot.org/c/coreboot/+/46091/7/src/mainboard/intel/adlrvp/... PS7, Line 29: uint8_t buffer[2]; : size_t index; : if (send_ec_command(EC_FAB_ID_CMD) == 0) { : for (index = 0; index < sizeof(buffer); index++) : buffer[index] = recv_ec_data(); : id = (buffer[0] << 8) | buffer[1]; : } suggestion: I would rewrite this buffer and the loop: ``` if (send_ec_command(EC_FAB_ID_CMD) == 0) { id = recv_ec_data() << 8; id |= recv_ec_data(); } ```
https://review.coreboot.org/c/coreboot/+/46091/7/src/mainboard/intel/adlrvp/... PS7, Line 39: 0x3f symbolic constant here would be nice, even if it's BOARD_ID_MASK 😊
https://review.coreboot.org/c/coreboot/+/46091/7/src/mainboard/intel/adlrvp/... File src/mainboard/intel/adlrvp/romstage_fsp_params.c:
https://review.coreboot.org/c/coreboot/+/46091/7/src/mainboard/intel/adlrvp/... PS7, Line 13: mainboard_get_spd_index nit: this function is a "local" function, no need for the `mainboard` prefix
https://review.coreboot.org/c/coreboot/+/46091/7/src/mainboard/intel/adlrvp/... PS7, Line 20: 0x1F) & 0x7; symbolic constants would be nice
https://review.coreboot.org/c/coreboot/+/46091/7/src/mainboard/intel/adlrvp/... PS7, Line 48: bool const and can go up at the top w/ the other locals
https://review.coreboot.org/c/coreboot/+/46091/7/src/mainboard/intel/adlrvp/... File src/mainboard/intel/adlrvp/variants/adlrvp_p/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/46091/7/src/mainboard/intel/adlrvp/... PS7, Line 8: register "SaGv" = "SaGv_Disabled" nit: this is the default value
https://review.coreboot.org/c/coreboot/+/46091/7/src/mainboard/intel/adlrvp/... PS7, Line 43: disable disabled
https://review.coreboot.org/c/coreboot/+/46091/7/src/mainboard/intel/adlrvp/... File src/mainboard/intel/adlrvp/variants/baseboard/include/baseboard/variants.h:
https://review.coreboot.org/c/coreboot/+/46091/7/src/mainboard/intel/adlrvp/... PS7, Line 13: adl_p_lp4_1 = 0x10, : adl_p_lp4_2 = 0x11, : /* ADL-P DDR4 RVPs */ : adl_p_ddr4_1 = 0x14, : adl_p_ddr4_2 = 0x3F, : typically prefer uppercase enum values
Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46091 )
Change subject: mb/intel/adlrvp: Add ADL-P romstage mainboard code ......................................................................
Patch Set 7:
(9 comments)
https://review.coreboot.org/c/coreboot/+/46091/7/src/mainboard/intel/adlrvp/... File src/mainboard/intel/adlrvp/board_id.h:
https://review.coreboot.org/c/coreboot/+/46091/7/src/mainboard/intel/adlrvp/... PS7, Line 6: #include <stdint.h>
not required
Ack
https://review.coreboot.org/c/coreboot/+/46091/7/src/mainboard/intel/adlrvp/... File src/mainboard/intel/adlrvp/board_id.c:
https://review.coreboot.org/c/coreboot/+/46091/7/src/mainboard/intel/adlrvp/... PS7, Line 29: uint8_t buffer[2]; : size_t index; : if (send_ec_command(EC_FAB_ID_CMD) == 0) { : for (index = 0; index < sizeof(buffer); index++) : buffer[index] = recv_ec_data(); : id = (buffer[0] << 8) | buffer[1]; : }
suggestion: I would rewrite this buffer and the loop: […]
Ack
https://review.coreboot.org/c/coreboot/+/46091/7/src/mainboard/intel/adlrvp/... PS7, Line 39: 0x3f
symbolic constant here would be nice, even if it's BOARD_ID_MASK 😊
Ack
https://review.coreboot.org/c/coreboot/+/46091/7/src/mainboard/intel/adlrvp/... File src/mainboard/intel/adlrvp/romstage_fsp_params.c:
https://review.coreboot.org/c/coreboot/+/46091/7/src/mainboard/intel/adlrvp/... PS7, Line 13: mainboard_get_spd_index
nit: this function is a "local" function, no need for the `mainboard` prefix
Ack
https://review.coreboot.org/c/coreboot/+/46091/7/src/mainboard/intel/adlrvp/... PS7, Line 20: 0x1F) & 0x7;
symbolic constants would be nice
Ack
https://review.coreboot.org/c/coreboot/+/46091/7/src/mainboard/intel/adlrvp/... PS7, Line 48: bool
const and can go up at the top w/ the other locals
Ack
https://review.coreboot.org/c/coreboot/+/46091/7/src/mainboard/intel/adlrvp/... File src/mainboard/intel/adlrvp/variants/adlrvp_p/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/46091/7/src/mainboard/intel/adlrvp/... PS7, Line 8: register "SaGv" = "SaGv_Disabled"
nit: this is the default value
Tim, Default is subject to change over FSP version, in latest code I'm seeing default is 0x5 enable but for early SOC i would like to make Sagv disable
https://review.coreboot.org/c/coreboot/+/46091/7/src/mainboard/intel/adlrvp/... PS7, Line 43: disable
disabled
Ack
https://review.coreboot.org/c/coreboot/+/46091/7/src/mainboard/intel/adlrvp/... File src/mainboard/intel/adlrvp/variants/baseboard/include/baseboard/variants.h:
https://review.coreboot.org/c/coreboot/+/46091/7/src/mainboard/intel/adlrvp/... PS7, Line 13: adl_p_lp4_1 = 0x10, : adl_p_lp4_2 = 0x11, : /* ADL-P DDR4 RVPs */ : adl_p_ddr4_1 = 0x14, : adl_p_ddr4_2 = 0x3F, :
typically prefer uppercase enum values
Ack
Hello build bot (Jenkins), Furquan Shaikh, Patrick Georgi, Martin Roth, Tim Wawrzynczak, Angel Pons,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/46091
to look at the new patch set (#8).
Change subject: mb/intel/adlrvp: Add ADL-P romstage mainboard code ......................................................................
mb/intel/adlrvp: Add ADL-P romstage mainboard code
List of changes: 1. Add DDR4 and LPDDR4 memory related code - SPD for LPDDR4 - DQ byte map - DQS CPU-DRAM map - Rcomp resistor - Rcomp target 2. Fill FSP-M related UPD parameters 3. Add devicetree.cb config parameters related to FSP-M UPD
TEST=Able to build and boot ADL-P RVP till ramstage early
Change-Id: Iffc5c17ed0725f61c8c274a80a1d27161ca6cebf Signed-off-by: Subrata Banik subrata.banik@intel.com --- M src/mainboard/intel/adlrvp/Kconfig M src/mainboard/intel/adlrvp/Makefile.inc A src/mainboard/intel/adlrvp/board_id.c A src/mainboard/intel/adlrvp/board_id.h A src/mainboard/intel/adlrvp/romstage_fsp_params.c A src/mainboard/intel/adlrvp/spd/Makefile.inc A src/mainboard/intel/adlrvp/spd/adlrvp_lp4.spd.hex A src/mainboard/intel/adlrvp/spd/empty.spd.hex M src/mainboard/intel/adlrvp/variants/adlrvp_p/Makefile.inc M src/mainboard/intel/adlrvp/variants/adlrvp_p/devicetree.cb A src/mainboard/intel/adlrvp/variants/adlrvp_p/memory.c M src/mainboard/intel/adlrvp/variants/baseboard/include/baseboard/variants.h 12 files changed, 299 insertions(+), 8 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/91/46091/8
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46091 )
Change subject: mb/intel/adlrvp: Add ADL-P romstage mainboard code ......................................................................
Patch Set 8: Code-Review+1
(3 comments)
https://review.coreboot.org/c/coreboot/+/46091/8/src/mainboard/intel/adlrvp/... File src/mainboard/intel/adlrvp/romstage_fsp_params.c:
https://review.coreboot.org/c/coreboot/+/46091/8/src/mainboard/intel/adlrvp/... PS8, Line 16: uintptr_t why is this an uintptr_t? it's not really a pointer to anything
https://review.coreboot.org/c/coreboot/+/46091/8/src/mainboard/intel/adlrvp/... PS8, Line 23: spd_index = (board_id & BIT_4_0) & BIT_2_0; Hmm, this is essentially the same as `board_id & BIT_2_0`. Is it correct?
https://review.coreboot.org/c/coreboot/+/46091/7/src/mainboard/intel/adlrvp/... File src/mainboard/intel/adlrvp/variants/adlrvp_p/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/46091/7/src/mainboard/intel/adlrvp/... PS7, Line 8: register "SaGv" = "SaGv_Disabled"
Tim, Default is subject to change over FSP version, in latest code I'm seeing default is 0x5 enable […]
Sounds good.
Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46091 )
Change subject: mb/intel/adlrvp: Add ADL-P romstage mainboard code ......................................................................
Patch Set 8: Code-Review+1
(2 comments)
https://review.coreboot.org/c/coreboot/+/46091/8/src/mainboard/intel/adlrvp/... File src/mainboard/intel/adlrvp/romstage_fsp_params.c:
https://review.coreboot.org/c/coreboot/+/46091/8/src/mainboard/intel/adlrvp/... PS8, Line 16: uintptr_t
why is this an uintptr_t? it's not really a pointer to anything
`size_t` is probably more appropriate here, for `spd_index` too
https://review.coreboot.org/c/coreboot/+/46091/7/src/mainboard/intel/adlrvp/... File src/mainboard/intel/adlrvp/variants/adlrvp_p/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/46091/7/src/mainboard/intel/adlrvp/... PS7, Line 8: register "SaGv" = "SaGv_Disabled"
Sounds good.
Sorry, I don't mean the FSP default, I mean the devicetree default; if you don't set the `SaGv` register, `SaGv_Disabled` is the default value because it's 0.
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46091 )
Change subject: mb/intel/adlrvp: Add ADL-P romstage mainboard code ......................................................................
Patch Set 8:
(1 comment)
https://review.coreboot.org/c/coreboot/+/46091/7/src/mainboard/intel/adlrvp/... File src/mainboard/intel/adlrvp/variants/adlrvp_p/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/46091/7/src/mainboard/intel/adlrvp/... PS7, Line 8: register "SaGv" = "SaGv_Disabled"
Sorry, I don't mean the FSP default, I mean the devicetree default; if you don't set the `SaGv` regi […]
Ah, hrm. Couldn't SaGv be controlled by Kconfig, though? If SaGv doesn't have any mainboard-specific requirements, it would be good if it were a Kconfig option.
I usually want to set SaGv to FixedHigh to improve boot times when testing stuff, but would want to use Enabled to get better battery life. Having to patch the devicetree to do so is annoying.
Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46091 )
Change subject: mb/intel/adlrvp: Add ADL-P romstage mainboard code ......................................................................
Patch Set 8:
(1 comment)
https://review.coreboot.org/c/coreboot/+/46091/7/src/mainboard/intel/adlrvp/... File src/mainboard/intel/adlrvp/variants/adlrvp_p/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/46091/7/src/mainboard/intel/adlrvp/... PS7, Line 8: register "SaGv" = "SaGv_Disabled"
Ah, hrm. […]
I'm totally agree with you Angel, Sagv shouldn't need to manage from MB devicetree as this is more SoC related but the only concern we have in some new MB PO with untested DIMM we have seen recommendation coming from HW team to not enable SaGv and allow it to boot with lower freq scaling hence keeping it in MB. But we can safely move FSI products SaGv into Kconfig and make this practice. May be you can look at CNL/CML/SKL/ICL boards and come up with those changes ?
Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46091 )
Change subject: mb/intel/adlrvp: Add ADL-P romstage mainboard code ......................................................................
Patch Set 8:
(2 comments)
https://review.coreboot.org/c/coreboot/+/46091/8/src/mainboard/intel/adlrvp/... File src/mainboard/intel/adlrvp/romstage_fsp_params.c:
https://review.coreboot.org/c/coreboot/+/46091/8/src/mainboard/intel/adlrvp/... PS8, Line 16: uintptr_t
`size_t` is probably more appropriate here, for `spd_index` too
Ack
https://review.coreboot.org/c/coreboot/+/46091/8/src/mainboard/intel/adlrvp/... PS8, Line 23: spd_index = (board_id & BIT_4_0) & BIT_2_0;
Hmm, this is essentially the same as `board_id & BIT_2_0`. […]
Ack
Hello build bot (Jenkins), Furquan Shaikh, Patrick Georgi, Martin Roth, Tim Wawrzynczak, Angel Pons,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/46091
to look at the new patch set (#9).
Change subject: mb/intel/adlrvp: Add ADL-P romstage mainboard code ......................................................................
mb/intel/adlrvp: Add ADL-P romstage mainboard code
List of changes: 1. Add DDR4 and LPDDR4 memory related code - SPD for LPDDR4 - DQ byte map - DQS CPU-DRAM map - Rcomp resistor - Rcomp target 2. Fill FSP-M related UPD parameters 3. Add devicetree.cb config parameters related to FSP-M UPD
TEST=Able to build and boot ADL-P RVP till ramstage early
Change-Id: Iffc5c17ed0725f61c8c274a80a1d27161ca6cebf Signed-off-by: Subrata Banik subrata.banik@intel.com --- M src/mainboard/intel/adlrvp/Kconfig M src/mainboard/intel/adlrvp/Makefile.inc A src/mainboard/intel/adlrvp/board_id.c A src/mainboard/intel/adlrvp/board_id.h A src/mainboard/intel/adlrvp/romstage_fsp_params.c A src/mainboard/intel/adlrvp/spd/Makefile.inc A src/mainboard/intel/adlrvp/spd/adlrvp_lp4.spd.hex A src/mainboard/intel/adlrvp/spd/empty.spd.hex M src/mainboard/intel/adlrvp/variants/adlrvp_p/Makefile.inc M src/mainboard/intel/adlrvp/variants/adlrvp_p/devicetree.cb A src/mainboard/intel/adlrvp/variants/adlrvp_p/memory.c M src/mainboard/intel/adlrvp/variants/baseboard/include/baseboard/variants.h 12 files changed, 296 insertions(+), 8 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/91/46091/9
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46091 )
Change subject: mb/intel/adlrvp: Add ADL-P romstage mainboard code ......................................................................
Patch Set 9: Code-Review+1
(2 comments)
https://review.coreboot.org/c/coreboot/+/46091/9/src/mainboard/intel/adlrvp/... File src/mainboard/intel/adlrvp/romstage_fsp_params.c:
https://review.coreboot.org/c/coreboot/+/46091/9/src/mainboard/intel/adlrvp/... PS9, Line 22: BIT_2_0 BOARD_ID_MASK maybe?
https://review.coreboot.org/c/coreboot/+/46091/7/src/mainboard/intel/adlrvp/... File src/mainboard/intel/adlrvp/variants/adlrvp_p/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/46091/7/src/mainboard/intel/adlrvp/... PS7, Line 8: register "SaGv" = "SaGv_Disabled"
I'm totally agree with you Angel, Sagv shouldn't need to manage from MB devicetree as this is more S […]
Sure, I can give it a try.
Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46091 )
Change subject: mb/intel/adlrvp: Add ADL-P romstage mainboard code ......................................................................
Patch Set 9:
(1 comment)
https://review.coreboot.org/c/coreboot/+/46091/9/src/mainboard/intel/adlrvp/... File src/mainboard/intel/adlrvp/romstage_fsp_params.c:
https://review.coreboot.org/c/coreboot/+/46091/9/src/mainboard/intel/adlrvp/... PS9, Line 22: BIT_2_0
BOARD_ID_MASK maybe?
we just need 3 bits here, BOARD_ID_MASK we already have https://review.coreboot.org/c/coreboot/+/46091/9/src/mainboard/intel/adlrvp/... which is bit 5:0
Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46091 )
Change subject: mb/intel/adlrvp: Add ADL-P romstage mainboard code ......................................................................
Patch Set 9:
(1 comment)
https://review.coreboot.org/c/coreboot/+/46091/9/src/mainboard/intel/adlrvp/... File src/mainboard/intel/adlrvp/romstage_fsp_params.c:
https://review.coreboot.org/c/coreboot/+/46091/9/src/mainboard/intel/adlrvp/... PS9, Line 22: BIT_2_0
we just need 3 bits here, BOARD_ID_MASK we already have https://review.coreboot. […]
Ack
Hello build bot (Jenkins), Furquan Shaikh, Patrick Georgi, Martin Roth, Tim Wawrzynczak, Angel Pons,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/46091
to look at the new patch set (#10).
Change subject: mb/intel/adlrvp: Add ADL-P romstage mainboard code ......................................................................
mb/intel/adlrvp: Add ADL-P romstage mainboard code
List of changes: 1. Add DDR4 and LPDDR4 memory related code - SPD for LPDDR4 - DQ byte map - DQS CPU-DRAM map - Rcomp resistor - Rcomp target 2. Fill FSP-M related UPD parameters 3. Add devicetree.cb config parameters related to FSP-M UPD
TEST=Able to build and boot ADL-P RVP till ramstage early
Change-Id: Iffc5c17ed0725f61c8c274a80a1d27161ca6cebf Signed-off-by: Subrata Banik subrata.banik@intel.com --- M src/mainboard/intel/adlrvp/Kconfig M src/mainboard/intel/adlrvp/Makefile.inc A src/mainboard/intel/adlrvp/board_id.c A src/mainboard/intel/adlrvp/board_id.h A src/mainboard/intel/adlrvp/romstage_fsp_params.c A src/mainboard/intel/adlrvp/spd/Makefile.inc A src/mainboard/intel/adlrvp/spd/adlrvp_lp4.spd.hex A src/mainboard/intel/adlrvp/spd/empty.spd.hex M src/mainboard/intel/adlrvp/variants/adlrvp_p/Makefile.inc M src/mainboard/intel/adlrvp/variants/adlrvp_p/devicetree.cb A src/mainboard/intel/adlrvp/variants/adlrvp_p/memory.c M src/mainboard/intel/adlrvp/variants/baseboard/include/baseboard/variants.h 12 files changed, 296 insertions(+), 8 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/91/46091/10
Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46091 )
Change subject: mb/intel/adlrvp: Add ADL-P romstage mainboard code ......................................................................
Patch Set 10:
(1 comment)
https://review.coreboot.org/c/coreboot/+/46091/9/src/mainboard/intel/adlrvp/... File src/mainboard/intel/adlrvp/romstage_fsp_params.c:
https://review.coreboot.org/c/coreboot/+/46091/9/src/mainboard/intel/adlrvp/... PS9, Line 22: BIT_2_0
Ack
Angel hope this is good now?
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46091 )
Change subject: mb/intel/adlrvp: Add ADL-P romstage mainboard code ......................................................................
Patch Set 10: Code-Review+2
(1 comment)
https://review.coreboot.org/c/coreboot/+/46091/9/src/mainboard/intel/adlrvp/... File src/mainboard/intel/adlrvp/romstage_fsp_params.c:
https://review.coreboot.org/c/coreboot/+/46091/9/src/mainboard/intel/adlrvp/... PS9, Line 22: BIT_2_0
Angel hope this is good now?
Perfect.
Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/46091 )
Change subject: mb/intel/adlrvp: Add ADL-P romstage mainboard code ......................................................................
mb/intel/adlrvp: Add ADL-P romstage mainboard code
List of changes: 1. Add DDR4 and LPDDR4 memory related code - SPD for LPDDR4 - DQ byte map - DQS CPU-DRAM map - Rcomp resistor - Rcomp target 2. Fill FSP-M related UPD parameters 3. Add devicetree.cb config parameters related to FSP-M UPD
TEST=Able to build and boot ADL-P RVP till ramstage early
Change-Id: Iffc5c17ed0725f61c8c274a80a1d27161ca6cebf Signed-off-by: Subrata Banik subrata.banik@intel.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/46091 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Angel Pons th3fanbus@gmail.com --- M src/mainboard/intel/adlrvp/Kconfig M src/mainboard/intel/adlrvp/Makefile.inc A src/mainboard/intel/adlrvp/board_id.c A src/mainboard/intel/adlrvp/board_id.h A src/mainboard/intel/adlrvp/romstage_fsp_params.c A src/mainboard/intel/adlrvp/spd/Makefile.inc A src/mainboard/intel/adlrvp/spd/adlrvp_lp4.spd.hex A src/mainboard/intel/adlrvp/spd/empty.spd.hex M src/mainboard/intel/adlrvp/variants/adlrvp_p/Makefile.inc M src/mainboard/intel/adlrvp/variants/adlrvp_p/devicetree.cb A src/mainboard/intel/adlrvp/variants/adlrvp_p/memory.c M src/mainboard/intel/adlrvp/variants/baseboard/include/baseboard/variants.h 12 files changed, 296 insertions(+), 8 deletions(-)
Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, approved
diff --git a/src/mainboard/intel/adlrvp/Kconfig b/src/mainboard/intel/adlrvp/Kconfig index 27c3957..97b4bf7 100644 --- a/src/mainboard/intel/adlrvp/Kconfig +++ b/src/mainboard/intel/adlrvp/Kconfig @@ -12,6 +12,7 @@ select DRIVERS_USB_ACPI select DRIVERS_SPI_ACPI select SOC_INTEL_ALDERLAKE + select HAVE_SPD_IN_CBFS
config CHROMEOS bool diff --git a/src/mainboard/intel/adlrvp/Makefile.inc b/src/mainboard/intel/adlrvp/Makefile.inc index eb4a981..e8a0eca 100644 --- a/src/mainboard/intel/adlrvp/Makefile.inc +++ b/src/mainboard/intel/adlrvp/Makefile.inc @@ -1,11 +1,15 @@ ## SPDX-License-Identifier: GPL-2.0-only
+subdirs-y += spd + bootblock-y += bootblock.c bootblock-$(CONFIG_CHROMEOS) += chromeos.c
verstage-$(CONFIG_CHROMEOS) += chromeos.c
romstage-$(CONFIG_CHROMEOS) += chromeos.c +romstage-y += romstage_fsp_params.c +romstage-y += board_id.c
ramstage-$(CONFIG_CHROMEOS) += chromeos.c
diff --git a/src/mainboard/intel/adlrvp/board_id.c b/src/mainboard/intel/adlrvp/board_id.c new file mode 100644 index 0000000..332ba1b --- /dev/null +++ b/src/mainboard/intel/adlrvp/board_id.c @@ -0,0 +1,36 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <boardid.h> +#include <ec/acpi/ec.h> +#include <ec/google/chromeec/ec.h> +#include <stdint.h> +#include <types.h> +#include "board_id.h" + +static uint32_t get_board_id_via_ext_ec(void) +{ + uint32_t id = BOARD_ID_INIT; + + if (google_chromeec_get_board_version(&id)) + id = BOARD_ID_UNKNOWN; + + return id; +} + +/* Get Board ID via EC I/O port write/read */ +int get_board_id(void) +{ + MAYBE_STATIC_NONZERO int id = -1; + + if (id < 0) { + if (CONFIG(EC_GOOGLE_CHROMEEC)) { + id = get_board_id_via_ext_ec(); + } else { + if (send_ec_command(EC_FAB_ID_CMD) == 0) { + id = recv_ec_data() << 8; + id |= recv_ec_data(); + } + } + } + return (id & BOARD_ID_MASK); +} diff --git a/src/mainboard/intel/adlrvp/board_id.h b/src/mainboard/intel/adlrvp/board_id.h new file mode 100644 index 0000000..2988127 --- /dev/null +++ b/src/mainboard/intel/adlrvp/board_id.h @@ -0,0 +1,17 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _MAINBOARD_COMMON_BOARD_ID_H_ +#define _MAINBOARD_COMMON_BOARD_ID_H_ + +/* Board/FAB ID Command */ +#define EC_FAB_ID_CMD 0x0d +/* Bit 5:0 for Board ID */ +#define BOARD_ID_MASK 0x3f + +/* + * Returns board information (board id[15:8] and + * Fab info[7:0]) on success and < 0 on error + */ +int get_board_id(void); + +#endif /* _MAINBOARD_COMMON_BOARD_ID_H_ */ diff --git a/src/mainboard/intel/adlrvp/romstage_fsp_params.c b/src/mainboard/intel/adlrvp/romstage_fsp_params.c new file mode 100644 index 0000000..9d7cc91 --- /dev/null +++ b/src/mainboard/intel/adlrvp/romstage_fsp_params.c @@ -0,0 +1,66 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +#include <assert.h> +#include <console/console.h> +#include <fsp/api.h> +#include <soc/romstage.h> +#include <spd_bin.h> +#include <string.h> +#include <soc/meminit.h> +#include <baseboard/variants.h> +#include <cbfs.h> +#include "board_id.h" + +#define SPD_ID_MASK 0x7 + +static size_t get_spd_index(void) +{ + uint8_t board_id = get_board_id(); + size_t spd_index; + + printk(BIOS_INFO, "board id is 0x%x\n", board_id); + + spd_index = board_id & SPD_ID_MASK; + + printk(BIOS_INFO, "SPD index is 0x%x\n", (unsigned int)spd_index); + return spd_index; +} + +void mainboard_memory_init_params(FSPM_UPD *mupd) +{ + const struct mb_cfg *mem_config = variant_memory_params(); + int board_id = get_board_id(); + const bool half_populated = false; + + const struct spd_info lpddr4_spd_info = { + .read_type = READ_SPD_CBFS, + .spd_spec.spd_index = get_spd_index(), + }; + + const struct spd_info ddr4_spd_info = { + .read_type = READ_SMBUS, + .spd_spec = { + .spd_smbus_address = { + [0] = 0xa0, + [1] = 0xa2, + [8] = 0xa4, + [9] = 0xa6, + }, + }, + }; + + switch (board_id) { + case ADL_P_DDR4_1: + case ADL_P_DDR4_2: + mupd->FspmConfig.DqPinsInterleaved = 1; + memcfg_init(&mupd->FspmConfig, mem_config, &ddr4_spd_info, half_populated); + break; + case ADL_P_LP4_1: + case ADL_P_LP4_2: + mupd->FspmConfig.DqPinsInterleaved = 0; + memcfg_init(&mupd->FspmConfig, mem_config, &lpddr4_spd_info, half_populated); + break; + default: + die("Unknown board id = 0x%x\n", board_id); + break; + } +} diff --git a/src/mainboard/intel/adlrvp/spd/Makefile.inc b/src/mainboard/intel/adlrvp/spd/Makefile.inc new file mode 100644 index 0000000..1218a76 --- /dev/null +++ b/src/mainboard/intel/adlrvp/spd/Makefile.inc @@ -0,0 +1,4 @@ +## SPDX-License-Identifier: GPL-2.0-only + +SPD_SOURCES = adlrvp_lp4 #0b000 +SPD_SOURCES += empty # 0b001 diff --git a/src/mainboard/intel/adlrvp/spd/adlrvp_lp4.spd.hex b/src/mainboard/intel/adlrvp/spd/adlrvp_lp4.spd.hex new file mode 100644 index 0000000..17f270d --- /dev/null +++ b/src/mainboard/intel/adlrvp/spd/adlrvp_lp4.spd.hex @@ -0,0 +1,32 @@ +23 12 11 0E 15 21 B5 08 00 40 00 00 0A 01 00 00 +48 00 04 00 D2 54 01 00 87 40 90 A8 90 C0 08 60 +04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 E4 00 60 A1 AC +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 55 00 00 00 20 20 20 20 20 20 20 +20 20 20 20 20 20 20 20 20 20 20 20 20 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/intel/adlrvp/spd/empty.spd.hex b/src/mainboard/intel/adlrvp/spd/empty.spd.hex new file mode 100644 index 0000000..67b46cd --- /dev/null +++ b/src/mainboard/intel/adlrvp/spd/empty.spd.hex @@ -0,0 +1,32 @@ +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 80 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 80 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/intel/adlrvp/variants/adlrvp_p/Makefile.inc b/src/mainboard/intel/adlrvp/variants/adlrvp_p/Makefile.inc index 9b21a1b..8c05721 100644 --- a/src/mainboard/intel/adlrvp/variants/adlrvp_p/Makefile.inc +++ b/src/mainboard/intel/adlrvp/variants/adlrvp_p/Makefile.inc @@ -1,3 +1,5 @@ ## SPDX-License-Identifier: GPL-2.0-only
bootblock-y += early_gpio.c + +romstage-y += memory.c diff --git a/src/mainboard/intel/adlrvp/variants/adlrvp_p/devicetree.cb b/src/mainboard/intel/adlrvp/variants/adlrvp_p/devicetree.cb index e16de65..a6b0039 100644 --- a/src/mainboard/intel/adlrvp/variants/adlrvp_p/devicetree.cb +++ b/src/mainboard/intel/adlrvp/variants/adlrvp_p/devicetree.cb @@ -11,6 +11,36 @@ register "gen3_dec" = "0x00fc0901" register "gen4_dec" = "0x000c0081"
+ register "PrmrrSize" = "0" + + # Enable PCH PCIE RP 5 using CLK 2 + register "PcieRpEnable[4]" = "1" + register "PcieClkSrcClkReq[4]" = "4" + register "PcieClkSrcUsage[2]" = "0x4" + register "PcieRpClkReqDetect[4]" = "1" + + # Enable PCH PCIE RP 6 using CLK 5 + register "PcieRpEnable[5]" = "1" + register "PcieClkSrcClkReq[5]" = "5" + register "PcieClkSrcUsage[5]" = "0x5" + register "PcieRpClkReqDetect[5]" = "1" + + # Enable PCH PCIE RP 9 using CLK 1 + register "PcieRpEnable[8]" = "1" + register "PcieClkSrcClkReq[8]" = "8" + register "PcieClkSrcUsage[1]" = "0x8" + register "PcieRpClkReqDetect[8]" = "1" + + # Enable CPU PCIE RP 1 using PEG CLK 0 + register "PcieClkSrcUsage[0]" = "0x40" + + # Enable PCU PCIE PEG Slot 1 and 2 + register "PcieClkSrcUsage[3]" = "0x41" + register "PcieClkSrcUsage[4]" = "0x42" + + # Mark LAN CLK pins as unused as GbE 0:0x1f.6 is disabled below + register "PcieClkSrcUsage[6]" = "0xff" + device domain 0 on device pci 00.0 on end # Host Bridge device pci 02.0 on end # Graphics @@ -79,17 +109,17 @@ device pci 19.1 on end # I2C5 device pci 19.2 on end # UART2 device pci 1c.0 on end # RP1 - device pci 1c.1 on end # RP2 - device pci 1c.2 on end # RP3 - device pci 1c.3 on end # RP4 + device pci 1c.1 off end # RP2 + device pci 1c.2 off end # RP3 + device pci 1c.3 off end # RP4 device pci 1c.4 on end # RP5 device pci 1c.5 on end # RP6 - device pci 1c.6 on end # RP7 - device pci 1c.7 on end # RP8 + device pci 1c.6 off end # RP7 + device pci 1c.7 off end # RP8 device pci 1d.0 on end # RP9 - device pci 1d.1 on end # RP10 - device pci 1d.2 on end # RP11 - device pci 1d.3 on end # RP12 + device pci 1d.1 off end # RP10 + device pci 1d.2 off end # RP11 + device pci 1d.3 off end # RP12 device pci 1e.0 off end # UART0 device pci 1e.1 off end # UART1 device pci 1e.2 off end # GSPI0 diff --git a/src/mainboard/intel/adlrvp/variants/adlrvp_p/memory.c b/src/mainboard/intel/adlrvp/variants/adlrvp_p/memory.c new file mode 100644 index 0000000..f8b3660 --- /dev/null +++ b/src/mainboard/intel/adlrvp/variants/adlrvp_p/memory.c @@ -0,0 +1,52 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <arch/cpu.h> +#include "../../board_id.h" +#include <baseboard/variants.h> +#include <soc/romstage.h> + +static const struct mb_cfg mem_config = { + /* DQ byte map */ + .dq_map = { + { 0, 2, 3, 1, 6, 7, 5, 4, /* Byte 0 */ + 10, 8, 11, 9, 14, 12, 13, 15 }, /* Byte 1 */ + { 12, 8, 14, 10, 11, 13, 15, 9, /* Byte 2 */ + 5, 0, 7, 3, 6, 2, 1, 4 }, /* Byte 3 */ + { 3, 0, 2, 1, 6, 5, 4, 7, /* Byte 4 */ + 12, 13, 14, 15, 10, 9, 8, 11 }, /* Byte 5 */ + { 2, 6, 7, 1, 3, 4, 0, 5, /* Byte 6 */ + 9, 13, 8, 15, 14, 11, 12, 10 }, /* Byte 7 */ + { 3, 0, 1, 2, 7, 4, 6, 5, /* Byte 0 */ + 10, 8, 11, 9, 14, 13, 12, 15 }, /* Byte 1 */ + { 10, 12, 14, 8, 9, 13, 15, 11, /* Byte 2 */ + 3, 7, 6, 2, 0, 4, 5, 1 }, /* Byte 3 */ + { 12, 15, 14, 13, 9, 10, 11, 8, /* Byte 4 */ + 7, 4, 6, 5, 0, 1, 3, 2 }, /* Byte 5 */ + { 0, 2, 4, 3, 1, 6, 7, 5, /* Byte 6 */ + 13, 9, 10, 11, 8, 12, 14, 15 }, /* Byte 7 */ + }, + + /* DQS CPU<>DRAM map */ + .dqs_map = { + /* Ch 0 1 2 3 */ + { 0, 1 }, { 1, 0 }, { 0, 1 }, { 0, 1 }, + { 0, 1 }, { 1, 0 }, { 1, 0 }, { 0, 1 } + }, + + /* Baseboard uses only 100ohm Rcomp resistors */ + .rcomp_resistor = {100, 100, 100}, + + /* + * Baseboard Rcomp target values. + */ + .rcomp_targets = {40, 30, 33, 33, 30}, + + .ect = true, /* Early Command Training */ + + .UserBd = BOARD_TYPE_MOBILE, +}; + +const struct mb_cfg *variant_memory_params(void) +{ + return &mem_config; +} diff --git a/src/mainboard/intel/adlrvp/variants/baseboard/include/baseboard/variants.h b/src/mainboard/intel/adlrvp/variants/baseboard/include/baseboard/variants.h index 7a8f444..5288b6f 100644 --- a/src/mainboard/intel/adlrvp/variants/baseboard/include/baseboard/variants.h +++ b/src/mainboard/intel/adlrvp/variants/baseboard/include/baseboard/variants.h @@ -4,13 +4,25 @@ #define __BASEBOARD_VARIANTS_H__
#include <soc/gpio.h> +#include <soc/meminit.h> #include <stdint.h> #include <vendorcode/google/chromeos/chromeos.h>
+enum adl_boardid { + /* ADL-P LPDDR4 RVPs */ + ADL_P_LP4_1 = 0x10, + ADL_P_LP4_2 = 0x11, + /* ADL-P DDR4 RVPs */ + ADL_P_DDR4_1 = 0x14, + ADL_P_DDR4_2 = 0x3F, +}; + /* The next set of functions return the gpio table and fill in the number of * entries for each table. */ const struct cros_gpio *variant_cros_gpios(size_t *num);
void variant_configure_early_gpio_pads(void);
+size_t variant_memory_sku(void); +const struct mb_cfg *variant_memory_params(void); #endif /*__BASEBOARD_VARIANTS_H__ */
-
Angel Pons (Code Review) -
build bot (Jenkins) (Code Review)
-
Subrata Banik (Code Review)
-
Tim Wawrzynczak (Code Review)