Subrata Banik submitted this change.
mb/intel/adlrvp: Add ADL-P romstage mainboard code
List of changes:
1. Add DDR4 and LPDDR4 memory related code
- SPD for LPDDR4
- DQ byte map
- DQS CPU-DRAM map
- Rcomp resistor
- Rcomp target
2. Fill FSP-M related UPD parameters
3. Add devicetree.cb config parameters related to FSP-M UPD
TEST=Able to build and boot ADL-P RVP till ramstage early
Change-Id: Iffc5c17ed0725f61c8c274a80a1d27161ca6cebf
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46091
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
---
M src/mainboard/intel/adlrvp/Kconfig
M src/mainboard/intel/adlrvp/Makefile.inc
A src/mainboard/intel/adlrvp/board_id.c
A src/mainboard/intel/adlrvp/board_id.h
A src/mainboard/intel/adlrvp/romstage_fsp_params.c
A src/mainboard/intel/adlrvp/spd/Makefile.inc
A src/mainboard/intel/adlrvp/spd/adlrvp_lp4.spd.hex
A src/mainboard/intel/adlrvp/spd/empty.spd.hex
M src/mainboard/intel/adlrvp/variants/adlrvp_p/Makefile.inc
M src/mainboard/intel/adlrvp/variants/adlrvp_p/devicetree.cb
A src/mainboard/intel/adlrvp/variants/adlrvp_p/memory.c
M src/mainboard/intel/adlrvp/variants/baseboard/include/baseboard/variants.h
12 files changed, 296 insertions(+), 8 deletions(-)
diff --git a/src/mainboard/intel/adlrvp/Kconfig b/src/mainboard/intel/adlrvp/Kconfig
index 27c3957..97b4bf7 100644
--- a/src/mainboard/intel/adlrvp/Kconfig
+++ b/src/mainboard/intel/adlrvp/Kconfig
@@ -12,6 +12,7 @@
select DRIVERS_USB_ACPI
select DRIVERS_SPI_ACPI
select SOC_INTEL_ALDERLAKE
+ select HAVE_SPD_IN_CBFS
config CHROMEOS
bool
diff --git a/src/mainboard/intel/adlrvp/Makefile.inc b/src/mainboard/intel/adlrvp/Makefile.inc
index eb4a981..e8a0eca 100644
--- a/src/mainboard/intel/adlrvp/Makefile.inc
+++ b/src/mainboard/intel/adlrvp/Makefile.inc
@@ -1,11 +1,15 @@
## SPDX-License-Identifier: GPL-2.0-only
+subdirs-y += spd
+
bootblock-y += bootblock.c
bootblock-$(CONFIG_CHROMEOS) += chromeos.c
verstage-$(CONFIG_CHROMEOS) += chromeos.c
romstage-$(CONFIG_CHROMEOS) += chromeos.c
+romstage-y += romstage_fsp_params.c
+romstage-y += board_id.c
ramstage-$(CONFIG_CHROMEOS) += chromeos.c
diff --git a/src/mainboard/intel/adlrvp/board_id.c b/src/mainboard/intel/adlrvp/board_id.c
new file mode 100644
index 0000000..332ba1b
--- /dev/null
+++ b/src/mainboard/intel/adlrvp/board_id.c
@@ -0,0 +1,36 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <boardid.h>
+#include <ec/acpi/ec.h>
+#include <ec/google/chromeec/ec.h>
+#include <stdint.h>
+#include <types.h>
+#include "board_id.h"
+
+static uint32_t get_board_id_via_ext_ec(void)
+{
+ uint32_t id = BOARD_ID_INIT;
+
+ if (google_chromeec_get_board_version(&id))
+ id = BOARD_ID_UNKNOWN;
+
+ return id;
+}
+
+/* Get Board ID via EC I/O port write/read */
+int get_board_id(void)
+{
+ MAYBE_STATIC_NONZERO int id = -1;
+
+ if (id < 0) {
+ if (CONFIG(EC_GOOGLE_CHROMEEC)) {
+ id = get_board_id_via_ext_ec();
+ } else {
+ if (send_ec_command(EC_FAB_ID_CMD) == 0) {
+ id = recv_ec_data() << 8;
+ id |= recv_ec_data();
+ }
+ }
+ }
+ return (id & BOARD_ID_MASK);
+}
diff --git a/src/mainboard/intel/adlrvp/board_id.h b/src/mainboard/intel/adlrvp/board_id.h
new file mode 100644
index 0000000..2988127
--- /dev/null
+++ b/src/mainboard/intel/adlrvp/board_id.h
@@ -0,0 +1,17 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef _MAINBOARD_COMMON_BOARD_ID_H_
+#define _MAINBOARD_COMMON_BOARD_ID_H_
+
+/* Board/FAB ID Command */
+#define EC_FAB_ID_CMD 0x0d
+/* Bit 5:0 for Board ID */
+#define BOARD_ID_MASK 0x3f
+
+/*
+ * Returns board information (board id[15:8] and
+ * Fab info[7:0]) on success and < 0 on error
+ */
+int get_board_id(void);
+
+#endif /* _MAINBOARD_COMMON_BOARD_ID_H_ */
diff --git a/src/mainboard/intel/adlrvp/romstage_fsp_params.c b/src/mainboard/intel/adlrvp/romstage_fsp_params.c
new file mode 100644
index 0000000..9d7cc91
--- /dev/null
+++ b/src/mainboard/intel/adlrvp/romstage_fsp_params.c
@@ -0,0 +1,66 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+#include <assert.h>
+#include <console/console.h>
+#include <fsp/api.h>
+#include <soc/romstage.h>
+#include <spd_bin.h>
+#include <string.h>
+#include <soc/meminit.h>
+#include <baseboard/variants.h>
+#include <cbfs.h>
+#include "board_id.h"
+
+#define SPD_ID_MASK 0x7
+
+static size_t get_spd_index(void)
+{
+ uint8_t board_id = get_board_id();
+ size_t spd_index;
+
+ printk(BIOS_INFO, "board id is 0x%x\n", board_id);
+
+ spd_index = board_id & SPD_ID_MASK;
+
+ printk(BIOS_INFO, "SPD index is 0x%x\n", (unsigned int)spd_index);
+ return spd_index;
+}
+
+void mainboard_memory_init_params(FSPM_UPD *mupd)
+{
+ const struct mb_cfg *mem_config = variant_memory_params();
+ int board_id = get_board_id();
+ const bool half_populated = false;
+
+ const struct spd_info lpddr4_spd_info = {
+ .read_type = READ_SPD_CBFS,
+ .spd_spec.spd_index = get_spd_index(),
+ };
+
+ const struct spd_info ddr4_spd_info = {
+ .read_type = READ_SMBUS,
+ .spd_spec = {
+ .spd_smbus_address = {
+ [0] = 0xa0,
+ [1] = 0xa2,
+ [8] = 0xa4,
+ [9] = 0xa6,
+ },
+ },
+ };
+
+ switch (board_id) {
+ case ADL_P_DDR4_1:
+ case ADL_P_DDR4_2:
+ mupd->FspmConfig.DqPinsInterleaved = 1;
+ memcfg_init(&mupd->FspmConfig, mem_config, &ddr4_spd_info, half_populated);
+ break;
+ case ADL_P_LP4_1:
+ case ADL_P_LP4_2:
+ mupd->FspmConfig.DqPinsInterleaved = 0;
+ memcfg_init(&mupd->FspmConfig, mem_config, &lpddr4_spd_info, half_populated);
+ break;
+ default:
+ die("Unknown board id = 0x%x\n", board_id);
+ break;
+ }
+}
diff --git a/src/mainboard/intel/adlrvp/spd/Makefile.inc b/src/mainboard/intel/adlrvp/spd/Makefile.inc
new file mode 100644
index 0000000..1218a76
--- /dev/null
+++ b/src/mainboard/intel/adlrvp/spd/Makefile.inc
@@ -0,0 +1,4 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
+SPD_SOURCES = adlrvp_lp4 #0b000
+SPD_SOURCES += empty # 0b001
diff --git a/src/mainboard/intel/adlrvp/spd/adlrvp_lp4.spd.hex b/src/mainboard/intel/adlrvp/spd/adlrvp_lp4.spd.hex
new file mode 100644
index 0000000..17f270d
--- /dev/null
+++ b/src/mainboard/intel/adlrvp/spd/adlrvp_lp4.spd.hex
@@ -0,0 +1,32 @@
+23 12 11 0E 15 21 B5 08 00 40 00 00 0A 01 00 00
+48 00 04 00 D2 54 01 00 87 40 90 A8 90 C0 08 60
+04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 E4 00 60 A1 AC
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 55 00 00 00 20 20 20 20 20 20 20
+20 20 20 20 20 20 20 20 20 20 20 20 20 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
diff --git a/src/mainboard/intel/adlrvp/spd/empty.spd.hex b/src/mainboard/intel/adlrvp/spd/empty.spd.hex
new file mode 100644
index 0000000..67b46cd
--- /dev/null
+++ b/src/mainboard/intel/adlrvp/spd/empty.spd.hex
@@ -0,0 +1,32 @@
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 80 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 80 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
diff --git a/src/mainboard/intel/adlrvp/variants/adlrvp_p/Makefile.inc b/src/mainboard/intel/adlrvp/variants/adlrvp_p/Makefile.inc
index 9b21a1b..8c05721 100644
--- a/src/mainboard/intel/adlrvp/variants/adlrvp_p/Makefile.inc
+++ b/src/mainboard/intel/adlrvp/variants/adlrvp_p/Makefile.inc
@@ -1,3 +1,5 @@
## SPDX-License-Identifier: GPL-2.0-only
bootblock-y += early_gpio.c
+
+romstage-y += memory.c
diff --git a/src/mainboard/intel/adlrvp/variants/adlrvp_p/devicetree.cb b/src/mainboard/intel/adlrvp/variants/adlrvp_p/devicetree.cb
index e16de65..a6b0039 100644
--- a/src/mainboard/intel/adlrvp/variants/adlrvp_p/devicetree.cb
+++ b/src/mainboard/intel/adlrvp/variants/adlrvp_p/devicetree.cb
@@ -11,6 +11,36 @@
register "gen3_dec" = "0x00fc0901"
register "gen4_dec" = "0x000c0081"
+ register "PrmrrSize" = "0"
+
+ # Enable PCH PCIE RP 5 using CLK 2
+ register "PcieRpEnable[4]" = "1"
+ register "PcieClkSrcClkReq[4]" = "4"
+ register "PcieClkSrcUsage[2]" = "0x4"
+ register "PcieRpClkReqDetect[4]" = "1"
+
+ # Enable PCH PCIE RP 6 using CLK 5
+ register "PcieRpEnable[5]" = "1"
+ register "PcieClkSrcClkReq[5]" = "5"
+ register "PcieClkSrcUsage[5]" = "0x5"
+ register "PcieRpClkReqDetect[5]" = "1"
+
+ # Enable PCH PCIE RP 9 using CLK 1
+ register "PcieRpEnable[8]" = "1"
+ register "PcieClkSrcClkReq[8]" = "8"
+ register "PcieClkSrcUsage[1]" = "0x8"
+ register "PcieRpClkReqDetect[8]" = "1"
+
+ # Enable CPU PCIE RP 1 using PEG CLK 0
+ register "PcieClkSrcUsage[0]" = "0x40"
+
+ # Enable PCU PCIE PEG Slot 1 and 2
+ register "PcieClkSrcUsage[3]" = "0x41"
+ register "PcieClkSrcUsage[4]" = "0x42"
+
+ # Mark LAN CLK pins as unused as GbE 0:0x1f.6 is disabled below
+ register "PcieClkSrcUsage[6]" = "0xff"
+
device domain 0 on
device pci 00.0 on end # Host Bridge
device pci 02.0 on end # Graphics
@@ -79,17 +109,17 @@
device pci 19.1 on end # I2C5
device pci 19.2 on end # UART2
device pci 1c.0 on end # RP1
- device pci 1c.1 on end # RP2
- device pci 1c.2 on end # RP3
- device pci 1c.3 on end # RP4
+ device pci 1c.1 off end # RP2
+ device pci 1c.2 off end # RP3
+ device pci 1c.3 off end # RP4
device pci 1c.4 on end # RP5
device pci 1c.5 on end # RP6
- device pci 1c.6 on end # RP7
- device pci 1c.7 on end # RP8
+ device pci 1c.6 off end # RP7
+ device pci 1c.7 off end # RP8
device pci 1d.0 on end # RP9
- device pci 1d.1 on end # RP10
- device pci 1d.2 on end # RP11
- device pci 1d.3 on end # RP12
+ device pci 1d.1 off end # RP10
+ device pci 1d.2 off end # RP11
+ device pci 1d.3 off end # RP12
device pci 1e.0 off end # UART0
device pci 1e.1 off end # UART1
device pci 1e.2 off end # GSPI0
diff --git a/src/mainboard/intel/adlrvp/variants/adlrvp_p/memory.c b/src/mainboard/intel/adlrvp/variants/adlrvp_p/memory.c
new file mode 100644
index 0000000..f8b3660
--- /dev/null
+++ b/src/mainboard/intel/adlrvp/variants/adlrvp_p/memory.c
@@ -0,0 +1,52 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <arch/cpu.h>
+#include "../../board_id.h"
+#include <baseboard/variants.h>
+#include <soc/romstage.h>
+
+static const struct mb_cfg mem_config = {
+ /* DQ byte map */
+ .dq_map = {
+ { 0, 2, 3, 1, 6, 7, 5, 4, /* Byte 0 */
+ 10, 8, 11, 9, 14, 12, 13, 15 }, /* Byte 1 */
+ { 12, 8, 14, 10, 11, 13, 15, 9, /* Byte 2 */
+ 5, 0, 7, 3, 6, 2, 1, 4 }, /* Byte 3 */
+ { 3, 0, 2, 1, 6, 5, 4, 7, /* Byte 4 */
+ 12, 13, 14, 15, 10, 9, 8, 11 }, /* Byte 5 */
+ { 2, 6, 7, 1, 3, 4, 0, 5, /* Byte 6 */
+ 9, 13, 8, 15, 14, 11, 12, 10 }, /* Byte 7 */
+ { 3, 0, 1, 2, 7, 4, 6, 5, /* Byte 0 */
+ 10, 8, 11, 9, 14, 13, 12, 15 }, /* Byte 1 */
+ { 10, 12, 14, 8, 9, 13, 15, 11, /* Byte 2 */
+ 3, 7, 6, 2, 0, 4, 5, 1 }, /* Byte 3 */
+ { 12, 15, 14, 13, 9, 10, 11, 8, /* Byte 4 */
+ 7, 4, 6, 5, 0, 1, 3, 2 }, /* Byte 5 */
+ { 0, 2, 4, 3, 1, 6, 7, 5, /* Byte 6 */
+ 13, 9, 10, 11, 8, 12, 14, 15 }, /* Byte 7 */
+ },
+
+ /* DQS CPU<>DRAM map */
+ .dqs_map = {
+ /* Ch 0 1 2 3 */
+ { 0, 1 }, { 1, 0 }, { 0, 1 }, { 0, 1 },
+ { 0, 1 }, { 1, 0 }, { 1, 0 }, { 0, 1 }
+ },
+
+ /* Baseboard uses only 100ohm Rcomp resistors */
+ .rcomp_resistor = {100, 100, 100},
+
+ /*
+ * Baseboard Rcomp target values.
+ */
+ .rcomp_targets = {40, 30, 33, 33, 30},
+
+ .ect = true, /* Early Command Training */
+
+ .UserBd = BOARD_TYPE_MOBILE,
+};
+
+const struct mb_cfg *variant_memory_params(void)
+{
+ return &mem_config;
+}
diff --git a/src/mainboard/intel/adlrvp/variants/baseboard/include/baseboard/variants.h b/src/mainboard/intel/adlrvp/variants/baseboard/include/baseboard/variants.h
index 7a8f444..5288b6f 100644
--- a/src/mainboard/intel/adlrvp/variants/baseboard/include/baseboard/variants.h
+++ b/src/mainboard/intel/adlrvp/variants/baseboard/include/baseboard/variants.h
@@ -4,13 +4,25 @@
#define __BASEBOARD_VARIANTS_H__
#include <soc/gpio.h>
+#include <soc/meminit.h>
#include <stdint.h>
#include <vendorcode/google/chromeos/chromeos.h>
+enum adl_boardid {
+ /* ADL-P LPDDR4 RVPs */
+ ADL_P_LP4_1 = 0x10,
+ ADL_P_LP4_2 = 0x11,
+ /* ADL-P DDR4 RVPs */
+ ADL_P_DDR4_1 = 0x14,
+ ADL_P_DDR4_2 = 0x3F,
+};
+
/* The next set of functions return the gpio table and fill in the number of
* entries for each table. */
const struct cros_gpio *variant_cros_gpios(size_t *num);
void variant_configure_early_gpio_pads(void);
+size_t variant_memory_sku(void);
+const struct mb_cfg *variant_memory_params(void);
#endif /*__BASEBOARD_VARIANTS_H__ */
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