Subrata Banik uploaded patch set #2 to this change.

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mb/intel/adlrvp: Add ADL-P romstage mainboard code

List of changes:
1. Add DDR4 and LPDDR4 memory related code
- SPD for LPDDR4
- DQ byte map
- DQS CPU-DRAM map
- Rcomp resistor
- Rcomp target
2. Fill FSP-M related memory UPD parameters
3. Add devicetree.cb config parameters related to FSP-M UPD

TEST=Able to build and boot ADL-P RVP till ramstage early

Change-Id: Iffc5c17ed0725f61c8c274a80a1d27161ca6cebf
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
---
M src/mainboard/intel/adlrvp/Makefile.inc
A src/mainboard/intel/adlrvp/board_id.c
A src/mainboard/intel/adlrvp/board_id.h
A src/mainboard/intel/adlrvp/romstage_fsp_params.c
A src/mainboard/intel/adlrvp/spd/Makefile.inc
A src/mainboard/intel/adlrvp/spd/adlrvp_lp4.spd.hex
A src/mainboard/intel/adlrvp/spd/empty.spd.hex
A src/mainboard/intel/adlrvp/spd/spd.h
M src/mainboard/intel/adlrvp/variants/adlrvp_p/Makefile.inc
M src/mainboard/intel/adlrvp/variants/adlrvp_p/devicetree.cb
A src/mainboard/intel/adlrvp/variants/adlrvp_p/memory.c
M src/mainboard/intel/adlrvp/variants/baseboard/include/baseboard/variants.h
12 files changed, 342 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/91/46091/2

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