Patch set 5:Code-Review +1

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2 comments:

• File src/mainboard/intel/adlrvp/variants/adlrvp_p/devicetree.cb:

  • Patch Set #5, Line 29: register "PcieRpEnable[11]" = "1"

    I find it weird that all PCIe RPs are enabled. I would expect that not all PCH PCIe ports are x1.

  • Patch Set #5, Line 50: 0x70

    This setting seems to be for use with Intel GbE, but its PCI device is disabled?

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