Change in coreboot[master]: mb/hp: Add Elitebook 8560w as an HP Sandy/Ivy Bridge laptop variant
Hello Iru Cai,
I'd like you to do a code review. Please visit
https://review.coreboot.org/c/coreboot/+/39398
to review the following change.
Change subject: mb/hp: Add Elitebook 8560w as an HP Sandy/Ivy Bridge laptop variant ......................................................................
mb/hp: Add Elitebook 8560w as an HP Sandy/Ivy Bridge laptop variant
Change-Id: I15181792b1efa45a2a94d78e43c6257da1acf950 Signed-off-by: Iru Cai mytbk920423@gmail.com --- A Documentation/mainboard/hp/8560w.md A Documentation/mainboard/hp/8560w_flash.webp M Documentation/mainboard/index.md M src/mainboard/hp/snb_ivb_laptops/Kconfig M src/mainboard/hp/snb_ivb_laptops/Kconfig.name A src/mainboard/hp/snb_ivb_laptops/variants/8560w/board_info.txt A src/mainboard/hp/snb_ivb_laptops/variants/8560w/early_init.c A src/mainboard/hp/snb_ivb_laptops/variants/8560w/gpio.c A src/mainboard/hp/snb_ivb_laptops/variants/8560w/hda_verb.c A src/mainboard/hp/snb_ivb_laptops/variants/8560w/overridetree.cb 10 files changed, 477 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/39398/1
diff --git a/Documentation/mainboard/hp/8560w.md b/Documentation/mainboard/hp/8560w.md new file mode 100644 index 0000000..6a7c197 --- /dev/null +++ b/Documentation/mainboard/hp/8560w.md @@ -0,0 +1,82 @@ +# HP EliteBook 8560w + +This page describes how to run coreboot on the [HP EliteBook 8560w]. + +## Required proprietary blobs + +- Intel Firmware Descriptor, ME and GbE firmware +- EC: please read [EliteBook Series](elitebook_series) + +## Flashing instructions + +HP EliteBook 8560w has an 8MB SOIC-8 flash chip on the bottom of the +mainboard. You just need to remove the service cover, and use an SOIC-8 +clip to read and flash the chip. + + + +```eval_rst ++---------------------+------------+ +| Type | Value | ++=====================+============+ +| Socketed flash | no | ++---------------------+------------+ +| Model | MX25L6406E | ++---------------------+------------+ +| Size | 8 MiB | ++---------------------+------------+ +| Package | SOIC-8 | ++---------------------+------------+ +| Write protection | no | ++---------------------+------------+ +| Dual BIOS feature | no | ++---------------------+------------+ +| In circuit flashing | yes | ++---------------------+------------+ +| Internal flashing | yes | ++---------------------+------------+ +``` + +## Untested + +- mainboards with 4 memory slots + +## Working + +- i7-2720QM, 8G+8G +- Arch Linux boot from SeaBIOS payload +- EHCI debug: the port is beside the eSATA port +- SATA +- eSATA +- USB2 and USB3 +- keyboard +- Gigabit Ethernet +- WLAN +- WWAN +- VGA and DisplayPort +- audio +- EC ACPI +- Using `me_cleaner` +- dock: PS/2 keyboard, USB, DisplayPort +- TPM +- S3 suspend/resume + +## Technology + +```eval_rst ++------------------+--------------------------------------------------+ +| Northbridge | :doc:`../../northbridge/intel/sandybridge/index` | ++------------------+--------------------------------------------------+ +| Southbridge | bd82x6x | ++------------------+--------------------------------------------------+ +| CPU | model_206ax | ++------------------+--------------------------------------------------+ +| Super I/O | SMSC LPC47n217 | ++------------------+--------------------------------------------------+ +| EC | SMSC KBC1126 | ++------------------+--------------------------------------------------+ +| Coprocessor | Intel Management Engine | ++------------------+--------------------------------------------------+ +``` + +[HP EliteBook 8560w]: https://support.hp.com/us-en/product/hp-elitebook-8560w-mobile-workstation/5... diff --git a/Documentation/mainboard/hp/8560w_flash.webp b/Documentation/mainboard/hp/8560w_flash.webp new file mode 100644 index 0000000..b8295bc --- /dev/null +++ b/Documentation/mainboard/hp/8560w_flash.webp Binary files differ diff --git a/Documentation/mainboard/index.md b/Documentation/mainboard/index.md index e46e0f3..a20a0bf 100644 --- a/Documentation/mainboard/index.md +++ b/Documentation/mainboard/index.md @@ -55,6 +55,7 @@ ### EliteBook series
- [EliteBook common](hp/elitebook_series.md) +- [EliteBook 8560w](hp/8560w.md) - [EliteBook 8760w](hp/8760w.md)
## Intel diff --git a/src/mainboard/hp/snb_ivb_laptops/Kconfig b/src/mainboard/hp/snb_ivb_laptops/Kconfig index d0105ff..0ec0d27 100644 --- a/src/mainboard/hp/snb_ivb_laptops/Kconfig +++ b/src/mainboard/hp/snb_ivb_laptops/Kconfig @@ -37,6 +37,7 @@ default "2760p" if BOARD_HP_2760P default "8460p" if BOARD_HP_8460P default "8470p" if BOARD_HP_8470P + default "8560w" if BOARD_HP_8560W default "8770w" if BOARD_HP_8770W default "folio_9470m" if BOARD_HP_FOLIO_9470M default "revolve_810_g1" if BOARD_HP_REVOLVE_810_G1 @@ -47,6 +48,7 @@ default "EliteBook 2760p" if BOARD_HP_2760P default "EliteBook 8460p" if BOARD_HP_8460P default "EliteBook 8470p" if BOARD_HP_8470P + default "EliteBook 8560w" if BOARD_HP_8560W default "EliteBook 8770w" if BOARD_HP_8770W default "EliteBook Folio 9470m" if BOARD_HP_FOLIO_9470M default "EliteBook Revolve 810 G1" if BOARD_HP_REVOLVE_810_G1 @@ -75,6 +77,7 @@ default 1 if BOARD_HP_2760P default 1 if BOARD_HP_8460P default 2 if BOARD_HP_8470P + default 1 if BOARD_HP_8560W default 2 if BOARD_HP_8770W default 0 if BOARD_HP_FOLIO_9470M default 2 if BOARD_HP_REVOLVE_810_G1 # FIXME: check this diff --git a/src/mainboard/hp/snb_ivb_laptops/Kconfig.name b/src/mainboard/hp/snb_ivb_laptops/Kconfig.name index c4a8662..360373e 100644 --- a/src/mainboard/hp/snb_ivb_laptops/Kconfig.name +++ b/src/mainboard/hp/snb_ivb_laptops/Kconfig.name @@ -61,6 +61,17 @@ select SOUTHBRIDGE_INTEL_C216 select SUPERIO_SMSC_LPC47N217
+config BOARD_HP_8560W + bool "EliteBook 8560w" + + select BOARD_HP_SNB_IVB_LAPTOPS + select BOARD_ROMSIZE_KB_8192 + select MAINBOARD_USES_IFD_GBE_REGION + select SOUTHBRIDGE_INTEL_BD82X6X + select SUPERIO_SMSC_LPC47N217 + select MAINBOARD_HAS_LPC_TPM + select MAINBOARD_HAS_TPM1 + config BOARD_HP_8770W bool "EliteBook 8770w"
diff --git a/src/mainboard/hp/snb_ivb_laptops/variants/8560w/board_info.txt b/src/mainboard/hp/snb_ivb_laptops/variants/8560w/board_info.txt new file mode 100644 index 0000000..af1e296 --- /dev/null +++ b/src/mainboard/hp/snb_ivb_laptops/variants/8560w/board_info.txt @@ -0,0 +1,7 @@ +Category: laptop +Board URL: https://support.hp.com/us-en/product/hp-elitebook-8560w-mobile-workstation/5... +ROM package: SOIC-8 +ROM protocol: SPI +ROM socketed: n +Flashrom support: n +Release year: 2011 diff --git a/src/mainboard/hp/snb_ivb_laptops/variants/8560w/early_init.c b/src/mainboard/hp/snb_ivb_laptops/variants/8560w/early_init.c new file mode 100644 index 0000000..57eafe2 --- /dev/null +++ b/src/mainboard/hp/snb_ivb_laptops/variants/8560w/early_init.c @@ -0,0 +1,52 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2020 The coreboot project Authors. + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include <bootblock_common.h> +#include <northbridge/intel/sandybridge/sandybridge.h> +#include <northbridge/intel/sandybridge/raminit_native.h> +#include <southbridge/intel/bd82x6x/pch.h> +#include <superio/smsc/lpc47n217/lpc47n217.h> +#include <ec/hp/kbc1126/ec.h> + +#define SERIAL_DEV PNP_DEV(0x4e, LPC47N217_SP1) + +const struct southbridge_usb_port mainboard_usb_ports[] = { + { 1, 1, 0 }, /* USB0 */ + { 1, 1, 0 }, /* USB1 */ + { 1, 1, 1 }, /* eSATA */ + { 1, 1, 1 }, /* camera */ + { 0, 0, 2 }, + { 1, 0, 2 }, /* bluetooth */ + { 0, 0, 3 }, + { 1, 0, 3 }, + { 0, 1, 4 }, + { 1, 1, 4 }, /* WWAN */ + { 1, 0, 5 }, + { 1, 0, 5 }, /* dock */ + { 1, 0, 6 }, + { 1, 0, 6 }, +}; + +void bootblock_mainboard_early_init(void) +{ + lpc47n217_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + kbc1126_enter_conf(); + kbc1126_mailbox_init(); + kbc1126_kbc_init(); + kbc1126_ec_init(); + kbc1126_pm1_init(); + kbc1126_exit_conf(); +} + +void mainboard_get_spd(spd_raw_data *spd, bool id_only) +{ + read_spd(&spd[0], 0x50, id_only); + read_spd(&spd[1], 0x51, id_only); + read_spd(&spd[2], 0x52, id_only); + read_spd(&spd[3], 0x53, id_only); +} diff --git a/src/mainboard/hp/snb_ivb_laptops/variants/8560w/gpio.c b/src/mainboard/hp/snb_ivb_laptops/variants/8560w/gpio.c new file mode 100644 index 0000000..29358aa --- /dev/null +++ b/src/mainboard/hp/snb_ivb_laptops/variants/8560w/gpio.c @@ -0,0 +1,230 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2020 The coreboot project Authors. + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include <southbridge/intel/common/gpio.h> + +static const struct pch_gpio_set1 pch_gpio_set1_mode = { + .gpio0 = GPIO_MODE_GPIO, + .gpio1 = GPIO_MODE_GPIO, + .gpio2 = GPIO_MODE_GPIO, + .gpio3 = GPIO_MODE_GPIO, + .gpio4 = GPIO_MODE_GPIO, + .gpio5 = GPIO_MODE_NATIVE, + .gpio6 = GPIO_MODE_GPIO, + .gpio7 = GPIO_MODE_GPIO, + .gpio8 = GPIO_MODE_GPIO, + .gpio9 = GPIO_MODE_NATIVE, + .gpio10 = GPIO_MODE_GPIO, + .gpio11 = GPIO_MODE_GPIO, + .gpio12 = GPIO_MODE_NATIVE, + .gpio13 = GPIO_MODE_GPIO, + .gpio14 = GPIO_MODE_GPIO, + .gpio15 = GPIO_MODE_GPIO, + .gpio16 = GPIO_MODE_GPIO, + .gpio17 = GPIO_MODE_GPIO, + .gpio18 = GPIO_MODE_NATIVE, + .gpio19 = GPIO_MODE_GPIO, + .gpio20 = GPIO_MODE_NATIVE, + .gpio21 = GPIO_MODE_GPIO, + .gpio22 = GPIO_MODE_GPIO, + .gpio23 = GPIO_MODE_GPIO, + .gpio24 = GPIO_MODE_GPIO, + .gpio25 = GPIO_MODE_NATIVE, + .gpio26 = GPIO_MODE_NATIVE, + .gpio27 = GPIO_MODE_GPIO, + .gpio28 = GPIO_MODE_GPIO, + .gpio29 = GPIO_MODE_GPIO, + .gpio30 = GPIO_MODE_NATIVE, + .gpio31 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_direction = { + .gpio0 = GPIO_DIR_OUTPUT, + .gpio1 = GPIO_DIR_INPUT, + .gpio2 = GPIO_DIR_INPUT, + .gpio3 = GPIO_DIR_INPUT, + .gpio4 = GPIO_DIR_INPUT, + .gpio6 = GPIO_DIR_INPUT, + .gpio7 = GPIO_DIR_INPUT, + .gpio8 = GPIO_DIR_INPUT, + .gpio10 = GPIO_DIR_INPUT, + .gpio11 = GPIO_DIR_OUTPUT, + .gpio13 = GPIO_DIR_INPUT, + .gpio14 = GPIO_DIR_INPUT, + .gpio15 = GPIO_DIR_INPUT, + .gpio16 = GPIO_DIR_INPUT, + .gpio17 = GPIO_DIR_OUTPUT, + .gpio19 = GPIO_DIR_INPUT, + .gpio21 = GPIO_DIR_INPUT, + .gpio22 = GPIO_DIR_OUTPUT, + .gpio23 = GPIO_DIR_INPUT, + .gpio24 = GPIO_DIR_OUTPUT, + .gpio27 = GPIO_DIR_OUTPUT, + .gpio28 = GPIO_DIR_OUTPUT, + .gpio29 = GPIO_DIR_OUTPUT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_level = { + .gpio0 = GPIO_LEVEL_LOW, + .gpio11 = GPIO_LEVEL_LOW, + .gpio17 = GPIO_LEVEL_HIGH, + .gpio22 = GPIO_LEVEL_HIGH, + .gpio24 = GPIO_LEVEL_HIGH, + .gpio27 = GPIO_LEVEL_LOW, + .gpio28 = GPIO_LEVEL_LOW, + .gpio29 = GPIO_LEVEL_HIGH, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_reset = { + .gpio24 = GPIO_RESET_RSMRST, + .gpio30 = GPIO_RESET_RSMRST, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_invert = { + .gpio1 = GPIO_INVERT, + .gpio3 = GPIO_INVERT, + .gpio6 = GPIO_INVERT, + .gpio7 = GPIO_INVERT, + .gpio10 = GPIO_INVERT, + .gpio13 = GPIO_INVERT, + .gpio14 = GPIO_INVERT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_blink = { +}; + +static const struct pch_gpio_set2 pch_gpio_set2_mode = { + .gpio32 = GPIO_MODE_NATIVE, + .gpio33 = GPIO_MODE_GPIO, + .gpio34 = GPIO_MODE_GPIO, + .gpio35 = GPIO_MODE_GPIO, + .gpio36 = GPIO_MODE_NATIVE, + .gpio37 = GPIO_MODE_GPIO, + .gpio38 = GPIO_MODE_GPIO, + .gpio39 = GPIO_MODE_GPIO, + .gpio40 = GPIO_MODE_NATIVE, + .gpio41 = GPIO_MODE_NATIVE, + .gpio42 = GPIO_MODE_NATIVE, + .gpio43 = GPIO_MODE_NATIVE, + .gpio44 = GPIO_MODE_GPIO, + .gpio45 = GPIO_MODE_NATIVE, + .gpio46 = GPIO_MODE_GPIO, + .gpio47 = GPIO_MODE_NATIVE, + .gpio48 = GPIO_MODE_GPIO, + .gpio49 = GPIO_MODE_GPIO, + .gpio50 = GPIO_MODE_GPIO, + .gpio51 = GPIO_MODE_GPIO, + .gpio52 = GPIO_MODE_GPIO, + .gpio53 = GPIO_MODE_GPIO, + .gpio54 = GPIO_MODE_GPIO, + .gpio55 = GPIO_MODE_GPIO, + .gpio56 = GPIO_MODE_NATIVE, + .gpio57 = GPIO_MODE_GPIO, + .gpio58 = GPIO_MODE_NATIVE, + .gpio59 = GPIO_MODE_NATIVE, + .gpio60 = GPIO_MODE_GPIO, + .gpio61 = GPIO_MODE_GPIO, + .gpio62 = GPIO_MODE_NATIVE, + .gpio63 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_direction = { + .gpio33 = GPIO_DIR_OUTPUT, + .gpio34 = GPIO_DIR_INPUT, + .gpio35 = GPIO_DIR_OUTPUT, + .gpio37 = GPIO_DIR_OUTPUT, + .gpio38 = GPIO_DIR_INPUT, + .gpio39 = GPIO_DIR_INPUT, + .gpio44 = GPIO_DIR_INPUT, + .gpio46 = GPIO_DIR_INPUT, + .gpio48 = GPIO_DIR_INPUT, + .gpio49 = GPIO_DIR_OUTPUT, + .gpio50 = GPIO_DIR_INPUT, + .gpio51 = GPIO_DIR_INPUT, + .gpio52 = GPIO_DIR_INPUT, + .gpio53 = GPIO_DIR_OUTPUT, + .gpio54 = GPIO_DIR_INPUT, + .gpio55 = GPIO_DIR_INPUT, + .gpio57 = GPIO_DIR_OUTPUT, + .gpio60 = GPIO_DIR_OUTPUT, + .gpio61 = GPIO_DIR_OUTPUT, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_level = { + .gpio33 = GPIO_LEVEL_LOW, + .gpio35 = GPIO_LEVEL_LOW, + .gpio37 = GPIO_LEVEL_LOW, + .gpio49 = GPIO_LEVEL_LOW, + .gpio53 = GPIO_LEVEL_HIGH, + .gpio57 = GPIO_LEVEL_LOW, + .gpio60 = GPIO_LEVEL_HIGH, + .gpio61 = GPIO_LEVEL_HIGH, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_reset = { +}; + +static const struct pch_gpio_set3 pch_gpio_set3_mode = { + .gpio64 = GPIO_MODE_NATIVE, + .gpio65 = GPIO_MODE_NATIVE, + .gpio66 = GPIO_MODE_NATIVE, + .gpio67 = GPIO_MODE_NATIVE, + .gpio68 = GPIO_MODE_GPIO, + .gpio69 = GPIO_MODE_GPIO, + .gpio70 = GPIO_MODE_GPIO, + .gpio71 = GPIO_MODE_GPIO, + .gpio72 = GPIO_MODE_GPIO, + .gpio73 = GPIO_MODE_GPIO, + .gpio74 = GPIO_MODE_GPIO, + .gpio75 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_direction = { + .gpio68 = GPIO_DIR_OUTPUT, + .gpio69 = GPIO_DIR_INPUT, + .gpio70 = GPIO_DIR_OUTPUT, + .gpio71 = GPIO_DIR_OUTPUT, + .gpio72 = GPIO_DIR_OUTPUT, + .gpio73 = GPIO_DIR_OUTPUT, + .gpio74 = GPIO_DIR_OUTPUT, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_level = { + .gpio68 = GPIO_LEVEL_HIGH, + .gpio70 = GPIO_LEVEL_HIGH, + .gpio71 = GPIO_LEVEL_HIGH, + .gpio72 = GPIO_LEVEL_LOW, + .gpio73 = GPIO_LEVEL_HIGH, + .gpio74 = GPIO_LEVEL_HIGH, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_reset = { +}; + +const struct pch_gpio_map mainboard_gpio_map = { + .set1 = { + .mode = &pch_gpio_set1_mode, + .direction = &pch_gpio_set1_direction, + .level = &pch_gpio_set1_level, + .blink = &pch_gpio_set1_blink, + .invert = &pch_gpio_set1_invert, + .reset = &pch_gpio_set1_reset, + }, + .set2 = { + .mode = &pch_gpio_set2_mode, + .direction = &pch_gpio_set2_direction, + .level = &pch_gpio_set2_level, + .reset = &pch_gpio_set2_reset, + }, + .set3 = { + .mode = &pch_gpio_set3_mode, + .direction = &pch_gpio_set3_direction, + .level = &pch_gpio_set3_level, + .reset = &pch_gpio_set3_reset, + }, +}; diff --git a/src/mainboard/hp/snb_ivb_laptops/variants/8560w/hda_verb.c b/src/mainboard/hp/snb_ivb_laptops/variants/8560w/hda_verb.c new file mode 100644 index 0000000..d7573d5 --- /dev/null +++ b/src/mainboard/hp/snb_ivb_laptops/variants/8560w/hda_verb.c @@ -0,0 +1,31 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2020 The coreboot project Authors. + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include <device/azalia_device.h> + +const u32 cim_verb_data[] = { + 0x111d7605, /* Codec Vendor / Device ID: IDT */ + 0x103c1631, /* Subsystem ID */ + + 11, /* Number of 4 dword sets */ + AZALIA_SUBVENDOR(0, 0x103c1631), + AZALIA_PIN_CFG(0, 0x0a, 0x40f000f0), + AZALIA_PIN_CFG(0, 0x0b, 0x0421401f), + AZALIA_PIN_CFG(0, 0x0c, 0x04a11020), + AZALIA_PIN_CFG(0, 0x0d, 0x90170110), + AZALIA_PIN_CFG(0, 0x0e, 0x40f000f0), + AZALIA_PIN_CFG(0, 0x0f, 0x40f000f0), + AZALIA_PIN_CFG(0, 0x10, 0x40f000f0), + AZALIA_PIN_CFG(0, 0x11, 0x90a60130), + AZALIA_PIN_CFG(0, 0x1f, 0x40f000f0), + AZALIA_PIN_CFG(0, 0x20, 0x40f000f0), +}; + +const u32 pc_beep_verbs[0] = {}; + +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/hp/snb_ivb_laptops/variants/8560w/overridetree.cb b/src/mainboard/hp/snb_ivb_laptops/variants/8560w/overridetree.cb new file mode 100644 index 0000000..d716b46 --- /dev/null +++ b/src/mainboard/hp/snb_ivb_laptops/variants/8560w/overridetree.cb @@ -0,0 +1,60 @@ +# +# This file is part of the coreboot project. +# +# Copyright 2020 The coreboot project Authors. +# +# SPDX-License-Identifier: GPL-2.0-or-later +# + +chip northbridge/intel/sandybridge + device domain 0x0 on + subsystemid 0x103c 0x1631 inherit + device pci 01.0 on end # PCIe Bridge for discrete graphics + device pci 02.0 off end # Internal graphics + + chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH + register "docking_supported" = "0" + register "gen1_dec" = "0x007c0201" + register "gen2_dec" = "0x000c0101" + register "gen3_dec" = "0x00fcfe01" + register "gen4_dec" = "0x000402e9" + register "gpi6_routing" = "2" + register "pcie_hotplug_map" = "{ 0, 1, 1, 0, 0, 0, 0, 0 }" + # HDD(0), ODD(1), eSATA(4) + register "sata_port_map" = "0x3b" + + device pci 1c.0 on end # PCIe Port #1, WWAN + device pci 1c.1 on end # PCIe Port #2, ExpressCard + device pci 1c.2 on end # PCIe Port #3, SD/MMC + device pci 1c.3 on end # PCIe Port #4, WLAN + device pci 1c.4 off end # PCIe Port #5 + device pci 1c.5 off end # PCIe Port #6 + device pci 1c.6 off end # PCIe Port #7 + device pci 1c.7 on end # PCIe Port #8, NEC USB 3.0 Host Controller + device pci 1f.0 on # LPC bridge + chip ec/hp/kbc1126 + register "ec_data_port" = "0x60" + register "ec_cmd_port" = "0x64" + register "ec_ctrl_reg" = "0xca" + register "ec_fan_ctrl_value" = "0x6b" + device pnp ff.1 off end + end + chip superio/smsc/lpc47n217 + device pnp 4e.3 on # Parallel + io 0x60 = 0x378 + irq 0x70 = 7 + end + device pnp 4e.4 on # COM1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 4e.5 off end # COM2 + end + + chip drivers/pc80/tpm + device pnp 0c31.0 on end + end + end + end + end +end
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39398 )
Change subject: mb/hp: Add Elitebook 8560w as an HP Sandy/Ivy Bridge laptop variant ......................................................................
Patch Set 1: Code-Review+1
(6 comments)
https://review.coreboot.org/c/coreboot/+/39398/1/Documentation/mainboard/hp/... File Documentation/mainboard/hp/8560w.md:
https://review.coreboot.org/c/coreboot/+/39398/1/Documentation/mainboard/hp/... PS1, Line 12: 8MB 8 MiB
https://review.coreboot.org/c/coreboot/+/39398/1/src/mainboard/hp/snb_ivb_la... File src/mainboard/hp/snb_ivb_laptops/variants/8560w/early_init.c:
https://review.coreboot.org/c/coreboot/+/39398/1/src/mainboard/hp/snb_ivb_la... PS1, Line 1: /* : * This file is part of the coreboot project. : * : * Copyright 2020 The coreboot project Authors. : * : * SPDX-License-Identifier: GPL-2.0-or-later : */ /* SPDX-License-Identifier: GPL-2.0-or-later */
https://review.coreboot.org/c/coreboot/+/39398/1/src/mainboard/hp/snb_ivb_la... File src/mainboard/hp/snb_ivb_laptops/variants/8560w/gpio.c:
https://review.coreboot.org/c/coreboot/+/39398/1/src/mainboard/hp/snb_ivb_la... PS1, Line 1: /* : * This file is part of the coreboot project. : * : * Copyright 2020 The coreboot project Authors. : * : * SPDX-License-Identifier: GPL-2.0-or-later : */ /* SPDX-License-Identifier: GPL-2.0-or-later */
https://review.coreboot.org/c/coreboot/+/39398/1/src/mainboard/hp/snb_ivb_la... File src/mainboard/hp/snb_ivb_laptops/variants/8560w/hda_verb.c:
https://review.coreboot.org/c/coreboot/+/39398/1/src/mainboard/hp/snb_ivb_la... PS1, Line 1: /* : * This file is part of the coreboot project. : * : * Copyright 2020 The coreboot project Authors. : * : * SPDX-License-Identifier: GPL-2.0-or-later : */ /* SPDX-License-Identifier: GPL-2.0-or-later */
https://review.coreboot.org/c/coreboot/+/39398/1/src/mainboard/hp/snb_ivb_la... File src/mainboard/hp/snb_ivb_laptops/variants/8560w/overridetree.cb:
https://review.coreboot.org/c/coreboot/+/39398/1/src/mainboard/hp/snb_ivb_la... PS1, Line 1: # : # This file is part of the coreboot project. : # : # Copyright 2020 The coreboot project Authors. : # : # SPDX-License-Identifier: GPL-2.0-or-later : # ## SPDX-License-Identifier: GPL-2.0-or-later
https://review.coreboot.org/c/coreboot/+/39398/1/src/mainboard/hp/snb_ivb_la... PS1, Line 26: end nit: align the `end` words?
Hello build bot (Jenkins), Angel Pons, Iru Cai,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/39398
to look at the new patch set (#2).
Change subject: mb/hp: Add Elitebook 8560w as an HP Sandy/Ivy Bridge laptop variant ......................................................................
mb/hp: Add Elitebook 8560w as an HP Sandy/Ivy Bridge laptop variant
Change-Id: I15181792b1efa45a2a94d78e43c6257da1acf950 Signed-off-by: Iru Cai mytbk920423@gmail.com --- A Documentation/mainboard/hp/8560w.md A Documentation/mainboard/hp/8560w_flash.webp M Documentation/mainboard/index.md M src/mainboard/hp/snb_ivb_laptops/Kconfig M src/mainboard/hp/snb_ivb_laptops/Kconfig.name A src/mainboard/hp/snb_ivb_laptops/variants/8560w/board_info.txt A src/mainboard/hp/snb_ivb_laptops/variants/8560w/early_init.c A src/mainboard/hp/snb_ivb_laptops/variants/8560w/gpio.c A src/mainboard/hp/snb_ivb_laptops/variants/8560w/hda_verb.c A src/mainboard/hp/snb_ivb_laptops/variants/8560w/overridetree.cb 10 files changed, 453 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/39398/2
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Change subject: mb/hp: Add Elitebook 8560w as an HP Sandy/Ivy Bridge laptop variant ......................................................................
Patch Set 2:
(4 comments)
File src/mainboard/hp/snb_ivb_laptops/variants/8560w/early_init.c:
https://review.coreboot.org/c/coreboot/+/39398/comment/11b02e53_ec71ca43 PS1, Line 1: /* : * This file is part of the coreboot project. : * : * Copyright 2020 The coreboot project Authors. : * : * SPDX-License-Identifier: GPL-2.0-or-later : */
/* SPDX-License-Identifier: GPL-2. […]
Done
File src/mainboard/hp/snb_ivb_laptops/variants/8560w/gpio.c:
https://review.coreboot.org/c/coreboot/+/39398/comment/7dd3b5e5_302d2657 PS1, Line 1: /* : * This file is part of the coreboot project. : * : * Copyright 2020 The coreboot project Authors. : * : * SPDX-License-Identifier: GPL-2.0-or-later : */
/* SPDX-License-Identifier: GPL-2. […]
Done
File src/mainboard/hp/snb_ivb_laptops/variants/8560w/hda_verb.c:
https://review.coreboot.org/c/coreboot/+/39398/comment/cc4e46de_10aef365 PS1, Line 1: /* : * This file is part of the coreboot project. : * : * Copyright 2020 The coreboot project Authors. : * : * SPDX-License-Identifier: GPL-2.0-or-later : */
/* SPDX-License-Identifier: GPL-2. […]
Done
File src/mainboard/hp/snb_ivb_laptops/variants/8560w/overridetree.cb:
https://review.coreboot.org/c/coreboot/+/39398/comment/63952ff8_f28e2d35 PS1, Line 1: # : # This file is part of the coreboot project. : # : # Copyright 2020 The coreboot project Authors. : # : # SPDX-License-Identifier: GPL-2.0-or-later : #
## SPDX-License-Identifier: GPL-2. […]
Done
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Change subject: mb/hp: Add Elitebook 8560w as an HP Sandy/Ivy Bridge laptop variant ......................................................................
Patch Set 2:
(2 comments)
File Documentation/mainboard/hp/8560w.md:
https://review.coreboot.org/c/coreboot/+/39398/comment/39503f67_cba56c20 PS2, Line 10: ## Flashing instructions Is it possible to flash coreboot internally when running vendor firmware? The flashing instructions don't say anything about it, but seem to suggest that it works: the table says there's no write protection and that internal flashing is possible, but is it always the case?
File src/mainboard/hp/snb_ivb_laptops/variants/8560w/board_info.txt:
https://review.coreboot.org/c/coreboot/+/39398/comment/edb9f9ea_942933cd PS2, Line 6: n huh?
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Change subject: mb/hp: Add Elitebook 8560w as an HP Sandy/Ivy Bridge laptop variant ......................................................................
Patch Set 3:
(1 comment)
Patchset:
PS3: I still have this laptop, but I'm too tired to work on coreboot for a long time.
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Change subject: mb/hp: Add Elitebook 8560w as an HP Sandy/Ivy Bridge laptop variant ......................................................................
Patch Set 3:
(2 comments)
Patchset:
PS3: I have an 8560w now too. Compiled this branch with SeaBIOS for it and it successfully boots to Linux. With an annoying delay before SeaBIOS prompt though:
ERROR: Valid MXM Structure not found. POST halted for 30 seconds, P-state limited to P10...
It has i7-2670QM and 4G+4G+4G+4G (all four slots work) and a Quadro 2000M.
File Documentation/mainboard/hp/8560w.md:
https://review.coreboot.org/c/coreboot/+/39398/comment/f557e5fc_2d92a1ee : PS2, Line 10: ## Flashing instructions
Is it possible to flash coreboot internally when running vendor firmware? The flashing instructions […]
flashrom output on vendor BIOS: https://termbin.com/gzaq6 I don't think it looks internally flashable. Or maybe it is and I'm just not aware of how.
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I'd like you to reexamine a change. Please visit
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Change subject: mb/hp: Add Elitebook 8560w as an HP Sandy/Ivy Bridge laptop variant ......................................................................
mb/hp: Add Elitebook 8560w as an HP Sandy/Ivy Bridge laptop variant
Change-Id: I15181792b1efa45a2a94d78e43c6257da1acf950 Signed-off-by: Iru Cai mytbk920423@gmail.com --- A Documentation/mainboard/hp/8560w.md A Documentation/mainboard/hp/8560w_flash.webp M Documentation/mainboard/index.md M src/mainboard/hp/snb_ivb_laptops/Kconfig M src/mainboard/hp/snb_ivb_laptops/Kconfig.name A src/mainboard/hp/snb_ivb_laptops/variants/8560w/board_info.txt A src/mainboard/hp/snb_ivb_laptops/variants/8560w/early_init.c A src/mainboard/hp/snb_ivb_laptops/variants/8560w/gpio.c A src/mainboard/hp/snb_ivb_laptops/variants/8560w/hda_verb.c A src/mainboard/hp/snb_ivb_laptops/variants/8560w/overridetree.cb 10 files changed, 438 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/39398/4
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Change subject: mb/hp: Add Elitebook 8560w as an HP Sandy/Ivy Bridge laptop variant ......................................................................
Patch Set 4:
(9 comments)
Patchset:
PS3:
I have an 8560w now too. […]
Hmm, I haven't read the debug log, but I can see the boot time is longer than the vendor firmware. I use an NVIDIA card.
Patchset:
PS4: Update on the current coreboot code. It still boots, but I haven't tested the components yet.
File Documentation/mainboard/hp/8560w.md:
https://review.coreboot.org/c/coreboot/+/39398/comment/379bff41_0896560b : PS1, Line 12: 8MB
8 MiB
Done
File Documentation/mainboard/hp/8560w.md:
https://review.coreboot.org/c/coreboot/+/39398/comment/2c5e3ba2_f840b5f5 : PS2, Line 10: ## Flashing instructions
flashrom output on vendor BIOS: https://termbin.com/gzaq6 […]
I haven't tried flashing on vendor firmware yet.
File src/mainboard/hp/snb_ivb_laptops/variants/8560w/board_info.txt:
https://review.coreboot.org/c/coreboot/+/39398/comment/17f5daea_66e9b1a2 : PS2, Line 6: n
huh?
Done
File src/mainboard/hp/snb_ivb_laptops/variants/8560w/early_init.c:
https://review.coreboot.org/c/coreboot/+/39398/comment/2acba906_841dc62d : PS1, Line 1: /* : * This file is part of the coreboot project. : * : * Copyright 2020 The coreboot project Authors. : * : * SPDX-License-Identifier: GPL-2.0-or-later : */
/* SPDX-License-Identifier: GPL-2. […]
Done
File src/mainboard/hp/snb_ivb_laptops/variants/8560w/gpio.c:
https://review.coreboot.org/c/coreboot/+/39398/comment/e09e41e9_a73dc33b : PS1, Line 1: /* : * This file is part of the coreboot project. : * : * Copyright 2020 The coreboot project Authors. : * : * SPDX-License-Identifier: GPL-2.0-or-later : */
/* SPDX-License-Identifier: GPL-2. […]
Done
File src/mainboard/hp/snb_ivb_laptops/variants/8560w/hda_verb.c:
https://review.coreboot.org/c/coreboot/+/39398/comment/84e0ba5a_3e52272d : PS1, Line 1: /* : * This file is part of the coreboot project. : * : * Copyright 2020 The coreboot project Authors. : * : * SPDX-License-Identifier: GPL-2.0-or-later : */
/* SPDX-License-Identifier: GPL-2. […]
Done
File src/mainboard/hp/snb_ivb_laptops/variants/8560w/overridetree.cb:
https://review.coreboot.org/c/coreboot/+/39398/comment/f8857902_5f321d37 : PS1, Line 26: end
nit: align the `end` words?
Done
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Change subject: mb/hp: Add Elitebook 8560w as an HP Sandy/Ivy Bridge laptop variant ......................................................................
Patch Set 4:
(1 comment)
Patchset:
PS3:
Hmm, I haven't read the debug log, but I can see the boot time is longer than the vendor firmware. […]
Just found that the 8770w port in CB:23651 mentioned the lack of MXM structure, but I cannot find the said work around in the wiki.
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Change subject: mb/hp: Add Elitebook 8560w as an HP Sandy/Ivy Bridge laptop variant ......................................................................
Patch Set 4:
(1 comment)
Patchset:
PS3:
Just found that the 8770w port in CB:23651 mentioned the lack of MXM structure, but I cannot find th […]
I implemented the missing interrupts in SeaBIOS, patches for review: https://mail.coreboot.org/hyperkitty/list/seabios@seabios.org/thread/LK2ZHY6...
Also wrote a tool for dumping and parsing the structure from vendor BIOS: https://codeberg.org/Riku_V/mxmdump/
It's a variable length (in this case 129 byte) binary configuration file, surely it could be included in coreboot?
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Change subject: mb/hp: Add Elitebook 8560w as an HP Sandy/Ivy Bridge laptop variant ......................................................................
Patch Set 4:
(1 comment)
File src/mainboard/hp/snb_ivb_laptops/variants/8560w/gpio.c:
https://review.coreboot.org/c/coreboot/+/39398/comment/349e2cff_ce7c9f69 : PS4, Line 158: .gpio57 = GPIO_LEVEL_LOW, That's `WLAN_TRN_OFF#`, so if Wi-Fi doesn't work try setting this to `GPIO_LEVEL_HIGH`
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Change subject: mb/hp: Add Elitebook 8560w as an HP Sandy/Ivy Bridge laptop variant ......................................................................
Patch Set 4:
(1 comment)
Patchset:
PS4: This is on Gerrit for 4 years now, but it looks overall good. The remaining comments don't seem critical and could be solved in follow-up patches, I think.
Any strong opinions? Can we get this in?
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Change subject: mb/hp: Add Elitebook 8560w as an HP Sandy/Ivy Bridge laptop variant ......................................................................
Patch Set 4:
(1 comment)
Patchset:
PS4:
This is on Gerrit for 4 years now, but it looks overall good. […]
It's untested
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Change subject: mb/hp: Add Elitebook 8560w as an HP Sandy/Ivy Bridge laptop variant ......................................................................
Patch Set 4:
(1 comment)
Patchset:
PS4:
It's untested
Riku seemed to test it in summer last year. Still with some issue, but it doesn't sound like it should block this patch. https://review.coreboot.org/c/coreboot/+/39398/4#message-a80ca8e6ca72b4c5086...
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Change subject: mb/hp: Add Elitebook 8560w as an HP Sandy/Ivy Bridge laptop variant ......................................................................
Patch Set 4:
(1 comment)
Patchset:
PS4:
Riku seemed to test it in summer last year. […]
Well, it'd be great to update this with any improvements. If someone can test and update this change (or another change), I don't mind reviewing. It's just that submitting a mainboard port in an unknown condition feels wrong.
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Hello Angel Pons, Felix Singer, Iru Cai, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
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to look at the new patch set (#5).
The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins)
Change subject: mb/hp: Add Elitebook 8560w as an HP Sandy/Ivy Bridge laptop variant ......................................................................
mb/hp: Add Elitebook 8560w as an HP Sandy/Ivy Bridge laptop variant
The components listed in the documentation work in this port. The lack of an MXM structure in the firmware makes the laptop boot slower than the vendor firmware, which can be resolved by by adding the MXM structure and adding MXM interrupts in SeaBIOS.
Change-Id: I15181792b1efa45a2a94d78e43c6257da1acf950 Signed-off-by: Iru Cai mytbk920423@gmail.com --- A Documentation/mainboard/hp/8560w.md A Documentation/mainboard/hp/8560w_flash.webp M Documentation/mainboard/index.md M src/mainboard/hp/snb_ivb_laptops/Kconfig M src/mainboard/hp/snb_ivb_laptops/Kconfig.name A src/mainboard/hp/snb_ivb_laptops/variants/8560w/board_info.txt A src/mainboard/hp/snb_ivb_laptops/variants/8560w/early_init.c A src/mainboard/hp/snb_ivb_laptops/variants/8560w/gpio.c A src/mainboard/hp/snb_ivb_laptops/variants/8560w/hda_verb.c A src/mainboard/hp/snb_ivb_laptops/variants/8560w/overridetree.cb 10 files changed, 453 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/39398/5
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Change subject: mb/hp: Add Elitebook 8560w as an HP Sandy/Ivy Bridge laptop variant ......................................................................
Patch Set 5: Code-Review+1
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/39398/comment/9c14b0b2_df103fd0?usp... : PS5, Line 10: MXM structure What's a MXM structure?
File src/mainboard/hp/snb_ivb_laptops/variants/8560w/gpio.c:
https://review.coreboot.org/c/coreboot/+/39398/comment/eb18e542_7543fd03?usp... : PS4, Line 158: .gpio57 = GPIO_LEVEL_LOW,
That's `WLAN_TRN_OFF#`, so if Wi-Fi doesn't work try setting this to `GPIO_LEVEL_HIGH`
Done
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Change subject: mb/hp: Add Elitebook 8560w as an HP Sandy/Ivy Bridge laptop variant ......................................................................
Patch Set 5:
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/39398/comment/2ef51075_9eda7708?usp... : PS5, Line 10: MXM structure
What's a MXM structure?
It's a data structure describing the system, including display output configurations, power supply capabilities.
MXM 2.1: https://lekensteyn.nl/files/docs/mxm-2.1-software-spec.pdf MXM 3.0: https://lekensteyn.nl/files/docs/mxm-graphics-module-software-specification-...
File Documentation/mainboard/hp/8560w.md:
https://review.coreboot.org/c/coreboot/+/39398/comment/9dc298fa_856a8381?usp... : PS2, Line 10: ## Flashing instructions
I haven't tried flashing on vendor firmware yet.
Done
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Hello Angel Pons, Felix Singer, Iru Cai, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
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to look at the new patch set (#6).
The following approvals got outdated and were removed: Code-Review+1 by Angel Pons, Verified+1 by build bot (Jenkins)
Change subject: mb/hp: Add Elitebook 8560w as an HP Sandy/Ivy Bridge laptop variant ......................................................................
mb/hp: Add Elitebook 8560w as an HP Sandy/Ivy Bridge laptop variant
The components listed in the documentation work in this port. The MXM structure of the vendor firmware is added.
Change-Id: I15181792b1efa45a2a94d78e43c6257da1acf950 Signed-off-by: Iru Cai mytbk920423@gmail.com --- A Documentation/mainboard/hp/8560w.md A Documentation/mainboard/hp/8560w_flash.webp M Documentation/mainboard/index.md M src/mainboard/hp/snb_ivb_laptops/Kconfig M src/mainboard/hp/snb_ivb_laptops/Kconfig.name M src/mainboard/hp/snb_ivb_laptops/Makefile.mk A src/mainboard/hp/snb_ivb_laptops/variants/8560w/board_info.txt A src/mainboard/hp/snb_ivb_laptops/variants/8560w/early_init.c A src/mainboard/hp/snb_ivb_laptops/variants/8560w/gpio.c A src/mainboard/hp/snb_ivb_laptops/variants/8560w/hda_verb.c A src/mainboard/hp/snb_ivb_laptops/variants/8560w/mxm.cfg A src/mainboard/hp/snb_ivb_laptops/variants/8560w/overridetree.cb 12 files changed, 442 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/39398/6
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Change subject: mb/hp: Add Elitebook 8560w as an HP Sandy/Ivy Bridge laptop variant ......................................................................
Patch Set 6:
(1 comment)
Patchset:
PS6: I tried to add the MXM structure file, while using the .cfg suffix can pass the lint check, jenkins will check the newline in this file and fail.
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Change subject: mb/hp: Add Elitebook 8560w as an HP Sandy/Ivy Bridge laptop variant ......................................................................
Patch Set 6:
(1 comment)
File src/mainboard/hp/snb_ivb_laptops/variants/8560w/mxm.cfg:
PS6: How is this table used by coreboot? I see it gets added to CBFS, but what does it do there?
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Change subject: mb/hp: Add Elitebook 8560w as an HP Sandy/Ivy Bridge laptop variant ......................................................................
Patch Set 6:
(1 comment)
File src/mainboard/hp/snb_ivb_laptops/variants/8560w/mxm.cfg:
PS6:
How is this table used by coreboot? I see it gets added to CBFS, but what does it do there?
Riku has a SeaBIOS change that can read the MXM data from CBFS and use it in an int15 handler. It's now used in Libreboot. https://codeberg.org/libreboot/lbmk/pulls/187
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Change subject: mb/hp: Add Elitebook 8560w as an HP Sandy/Ivy Bridge laptop variant ......................................................................
Patch Set 6:
(1 comment)
File src/mainboard/hp/snb_ivb_laptops/variants/8560w/mxm.cfg:
PS6:
Riku has a SeaBIOS change that can read the MXM data from CBFS and use it in an int15 handler. […]
Okay. Regarding Jenkins being unhappy, as this is a binary data structure, I would rename its extension to .bin
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Change subject: mb/hp: Add Elitebook 8560w as an HP Sandy/Ivy Bridge laptop variant ......................................................................
Patch Set 6:
(1 comment)
File src/mainboard/hp/snb_ivb_laptops/Makefile.mk:
https://review.coreboot.org/c/coreboot/+/39398/comment/bca18716_dbb7685a?usp... : PS6, Line 13: ifeq ($(CONFIG_BOARD_HP_8560W),y) : cbfs-files-y += mxm-30-sis : mxm-30-sis-file := variants/$(VARIANT_DIR)/mxm.cfg : mxm-30-sis-type := raw : endif ```suggestion subdirs-y += $(wildcard variants/$(VARIANT_DIR)/Makefile.mk) ```
Then put this in your variant's `Makefile.mk`:
``` ## <license header>
cbfs-files-y += mxm-30-sis mxm-30-sis-file := mxm.bin mxm-30-sis-type := raw ```
If you expect other boards to use this in the future, perhaps it should be moved out of mainboards and controlled via a Kconfig option.
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Change subject: mb/hp: Add Elitebook 8560w as an HP Sandy/Ivy Bridge laptop variant ......................................................................
Patch Set 6:
(1 comment)
File src/mainboard/hp/snb_ivb_laptops/variants/8560w/mxm.cfg:
PS6:
Okay. […]
How is that file obtained?
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Change subject: mb/hp: Add Elitebook 8560w as an HP Sandy/Ivy Bridge laptop variant ......................................................................
Patch Set 6:
(1 comment)
File src/mainboard/hp/snb_ivb_laptops/variants/8560w/mxm.cfg:
PS6:
How is that file obtained?
It can be dumped from a running system. I searched in the vendor firmware with UEFI tool, and extract the same file as used in Libreboot.
I tried to name the file as mxm.bin, and found it in .gitignore, so I changed the name to .cfg.
https://codeberg.org/Riku_V/mxmdump/
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Change subject: mb/hp: Add Elitebook 8560w as an HP Sandy/Ivy Bridge laptop variant ......................................................................
Patch Set 6:
(1 comment)
File src/mainboard/hp/snb_ivb_laptops/variants/8560w/mxm.cfg:
PS6:
It can be dumped from a running system. […]
OK, then perhaps use `.mxm` as file extension and update the list in https://github.com/coreboot/coreboot/blob/05bb053e6356b30bfa2ae27d0b38e592e4...
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I'd like you to reexamine a change. Please visit
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Change subject: mb/hp: Add Elitebook 8560w as an HP Sandy/Ivy Bridge laptop variant ......................................................................
mb/hp: Add Elitebook 8560w as an HP Sandy/Ivy Bridge laptop variant
The components listed in the documentation work in this port. The MXM structure of the vendor firmware is added, which is used by the VGA option ROM with int15h functions.
Change-Id: I15181792b1efa45a2a94d78e43c6257da1acf950 Signed-off-by: Iru Cai mytbk920423@gmail.com --- A Documentation/mainboard/hp/8560w.md A Documentation/mainboard/hp/8560w_flash.webp M Documentation/mainboard/index.md M src/mainboard/hp/snb_ivb_laptops/Kconfig M src/mainboard/hp/snb_ivb_laptops/Kconfig.name M src/mainboard/hp/snb_ivb_laptops/Makefile.mk A src/mainboard/hp/snb_ivb_laptops/variants/8560w/Makefile.mk A src/mainboard/hp/snb_ivb_laptops/variants/8560w/board_info.txt A src/mainboard/hp/snb_ivb_laptops/variants/8560w/early_init.c A src/mainboard/hp/snb_ivb_laptops/variants/8560w/gpio.c A src/mainboard/hp/snb_ivb_laptops/variants/8560w/hda_verb.c A src/mainboard/hp/snb_ivb_laptops/variants/8560w/mxm.bin A src/mainboard/hp/snb_ivb_laptops/variants/8560w/overridetree.cb 13 files changed, 443 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/39398/7
Attention is currently required from: Angel Pons, Felix Singer, Riku Viitanen.
Iru Cai has posted comments on this change by Iru Cai. ( https://review.coreboot.org/c/coreboot/+/39398?usp=email )
Change subject: mb/hp: Add Elitebook 8560w as an HP Sandy/Ivy Bridge laptop variant ......................................................................
Patch Set 7:
(2 comments)
Patchset:
PS3:
I implemented the missing interrupts in SeaBIOS, patches for review: https://mail.coreboot. […]
I've just added this now.
File src/mainboard/hp/snb_ivb_laptops/variants/8560w/mxm.cfg:
PS6:
OK, then perhaps use `.mxm` as file extension and update the list in https://github. […]
I'll still use .bin and use git add -f.
Attention is currently required from: Angel Pons, Felix Singer, Riku Viitanen.
Hello Angel Pons, Felix Singer, Iru Cai, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/39398?usp=email
to look at the new patch set (#8).
The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins)
Change subject: mb/hp: Add Elitebook 8560w as an HP Sandy/Ivy Bridge laptop variant ......................................................................
mb/hp: Add Elitebook 8560w as an HP Sandy/Ivy Bridge laptop variant
The components listed in the documentation work in this port. The MXM structure of the vendor firmware is added, which is used by the VGA option ROM with int15h functions.
Change-Id: I15181792b1efa45a2a94d78e43c6257da1acf950 Signed-off-by: Iru Cai mytbk920423@gmail.com --- A Documentation/mainboard/hp/8560w.md A Documentation/mainboard/hp/8560w_flash.webp M Documentation/mainboard/index.md M src/mainboard/hp/snb_ivb_laptops/Kconfig M src/mainboard/hp/snb_ivb_laptops/Kconfig.name M src/mainboard/hp/snb_ivb_laptops/Makefile.mk A src/mainboard/hp/snb_ivb_laptops/variants/8560w/Makefile.mk A src/mainboard/hp/snb_ivb_laptops/variants/8560w/board_info.txt A src/mainboard/hp/snb_ivb_laptops/variants/8560w/early_init.c A src/mainboard/hp/snb_ivb_laptops/variants/8560w/gpio.c A src/mainboard/hp/snb_ivb_laptops/variants/8560w/hda_verb.c A src/mainboard/hp/snb_ivb_laptops/variants/8560w/mxm.bin A src/mainboard/hp/snb_ivb_laptops/variants/8560w/overridetree.cb 13 files changed, 443 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/39398/8
Attention is currently required from: Angel Pons, Iru Cai, Riku Viitanen.
Felix Singer has posted comments on this change by Iru Cai. ( https://review.coreboot.org/c/coreboot/+/39398?usp=email )
Change subject: mb/hp: Add Elitebook 8560w as an HP Sandy/Ivy Bridge laptop variant ......................................................................
Patch Set 8:
(2 comments)
Patchset:
PS4:
Well, it'd be great to update this with any improvements. […]
Done
File src/mainboard/hp/snb_ivb_laptops/Makefile.mk:
https://review.coreboot.org/c/coreboot/+/39398/comment/ddb823d9_695161c9?usp... : PS6, Line 13: ifeq ($(CONFIG_BOARD_HP_8560W),y) : cbfs-files-y += mxm-30-sis : mxm-30-sis-file := variants/$(VARIANT_DIR)/mxm.cfg : mxm-30-sis-type := raw : endif
Done
Attention is currently required from: Angel Pons, Iru Cai, Riku Viitanen.
Felix Singer has posted comments on this change by Iru Cai. ( https://review.coreboot.org/c/coreboot/+/39398?usp=email )
Change subject: mb/hp: Add Elitebook 8560w as an HP Sandy/Ivy Bridge laptop variant ......................................................................
Patch Set 8: Code-Review+2
Felix Singer has submitted this change. ( https://review.coreboot.org/c/coreboot/+/39398?usp=email )
Change subject: mb/hp: Add Elitebook 8560w as an HP Sandy/Ivy Bridge laptop variant ......................................................................
mb/hp: Add Elitebook 8560w as an HP Sandy/Ivy Bridge laptop variant
The components listed in the documentation work in this port. The MXM structure of the vendor firmware is added, which is used by the VGA option ROM with int15h functions.
Change-Id: I15181792b1efa45a2a94d78e43c6257da1acf950 Signed-off-by: Iru Cai mytbk920423@gmail.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/39398 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Felix Singer service+coreboot-gerrit@felixsinger.de --- A Documentation/mainboard/hp/8560w.md A Documentation/mainboard/hp/8560w_flash.webp M Documentation/mainboard/index.md M src/mainboard/hp/snb_ivb_laptops/Kconfig M src/mainboard/hp/snb_ivb_laptops/Kconfig.name M src/mainboard/hp/snb_ivb_laptops/Makefile.mk A src/mainboard/hp/snb_ivb_laptops/variants/8560w/Makefile.mk A src/mainboard/hp/snb_ivb_laptops/variants/8560w/board_info.txt A src/mainboard/hp/snb_ivb_laptops/variants/8560w/early_init.c A src/mainboard/hp/snb_ivb_laptops/variants/8560w/gpio.c A src/mainboard/hp/snb_ivb_laptops/variants/8560w/hda_verb.c A src/mainboard/hp/snb_ivb_laptops/variants/8560w/mxm.bin A src/mainboard/hp/snb_ivb_laptops/variants/8560w/overridetree.cb 13 files changed, 443 insertions(+), 1 deletion(-)
Approvals: Felix Singer: Looks good to me, approved build bot (Jenkins): Verified
diff --git a/Documentation/mainboard/hp/8560w.md b/Documentation/mainboard/hp/8560w.md new file mode 100644 index 0000000..babd632 --- /dev/null +++ b/Documentation/mainboard/hp/8560w.md @@ -0,0 +1,80 @@ +# HP EliteBook 8560w + +This page describes how to run coreboot on the [HP EliteBook 8560w]. + +## Required proprietary blobs + +- Intel Firmware Descriptor, ME and GbE firmware +- EC: please read [HP Laptops with KBC1126 Embedded Controller](hp_kbc1126_laptops) + +## Flashing instructions + +When running vendor firmware, external flashing is needed. + +HP EliteBook 8560w has an 8MiB SOIC-8 flash chip on the bottom of the +mainboard. You just need to remove the service cover, and use an SOIC-8 +clip to read and flash the chip. + + + +```eval_rst ++---------------------+------------+ +| Type | Value | ++=====================+============+ +| Socketed flash | no | ++---------------------+------------+ +| Model | MX25L6406E | ++---------------------+------------+ +| Size | 8 MiB | ++---------------------+------------+ +| Package | SOIC-8 | ++---------------------+------------+ +| Write protection | no | ++---------------------+------------+ +| Dual BIOS feature | no | ++---------------------+------------+ +| In circuit flashing | yes | ++---------------------+------------+ +| Internal flashing | yes | ++---------------------+------------+ +``` + +## Working + +- i7-2720QM, 8G+8G +- Arch Linux boot from SeaBIOS payload +- EHCI debug: the port is beside the eSATA port +- SATA +- eSATA +- USB2 and USB3 +- keyboard +- Gigabit Ethernet +- WLAN +- WWAN +- VGA and DisplayPort +- audio +- EC ACPI +- Using `me_cleaner` +- dock: PS/2 keyboard, USB, DisplayPort +- TPM +- S3 suspend/resume + +## Technology + +```eval_rst ++------------------+--------------------------------------------------+ +| Northbridge | :doc:`../../northbridge/intel/sandybridge/index` | ++------------------+--------------------------------------------------+ +| Southbridge | bd82x6x | ++------------------+--------------------------------------------------+ +| CPU | model_206ax | ++------------------+--------------------------------------------------+ +| Super I/O | SMSC LPC47n217 | ++------------------+--------------------------------------------------+ +| EC | SMSC KBC1126 | ++------------------+--------------------------------------------------+ +| Coprocessor | Intel Management Engine | ++------------------+--------------------------------------------------+ +``` + +[HP EliteBook 8560w]: https://support.hp.com/us-en/product/hp-elitebook-8560w-mobile-workstation/5... diff --git a/Documentation/mainboard/hp/8560w_flash.webp b/Documentation/mainboard/hp/8560w_flash.webp new file mode 100644 index 0000000..b8295bc --- /dev/null +++ b/Documentation/mainboard/hp/8560w_flash.webp Binary files differ diff --git a/Documentation/mainboard/index.md b/Documentation/mainboard/index.md index e54b01f..67de67b 100644 --- a/Documentation/mainboard/index.md +++ b/Documentation/mainboard/index.md @@ -142,6 +142,7 @@ HP Sure Start <hp/hp_sure_start.md> EliteBook 2170p <hp/2170p.md> EliteBook 2560p <hp/2560p.md> +EliteBook 8560w <hp/8560w.md> EliteBook 8760w <hp/8760w.md> EliteBook Folio 9480m <hp/folio_9480m.md> EliteBook 820 G2 <hp/elitebook_820_g2.md> diff --git a/src/mainboard/hp/snb_ivb_laptops/Kconfig b/src/mainboard/hp/snb_ivb_laptops/Kconfig index f0bd55f..f180bca 100644 --- a/src/mainboard/hp/snb_ivb_laptops/Kconfig +++ b/src/mainboard/hp/snb_ivb_laptops/Kconfig @@ -69,6 +69,12 @@ select SOUTHBRIDGE_INTEL_C216 select SUPERIO_SMSC_LPC47N217
+config BOARD_HP_8560W + select BOARD_HP_SNB_IVB_LAPTOPS_COMMON + select BOARD_ROMSIZE_KB_8192 + select SOUTHBRIDGE_INTEL_BD82X6X + select SUPERIO_SMSC_LPC47N217 + config BOARD_HP_8770W select BOARD_HP_SNB_IVB_LAPTOPS_COMMON select BOARD_ROMSIZE_KB_16384 @@ -118,6 +124,7 @@ default "2760p" if BOARD_HP_2760P default "8460p" if BOARD_HP_8460P default "8470p" if BOARD_HP_8470P + default "8560w" if BOARD_HP_8560W default "8770w" if BOARD_HP_8770W default "folio_9470m" if BOARD_HP_FOLIO_9470M default "probook_6360b" if BOARD_HP_PROBOOK_6360B @@ -130,6 +137,7 @@ default "EliteBook 2760p" if BOARD_HP_2760P default "EliteBook 8460p" if BOARD_HP_8460P default "EliteBook 8470p" if BOARD_HP_8470P + default "EliteBook 8560w" if BOARD_HP_8560W default "EliteBook 8770w" if BOARD_HP_8770W default "EliteBook Folio 9470m" if BOARD_HP_FOLIO_9470M default "ProBook 6360b" if BOARD_HP_PROBOOK_6360B @@ -146,7 +154,7 @@ config USBDEBUG_HCD_INDEX int default 0 if BOARD_HP_2170P || BOARD_HP_FOLIO_9470M - default 1 if BOARD_HP_2560P || BOARD_HP_2760P || BOARD_HP_8460P + default 1 if BOARD_HP_2560P || BOARD_HP_2760P || BOARD_HP_8460P || BOARD_HP_8560W default 2 if BOARD_HP_2570P || BOARD_HP_8470P || BOARD_HP_8770W default 1 if BOARD_HP_PROBOOK_6360B # FIXME: check this default 2 if BOARD_HP_REVOLVE_810_G1 # FIXME: check this diff --git a/src/mainboard/hp/snb_ivb_laptops/Kconfig.name b/src/mainboard/hp/snb_ivb_laptops/Kconfig.name index f72e0f6..fdd1b93 100644 --- a/src/mainboard/hp/snb_ivb_laptops/Kconfig.name +++ b/src/mainboard/hp/snb_ivb_laptops/Kconfig.name @@ -18,6 +18,9 @@ config BOARD_HP_8470P bool "EliteBook 8470p"
+config BOARD_HP_8560W + bool "EliteBook 8560w" + config BOARD_HP_8770W bool "EliteBook 8770w"
diff --git a/src/mainboard/hp/snb_ivb_laptops/Makefile.mk b/src/mainboard/hp/snb_ivb_laptops/Makefile.mk index c007bb6..c7b3069 100644 --- a/src/mainboard/hp/snb_ivb_laptops/Makefile.mk +++ b/src/mainboard/hp/snb_ivb_laptops/Makefile.mk @@ -9,3 +9,5 @@
# FIXME: Other variants with same size onboard RAM may exist. SPD_SOURCES = hynix_4g + +subdirs-y += variants/$(VARIANT_DIR) diff --git a/src/mainboard/hp/snb_ivb_laptops/variants/8560w/Makefile.mk b/src/mainboard/hp/snb_ivb_laptops/variants/8560w/Makefile.mk new file mode 100644 index 0000000..e8975cc --- /dev/null +++ b/src/mainboard/hp/snb_ivb_laptops/variants/8560w/Makefile.mk @@ -0,0 +1,5 @@ +## SPDX-License-Identifier: GPL-2.0-only + +cbfs-files-y += mxm-30-sis +mxm-30-sis-file := mxm.bin +mxm-30-sis-type := raw diff --git a/src/mainboard/hp/snb_ivb_laptops/variants/8560w/board_info.txt b/src/mainboard/hp/snb_ivb_laptops/variants/8560w/board_info.txt new file mode 100644 index 0000000..558e904 --- /dev/null +++ b/src/mainboard/hp/snb_ivb_laptops/variants/8560w/board_info.txt @@ -0,0 +1,7 @@ +Category: laptop +Board URL: https://support.hp.com/us-en/product/hp-elitebook-8560w-mobile-workstation/5... +ROM package: SOIC-8 +ROM protocol: SPI +ROM socketed: n +Flashrom support: y +Release year: 2011 diff --git a/src/mainboard/hp/snb_ivb_laptops/variants/8560w/early_init.c b/src/mainboard/hp/snb_ivb_laptops/variants/8560w/early_init.c new file mode 100644 index 0000000..3c966a4 --- /dev/null +++ b/src/mainboard/hp/snb_ivb_laptops/variants/8560w/early_init.c @@ -0,0 +1,19 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <bootblock_common.h> +#include <southbridge/intel/bd82x6x/pch.h> +#include <superio/smsc/lpc47n217/lpc47n217.h> +#include <ec/hp/kbc1126/ec.h> + +#define SERIAL_DEV PNP_DEV(0x4e, LPC47N217_SP1) + +void bootblock_mainboard_early_init(void) +{ + lpc47n217_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + kbc1126_enter_conf(); + kbc1126_mailbox_init(); + kbc1126_kbc_init(); + kbc1126_ec_init(); + kbc1126_pm1_init(); + kbc1126_exit_conf(); +} diff --git a/src/mainboard/hp/snb_ivb_laptops/variants/8560w/gpio.c b/src/mainboard/hp/snb_ivb_laptops/variants/8560w/gpio.c new file mode 100644 index 0000000..10cd11c --- /dev/null +++ b/src/mainboard/hp/snb_ivb_laptops/variants/8560w/gpio.c @@ -0,0 +1,224 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <southbridge/intel/common/gpio.h> + +static const struct pch_gpio_set1 pch_gpio_set1_mode = { + .gpio0 = GPIO_MODE_GPIO, + .gpio1 = GPIO_MODE_GPIO, + .gpio2 = GPIO_MODE_GPIO, + .gpio3 = GPIO_MODE_GPIO, + .gpio4 = GPIO_MODE_GPIO, + .gpio5 = GPIO_MODE_NATIVE, + .gpio6 = GPIO_MODE_GPIO, + .gpio7 = GPIO_MODE_GPIO, + .gpio8 = GPIO_MODE_GPIO, + .gpio9 = GPIO_MODE_NATIVE, + .gpio10 = GPIO_MODE_GPIO, + .gpio11 = GPIO_MODE_GPIO, + .gpio12 = GPIO_MODE_NATIVE, + .gpio13 = GPIO_MODE_GPIO, + .gpio14 = GPIO_MODE_GPIO, + .gpio15 = GPIO_MODE_GPIO, + .gpio16 = GPIO_MODE_GPIO, + .gpio17 = GPIO_MODE_GPIO, + .gpio18 = GPIO_MODE_NATIVE, + .gpio19 = GPIO_MODE_GPIO, + .gpio20 = GPIO_MODE_NATIVE, + .gpio21 = GPIO_MODE_GPIO, + .gpio22 = GPIO_MODE_GPIO, + .gpio23 = GPIO_MODE_GPIO, + .gpio24 = GPIO_MODE_GPIO, + .gpio25 = GPIO_MODE_NATIVE, + .gpio26 = GPIO_MODE_NATIVE, + .gpio27 = GPIO_MODE_GPIO, + .gpio28 = GPIO_MODE_GPIO, + .gpio29 = GPIO_MODE_GPIO, + .gpio30 = GPIO_MODE_NATIVE, + .gpio31 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_direction = { + .gpio0 = GPIO_DIR_OUTPUT, + .gpio1 = GPIO_DIR_INPUT, + .gpio2 = GPIO_DIR_INPUT, + .gpio3 = GPIO_DIR_INPUT, + .gpio4 = GPIO_DIR_INPUT, + .gpio6 = GPIO_DIR_INPUT, + .gpio7 = GPIO_DIR_INPUT, + .gpio8 = GPIO_DIR_INPUT, + .gpio10 = GPIO_DIR_INPUT, + .gpio11 = GPIO_DIR_OUTPUT, + .gpio13 = GPIO_DIR_INPUT, + .gpio14 = GPIO_DIR_INPUT, + .gpio15 = GPIO_DIR_INPUT, + .gpio16 = GPIO_DIR_INPUT, + .gpio17 = GPIO_DIR_OUTPUT, + .gpio19 = GPIO_DIR_INPUT, + .gpio21 = GPIO_DIR_INPUT, + .gpio22 = GPIO_DIR_OUTPUT, + .gpio23 = GPIO_DIR_INPUT, + .gpio24 = GPIO_DIR_OUTPUT, + .gpio27 = GPIO_DIR_OUTPUT, + .gpio28 = GPIO_DIR_OUTPUT, + .gpio29 = GPIO_DIR_OUTPUT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_level = { + .gpio0 = GPIO_LEVEL_LOW, + .gpio11 = GPIO_LEVEL_LOW, + .gpio17 = GPIO_LEVEL_HIGH, + .gpio22 = GPIO_LEVEL_HIGH, + .gpio24 = GPIO_LEVEL_HIGH, + .gpio27 = GPIO_LEVEL_LOW, + .gpio28 = GPIO_LEVEL_LOW, + .gpio29 = GPIO_LEVEL_HIGH, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_reset = { + .gpio24 = GPIO_RESET_RSMRST, + .gpio30 = GPIO_RESET_RSMRST, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_invert = { + .gpio1 = GPIO_INVERT, + .gpio3 = GPIO_INVERT, + .gpio6 = GPIO_INVERT, + .gpio7 = GPIO_INVERT, + .gpio10 = GPIO_INVERT, + .gpio13 = GPIO_INVERT, + .gpio14 = GPIO_INVERT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_blink = { +}; + +static const struct pch_gpio_set2 pch_gpio_set2_mode = { + .gpio32 = GPIO_MODE_NATIVE, + .gpio33 = GPIO_MODE_GPIO, + .gpio34 = GPIO_MODE_GPIO, + .gpio35 = GPIO_MODE_GPIO, + .gpio36 = GPIO_MODE_NATIVE, + .gpio37 = GPIO_MODE_GPIO, + .gpio38 = GPIO_MODE_GPIO, + .gpio39 = GPIO_MODE_GPIO, + .gpio40 = GPIO_MODE_NATIVE, + .gpio41 = GPIO_MODE_NATIVE, + .gpio42 = GPIO_MODE_NATIVE, + .gpio43 = GPIO_MODE_NATIVE, + .gpio44 = GPIO_MODE_GPIO, + .gpio45 = GPIO_MODE_NATIVE, + .gpio46 = GPIO_MODE_GPIO, + .gpio47 = GPIO_MODE_NATIVE, + .gpio48 = GPIO_MODE_GPIO, + .gpio49 = GPIO_MODE_GPIO, + .gpio50 = GPIO_MODE_GPIO, + .gpio51 = GPIO_MODE_GPIO, + .gpio52 = GPIO_MODE_GPIO, + .gpio53 = GPIO_MODE_GPIO, + .gpio54 = GPIO_MODE_GPIO, + .gpio55 = GPIO_MODE_GPIO, + .gpio56 = GPIO_MODE_NATIVE, + .gpio57 = GPIO_MODE_GPIO, + .gpio58 = GPIO_MODE_NATIVE, + .gpio59 = GPIO_MODE_NATIVE, + .gpio60 = GPIO_MODE_GPIO, + .gpio61 = GPIO_MODE_GPIO, + .gpio62 = GPIO_MODE_NATIVE, + .gpio63 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_direction = { + .gpio33 = GPIO_DIR_OUTPUT, + .gpio34 = GPIO_DIR_INPUT, + .gpio35 = GPIO_DIR_OUTPUT, + .gpio37 = GPIO_DIR_OUTPUT, + .gpio38 = GPIO_DIR_INPUT, + .gpio39 = GPIO_DIR_INPUT, + .gpio44 = GPIO_DIR_INPUT, + .gpio46 = GPIO_DIR_INPUT, + .gpio48 = GPIO_DIR_INPUT, + .gpio49 = GPIO_DIR_OUTPUT, + .gpio50 = GPIO_DIR_INPUT, + .gpio51 = GPIO_DIR_INPUT, + .gpio52 = GPIO_DIR_INPUT, + .gpio53 = GPIO_DIR_OUTPUT, + .gpio54 = GPIO_DIR_INPUT, + .gpio55 = GPIO_DIR_INPUT, + .gpio57 = GPIO_DIR_OUTPUT, + .gpio60 = GPIO_DIR_OUTPUT, + .gpio61 = GPIO_DIR_OUTPUT, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_level = { + .gpio33 = GPIO_LEVEL_LOW, + .gpio35 = GPIO_LEVEL_LOW, + .gpio37 = GPIO_LEVEL_LOW, + .gpio49 = GPIO_LEVEL_LOW, + .gpio53 = GPIO_LEVEL_HIGH, + .gpio57 = GPIO_LEVEL_HIGH, + .gpio60 = GPIO_LEVEL_HIGH, + .gpio61 = GPIO_LEVEL_HIGH, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_reset = { +}; + +static const struct pch_gpio_set3 pch_gpio_set3_mode = { + .gpio64 = GPIO_MODE_NATIVE, + .gpio65 = GPIO_MODE_NATIVE, + .gpio66 = GPIO_MODE_NATIVE, + .gpio67 = GPIO_MODE_NATIVE, + .gpio68 = GPIO_MODE_GPIO, + .gpio69 = GPIO_MODE_GPIO, + .gpio70 = GPIO_MODE_GPIO, + .gpio71 = GPIO_MODE_GPIO, + .gpio72 = GPIO_MODE_GPIO, + .gpio73 = GPIO_MODE_GPIO, + .gpio74 = GPIO_MODE_GPIO, + .gpio75 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_direction = { + .gpio68 = GPIO_DIR_OUTPUT, + .gpio69 = GPIO_DIR_INPUT, + .gpio70 = GPIO_DIR_OUTPUT, + .gpio71 = GPIO_DIR_OUTPUT, + .gpio72 = GPIO_DIR_OUTPUT, + .gpio73 = GPIO_DIR_OUTPUT, + .gpio74 = GPIO_DIR_OUTPUT, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_level = { + .gpio68 = GPIO_LEVEL_HIGH, + .gpio70 = GPIO_LEVEL_HIGH, + .gpio71 = GPIO_LEVEL_HIGH, + .gpio72 = GPIO_LEVEL_LOW, + .gpio73 = GPIO_LEVEL_HIGH, + .gpio74 = GPIO_LEVEL_HIGH, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_reset = { +}; + +const struct pch_gpio_map mainboard_gpio_map = { + .set1 = { + .mode = &pch_gpio_set1_mode, + .direction = &pch_gpio_set1_direction, + .level = &pch_gpio_set1_level, + .blink = &pch_gpio_set1_blink, + .invert = &pch_gpio_set1_invert, + .reset = &pch_gpio_set1_reset, + }, + .set2 = { + .mode = &pch_gpio_set2_mode, + .direction = &pch_gpio_set2_direction, + .level = &pch_gpio_set2_level, + .reset = &pch_gpio_set2_reset, + }, + .set3 = { + .mode = &pch_gpio_set3_mode, + .direction = &pch_gpio_set3_direction, + .level = &pch_gpio_set3_level, + .reset = &pch_gpio_set3_reset, + }, +}; diff --git a/src/mainboard/hp/snb_ivb_laptops/variants/8560w/hda_verb.c b/src/mainboard/hp/snb_ivb_laptops/variants/8560w/hda_verb.c new file mode 100644 index 0000000..2f5469f --- /dev/null +++ b/src/mainboard/hp/snb_ivb_laptops/variants/8560w/hda_verb.c @@ -0,0 +1,25 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <device/azalia_device.h> + +const u32 cim_verb_data[] = { + 0x111d7605, /* Codec Vendor / Device ID: IDT */ + 0x103c1631, /* Subsystem ID */ + + 11, /* Number of 4 dword sets */ + AZALIA_SUBVENDOR(0, 0x103c1631), + AZALIA_PIN_CFG(0, 0x0a, 0x40f000f0), + AZALIA_PIN_CFG(0, 0x0b, 0x0421401f), + AZALIA_PIN_CFG(0, 0x0c, 0x04a11020), + AZALIA_PIN_CFG(0, 0x0d, 0x90170110), + AZALIA_PIN_CFG(0, 0x0e, 0x40f000f0), + AZALIA_PIN_CFG(0, 0x0f, 0x40f000f0), + AZALIA_PIN_CFG(0, 0x10, 0x40f000f0), + AZALIA_PIN_CFG(0, 0x11, 0x90a60130), + AZALIA_PIN_CFG(0, 0x1f, 0x40f000f0), + AZALIA_PIN_CFG(0, 0x20, 0x40f000f0), +}; + +const u32 pc_beep_verbs[0] = {}; + +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/hp/snb_ivb_laptops/variants/8560w/mxm.bin b/src/mainboard/hp/snb_ivb_laptops/variants/8560w/mxm.bin new file mode 100644 index 0000000..7e4e245 --- /dev/null +++ b/src/mainboard/hp/snb_ivb_laptops/variants/8560w/mxm.bin Binary files differ diff --git a/src/mainboard/hp/snb_ivb_laptops/variants/8560w/overridetree.cb b/src/mainboard/hp/snb_ivb_laptops/variants/8560w/overridetree.cb new file mode 100644 index 0000000..ed19d3f --- /dev/null +++ b/src/mainboard/hp/snb_ivb_laptops/variants/8560w/overridetree.cb @@ -0,0 +1,68 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +chip northbridge/intel/sandybridge + register "spd_addresses" = "{0x50, 0x51, 0x52, 0x53}" + device domain 0 on + subsystemid 0x103c 0x1631 inherit + device pci 01.0 on end # PCIe Bridge for discrete graphics + device pci 02.0 off end # Internal graphics + + chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH + register "docking_supported" = "0" + register "gen1_dec" = "0x007c0201" + register "gen2_dec" = "0x000c0101" + register "gen3_dec" = "0x00fcfe01" + register "gen4_dec" = "0x000402e9" + register "gpi6_routing" = "2" + register "pcie_hotplug_map" = "{ 0, 1, 1, 0, 0, 0, 0, 0 }" + # HDD(0), ODD(1), eSATA(4) + register "sata_port_map" = "0x3b" + + register "usb_port_config" = "{ + { 1, 1, 0 }, /* USB0 */ + { 1, 1, 0 }, /* USB1 */ + { 1, 1, 1 }, /* eSATA */ + { 1, 1, 1 }, /* camera */ + { 0, 0, 2 }, + { 1, 0, 2 }, /* bluetooth */ + { 0, 0, 3 }, + { 1, 0, 3 }, + { 0, 1, 4 }, + { 1, 1, 4 }, /* WWAN */ + { 1, 0, 5 }, + { 1, 0, 5 }, /* dock */ + { 1, 0, 6 }, + { 1, 0, 6 }, + }" + + device pci 1c.0 on end # PCIe Port #1, WWAN + device pci 1c.1 on end # PCIe Port #2, ExpressCard + device pci 1c.2 on end # PCIe Port #3, SD/MMC + device pci 1c.3 on end # PCIe Port #4, WLAN + device pci 1c.4 off end # PCIe Port #5 + device pci 1c.5 off end # PCIe Port #6 + device pci 1c.6 off end # PCIe Port #7 + device pci 1c.7 on end # PCIe Port #8, NEC USB 3.0 Host Controller + device pci 1f.0 on # LPC bridge + chip ec/hp/kbc1126 + register "ec_data_port" = "0x60" + register "ec_cmd_port" = "0x64" + register "ec_ctrl_reg" = "0xca" + register "ec_fan_ctrl_value" = "0x6b" + device pnp ff.1 off end + end + chip superio/smsc/lpc47n217 + device pnp 4e.3 on # Parallel + io 0x60 = 0x378 + irq 0x70 = 7 + end + device pnp 4e.4 on # COM1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 4e.5 off end # COM2 + end + end + end + end +end
9elements QA has posted comments on this change by Iru Cai. ( https://review.coreboot.org/c/coreboot/+/39398?usp=email )
Change subject: mb/hp: Add Elitebook 8560w as an HP Sandy/Ivy Bridge laptop variant ......................................................................
Patch Set 9:
Automatic boot test returned (PASS/FAIL/TOTAL): 11 / 1 / 12
PASS: x86_32 "Hermes CFL" , build config PRODRIVE_HERMES_ and payload TianoCore_UefiPayloadPkg : https://lava.9esec.io/r/210929 PASS: x86_32 "Hermes CFL" , build config PRODRIVE_HERMES and payload TianoCore_UefiPayloadPkg : https://lava.9esec.io/r/210927 PASS: x86_32 "ThinkPad T500" , build config LENOVO_T500 and payload SeaBIOS : https://lava.9esec.io/r/210926 PASS: x86_32 "HP Z220 SFF Workstation" , build config HP_Z220_SFF_WORKSTATION and payload LinuxBoot_BB_kexec : https://lava.9esec.io/r/210925 PASS: x86_64 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC.X86_64 and payload TianoCore : https://lava.9esec.io/r/210924 PASS: x86_64 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC.X86_64 and payload SeaBIOS : https://lava.9esec.io/r/210923 PASS: x86_32 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC and payload TianoCore : https://lava.9esec.io/r/210922 PASS: x86_32 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC and payload SeaBIOS : https://lava.9esec.io/r/210921 PASS: x86_64 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_X86_64 and payload SeaBIOS : https://lava.9esec.io/r/210920 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_ASAN and payload SeaBIOS : https://lava.9esec.io/r/210919 FAIL: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_ and payload SeaBIOS : https://lava.9esec.io/r/210918 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX and payload SeaBIOS : https://lava.9esec.io/r/210917
Please note: This test is under development and might not be accurate at all!
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9elements QA (Code Review) -
Angel Pons (Code Review)
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Felix Singer (Code Review)
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Iru Cai (Code Review)
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Iru Cai (vimacs) (Code Review)
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Riku Viitanen (Code Review)