Ravishankar Sarawadi has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44748 )
Change subject: [WIP]mb/volteer: Remove DQ/DQS mappings for LPDDR4 ......................................................................
[WIP]mb/volteer: Remove DQ/DQS mappings for LPDDR4
MRC v incorporates algorithm which finds the Dq mapping between CPU and DRAM by using CPGC to issue reads and and walking through setting each bit and reading it back through datatrainfeedback.
Only LPDDR4 will be enabling this function at this time.
Signed-off-by: Ravi Sarawadi ravishankar.sarawadi@intel.com Change-Id: I70da3d482385fe6b1ccf071af8d8bd8e44d898ca --- M src/mainboard/google/volteer/variants/baseboard/memory.c M src/mainboard/google/volteer/variants/delbin/memory.c M src/mainboard/google/volteer/variants/halvor/memory.c M src/mainboard/google/volteer/variants/malefor/memory.c M src/mainboard/google/volteer/variants/terrador/memory.c M src/mainboard/google/volteer/variants/todor/memory.c M src/mainboard/google/volteer/variants/voxel/memory.c M src/soc/intel/tigerlake/include/soc/meminit.h M src/soc/intel/tigerlake/meminit.c 9 files changed, 0 insertions(+), 565 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/44748/1
diff --git a/src/mainboard/google/volteer/variants/baseboard/memory.c b/src/mainboard/google/volteer/variants/baseboard/memory.c index dafeb3b..910916b 100644 --- a/src/mainboard/google/volteer/variants/baseboard/memory.c +++ b/src/mainboard/google/volteer/variants/baseboard/memory.c @@ -5,54 +5,6 @@ #include <gpio.h>
static const struct lpddr4x_cfg baseboard_lpddr4x_memcfg = { - /* DQ CPU<>DRAM map */ - .dq_map = { - [0] = { - { 0, 1, 2, 3, 4, 5, 6, 7, }, /* DDR0_DQ0[7:0] */ - { 12, 13, 14, 15, 11, 10, 9, 8, }, /* DDR0_DQ1[7:0] */ - }, - [1] = { - { 7, 2, 6, 3, 5, 1, 4, 0, }, /* DDR1_DQ0[7:0] */ - { 10, 8, 9, 11, 15, 12, 14, 13, }, /* DDR1_DQ1[7:0] */ - }, - [2] = { - { 3, 2, 1, 0, 4, 5, 6, 7, }, /* DDR2_DQ0[7:0] */ - { 12, 13, 14, 15, 11, 10, 9, 8, }, /* DDR2_DQ1[7:0] */ - }, - [3] = { - { 7, 0, 1, 6, 5, 4, 2, 3, }, /* DDR3_DQ0[7:0] */ - { 15, 14, 8, 9, 10, 12, 11, 13, }, /* DDR3_DQ1[7:0] */ - }, - [4] = { - { 3, 2, 1, 0, 4, 5, 6, 7, }, /* DDR4_DQ0[7:0] */ - { 12, 13, 14, 15, 11, 10, 9, 8, }, /* DDR4_DQ1[7:0] */ - }, - [5] = { - { 3, 4, 2, 5, 0, 6, 1, 7, }, /* DDR5_DQ0[7:0] */ - { 13, 12, 11, 10, 14, 15, 9, 8, }, /* DDR5_DQ1[7:0] */ - }, - [6] = { - { 3, 2, 1, 0, 7, 4, 5, 6, }, /* DDR6_DQ0[7:0] */ - { 15, 14, 13, 12, 8, 9, 10, 11, }, /* DDR6_DQ1[7:0] */ - }, - [7] = { - { 3, 4, 2, 5, 1, 0, 7, 6, }, /* DDR7_DQ0[7:0] */ - { 15, 14, 9, 8, 12, 10, 11, 13, }, /* DDR7_DQ1[7:0] */ - }, - }, - - /* DQS CPU<>DRAM map */ - .dqs_map = { - [0] = { 0, 1 }, /* DDR0_DQS[1:0] */ - [1] = { 0, 1 }, /* DDR1_DQS[1:0] */ - [2] = { 0, 1 }, /* DDR2_DQS[1:0] */ - [3] = { 0, 1 }, /* DDR3_DQS[1:0] */ - [4] = { 0, 1 }, /* DDR4_DQS[1:0] */ - [5] = { 0, 1 }, /* DDR5_DQS[1:0] */ - [6] = { 0, 1 }, /* DDR6_DQS[1:0] */ - [7] = { 0, 1 }, /* DDR7_DQS[1:0] */ - }, - .ect = 1, /* Enable Early Command Training */ };
diff --git a/src/mainboard/google/volteer/variants/delbin/memory.c b/src/mainboard/google/volteer/variants/delbin/memory.c index 9d8ad40..1f93c38 100644 --- a/src/mainboard/google/volteer/variants/delbin/memory.c +++ b/src/mainboard/google/volteer/variants/delbin/memory.c @@ -3,54 +3,6 @@ #include <baseboard/variants.h>
static const struct lpddr4x_cfg delbin_memcfg = { - /* DQ byte map */ - .dq_map = { - [0] = { - { 3, 2, 1, 0, 4, 5, 7, 6, }, /* DDR0_DQ0[7:0] */ - { 12, 13, 14, 15, 11, 10, 9, 8 }, /* DDR0_DQ1[7:0] */ - }, - [1] = { - { 0, 7, 1, 6, 2, 5, 3, 4, }, /* DDR1_DQ0[7:0] */ - { 8, 15, 14, 9, 12, 10, 13, 11 }, /* DDR1_DQ1[7:0] */ - }, - [2] = { - { 2, 3, 0, 1, 4, 5, 6, 7, }, /* DDR2_DQ0[7:0] */ - { 12, 13, 15, 14, 11, 10, 9, 8 }, /* DDR2_DQ1[7:0] */ - }, - [3] = { - { 7, 0, 1, 6, 5, 4, 2, 3, }, /* DDR3_DQ0[7:0] */ - { 15, 14, 8, 9, 10, 13, 11, 12 }, /* DDR3_DQ1[7:0] */ - }, - [4] = { - { 4, 5, 2, 3, 7, 6, 0, 1, }, /* DDR4_DQ0[7:0] */ - { 12, 13, 15, 14, 11, 10, 8, 9 }, /* DDR4_DQ1[7:0] */ - }, - [5] = { - { 3, 4, 2, 5, 0, 6, 1, 7, }, /* DDR5_DQ0[7:0] */ - { 12, 13, 11, 10, 14, 15, 9, 8 }, /* DDR5_DQ1[7:0] */ - }, - [6] = { - { 3, 2, 1, 0, 7, 4, 5, 6, }, /* DDR6_DQ0[7:0] */ - { 15, 14, 13, 12, 8, 9, 10, 11 }, /* DDR6_DQ1[7:0] */ - }, - [7] = { - { 2, 4, 3, 5, 1, 0, 7, 6, }, /* DDR7_DQ0[7:0] */ - { 14, 15, 9, 8, 12, 10, 11, 13 }, /* DDR7_DQ1[7:0] */ - }, - }, - - /* DQS CPU<>DRAM map */ - .dqs_map = { - [0] = { 0, 1 }, /* DDR0_DQS[1:0] */ - [1] = { 0, 1 }, /* DDR1_DQS[1:0] */ - [2] = { 0, 1 }, /* DDR2_DQS[1:0] */ - [3] = { 0, 1 }, /* DDR3_DQS[1:0] */ - [4] = { 0, 1 }, /* DDR4_DQS[1:0] */ - [5] = { 0, 1 }, /* DDR5_DQS[1:0] */ - [6] = { 0, 1 }, /* DDR6_DQS[1:0] */ - [7] = { 0, 1 }, /* DDR7_DQS[1:0] */ - }, - .ect = 1, /* Enable Early Command Training */ };
diff --git a/src/mainboard/google/volteer/variants/halvor/memory.c b/src/mainboard/google/volteer/variants/halvor/memory.c index edbb681..cb0bbbae 100644 --- a/src/mainboard/google/volteer/variants/halvor/memory.c +++ b/src/mainboard/google/volteer/variants/halvor/memory.c @@ -3,54 +3,6 @@ #include <baseboard/variants.h>
static const struct lpddr4x_cfg halvor_memcfg = { - /* DQ byte map */ - .dq_map = { - [0] = { - { 10, 12, 13, 9, 11, 8, 15, 14,}, /* DDR0_DQ0[7:0] */ - { 3, 0, 1, 5, 4, 7, 6, 2 }, /* DDR0_DQ1[7:0] */ - }, - [1] = { - { 8, 10, 13, 9, 12, 15, 11, 14, }, /* DDR1_DQ0[7:0] */ - { 3, 5, 7, 2, 1, 0, 4, 6 }, /* DDR1_DQ1[7:0] */ - }, - [2] = { - { 1, 3, 0, 2, 5, 4, 7, 6, }, /* DDR2_DQ0[7:0] */ - { 15, 14, 12, 13, 8, 9, 10, 11 }, /* DDR2_DQ1[7:0] */ - }, - [3] = { - { 8, 9, 10, 11, 14, 12, 15, 13, }, /* DDR3_DQ0[7:0] */ - { 5, 6, 7, 4, 2, 3, 1, 0 }, /* DDR3_DQ1[7:0] */ - }, - [4] = { - { 9, 8, 10, 11, 12, 13, 14, 15, }, /* DDR4_DQ0[7:0] */ - { 6, 7, 4, 5, 0, 2, 1, 3 }, /* DDR4_DQ1[7:0] */ - }, - [5] = { - { 0, 1, 3, 2, 7, 4, 5, 6, }, /* DDR5_DQ0[7:0] */ - { 15, 14, 9, 12, 8, 13, 11, 10 }, /* DDR5_DQ1[7:0] */ - }, - [6] = { - { 7, 5, 3, 6, 1, 0, 4, 2, }, /* DDR6_DQ0[7:0] */ - { 12, 14, 15, 13, 8, 11, 9, 10 }, /* DDR6_DQ1[7:0] */ - }, - [7] = { - { 3, 7, 1, 6, 5, 4, 2, 0, }, /* DDR7_DQ0[7:0] */ - { 12, 11, 8, 14, 10, 9, 15, 13 }, /* DDR7_DQ1[7:0] */ - }, - }, - - /* DQS CPU<>DRAM map */ - .dqs_map = { - [0] = { 1, 0 }, /* DDR0_DQS[1:0] */ - [1] = { 1, 0 }, /* DDR1_DQS[1:0] */ - [2] = { 0, 1 }, /* DDR2_DQS[1:0] */ - [3] = { 1, 0 }, /* DDR3_DQS[1:0] */ - [4] = { 1, 0 }, /* DDR4_DQS[1:0] */ - [5] = { 0, 1 }, /* DDR5_DQS[1:0] */ - [6] = { 0, 1 }, /* DDR6_DQS[1:0] */ - [7] = { 0, 1 }, /* DDR7_DQS[1:0] */ - }, - .ect = 1, /* Enable Early Command Training */ };
diff --git a/src/mainboard/google/volteer/variants/malefor/memory.c b/src/mainboard/google/volteer/variants/malefor/memory.c index 2c879e0..b1ade9e 100644 --- a/src/mainboard/google/volteer/variants/malefor/memory.c +++ b/src/mainboard/google/volteer/variants/malefor/memory.c @@ -3,54 +3,6 @@ #include <baseboard/variants.h>
static const struct lpddr4x_cfg malefor_memcfg = { - /* DQ byte map */ - .dq_map = { - [0] = { - { 3, 1, 0, 2, 4, 6, 7, 5, }, /* DDR0_DQ0[7:0] */ - { 12, 13, 14, 15, 8, 9, 10, 11 }, /* DDR0_DQ1[7:0] */ - }, - [1] = { - { 0, 7, 1, 6, 2, 4, 3, 5, }, /* DDR1_DQ0[7:0] */ - { 8, 15, 14, 9, 13, 10, 12, 11 }, /* DDR1_DQ1[7:0] */ - }, - [2] = { - { 3, 2, 0, 1, 4, 5, 6, 7, }, /* DDR2_DQ0[7:0] */ - { 12, 13, 15, 14, 8, 9, 10, 11 }, /* DDR2_DQ1[7:0] */ - }, - [3] = { - { 6, 0, 1, 7, 5, 4, 2, 3, }, /* DDR3_DQ0[7:0] */ - { 15, 14, 8, 9, 10, 12, 11, 13 }, /* DDR3_DQ1[7:0] */ - }, - [4] = { - { 5, 0, 1, 3, 4, 2, 7, 6, }, /* DDR4_DQ0[7:0] */ - { 11, 14, 13, 12, 8, 9, 15, 10 }, /* DDR4_DQ1[7:0] */ - }, - [5] = { - { 3, 4, 2, 5, 0, 6, 1, 7, }, /* DDR5_DQ0[7:0] */ - { 13, 12, 11, 10, 14, 15, 9, 8 }, /* DDR5_DQ1[7:0] */ - }, - [6] = { - { 3, 2, 1, 0, 5, 4, 7, 6, }, /* DDR6_DQ0[7:0] */ - { 12, 13, 15, 14, 8, 11, 9, 10 }, /* DDR6_DQ1[7:0] */ - }, - [7] = { - { 3, 4, 2, 5, 1, 0, 7, 6, }, /* DDR7_DQ0[7:0] */ - { 15, 14, 9, 8, 12, 10, 11, 13 }, /* DDR7_DQ1[7:0] */ - }, - }, - - /* DQS CPU<>DRAM map */ - .dqs_map = { - [0] = { 0, 1 }, /* DDR0_DQS[1:0] */ - [1] = { 0, 1 }, /* DDR1_DQS[1:0] */ - [2] = { 0, 1 }, /* DDR2_DQS[1:0] */ - [3] = { 0, 1 }, /* DDR3_DQS[1:0] */ - [4] = { 0, 1 }, /* DDR4_DQS[1:0] */ - [5] = { 0, 1 }, /* DDR5_DQS[1:0] */ - [6] = { 0, 1 }, /* DDR6_DQS[1:0] */ - [7] = { 0, 1 }, /* DDR7_DQS[1:0] */ - }, - .ect = 1, /* Enable Early Command Training */ };
diff --git a/src/mainboard/google/volteer/variants/terrador/memory.c b/src/mainboard/google/volteer/variants/terrador/memory.c index 7d95658..a8f5ea8 100644 --- a/src/mainboard/google/volteer/variants/terrador/memory.c +++ b/src/mainboard/google/volteer/variants/terrador/memory.c @@ -3,54 +3,6 @@ #include <baseboard/variants.h>
static const struct lpddr4x_cfg terrador_memcfg = { - /* DQ byte map */ - .dq_map = { - [0] = { - { 7, 3, 1, 4, 0, 5, 2, 6, }, /* DDR0_DQ0[7:0] */ - { 13, 14, 8, 10, 9, 15, 11, 12 }, /* DDR0_DQ1[7:0] */ - }, - [1] = { - { 1, 2, 7, 6, 3, 5, 4, 0, }, /* DDR1_DQ0[7:0] */ - { 14, 15, 13, 10, 8, 11, 12, 9 }, /* DDR1_DQ1[7:0] */ - }, - [2] = { - { 11, 15, 10, 9, 8, 12, 13, 14, }, /* DDR2_DQ0[7:0] */ - { 5, 6, 4, 0, 7, 2, 3, 1 }, /* DDR2_DQ1[7:0] */ - }, - [3] = { - { 11, 15, 10, 9, 13, 12, 14, 8, }, /* DDR3_DQ0[7:0] */ - { 0, 5, 6, 4, 1, 2, 7, 3 }, /* DDR3_DQ1[7:0] */ - }, - [4] = { - { 7, 2, 3, 1, 4, 0, 5, 6, }, /* DDR4_DQ0[7:0] */ - { 13, 14, 8, 12, 10, 9, 15, 11 }, /* DDR4_DQ1[7:0] */ - }, - [5] = { - { 7, 3, 2, 1, 6, 4, 0, 5, }, /* DDR5_DQ0[7:0] */ - { 15, 14, 12, 8, 11, 13, 9, 10 }, /* DDR5_DQ1[7:0] */ - }, - [6] = { - { 11, 10, 15, 12, 8, 9, 14, 13, }, /* DDR6_DQ0[7:0] */ - { 6, 0, 5, 4, 3, 2, 7, 1 }, /* DDR6_DQ1[7:0] */ - }, - [7] = { - { 9, 10, 11, 8, 12, 14, 13, 15, }, /* DDR7_DQ0[7:0] */ - { 0, 5, 4, 7, 1, 6, 3, 2 }, /* DDR7_DQ1[7:0] */ - }, - }, - - /* DQS CPU<>DRAM map */ - .dqs_map = { - [0] = { 0, 1 }, /* DDR0_DQS[1:0] */ - [1] = { 0, 1 }, /* DDR1_DQS[1:0] */ - [2] = { 1, 0 }, /* DDR2_DQS[1:0] */ - [3] = { 1, 0 }, /* DDR3_DQS[1:0] */ - [4] = { 0, 1 }, /* DDR4_DQS[1:0] */ - [5] = { 0, 1 }, /* DDR5_DQS[1:0] */ - [6] = { 1, 0 }, /* DDR6_DQS[1:0] */ - [7] = { 1, 0 }, /* DDR7_DQS[1:0] */ - }, - .ect = 1, /* Enable Early Command Training */ };
diff --git a/src/mainboard/google/volteer/variants/todor/memory.c b/src/mainboard/google/volteer/variants/todor/memory.c index c8b4ab4..e61f3b8 100644 --- a/src/mainboard/google/volteer/variants/todor/memory.c +++ b/src/mainboard/google/volteer/variants/todor/memory.c @@ -3,54 +3,6 @@ #include <baseboard/variants.h>
static const struct lpddr4x_cfg todor_memcfg = { - /* DQ byte map */ - .dq_map = { - [0] = { - { 7, 3, 1, 4, 0, 5, 2, 6, }, /* DDR0_DQ0[7:0] */ - { 13, 14, 8, 10, 9, 15, 11, 12 }, /* DDR0_DQ1[7:0] */ - }, - [1] = { - { 1, 2, 7, 6, 3, 5, 4, 0, }, /* DDR1_DQ0[7:0] */ - { 14, 15, 13, 10, 8, 11, 12, 9 }, /* DDR1_DQ1[7:0] */ - }, - [2] = { - { 11, 15, 10, 9, 8, 12, 13, 14, }, /* DDR2_DQ0[7:0] */ - { 5, 6, 4, 0, 7, 2, 3, 1 }, /* DDR2_DQ1[7:0] */ - }, - [3] = { - { 11, 15, 10, 9, 13, 12, 14, 8, }, /* DDR3_DQ0[7:0] */ - { 0, 5, 6, 4, 1, 2, 7, 3 }, /* DDR3_DQ1[7:0] */ - }, - [4] = { - { 7, 2, 3, 1, 4, 0, 5, 6, }, /* DDR4_DQ0[7:0] */ - { 13, 14, 8, 12, 10, 9, 15, 11 }, /* DDR4_DQ1[7:0] */ - }, - [5] = { - { 7, 3, 2, 1, 6, 4, 0, 5, }, /* DDR5_DQ0[7:0] */ - { 15, 14, 12, 8, 11, 13, 9, 10 }, /* DDR5_DQ1[7:0] */ - }, - [6] = { - { 11, 10, 15, 12, 8, 9, 14, 13, }, /* DDR6_DQ0[7:0] */ - { 6, 0, 5, 4, 3, 2, 7, 1 }, /* DDR6_DQ1[7:0] */ - }, - [7] = { - { 9, 10, 11, 8, 12, 14, 13, 15, }, /* DDR7_DQ0[7:0] */ - { 0, 5, 4, 7, 1, 6, 3, 2 }, /* DDR7_DQ1[7:0] */ - }, - }, - - /* DQS CPU<>DRAM map */ - .dqs_map = { - [0] = { 0, 1 }, /* DDR0_DQS[1:0] */ - [1] = { 0, 1 }, /* DDR1_DQS[1:0] */ - [2] = { 1, 0 }, /* DDR2_DQS[1:0] */ - [3] = { 1, 0 }, /* DDR3_DQS[1:0] */ - [4] = { 0, 1 }, /* DDR4_DQS[1:0] */ - [5] = { 0, 1 }, /* DDR5_DQS[1:0] */ - [6] = { 1, 0 }, /* DDR6_DQS[1:0] */ - [7] = { 1, 0 }, /* DDR7_DQS[1:0] */ - }, - .ect = 1, /* Enable Early Command Training */ };
diff --git a/src/mainboard/google/volteer/variants/voxel/memory.c b/src/mainboard/google/volteer/variants/voxel/memory.c index 40b1086..a028ab7 100644 --- a/src/mainboard/google/volteer/variants/voxel/memory.c +++ b/src/mainboard/google/volteer/variants/voxel/memory.c @@ -3,54 +3,6 @@ #include <baseboard/variants.h>
static const struct lpddr4x_cfg voxel_memcfg = { - /* DQ byte map */ - .dq_map = { - [0] = { - { 3, 0, 1, 2, 6, 7, 5, 4, }, /* DDR0_DQ0[7:0] */ - { 12, 15, 14, 13, 8, 9, 10, 11 }, /* DDR0_DQ1[7:0] */ - }, - [1] = { - { 12, 15, 13, 14, 10, 8, 11, 9, }, /* DDR1_DQ0[7:0] */ - { 5, 6, 7, 4, 0, 3, 1, 2 }, /* DDR1_DQ1[7:0] */ - }, - [2] = { - { 2, 3, 0, 1, 7, 6, 5, 4, }, /* DDR2_DQ0[7:0] */ - { 12, 14, 15, 13, 10, 9, 8, 11 }, /* DDR2_DQ1[7:0] */ - }, - [3] = { - { 15, 12, 13, 14, 8, 9, 10, 11, }, /* DDR3_DQ0[7:0] */ - { 7, 6, 4, 5, 2, 0, 3, 1 }, /* DDR3_DQ1[7:0] */ - }, - [4] = { - { 6, 5, 4, 7, 0, 3, 2, 1, }, /* DDR4_DQ0[7:0] */ - { 15, 14, 13, 12, 11, 8, 9, 10 }, /* DDR4_DQ1[7:0] */ - }, - [5] = { - { 11, 9, 10, 8, 12, 14, 13, 15, }, /* DDR5_DQ0[7:0] */ - { 1, 0, 2, 3, 6, 7, 5, 4 }, /* DDR5_DQ1[7:0] */ - }, - [6] = { - { 2, 3, 0, 1, 5, 4, 6, 7, }, /* DDR6_DQ0[7:0] */ - { 13, 14, 15, 12, 11, 10, 8, 9 }, /* DDR6_DQ1[7:0] */ - }, - [7] = { - { 14, 13, 15, 12, 9, 8, 10, 11, }, /* DDR7_DQ0[7:0] */ - { 4, 5, 1, 2, 6, 0, 3, 7 }, /* DDR7_DQ1[7:0] */ - }, - }, - - /* DQS CPU<>DRAM map */ - .dqs_map = { - [0] = { 0, 1 }, /* DDR0_DQS[1:0] */ - [1] = { 1, 0 }, /* DDR1_DQS[1:0] */ - [2] = { 0, 1 }, /* DDR2_DQS[1:0] */ - [3] = { 1, 0 }, /* DDR3_DQS[1:0] */ - [4] = { 0, 1 }, /* DDR4_DQS[1:0] */ - [5] = { 1, 0 }, /* DDR5_DQS[1:0] */ - [6] = { 0, 1 }, /* DDR6_DQS[1:0] */ - [7] = { 1, 0 }, /* DDR7_DQS[1:0] */ - }, - .ect = 1, /* Enable Early Command Training */ };
diff --git a/src/soc/intel/tigerlake/include/soc/meminit.h b/src/soc/intel/tigerlake/include/soc/meminit.h index 4a52298..a9bf918 100644 --- a/src/soc/intel/tigerlake/include/soc/meminit.h +++ b/src/soc/intel/tigerlake/include/soc/meminit.h @@ -64,30 +64,6 @@ /* Board-specific memory configuration information */ struct lpddr4x_cfg { /* - * DQ CPU<>DRAM map: - * LPDDR4x memory interface has 2 DQs per channel. Each DQ consists of 8 bits(1 - * byte). Thus, dq_map is represented as DDR[7-0]_DQ[1-0][7:0], where - * DDR[7-0] : LPDDR4x channel # - * DQ[1-0] : DQ # within the channel - * [7:0] : Bits within the DQ - * - * Index of the array represents DQ pin# on the CPU, whereas value in - * the array represents DQ pin# on the memory part. - */ - uint8_t dq_map[LPDDR4X_CHANNELS][LPDDR4X_BYTES_PER_CHANNEL][BITS_PER_BYTE]; - - /* - * DQS CPU<>DRAM map: - * LPDDR4x memory interface has 2 DQS pairs(P/N) per channel. Thus, dqs_map is - * represented as DDR[7-0]_DQS[1:0], where - * DDR[7-0] : LPDDR4x channel # - * DQS[1-0] : DQS # within the channel - * - * Index of the array represents DQS pin# on the CPU, whereas value in - * the array represents DQ pin# on the memory part. - */ - uint8_t dqs_map[LPDDR4X_CHANNELS][LPDDR4X_BYTES_PER_CHANNEL]; - /* * Early Command Training Enable/Disable Control * 1 = enable, 0 = disable */ @@ -97,29 +73,6 @@ /* Board-specific memory configuration information for DDR4 memory variant */ struct mb_ddr4_cfg { /* - * DQ CPU<>DRAM map: - * DDR4 memory interface has 8 DQs per channel. Each DQ consists of 8 bits(1 - * byte). Thus, dq_map is represented as DDR[1-0]_DQ[7-0][7:0], where - * DDR[1-0] : DDR4 channel # - * DQ[7-0] : DQ # within the channel - * [7:0] : Bits within the DQ - * - * Index of the array represents DQ pin# on the CPU, whereas value in - * the array represents DQ pin# on the memory part. - */ - uint8_t dq_map[DDR4_CHANNELS][DDR4_BYTES_PER_CHANNEL][BITS_PER_BYTE]; - /* - * DQS CPU<>DRAM map: - * DDR4 memory interface has 8 DQS pairs per channel. Thus, dqs_map is represented as - * DDR[1-0]_DQS[7-0], where - * DDR[1-0] : DDR4 channel # - * DQS[7-0] : DQS # within the channel - * - * Index of the array represents DQS pin# on the CPU, whereas value in - * the array represents DQS pin# on the memory part. - */ - uint8_t dqs_map[DDR4_CHANNELS][DDR4_BYTES_PER_CHANNEL]; - /* * Indicates whether memory is interleaved. * Set to 1 for an interleaved design, * set to 0 for non-interleaved design. diff --git a/src/soc/intel/tigerlake/meminit.c b/src/soc/intel/tigerlake/meminit.c index 0c6f0b0..7093d3d 100644 --- a/src/soc/intel/tigerlake/meminit.c +++ b/src/soc/intel/tigerlake/meminit.c @@ -109,96 +109,6 @@ init_spd_upds(mem_cfg, channel, spd_dimm0, 0); }
-static void init_dq_upds(FSP_M_CONFIG *mem_cfg, int byte_pair, const uint8_t *dq_byte0, - const uint8_t *dq_byte1) -{ - uint8_t *dq_upd; - - switch (byte_pair) { - case 0: - dq_upd = mem_cfg->DqMapCpu2DramCh0; - break; - case 1: - dq_upd = mem_cfg->DqMapCpu2DramCh1; - break; - case 2: - dq_upd = mem_cfg->DqMapCpu2DramCh2; - break; - case 3: - dq_upd = mem_cfg->DqMapCpu2DramCh3; - break; - case 4: - dq_upd = mem_cfg->DqMapCpu2DramCh4; - break; - case 5: - dq_upd = mem_cfg->DqMapCpu2DramCh5; - break; - case 6: - dq_upd = mem_cfg->DqMapCpu2DramCh6; - break; - case 7: - dq_upd = mem_cfg->DqMapCpu2DramCh7; - break; - default: - die("Invalid byte_pair: %d\n", byte_pair); - } - - if (dq_byte0 && dq_byte1) { - memcpy(dq_upd, dq_byte0, BITS_PER_BYTE); - memcpy(dq_upd + BITS_PER_BYTE, dq_byte1, BITS_PER_BYTE); - } else { - memset(dq_upd, 0, BITS_PER_BYTE * 2); - } -} - -static inline void init_dq_upds_empty(FSP_M_CONFIG *mem_cfg, int byte_pair) -{ - init_dq_upds(mem_cfg, byte_pair, NULL, NULL); -} - -static void init_dqs_upds(FSP_M_CONFIG *mem_cfg, int byte_pair, uint8_t dqs_byte0, - uint8_t dqs_byte1) -{ - uint8_t *dqs_upd; - - switch (byte_pair) { - case 0: - dqs_upd = mem_cfg->DqsMapCpu2DramCh0; - break; - case 1: - dqs_upd = mem_cfg->DqsMapCpu2DramCh1; - break; - case 2: - dqs_upd = mem_cfg->DqsMapCpu2DramCh2; - break; - case 3: - dqs_upd = mem_cfg->DqsMapCpu2DramCh3; - break; - case 4: - dqs_upd = mem_cfg->DqsMapCpu2DramCh4; - break; - case 5: - dqs_upd = mem_cfg->DqsMapCpu2DramCh5; - break; - case 6: - dqs_upd = mem_cfg->DqsMapCpu2DramCh6; - break; - case 7: - dqs_upd = mem_cfg->DqsMapCpu2DramCh7; - break; - default: - die("Invalid byte_pair: %d\n", byte_pair); - } - - dqs_upd[0] = dqs_byte0; - dqs_upd[1] = dqs_byte1; -} - -static inline void init_dqs_upds_empty(FSP_M_CONFIG *mem_cfg, int byte_pair) -{ - init_dqs_upds(mem_cfg, byte_pair, 0, 0); -} - static void read_spd_from_cbfs(uint8_t index, uintptr_t *data, size_t *len) { struct region_device spd_rdev; @@ -252,51 +162,6 @@ else init_spd_upds_dimm0(mem_cfg, i, spd_data); } - - /* - * LPDDR4x memory interface has 2 DQs per channel. Each DQ consists of 8 bits (1 - * byte). However, FSP UPDs for DQ Map expect a DQ pair (i.e. mapping for 2 bytes) in - * each UPD. - * - * Thus, init_dq_upds() needs to be called for dq pair of each channel. - * DqMapCpu2DramCh0 --> dq_map[CHAN=0][0-1] - * DqMapCpu2DramCh1 --> dq_map[CHAN=1][0-1] - * DqMapCpu2DramCh2 --> dq_map[CHAN=2][0-1] - * DqMapCpu2DramCh3 --> dq_map[CHAN=3][0-1] - * DqMapCpu2DramCh4 --> dq_map[CHAN=4][0-1] - * DqMapCpu2DramCh5 --> dq_map[CHAN=5][0-1] - * DqMapCpu2DramCh6 --> dq_map[CHAN=6][0-1] - * DqMapCpu2DramCh7 --> dq_map[CHAN=7][0-1] - */ - for (i = 0; i < LPDDR4X_CHANNELS; i++) { - if (LPDDR4X_CHANNEL_UNPOPULATED(i, half_populated)) - init_dq_upds_empty(mem_cfg, i); - else - init_dq_upds(mem_cfg, i, board_cfg->dq_map[i][0], - board_cfg->dq_map[i][1]); - } - - /* - * LPDDR4x memory interface has 2 DQS pairs per channel. FSP UPDs for DQS Map expect a - * pair in each UPD. - * - * Thus, init_dqs_upds() needs to be called for dqs pair of each channel. - * DqsMapCpu2DramCh0 --> dqs_map[CHAN=0][0-1] - * DqsMapCpu2DramCh1 --> dqs_map[CHAN=1][0-1] - * DqsMapCpu2DramCh2 --> dqs_map[CHAN=2][0-1] - * DqsMapCpu2DramCh3 --> dqs_map[CHAN=3][0-1] - * DqsMapCpu2DramCh4 --> dqs_map[CHAN=4][0-1] - * DqsMapCpu2DramCh5 --> dqs_map[CHAN=5][0-1] - * DqsMapCpu2DramCh6 --> dqs_map[CHAN=6][0-1] - * DqsMapCpu2DramCh7 --> dqs_map[CHAN=7][0-1] - */ - for (i = 0; i < LPDDR4X_CHANNELS; i++) { - if (LPDDR4X_CHANNEL_UNPOPULATED(i, half_populated)) - init_dqs_upds_empty(mem_cfg, i); - else - init_dqs_upds(mem_cfg, i, board_cfg->dqs_map[i][0], - board_cfg->dqs_map[i][1]); - } }
static void read_sodimm_spd(const struct spd_info *info, struct spd_block *blk) @@ -363,7 +228,6 @@ uintptr_t spd_dimm1 = 0; struct spd_block spd_sodimm_blk; unsigned int i; - unsigned int index = 0;
/* Early Command Training Enabled */ mem_cfg->ECT = board_cfg->ect; @@ -388,52 +252,6 @@ half_populated, &spd_dimm0, &spd_dimm1); init_spd_upds(mem_cfg, DDR4_FSP_UPD_CHANNEL_IDX(i), spd_dimm0, spd_dimm1); } - - /* - * DDR4 memory interface has 8 DQs per channel. Each DQ consists of 8 bits (1 - * byte). However, FSP UPDs for DQ Map expect a DQ pair (i.e. mapping for 2 bytes) in - * each UPD. - * - * Thus, init_dq_upds() needs to be called for every dq pair of each channel. - * DqMapCpu2DramCh0 --> dq_map[CHAN=0][0-1] - * DqMapCpu2DramCh1 --> dq_map[CHAN=0][2-3] - * DqMapCpu2DramCh2 --> dq_map[CHAN=0][4-5] - * DqMapCpu2DramCh3 --> dq_map[CHAN=0][6-7] - * DqMapCpu2DramCh4 --> dq_map[CHAN=1][0-1] - * DqMapCpu2DramCh5 --> dq_map[CHAN=1][2-3] - * DqMapCpu2DramCh6 --> dq_map[CHAN=1][4-5] - * DqMapCpu2DramCh7 --> dq_map[CHAN=1][6-7] - */ - - /* - * DDR4 memory interface has 8 DQS pairs per channel. FSP UPDs for DQS Map expect a - * pair in each UPD. - * - * Thus, init_dqs_upds() needs to be called for every dqs pair of each channel. - * DqsMapCpu2DramCh0 --> dqs_map[CHAN=0][0-1] - * DqsMapCpu2DramCh1 --> dqs_map[CHAN=0][2-3] - * DqsMapCpu2DramCh2 --> dqs_map[CHAN=0][4-5] - * DqsMapCpu2DramCh3 --> dqs_map[CHAN=0][6-7] - * DqsMapCpu2DramCh4 --> dqs_map[CHAN=1][0-1] - * DqsMapCpu2DramCh5 --> dqs_map[CHAN=1][2-3] - * DqsMapCpu2DramCh6 --> dqs_map[CHAN=1][4-5] - * DqsMapCpu2DramCh7 --> dqs_map[CHAN=1][6-7] - */ - - for (i = 0; i < DDR4_CHANNELS; i++) { - for (int b = 0; b < DDR4_BYTES_PER_CHANNEL; b += 2) { - if (half_populated && (i == 1)) { - init_dq_upds_empty(mem_cfg, index); - init_dqs_upds_empty(mem_cfg, index); - } else { - init_dq_upds(mem_cfg, index, board_cfg->dq_map[i][b], - board_cfg->dq_map[i][b+1]); - init_dqs_upds(mem_cfg, index, board_cfg->dqs_map[i][b], - board_cfg->dqs_map[i][b+1]); - } - index++; - } - } }
void meminit_ddr(FSP_M_CONFIG *mem_cfg, const struct ddr_memory_cfg *board_cfg,
Hello Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/44748
to look at the new patch set (#2).
Change subject: [WIP]mb/volteer: Remove DQ/DQS mappings for LPDDR4 ......................................................................
[WIP]mb/volteer: Remove DQ/DQS mappings for LPDDR4
MRC v0.7.0 incorporates algorithm which finds the Dq mapping between CPU and DRAM by using CPGC to issue reads and and walking through setting each bit and reading it back through datatrainfeedback.
Only LPDDR4 will be enabling this function at this time.
Signed-off-by: Ravi Sarawadi ravishankar.sarawadi@intel.com Change-Id: I70da3d482385fe6b1ccf071af8d8bd8e44d898ca --- M src/mainboard/google/volteer/variants/baseboard/memory.c M src/mainboard/google/volteer/variants/delbin/memory.c M src/mainboard/google/volteer/variants/halvor/memory.c M src/mainboard/google/volteer/variants/malefor/memory.c M src/mainboard/google/volteer/variants/terrador/memory.c M src/mainboard/google/volteer/variants/todor/memory.c M src/mainboard/google/volteer/variants/voxel/memory.c M src/soc/intel/tigerlake/include/soc/meminit.h M src/soc/intel/tigerlake/meminit.c 9 files changed, 0 insertions(+), 565 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/44748/2
Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44748 )
Change subject: [WIP]mb/volteer: Remove DQ/DQS mappings for LPDDR4 ......................................................................
Patch Set 2:
a
Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44748 )
Change subject: [WIP]mb/volteer: Remove DQ/DQS mappings for LPDDR4 ......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/c/coreboot/+/44748/2//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/44748/2//COMMIT_MSG@9 PS2, Line 9: MRC v0.7.0 Where can the version numbers be found?
Ravishankar Sarawadi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44748 )
Change subject: [WIP]mb/volteer: Remove DQ/DQS mappings for LPDDR4 ......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/c/coreboot/+/44748/2//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/44748/2//COMMIT_MSG@9 PS2, Line 9: MRC v0.7.0
Where can the version numbers be found?
MRC version can be found using debug FSP-M logs. MRC Source code header file also includes the version.
Kane Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44748 )
Change subject: [WIP]mb/volteer: Remove DQ/DQS mappings for LPDDR4 ......................................................................
Patch Set 2:
i think you will still need DQS table for LP4
Hello build bot (Jenkins), Kane Chen, Derek Huang, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/44748
to look at the new patch set (#3).
Change subject: [WIP]mb/volteer: Remove DQ/DQS mappings for LPDDR4 ......................................................................
[WIP]mb/volteer: Remove DQ/DQS mappings for LPDDR4
MRC v0.7.0 incorporates algorithm which finds the Dq mapping between CPU and DRAM by using CPGC to issue reads and and walking through setting each bit and reading it back through datatrainfeedback.
Only LPDDR4 will be enabling this function at this time.
Signed-off-by: Ravi Sarawadi ravishankar.sarawadi@intel.com Change-Id: I70da3d482385fe6b1ccf071af8d8bd8e44d898ca --- M src/mainboard/google/volteer/variants/baseboard/memory.c M src/mainboard/google/volteer/variants/delbin/memory.c M src/mainboard/google/volteer/variants/halvor/memory.c M src/mainboard/google/volteer/variants/malefor/memory.c M src/mainboard/google/volteer/variants/terrador/memory.c M src/mainboard/google/volteer/variants/todor/memory.c M src/mainboard/google/volteer/variants/voxel/memory.c M src/soc/intel/tigerlake/include/soc/meminit.h M src/soc/intel/tigerlake/meminit.c 9 files changed, 0 insertions(+), 405 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/44748/3
Hello build bot (Jenkins), Kane Chen, Derek Huang, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/44748
to look at the new patch set (#4).
Change subject: mb/volteer: Remove DQ/DQS mappings for LPDDR4 ......................................................................
mb/volteer: Remove DQ/DQS mappings for LPDDR4
MRC v0.7.0 incorporates algorithm which finds the Dq mapping between CPU and DRAM by using CPGC to issue reads and and walking through setting each bit and reading it back through datatrainfeedback.
Only LPDDR4 will be enabling this function at this time.
BUG=None BRANCH=None TEST=Boot Delbin, Voxel to OS, memtester 10+ hours.
Signed-off-by: Ravi Sarawadi ravishankar.sarawadi@intel.com Change-Id: I70da3d482385fe6b1ccf071af8d8bd8e44d898ca --- M src/mainboard/google/volteer/variants/baseboard/memory.c M src/mainboard/google/volteer/variants/delbin/memory.c M src/mainboard/google/volteer/variants/halvor/memory.c M src/mainboard/google/volteer/variants/malefor/memory.c M src/mainboard/google/volteer/variants/terrador/memory.c M src/mainboard/google/volteer/variants/todor/memory.c M src/mainboard/google/volteer/variants/voxel/memory.c M src/soc/intel/tigerlake/include/soc/meminit.h M src/soc/intel/tigerlake/meminit.c 9 files changed, 0 insertions(+), 405 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/44748/4
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44748 )
Change subject: mb/volteer: Remove DQ/DQS mappings for LPDDR4 ......................................................................
Patch Set 4:
(5 comments)
https://review.coreboot.org/c/coreboot/+/44748/4//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/44748/4//COMMIT_MSG@9 PS4, Line 9: MRC v0.7.0 What FSP version does this correspond to? We need to ensure that proper Cq-Depends are set up on the FSP changes.
https://review.coreboot.org/c/coreboot/+/44748/4/src/mainboard/google/voltee... File src/mainboard/google/volteer/variants/baseboard/memory.c:
https://review.coreboot.org/c/coreboot/+/44748/4/src/mainboard/google/voltee... PS4, Line 9: dqs_map dqs_map is not really dropped here and in other variants.
https://review.coreboot.org/c/coreboot/+/44748/4/src/soc/intel/tigerlake/inc... File src/soc/intel/tigerlake/include/soc/meminit.h:
https://review.coreboot.org/c/coreboot/+/44748/4/src/soc/intel/tigerlake/inc... PS4, Line 89: dqs_map This needs to be dropped as well as per commit message.
https://review.coreboot.org/c/coreboot/+/44748/4/src/soc/intel/tigerlake/inc... PS4, Line 100: This part of the change is wrong. You are dropping dq/dqs mappings for DDR4 here.
https://review.coreboot.org/c/coreboot/+/44748/4/src/soc/intel/tigerlake/mem... File src/soc/intel/tigerlake/meminit.c:
https://review.coreboot.org/c/coreboot/+/44748/4/src/soc/intel/tigerlake/mem... PS4, Line 392: This is not correct. You are dropping the mappings for DDR4.
Kane Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44748 )
Change subject: mb/volteer: Remove DQ/DQS mappings for LPDDR4 ......................................................................
Patch Set 4:
(1 comment)
https://review.coreboot.org/c/coreboot/+/44748/4//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/44748/4//COMMIT_MSG@7 PS4, Line 7: DQ/DQS Should be remove DQ. DQS is still needed
Kane Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44748 )
Change subject: mb/volteer: Remove DQ/DQS mappings for LPDDR4 ......................................................................
Patch Set 4:
(2 comments)
https://review.coreboot.org/c/coreboot/+/44748/4//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/44748/4//COMMIT_MSG@9 PS4, Line 9: MRC v0.7.0
What FSP version does this correspond to? We need to ensure that proper Cq-Depends are set up on the […]
Current fsp 3312 (landed before) can support this feature. We tested delbin, voxel, todor, volteer evt and it can boot to os
https://review.coreboot.org/c/coreboot/+/44748/4/src/mainboard/google/voltee... File src/mainboard/google/volteer/variants/baseboard/memory.c:
https://review.coreboot.org/c/coreboot/+/44748/4/src/mainboard/google/voltee... PS4, Line 9: dqs_map
dqs_map is not really dropped here and in other variants.
Hi Furquan, dqs needs to be kept. Ravi, should change the title.
Hello build bot (Jenkins), Furquan Shaikh, Nick Vaccaro, Kane Chen, Derek Huang, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/44748
to look at the new patch set (#5).
Change subject: mb/volteer: Remove DQ mappings for LPDDR4 ......................................................................
mb/volteer: Remove DQ mappings for LPDDR4
MRC v0.7.0 incorporates algorithm which finds the Dq mapping between CPU and DRAM by using CPGC to issue reads and and walking through setting each bit and reading it back through datatrainfeedback.
Only LPDDR4 will be enabling this function at this time.
BUG=None BRANCH=None TEST=Boot Delbin, Voxel to OS, memtester 10+ hours.
Signed-off-by: Ravi Sarawadi ravishankar.sarawadi@intel.com Change-Id: I70da3d482385fe6b1ccf071af8d8bd8e44d898ca --- M src/mainboard/google/volteer/variants/baseboard/memory.c M src/mainboard/google/volteer/variants/delbin/memory.c M src/mainboard/google/volteer/variants/halvor/memory.c M src/mainboard/google/volteer/variants/malefor/memory.c M src/mainboard/google/volteer/variants/terrador/memory.c M src/mainboard/google/volteer/variants/todor/memory.c M src/mainboard/google/volteer/variants/voxel/memory.c M src/soc/intel/tigerlake/include/soc/meminit.h M src/soc/intel/tigerlake/meminit.c 9 files changed, 0 insertions(+), 405 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/44748/5
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44748 )
Change subject: mb/volteer: Remove DQ mappings for LPDDR4 ......................................................................
Patch Set 5:
(1 comment)
https://review.coreboot.org/c/coreboot/+/44748/4//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/44748/4//COMMIT_MSG@9 PS4, Line 9: MRC v0.7.0
Current fsp 3312 (landed before) can support this feature. […]
Thanks Kane!
Ravishankar Sarawadi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44748 )
Change subject: mb/volteer: Remove DQ mappings for LPDDR4 ......................................................................
Patch Set 5:
(5 comments)
https://review.coreboot.org/c/coreboot/+/44748/4//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/44748/4//COMMIT_MSG@7 PS4, Line 7: DQ/DQS
Should be remove DQ. […]
Done
https://review.coreboot.org/c/coreboot/+/44748/4//COMMIT_MSG@9 PS4, Line 9: MRC v0.7.0
Current fsp 3312 (landed before) can support this feature. […]
Ack
https://review.coreboot.org/c/coreboot/+/44748/4/src/mainboard/google/voltee... File src/mainboard/google/volteer/variants/baseboard/memory.c:
https://review.coreboot.org/c/coreboot/+/44748/4/src/mainboard/google/voltee... PS4, Line 9: dqs_map
Hi Furquan, […]
Ack
https://review.coreboot.org/c/coreboot/+/44748/4/src/soc/intel/tigerlake/inc... File src/soc/intel/tigerlake/include/soc/meminit.h:
https://review.coreboot.org/c/coreboot/+/44748/4/src/soc/intel/tigerlake/inc... PS4, Line 89: dqs_map
This needs to be dropped as well as per commit message.
Only DQ needs to be removed, commit msg updated.
https://review.coreboot.org/c/coreboot/+/44748/4/src/soc/intel/tigerlake/mem... File src/soc/intel/tigerlake/meminit.c:
https://review.coreboot.org/c/coreboot/+/44748/4/src/soc/intel/tigerlake/mem... PS4, Line 392:
This is not correct. You are dropping the mappings for DDR4.
I will remove this and keep it for LP4 only.
Hello build bot (Jenkins), Furquan Shaikh, Nick Vaccaro, Kane Chen, Derek Huang, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/44748
to look at the new patch set (#6).
Change subject: mb/volteer: Remove DQ mappings for LPDDR4 ......................................................................
mb/volteer: Remove DQ mappings for LPDDR4
MRC v0.7.0 incorporates algorithm which finds the Dq mapping between CPU and DRAM by using CPGC to issue reads and and walking through setting each bit and reading it back through datatrainfeedback.
Only LPDDR4 will be enabling this function at this time.
BUG=None BRANCH=None TEST=Boot Delbin, Voxel to OS, memtester 10+ hours.
Signed-off-by: Ravi Sarawadi ravishankar.sarawadi@intel.com Change-Id: I70da3d482385fe6b1ccf071af8d8bd8e44d898ca --- M src/mainboard/google/volteer/variants/baseboard/memory.c M src/mainboard/google/volteer/variants/delbin/memory.c M src/mainboard/google/volteer/variants/halvor/memory.c M src/mainboard/google/volteer/variants/malefor/memory.c M src/mainboard/google/volteer/variants/terrador/memory.c M src/mainboard/google/volteer/variants/todor/memory.c M src/mainboard/google/volteer/variants/voxel/memory.c M src/soc/intel/tigerlake/include/soc/meminit.h M src/soc/intel/tigerlake/meminit.c 9 files changed, 0 insertions(+), 335 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/44748/6
Kane Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44748 )
Change subject: mb/volteer: Remove DQ mappings for LPDDR4 ......................................................................
Patch Set 6:
Ravi, any plan to fix the issues found by build bot? i think you didn't remove the code for the below boards.
board.chromeos.GOOGLE_DELTAN board.chromeos.GOOGLE_DELTAUR board.chromeos.INTEL_TGLRVP_UP3 board.chromeos.INTEL_TGLRVP_UP4 board.GOOGLE_DELTAN board.GOOGLE_DELTAUR board.INTEL_TGLRVP_UP3 board.INTEL_TGLRVP_UP4
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44748 )
Change subject: mb/volteer: Remove DQ mappings for LPDDR4 ......................................................................
Patch Set 6:
(2 comments)
https://review.coreboot.org/c/coreboot/+/44748/6//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/44748/6//COMMIT_MSG@11 PS6, Line 11: setting each bit and reading it back through datatrainfeedback. Out of curiosity, how long does this additional training step take?
(I know this only needs to be done on full training flows, but I'm still curious)
https://review.coreboot.org/c/coreboot/+/44748/6//COMMIT_MSG@17 PS6, Line 17: TEST=Boot Delbin, Voxel to OS, memtester 10+ hours. Any errors, or no errors?
Nick Vaccaro has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44748 )
Change subject: mb/volteer: Remove DQ mappings for LPDDR4 ......................................................................
Patch Set 6:
(2 comments)
https://review.coreboot.org/c/coreboot/+/44748/6//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/44748/6//COMMIT_MSG@7 PS6, Line 7: LPDDR4 LPDDR4x
https://review.coreboot.org/c/coreboot/+/44748/6//COMMIT_MSG@13 PS6, Line 13: LPDDR4 Should this be LPDDR4x? What about DDR4?
Hello build bot (Jenkins), Furquan Shaikh, Nick Vaccaro, Kane Chen, Derek Huang, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/44748
to look at the new patch set (#7).
Change subject: mb/volteer: Remove DQ mappings for LPDDR4x ......................................................................
mb/volteer: Remove DQ mappings for LPDDR4x
MRC v0.7.0 incorporates algorithm which finds the Dq mapping between CPU and DRAM by using CPGC to issue reads and walking through setting each bit and reading it back through datatrainfeedback.
Only LPDDR4x will be enabling this function at this time.
BUG=None BRANCH=None TEST=Boot Delbin, Voxel to OS. Run memtester 10+ hours w/o errors.
Signed-off-by: Ravi Sarawadi ravishankar.sarawadi@intel.com Change-Id: I70da3d482385fe6b1ccf071af8d8bd8e44d898ca --- M src/mainboard/google/volteer/variants/baseboard/memory.c M src/mainboard/google/volteer/variants/delbin/memory.c M src/mainboard/google/volteer/variants/halvor/memory.c M src/mainboard/google/volteer/variants/malefor/memory.c M src/mainboard/google/volteer/variants/terrador/memory.c M src/mainboard/google/volteer/variants/todor/memory.c M src/mainboard/google/volteer/variants/voxel/memory.c M src/soc/intel/tigerlake/include/soc/meminit.h M src/soc/intel/tigerlake/meminit.c 9 files changed, 0 insertions(+), 335 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/44748/7
Ravishankar Sarawadi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44748 )
Change subject: mb/volteer: Remove DQ mappings for LPDDR4x ......................................................................
Patch Set 7:
(2 comments)
https://review.coreboot.org/c/coreboot/+/44748/6//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/44748/6//COMMIT_MSG@7 PS6, Line 7: LPDDR4
LPDDR4x
Done
https://review.coreboot.org/c/coreboot/+/44748/6//COMMIT_MSG@11 PS6, Line 11: setting each bit and reading it back through datatrainfeedback.
Out of curiosity, how long does this additional training step take? […]
I will update as soon as I have/collect data about this.
Hello build bot (Jenkins), Furquan Shaikh, Nick Vaccaro, Kane Chen, Derek Huang, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/44748
to look at the new patch set (#9).
Change subject: mb/volteer: Remove DQ mappings for LPDDR4x ......................................................................
mb/volteer: Remove DQ mappings for LPDDR4x
MRC v0.7.0 incorporates algorithm which finds the Dq mapping between CPU and DRAM by using CPGC to issue reads and walking through setting each bit and reading it back through datatrainfeedback.
Only LPDDR4x will be enabling this function at this time.
BUG=None BRANCH=None TEST=Boot Delbin, Voxel to OS. Run memtester 10+ hours w/o errors.
Signed-off-by: Ravi Sarawadi ravishankar.sarawadi@intel.com Change-Id: I70da3d482385fe6b1ccf071af8d8bd8e44d898ca --- M src/mainboard/google/volteer/variants/baseboard/memory.c M src/mainboard/google/volteer/variants/delbin/memory.c M src/mainboard/google/volteer/variants/halvor/memory.c M src/mainboard/google/volteer/variants/lindar/memory.c M src/mainboard/google/volteer/variants/malefor/memory.c M src/mainboard/google/volteer/variants/terrador/memory.c M src/mainboard/google/volteer/variants/todor/memory.c M src/mainboard/google/volteer/variants/voxel/memory.c M src/mainboard/intel/tglrvp/variants/tglrvp_up3/memory.c M src/mainboard/intel/tglrvp/variants/tglrvp_up4/memory.c M src/soc/intel/tigerlake/include/soc/meminit.h M src/soc/intel/tigerlake/meminit.c 12 files changed, 0 insertions(+), 396 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/44748/9
Ravishankar Sarawadi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44748 )
Change subject: mb/volteer: Remove DQ mappings for LPDDR4x ......................................................................
Patch Set 9:
Patch Set 6:
Ravi, any plan to fix the issues found by build bot? i think you didn't remove the code for the below boards.
board.chromeos.GOOGLE_DELTAN board.chromeos.GOOGLE_DELTAUR board.chromeos.INTEL_TGLRVP_UP3 board.chromeos.INTEL_TGLRVP_UP4 board.GOOGLE_DELTAN board.GOOGLE_DELTAUR board.INTEL_TGLRVP_UP3 board.INTEL_TGLRVP_UP4
Done
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44748 )
Change subject: mb/volteer: Remove DQ mappings for LPDDR4x ......................................................................
Patch Set 9:
What's the latest on this? Ravi - are you still working on pushing this change?
Ravishankar Sarawadi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44748 )
Change subject: mb/volteer: Remove DQ mappings for LPDDR4x ......................................................................
Patch Set 9:
Yes I want to get this code clean up in, I will work on rebasing and upstreaming asap.
Martin L Roth has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/44748?usp=email )
Change subject: mb/volteer: Remove DQ mappings for LPDDR4x ......................................................................
Abandoned
This patch has not been touched in over 12 months. Anyone who wants to take over work on this patch, please feel free to restore it and do any work needed to get it merged. If you create a new patch based on this work, please credit the original author.
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Angel Pons (Code Review) -
Furquan Shaikh (Code Review)
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Kane Chen (Code Review)
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Martin L Roth (Code Review)
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Nick Vaccaro (Code Review)
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Paul Menzel (Code Review)
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Ravishankar Sarawadi (Code Review)