Ravishankar Sarawadi uploaded patch set #5 to this change.

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mb/volteer: Remove DQ mappings for LPDDR4

MRC v0.7.0 incorporates algorithm which finds the Dq mapping between
CPU and DRAM by using CPGC to issue reads and and walking through
setting each bit and reading it back through datatrainfeedback.

Only LPDDR4 will be enabling this function at this time.

BUG=None
BRANCH=None
TEST=Boot Delbin, Voxel to OS, memtester 10+ hours.

Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com>
Change-Id: I70da3d482385fe6b1ccf071af8d8bd8e44d898ca
---
M src/mainboard/google/volteer/variants/baseboard/memory.c
M src/mainboard/google/volteer/variants/delbin/memory.c
M src/mainboard/google/volteer/variants/halvor/memory.c
M src/mainboard/google/volteer/variants/malefor/memory.c
M src/mainboard/google/volteer/variants/terrador/memory.c
M src/mainboard/google/volteer/variants/todor/memory.c
M src/mainboard/google/volteer/variants/voxel/memory.c
M src/soc/intel/tigerlake/include/soc/meminit.h
M src/soc/intel/tigerlake/meminit.c
9 files changed, 0 insertions(+), 405 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/44748/5

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