Shelley Chen has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46111 )
Change subject: trogdor: Modify DDR training to use mrc_cache ......................................................................
trogdor: Modify DDR training to use mrc_cache
Currently, trogdor devices have a section RO_DDR_TRAINING that is used to store memory training data. Changing so that we reuse the same mrc_cache API as x86 platforms. This requires renaming RW_DDR_TRAINING to RW_MRC_CACHE and removing RO_DDR_TRAINING in the fmap table.
BUG=b:150502246 BRANCH=None TEST=FW_NAME="lazor" emerge-trogdor coreboot chromeos-bootimage Make sure that first boot after flashing does memory training and next boot does not.
Change-Id: I16d429119563707123d538738348c7c4985b7b52 Signed-off-by: Shelley Chen shchen@google.com --- M src/lib/Makefile.inc M src/mainboard/google/trogdor/chromeos.fmd M src/soc/qualcomm/common/include/soc/qclib_common.h M src/soc/qualcomm/common/qclib.c M src/soc/qualcomm/sc7180/Kconfig 5 files changed, 11 insertions(+), 11 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/11/46111/1
diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc index ce57f51..c228f2a 100644 --- a/src/lib/Makefile.inc +++ b/src/lib/Makefile.inc @@ -100,6 +100,7 @@ romstage-y += romstage_handoff.c romstage-y += selfboot.c romstage-y += stack.c +romstage-y += rtc.c ramstage-y += rtc.c
romstage-$(CONFIG_COLLECT_TIMESTAMPS) += timestamp.c diff --git a/src/mainboard/google/trogdor/chromeos.fmd b/src/mainboard/google/trogdor/chromeos.fmd index 3aa0473..11f5d52 100644 --- a/src/mainboard/google/trogdor/chromeos.fmd +++ b/src/mainboard/google/trogdor/chromeos.fmd @@ -10,13 +10,12 @@ RO_FRID 0x100 } RO_VPD(PRESERVE) 228K - RO_DDR_TRAINING(PRESERVE) 8K RO_LIMITS_CFG(PRESERVE) 4K }
RW_VPD(PRESERVE) 32K RW_NVRAM(PRESERVE) 16K - RW_DDR_TRAINING(PRESERVE) 8K + RW_MRC_CACHE(PRESERVE) 8K RW_LIMITS_CFG(PRESERVE) 4K RW_ELOG(PRESERVE) 4K RW_SHARED 4K { diff --git a/src/soc/qualcomm/common/include/soc/qclib_common.h b/src/soc/qualcomm/common/include/soc/qclib_common.h index e8dc499..d32f69f 100644 --- a/src/soc/qualcomm/common/include/soc/qclib_common.h +++ b/src/soc/qualcomm/common/include/soc/qclib_common.h @@ -11,7 +11,7 @@ #define QCLIB_TE_NAME_LENGTH 24
/* FMAP_REGION names */ -#define QCLIB_FR_DDR_TRAINING_DATA "RO_DDR_TRAINING" +#define QCLIB_FR_DDR_TRAINING_DATA "RW_MRC_CACHE" #define QCLIB_FR_LIMITS_CFG_DATA "RO_LIMITS_CFG"
/* TE_NAME (table entry name) */ diff --git a/src/soc/qualcomm/common/qclib.c b/src/soc/qualcomm/common/qclib.c index d06cb42..ab09194 100644 --- a/src/soc/qualcomm/common/qclib.c +++ b/src/soc/qualcomm/common/qclib.c @@ -11,6 +11,7 @@ #include <console/console.h> #include <soc/mmu.h> #include <soc/mmu_common.h> +#include <mrc_cache.h> #include <soc/qclib_common.h> #include <soc/symbols_common.h> #include <security/vboot/misc.h> @@ -71,8 +72,8 @@ } else if (!strncmp(QCLIB_TE_DDR_TRAINING_DATA, te->name, sizeof(te->name))) {
- assert(fmap_overwrite_area(QCLIB_FR_DDR_TRAINING_DATA, - (const void *)te->blob_address, te->size)); + assert(!mrc_cache_stash_data(MRC_TRAINING_DATA, 0, + (const void *)te->blob_address, te->size));
} else if (!strncmp(QCLIB_TE_LIMITS_CFG_DATA, te->name, sizeof(te->name))) { @@ -112,7 +113,7 @@ void qclib_load_and_run(void) { int i; - ssize_t ssize; + size_t data_size; struct mmu_context pre_qclib_mmu_context;
/* zero ddr_information SRAM region, needs new data each boot */ @@ -128,12 +129,10 @@ qclib_add_if_table_entry(QCLIB_TE_DDR_INFORMATION, NULL, 0, 0);
/* Attempt to load DDR Training Blob */ - ssize = fmap_read_area(QCLIB_FR_DDR_TRAINING_DATA, _ddr_training, - REGION_SIZE(ddr_training)); - if (ssize < 0) - goto fail; + mrc_cache_load_current(MRC_TRAINING_DATA, 0, _ddr_training, + REGION_SIZE(ddr_training), &data_size); qclib_add_if_table_entry(QCLIB_TE_DDR_TRAINING_DATA, - _ddr_training, ssize, 0); + _ddr_training, data_size, 0);
/* hook for SoC specific binary blob loads */ if (qclib_soc_blob_load()) { diff --git a/src/soc/qualcomm/sc7180/Kconfig b/src/soc/qualcomm/sc7180/Kconfig index d543ef5..e251612 100644 --- a/src/soc/qualcomm/sc7180/Kconfig +++ b/src/soc/qualcomm/sc7180/Kconfig @@ -17,6 +17,7 @@ select MAINBOARD_HAS_NATIVE_VGA_INIT select MAINBOARD_FORCE_NATIVE_VGA_INIT select HAVE_LINEAR_FRAMEBUFFER + select CACHE_MRC_SETTINGS
if SOC_QUALCOMM_SC7180
Hello Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/46111
to look at the new patch set (#2).
Change subject: trogdor: Modify DDR training to use mrc_cache ......................................................................
trogdor: Modify DDR training to use mrc_cache
Currently, trogdor devices have a section RO_DDR_TRAINING that is used to store memory training data. Changing so that we reuse the same mrc_cache API as x86 platforms. This requires renaming RW_DDR_TRAINING to RW_MRC_CACHE and removing RO_DDR_TRAINING in the fmap table.
BUG=b:150502246 BRANCH=None TEST=FW_NAME="lazor" emerge-trogdor coreboot chromeos-bootimage Make sure that first boot after flashing does memory training and next boot does not.
Change-Id: I16d429119563707123d538738348c7c4985b7b52 Signed-off-by: Shelley Chen shchen@google.com --- M src/lib/Makefile.inc M src/mainboard/google/trogdor/chromeos.fmd M src/soc/qualcomm/common/include/soc/qclib_common.h M src/soc/qualcomm/common/qclib.c M src/soc/qualcomm/sc7180/Kconfig 5 files changed, 11 insertions(+), 11 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/11/46111/2
Julius Werner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46111 )
Change subject: trogdor: Modify DDR training to use mrc_cache ......................................................................
Patch Set 2:
(4 comments)
This implements nothing of the special recovery-mode behavior we discussed (both not using the cache at all in recovery mode, and erasing the cache when the retrain switch is hit). Can you please add those as well?
https://review.coreboot.org/c/coreboot/+/46111/1/src/soc/qualcomm/common/inc... File src/soc/qualcomm/common/include/soc/qclib_common.h:
https://review.coreboot.org/c/coreboot/+/46111/1/src/soc/qualcomm/common/inc... PS1, Line 14: #define QCLIB_FR_DDR_TRAINING_DATA "RW_MRC_CACHE" Shouldn't be needed at all anymore?
https://review.coreboot.org/c/coreboot/+/46111/1/src/soc/qualcomm/common/qcl... File src/soc/qualcomm/common/qclib.c:
https://review.coreboot.org/c/coreboot/+/46111/1/src/soc/qualcomm/common/qcl... PS1, Line 14: #include <mrc_cache.h> nit: please alphabetize above "soc"
https://review.coreboot.org/c/coreboot/+/46111/1/src/soc/qualcomm/common/qcl... PS1, Line 75: 0 Probably a good idea to define a macro for the version, even if we're probably not going to ever change it.
https://review.coreboot.org/c/coreboot/+/46111/1/src/soc/qualcomm/common/qcl... PS1, Line 132: mrc_cache_load_current(MRC_TRAINING_DATA, 0, _ddr_training, Still need to check return value, right?
Shelley Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46111 )
Change subject: trogdor: Modify DDR training to use mrc_cache ......................................................................
Patch Set 6:
(4 comments)
This change is ready for review.
https://review.coreboot.org/c/coreboot/+/46111/1/src/soc/qualcomm/common/inc... File src/soc/qualcomm/common/include/soc/qclib_common.h:
https://review.coreboot.org/c/coreboot/+/46111/1/src/soc/qualcomm/common/inc... PS1, Line 14: #define QCLIB_FR_DDR_TRAINING_DATA "RW_MRC_CACHE"
Shouldn't be needed at all anymore?
Done
https://review.coreboot.org/c/coreboot/+/46111/1/src/soc/qualcomm/common/qcl... File src/soc/qualcomm/common/qclib.c:
https://review.coreboot.org/c/coreboot/+/46111/1/src/soc/qualcomm/common/qcl... PS1, Line 14: #include <mrc_cache.h>
nit: please alphabetize above "soc"
Done
https://review.coreboot.org/c/coreboot/+/46111/1/src/soc/qualcomm/common/qcl... PS1, Line 75: 0
Probably a good idea to define a macro for the version, even if we're probably not going to ever cha […]
Done
https://review.coreboot.org/c/coreboot/+/46111/1/src/soc/qualcomm/common/qcl... PS1, Line 132: mrc_cache_load_current(MRC_TRAINING_DATA, 0, _ddr_training,
Still need to check return value, right?
Done
Julius Werner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46111 )
Change subject: trogdor: Modify DDR training to use mrc_cache ......................................................................
Patch Set 6:
(6 comments)
https://review.coreboot.org/c/coreboot/+/46111/6/src/mainboard/google/trogdo... File src/mainboard/google/trogdor/chromeos.fmd:
https://review.coreboot.org/c/coreboot/+/46111/6/src/mainboard/google/trogdo... PS6, Line 12: RO_VPD(PRESERVE) 228K Sorry, I just submitted CB:45705 so you'll have to rebase onto that.
Would you mind shifting another 128K from RO_VPD to COREBOOT? We don't really need such a big VPD, and with the new Groot requirements it's probably better to have most of the extra free space in the CBFS part. (The RO_SECTION would increase accordingly and the FMAP would move from 0x3c0000 to 0x3e0000 then.)
https://review.coreboot.org/c/coreboot/+/46111/6/src/soc/qualcomm/common/qcl... File src/soc/qualcomm/common/qclib.c:
https://review.coreboot.org/c/coreboot/+/46111/6/src/soc/qualcomm/common/qcl... PS6, Line 78: * because we always want to retrain. Well, the reason we're not writing it back is more that recovery uses RO firmware, and RW firmware might have been updated to a different training data format.
Also, coreboot comment style is either
/* * a blank line both * at the top and the * bottom. */
or
/* no star on the left for continuing lines */
https://review.coreboot.org/c/coreboot/+/46111/6/src/soc/qualcomm/common/qcl... PS6, Line 142: (CONFIG(VBOOT) && get_recovery_mode_retrain_switch())) { The retrain isn't really important here (retrain always implies recovery anyway), the important part for retrain is that we want to erase the MRC cache on flash (so the next time RW boots it will be forced to retrain).
I believe(?) the MRC cache driver will do that automatically already if we just select CONFIG_MRC_CLEAR_NORMAL_CACHE_ON_RECOVERY_RETRAIN? Would be good to test out if that actually works, though. (I'm also not sure if the retrain key combination is actually enabled on Trogdor, that's also a good thing to try out. If not, please talk to Tom about turning it on.)
https://review.coreboot.org/c/coreboot/+/46111/6/src/soc/qualcomm/common/qcl... PS6, Line 143: data_size = 0; We should probably still pass the full size of the region to QcLib even if we're not intending to use it, otherwise I'd be afraid we might confuse it (e.g. maybe it needs that area as scratch space during training or something, even if we throw it away again). We should just skip the part about loading something into it. Should probably just memset() the whole thing to 0 instead.
https://review.coreboot.org/c/coreboot/+/46111/6/src/soc/qualcomm/common/qcl... PS6, Line 149: printk(BIOS_ERR, "Unable to load previous training data.\n"); I think this is exactly the case we would hit if we would run the CONFIG_MRC_CLEAR_NORMAL_CACHE_ON_RECOVERY_RETRAIN thing. Probably worth to also memset() the memory buffer to 0 here just to make sure we're not passing random garbage data that might confuse QcLib.
https://review.coreboot.org/c/coreboot/+/46111/6/src/soc/qualcomm/common/qcl... PS6, Line 152: data_size As mentioned on the other patch, this would probably better be REGION_SIZE(ddr_training) after all.
Hello build bot (Jenkins), Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/46111
to look at the new patch set (#7).
Change subject: trogdor: Modify DDR training to use mrc_cache ......................................................................
trogdor: Modify DDR training to use mrc_cache
Currently, trogdor devices have a section RO_DDR_TRAINING that is used to store memory training data. Changing so that we reuse the same mrc_cache API as x86 platforms. This requires renaming RW_DDR_TRAINING to RW_MRC_CACHE and removing RO_DDR_TRAINING in the fmap table.
BUG=b:150502246 BRANCH=None TEST=FW_NAME="lazor" emerge-trogdor coreboot chromeos-bootimage Make sure that first boot after flashing does memory training and next boot does not.
Change-Id: I16d429119563707123d538738348c7c4985b7b52 Signed-off-by: Shelley Chen shchen@google.com --- M src/lib/Makefile.inc M src/mainboard/google/trogdor/chromeos.fmd M src/soc/qualcomm/common/include/soc/qclib_common.h M src/soc/qualcomm/common/qclib.c M src/soc/qualcomm/sc7180/Kconfig M src/soc/qualcomm/sdm845/Kconfig 6 files changed, 37 insertions(+), 15 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/11/46111/7
Shelley Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46111 )
Change subject: trogdor: Modify DDR training to use mrc_cache ......................................................................
Patch Set 8:
(6 comments)
This change is ready for review.
https://review.coreboot.org/c/coreboot/+/46111/6/src/mainboard/google/trogdo... File src/mainboard/google/trogdor/chromeos.fmd:
https://review.coreboot.org/c/coreboot/+/46111/6/src/mainboard/google/trogdo... PS6, Line 12: RO_VPD(PRESERVE) 228K
Sorry, I just submitted CB:45705 so you'll have to rebase onto that. […]
Done
https://review.coreboot.org/c/coreboot/+/46111/6/src/soc/qualcomm/common/qcl... File src/soc/qualcomm/common/qclib.c:
https://review.coreboot.org/c/coreboot/+/46111/6/src/soc/qualcomm/common/qcl... PS6, Line 78: * because we always want to retrain.
Well, the reason we're not writing it back is more that recovery uses RO firmware, and RW firmware m […]
Done
https://review.coreboot.org/c/coreboot/+/46111/6/src/soc/qualcomm/common/qcl... PS6, Line 142: (CONFIG(VBOOT) && get_recovery_mode_retrain_switch())) {
The retrain isn't really important here (retrain always implies recovery anyway), the important part […]
Ack. I've added the config and I'll ping Tom about how to force retraining from the EC.
https://review.coreboot.org/c/coreboot/+/46111/6/src/soc/qualcomm/common/qcl... PS6, Line 143: data_size = 0;
We should probably still pass the full size of the region to QcLib even if we're not intending to us […]
Done
https://review.coreboot.org/c/coreboot/+/46111/6/src/soc/qualcomm/common/qcl... PS6, Line 149: printk(BIOS_ERR, "Unable to load previous training data.\n");
I think this is exactly the case we would hit if we would run the CONFIG_MRC_CLEAR_NORMAL_CACHE_ON_R […]
Done
https://review.coreboot.org/c/coreboot/+/46111/6/src/soc/qualcomm/common/qcl... PS6, Line 152: data_size
As mentioned on the other patch, this would probably better be REGION_SIZE(ddr_training) after all.
Done
Hello build bot (Jenkins), Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/46111
to look at the new patch set (#9).
Change subject: trogdor: Modify DDR training to use mrc_cache ......................................................................
trogdor: Modify DDR training to use mrc_cache
Currently, trogdor devices have a section RO_DDR_TRAINING that is used to store memory training data. Changing so that we reuse the same mrc_cache API as x86 platforms. This requires renaming RW_DDR_TRAINING to RW_MRC_CACHE and removing RO_DDR_TRAINING in the fmap table.
BUG=b:150502246 BRANCH=None TEST=FW_NAME="lazor" emerge-trogdor coreboot chromeos-bootimage Make sure that first boot after flashing does memory training and next boot does not. Boot into recovery two consecutive times and make sure memory training occurs on both boots.
Change-Id: I16d429119563707123d538738348c7c4985b7b52 Signed-off-by: Shelley Chen shchen@google.com --- M src/lib/Makefile.inc M src/mainboard/google/trogdor/chromeos.fmd M src/soc/qualcomm/common/include/soc/qclib_common.h M src/soc/qualcomm/common/qclib.c M src/soc/qualcomm/sc7180/Kconfig M src/soc/qualcomm/sdm845/Kconfig 6 files changed, 39 insertions(+), 15 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/11/46111/9
Hello build bot (Jenkins), Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/46111
to look at the new patch set (#10).
Change subject: trogdor: Modify DDR training to use mrc_cache ......................................................................
trogdor: Modify DDR training to use mrc_cache
Currently, trogdor devices have a section RO_DDR_TRAINING that is used to store memory training data. Changing so that we reuse the same mrc_cache API as x86 platforms. This requires renaming RW_DDR_TRAINING to RW_MRC_CACHE and removing RO_DDR_TRAINING in the fmap table.
BUG=b:150502246 BRANCH=None TEST=FW_NAME="lazor" emerge-trogdor coreboot chromeos-bootimage Make sure that first boot after flashing does memory training and next boot does not. Boot into recovery two consecutive times and make sure memory training occurs on both boots.
Change-Id: I16d429119563707123d538738348c7c4985b7b52 Signed-off-by: Shelley Chen shchen@google.com --- M src/lib/Makefile.inc M src/mainboard/google/trogdor/chromeos.fmd M src/soc/qualcomm/common/include/soc/qclib_common.h M src/soc/qualcomm/common/qclib.c M src/soc/qualcomm/sc7180/Kconfig M src/soc/qualcomm/sdm845/Kconfig 6 files changed, 39 insertions(+), 15 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/11/46111/10
Julius Werner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46111 )
Change subject: trogdor: Modify DDR training to use mrc_cache ......................................................................
Patch Set 10: Code-Review+2
(3 comments)
Thanks, looks good!
https://review.coreboot.org/c/coreboot/+/46111/6/src/soc/qualcomm/common/qcl... File src/soc/qualcomm/common/qclib.c:
https://review.coreboot.org/c/coreboot/+/46111/6/src/soc/qualcomm/common/qcl... PS6, Line 142: (CONFIG(VBOOT) && get_recovery_mode_retrain_switch())) {
Ack. I've added the config and I'll ping Tom about how to force retraining from the EC.
I mean, generally you do it by pressing LShift+Esc+Refresh+Power. I'm just not sure if that combination is always enabled or if we need to turn on an extra config in the EC code.
https://review.coreboot.org/c/coreboot/+/46111/10/src/soc/qualcomm/common/qc... File src/soc/qualcomm/common/qclib.c:
https://review.coreboot.org/c/coreboot/+/46111/10/src/soc/qualcomm/common/qc... PS10, Line 142: if we're being forced to retrain. nit: this part doesn't really apply anymore.
https://review.coreboot.org/c/coreboot/+/46111/10/src/soc/qualcomm/common/qc... PS10, Line 145: data_size = REGION_SIZE(ddr_training); nit: this is kinda pointless here now
Hello build bot (Jenkins), Patrick Georgi, Martin Roth, Julius Werner,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/46111
to look at the new patch set (#11).
Change subject: trogdor: Modify DDR training to use mrc_cache ......................................................................
trogdor: Modify DDR training to use mrc_cache
Currently, trogdor devices have a section RO_DDR_TRAINING that is used to store memory training data. Changing so that we reuse the same mrc_cache API as x86 platforms. This requires renaming RW_DDR_TRAINING to RW_MRC_CACHE and removing RO_DDR_TRAINING in the fmap table.
BUG=b:150502246 BRANCH=None TEST=FW_NAME="lazor" emerge-trogdor coreboot chromeos-bootimage Make sure that first boot after flashing does memory training and next boot does not. Boot into recovery two consecutive times and make sure memory training occurs on both boots.
Change-Id: I16d429119563707123d538738348c7c4985b7b52 Signed-off-by: Shelley Chen shchen@google.com --- M src/lib/Makefile.inc M src/mainboard/google/trogdor/chromeos.fmd M src/soc/qualcomm/common/include/soc/qclib_common.h M src/soc/qualcomm/common/qclib.c M src/soc/qualcomm/sc7180/Kconfig M src/soc/qualcomm/sdm845/Kconfig 6 files changed, 39 insertions(+), 15 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/11/46111/11
Hello build bot (Jenkins), Patrick Georgi, Martin Roth, Julius Werner,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/46111
to look at the new patch set (#12).
Change subject: trogdor: Modify DDR training to use mrc_cache ......................................................................
trogdor: Modify DDR training to use mrc_cache
Currently, trogdor devices have a section RO_DDR_TRAINING that is used to store memory training data. Changing so that we reuse the same mrc_cache API as x86 platforms. This requires renaming RW_DDR_TRAINING to RW_MRC_CACHE and removing RO_DDR_TRAINING in the fmap table.
BUG=b:150502246 BRANCH=None TEST=FW_NAME="lazor" emerge-trogdor coreboot chromeos-bootimage Make sure that first boot after flashing does memory training and next boot does not. Boot into recovery two consecutive times and make sure memory training occurs on both boots.
Change-Id: I16d429119563707123d538738348c7c4985b7b52 Signed-off-by: Shelley Chen shchen@google.com --- M src/lib/Makefile.inc M src/mainboard/google/trogdor/chromeos.fmd M src/soc/qualcomm/common/include/soc/qclib_common.h M src/soc/qualcomm/common/qclib.c M src/soc/qualcomm/sc7180/Kconfig M src/soc/qualcomm/sdm845/Kconfig 6 files changed, 39 insertions(+), 15 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/11/46111/12
Shelley Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46111 )
Change subject: trogdor: Modify DDR training to use mrc_cache ......................................................................
Patch Set 12:
(2 comments)
https://review.coreboot.org/c/coreboot/+/46111/10/src/soc/qualcomm/common/qc... File src/soc/qualcomm/common/qclib.c:
https://review.coreboot.org/c/coreboot/+/46111/10/src/soc/qualcomm/common/qc... PS10, Line 142: if we're being forced to retrain.
nit: this part doesn't really apply anymore.
Removed.
https://review.coreboot.org/c/coreboot/+/46111/10/src/soc/qualcomm/common/qc... PS10, Line 145: data_size = REGION_SIZE(ddr_training);
nit: this is kinda pointless here now
Removed data_size assignment.
Julius Werner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46111 )
Change subject: trogdor: Modify DDR training to use mrc_cache ......................................................................
Patch Set 12: Code-Review+2
Julius Werner has submitted this change. ( https://review.coreboot.org/c/coreboot/+/46111 )
Change subject: trogdor: Modify DDR training to use mrc_cache ......................................................................
trogdor: Modify DDR training to use mrc_cache
Currently, trogdor devices have a section RO_DDR_TRAINING that is used to store memory training data. Changing so that we reuse the same mrc_cache API as x86 platforms. This requires renaming RW_DDR_TRAINING to RW_MRC_CACHE and removing RO_DDR_TRAINING in the fmap table.
BUG=b:150502246 BRANCH=None TEST=FW_NAME="lazor" emerge-trogdor coreboot chromeos-bootimage Make sure that first boot after flashing does memory training and next boot does not. Boot into recovery two consecutive times and make sure memory training occurs on both boots.
Change-Id: I16d429119563707123d538738348c7c4985b7b52 Signed-off-by: Shelley Chen shchen@google.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/46111 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Julius Werner jwerner@chromium.org --- M src/lib/Makefile.inc M src/mainboard/google/trogdor/chromeos.fmd M src/soc/qualcomm/common/include/soc/qclib_common.h M src/soc/qualcomm/common/qclib.c M src/soc/qualcomm/sc7180/Kconfig M src/soc/qualcomm/sdm845/Kconfig 6 files changed, 39 insertions(+), 15 deletions(-)
Approvals: build bot (Jenkins): Verified Julius Werner: Looks good to me, approved
diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc index ce57f51..c228f2a 100644 --- a/src/lib/Makefile.inc +++ b/src/lib/Makefile.inc @@ -100,6 +100,7 @@ romstage-y += romstage_handoff.c romstage-y += selfboot.c romstage-y += stack.c +romstage-y += rtc.c ramstage-y += rtc.c
romstage-$(CONFIG_COLLECT_TIMESTAMPS) += timestamp.c diff --git a/src/mainboard/google/trogdor/chromeos.fmd b/src/mainboard/google/trogdor/chromeos.fmd index 1801d34..d5324ee 100644 --- a/src/mainboard/google/trogdor/chromeos.fmd +++ b/src/mainboard/google/trogdor/chromeos.fmd @@ -2,20 +2,19 @@
FLASH@0x0 8M { WP_RO 4M { - RO_SECTION 0x3c4000 { + RO_SECTION 0x3e4000 { BOOTBLOCK 96K COREBOOT(CBFS) - FMAP@0x3c0000 0x1000 + FMAP@0x3e0000 0x1000 GBB 0x2f00 RO_FRID 0x100 } RO_VPD(PRESERVE) - RO_DDR_TRAINING(PRESERVE) 8K }
RW_VPD(PRESERVE) 32K RW_NVRAM(PRESERVE) 16K - RW_DDR_TRAINING(PRESERVE) 8K + RW_MRC_CACHE(PRESERVE) 8K RW_ELOG(PRESERVE) 4K RW_SHARED 4K { SHARED_DATA diff --git a/src/soc/qualcomm/common/include/soc/qclib_common.h b/src/soc/qualcomm/common/include/soc/qclib_common.h index e8dc499..c906ef2 100644 --- a/src/soc/qualcomm/common/include/soc/qclib_common.h +++ b/src/soc/qualcomm/common/include/soc/qclib_common.h @@ -11,7 +11,6 @@ #define QCLIB_TE_NAME_LENGTH 24
/* FMAP_REGION names */ -#define QCLIB_FR_DDR_TRAINING_DATA "RO_DDR_TRAINING" #define QCLIB_FR_LIMITS_CFG_DATA "RO_LIMITS_CFG"
/* TE_NAME (table entry name) */ diff --git a/src/soc/qualcomm/common/qclib.c b/src/soc/qualcomm/common/qclib.c index d06cb42..d4796a2 100644 --- a/src/soc/qualcomm/common/qclib.c +++ b/src/soc/qualcomm/common/qclib.c @@ -3,12 +3,14 @@ #include <console/cbmem_console.h> #include <cbmem.h> #include <boardid.h> +#include <bootmode.h> #include <string.h> #include <fmap.h> #include <assert.h> #include <arch/mmu.h> #include <cbfs.h> #include <console/console.h> +#include <mrc_cache.h> #include <soc/mmu.h> #include <soc/mmu_common.h> #include <soc/qclib_common.h> @@ -16,6 +18,8 @@ #include <security/vboot/misc.h> #include <vb2_api.h>
+#define QCLIB_VERSION 0 + struct qclib_cb_if_table qclib_cb_if_table = { .magic = QCLIB_MAGIC_NUMBER, .version = QCLIB_INTERFACE_VERSION, @@ -70,9 +74,16 @@
} else if (!strncmp(QCLIB_TE_DDR_TRAINING_DATA, te->name, sizeof(te->name))) { - - assert(fmap_overwrite_area(QCLIB_FR_DDR_TRAINING_DATA, - (const void *)te->blob_address, te->size)); + /* + * Don't store training data if we're in recovery mode + * because we always want to retrain due to + * possibility of RW training data possibly being + * updated to a different format. + */ + if (vboot_recovery_mode_enabled()) + return; + assert(!mrc_cache_stash_data(MRC_TRAINING_DATA, QCLIB_VERSION, + (const void *)te->blob_address, te->size));
} else if (!strncmp(QCLIB_TE_LIMITS_CFG_DATA, te->name, sizeof(te->name))) { @@ -112,7 +123,7 @@ void qclib_load_and_run(void) { int i; - ssize_t ssize; + ssize_t data_size; struct mmu_context pre_qclib_mmu_context;
/* zero ddr_information SRAM region, needs new data each boot */ @@ -127,13 +138,23 @@ /* output area, QCLib fills in DDR details */ qclib_add_if_table_entry(QCLIB_TE_DDR_INFORMATION, NULL, 0, 0);
- /* Attempt to load DDR Training Blob */ - ssize = fmap_read_area(QCLIB_FR_DDR_TRAINING_DATA, _ddr_training, - REGION_SIZE(ddr_training)); - if (ssize < 0) - goto fail; + /* + * We never want to use training data when booting into + * recovery mode. + */ + if (vboot_recovery_mode_enabled()) { + memset(_ddr_training, 0, REGION_SIZE(ddr_training)); + } else { + /* Attempt to load DDR Training Blob */ + data_size = mrc_cache_load_current(MRC_TRAINING_DATA, QCLIB_VERSION, + _ddr_training, REGION_SIZE(ddr_training)); + if (data_size < 0) { + printk(BIOS_ERR, "Unable to load previous training data.\n"); + memset(_ddr_training, 0, REGION_SIZE(ddr_training)); + } + } qclib_add_if_table_entry(QCLIB_TE_DDR_TRAINING_DATA, - _ddr_training, ssize, 0); + _ddr_training, REGION_SIZE(ddr_training), 0);
/* hook for SoC specific binary blob loads */ if (qclib_soc_blob_load()) { diff --git a/src/soc/qualcomm/sc7180/Kconfig b/src/soc/qualcomm/sc7180/Kconfig index d543ef5..570b68a 100644 --- a/src/soc/qualcomm/sc7180/Kconfig +++ b/src/soc/qualcomm/sc7180/Kconfig @@ -17,6 +17,7 @@ select MAINBOARD_HAS_NATIVE_VGA_INIT select MAINBOARD_FORCE_NATIVE_VGA_INIT select HAVE_LINEAR_FRAMEBUFFER + select CACHE_MRC_SETTINGS
if SOC_QUALCOMM_SC7180
@@ -29,6 +30,7 @@ select VBOOT_RETURN_FROM_VERSTAGE select VBOOT_MUST_REQUEST_DISPLAY select VBOOT_STARTS_IN_BOOTBLOCK + select MRC_CLEAR_NORMAL_CACHE_ON_RECOVERY_RETRAIN
config SC7180_QSPI bool diff --git a/src/soc/qualcomm/sdm845/Kconfig b/src/soc/qualcomm/sdm845/Kconfig index c93ec6c..2b9bef3 100644 --- a/src/soc/qualcomm/sdm845/Kconfig +++ b/src/soc/qualcomm/sdm845/Kconfig @@ -9,6 +9,7 @@ select GENERIC_GPIO_LIB select ARM64_USE_ARCH_TIMER select SOC_QUALCOMM_COMMON + select CACHE_MRC_SETTINGS
if SOC_QUALCOMM_SDM845
@@ -21,6 +22,7 @@ select VBOOT_RETURN_FROM_VERSTAGE select VBOOT_MUST_REQUEST_DISPLAY select VBOOT_STARTS_IN_BOOTBLOCK + select MRC_CLEAR_NORMAL_CACHE_ON_RECOVERY_RETRAIN
config SDM845_QSPI bool
-
Julius Werner (Code Review) -
Shelley Chen (Code Review)