Change in coreboot[master]: soc/intel/elkhartlake: Adding PSE TSN support & PSE UPDs configs
Lean Sheng Tan has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47388 )
Change subject: soc/intel/elkhartlake: Adding PSE TSN support & PSE UPDs configs ......................................................................
soc/intel/elkhartlake: Adding PSE TSN support & PSE UPDs configs
Enabled PSE TSN feature & set the PSE TSN ports as host owned. Added options for user to add PSE TSN related configuration blobs to be consumed by FSP-S. THis patch also added PSE UPD related default settings.
Signed-off-by: Tan, Lean Sheng lean.sheng.tan@intel.com Change-Id: I18ff0e7120358fa371c09a2c33bae602794c007b --- M src/soc/intel/elkhartlake/Kconfig M src/soc/intel/elkhartlake/Makefile.inc M src/soc/intel/elkhartlake/fsp_params.c 3 files changed, 123 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/88/47388/1
diff --git a/src/soc/intel/elkhartlake/Kconfig b/src/soc/intel/elkhartlake/Kconfig index 7fc2e5f..0b005cc 100644 --- a/src/soc/intel/elkhartlake/Kconfig +++ b/src/soc/intel/elkhartlake/Kconfig @@ -207,6 +207,11 @@ help The path and filename of the PSE binary.
+config ENABLE_TSN + bool "Enable TSN ethernet" + help + Enable the initialization of PCH & PSE TSN ethernet. + config SOC_INTEL_ELKHARTLAKE_DEBUG_CONSENT int "Debug Consent for EHL" # USB DBC is more common for developers so make this default to 3 if @@ -226,4 +231,22 @@ config PRERAM_CBMEM_CONSOLE_SIZE hex default 0x1400 + +config TSN_MAC_ADDRESS_FILE + string "TSN MAC adress binary path and filename" + depends on ENABLE_TSN + help + The path and filename of the TSN mac adress binary. + +config TSN_CONFIG_FILE + string "TSN configuration binary path and filename" + depends on ENABLE_TSN + help + The path and filename of the TSN config file binary. + +config PSE_TSN_IP_FILE + string "PSE TSN configuration binary path and filename" + depends on ENABLE_TSN + help + The path and filename of the TSN config file binary. endif diff --git a/src/soc/intel/elkhartlake/Makefile.inc b/src/soc/intel/elkhartlake/Makefile.inc index 9456d4e..2c02db4 100644 --- a/src/soc/intel/elkhartlake/Makefile.inc +++ b/src/soc/intel/elkhartlake/Makefile.inc @@ -63,4 +63,19 @@ pse.bin-align := 0x1000 pse.bin-compression := lzma
+cbfs-files-$(CONFIG_ENABLE_TSN) += tsnmac.bin +tsnmac.bin-file := $(CONFIG_TSN_MAC_ADDRESS_FILE) +tsnmac.bin-type := raw +tsnmac.bin-align := 0x10 + +cbfs-files-$(CONFIG_ENABLE_TSN) += tsnconfig.bin +tsnconfig.bin-file := $(CONFIG_TSN_CONFIG_FILE) +tsnconfig.bin-type := raw +tsnconfig.bin-align := 0x10 + +cbfs-files-$(CONFIG_ENABLE_TSN) += psetsnipconfig.bin +psetsnipconfig.bin-file := $(CONFIG_PSE_TSN_IP_FILE) +psetsnipconfig.bin-type := raw +psetsnipconfig.bin-align := 0x10 + endif diff --git a/src/soc/intel/elkhartlake/fsp_params.c b/src/soc/intel/elkhartlake/fsp_params.c index 4ec2cab..51c7d47 100644 --- a/src/soc/intel/elkhartlake/fsp_params.c +++ b/src/soc/intel/elkhartlake/fsp_params.c @@ -60,13 +60,97 @@ parse_devicetree(params);
- if (CONFIG(PSE_IMAGE)){ + if (CONFIG(PSE_IMAGE)) + { //uint32_t psebase =0x0; static char psefw[256 * KiB]; size_t psefwsize = cbfs_boot_load_file("pse.bin", psefw, sizeof(psefw), CBFS_TYPE_RAW); params->SiipRegionBase = (uint32_t)&psefw; params->SiipRegionSize = psefwsize; + params->PchPseDmaEnable[0] = 0x1; + params->PchPseDmaEnable[1] = 0x1; + params->PchPseDmaEnable[2] = 0x1; + params->PchPseDmaSbInterruptEnable[0] = 0x0; + params->PchPseDmaSbInterruptEnable[1] = 0x1; + params->PchPseDmaSbInterruptEnable[2] = 0x1; + params->PchPseUartEnable[0] = 0x2; + params->PchPseUartEnable[1] = 0x1; + params->PchPseUartEnable[2] = 0x1; + params->PchPseHsuartEnable[0] = 0x1; + params->PchPseHsuartEnable[1] = 0x1; + params->PchPseHsuartEnable[2] = 0x1; + params->PchPseI2cEnable[2] = 0x1; + params->PchPseI2cEnable[7] = 0x1; + params->PchPseTimedGpioEnable[0] = 0x1; + params->PchPseTimedGpioEnable[1] = 0x1; + params->PchPseTimedGpioPinAllocation[0] = 0x0; + params->PchPseTimedGpioPinAllocation[1] = 0x0; + params->PchPseTimedGpioPinEnable[5] = 0x1; + params->PchPseTimedGpioPinEnable[6] = 0x1; + params->PchPseTimedGpioPinEnable[41] = 0x1; + params->PchPseTgpio6PinMux = 0x8B81A203; + params->PchPseTgpio7PinMux= 0x8B82A40B; + params->PchPseTgpio8PinMux= 0x8B80A607; + params->PchPseTgpio9PinMux= 0x8B80A808; + params->PchPseTgpio10PinMux= 0x8B86AA07; + params->PchPseTgpio11PinMux= 0x8B86AC0B; + params->PchPseTgpio12PinMux= 0x8B86AE13; + params->PchPseTgpio13PinMux= 0x8B85B00C; + params->PchPseTgpio14PinMux= 0x8B90B214; + params->PchPseTgpio15PinMux= 0x8B90B403; + params->PchPseTgpio16PinMux= 0x8B90B607; + params->PchPseTgpio17PinMux= 0x8B90B80F; + params->PchPseTgpio18PinMux= 0x8B90BA06; + params->PchPseTgpio19PinMux= 0x8B8DBC01; + params->PchPsePwmEnable = 0x1; + params->PchPsePwmPinEnable[15] = 0x0; + params->PchPsePwmPinMux[8]= 0x7B706604; + params->PchPsePwmPinMux[9]= 0x7B706805; + params->PchPsePwmPinMux[10]= 0x7B706A06; + params->PchPsePwmPinMux[11]= 0x7B706C11; + params->PchPsePwmPinMux[12]= 0x7B706E12; + params->PchPsePwmPinMux[13]= 0x7B707013; + params->PchPsePwmPinMux[14]= 0x4B64720A; + params->PchPsePwmPinMux[15]= 0x4B64740B; + params->PchPseSpiMosiPinMux[1]= 0x4B852003; + params->PchPseSpiMisoPinMux[1]= 0x4B853002; + params->PchPseSpiClkPinMux[1]= 0x4B854001; + params->PchPseSpiCs0PinMux[1]= 0x4B855000; + params->PchPseI2sTxPinMux[0]= 0x1B702610; + params->PchPseI2sRxPinMux[0]= 0x1B70160F; + params->PchPseI2sSfrmPinMux[0]= 0x1B704614; + params->PchPseI2sSclkPinMux[0]= 0x1B703615; + params->PchPseLh2PseSbInterruptEnable = 0x1; + params->PchPseLogOutputChannel = 0x3; + params->EnableAllThermalFunctions =0x1; + params->PchPseEcliteEnabled =0x0; + } + if (CONFIG(ENABLE_TSN)){ + params->PchPseGbeEnable[0]=config->PSE_TSN[0]; + params->PchPseGbeEnable[1]=config->PSE_TSN[1]; + + size_t sz; + params->TsnMacAddrBase = (uint32_t)cbfs_boot_map_with_leak(\ + "tsnmac.bin", \ + CBFS_TYPE_RAW, &sz); + params->TsnMacAddrSize = sz; + + params->TsnConfigBase = (uint32_t)cbfs_boot_map_with_leak(\ + "tsnconfig.bin", \ + CBFS_TYPE_RAW, &sz); + params->TsnConfigSize = sz; + + params->PseTsnIpConfigBase = (uint32_t)cbfs_boot_map_with_leak(\ + "psetsnipconfig.bin", \ + CBFS_TYPE_RAW, &sz); + params->PseTsnIpConfigSize = sz; + params->PchPseShellEnabled = 0x1; + params->PseTsnGbeSgmiiEnable[0]=0x1; + params->PseTsnGbeSgmiiEnable[1]=0x1; + params->PseTsnGbePhyInterfaceType[0]=0x1; + params->PseTsnGbePhyInterfaceType[1]=0x1; + } /* Override/Fill FSP Silicon Param for mainboard */ mainboard_silicon_init_params(params); }
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47388 )
Change subject: soc/intel/elkhartlake: Adding PSE TSN support & PSE UPDs configs ......................................................................
Patch Set 1:
(48 comments)
https://review.coreboot.org/c/coreboot/+/47388/1/src/soc/intel/elkhartlake/K... File src/soc/intel/elkhartlake/Kconfig:
https://review.coreboot.org/c/coreboot/+/47388/1/src/soc/intel/elkhartlake/K... PS1, Line 236: string "TSN MAC adress binary path and filename" 'adress' may be misspelled - perhaps 'address'?
https://review.coreboot.org/c/coreboot/+/47388/1/src/soc/intel/elkhartlake/K... PS1, Line 239: The path and filename of the TSN mac adress binary. 'adress' may be misspelled - perhaps 'address'?
https://review.coreboot.org/c/coreboot/+/47388/1/src/soc/intel/elkhartlake/f... File src/soc/intel/elkhartlake/fsp_params.c:
https://review.coreboot.org/c/coreboot/+/47388/1/src/soc/intel/elkhartlake/f... PS1, Line 63: if (CONFIG(PSE_IMAGE)) that open brace { should be on the previous line
https://review.coreboot.org/c/coreboot/+/47388/1/src/soc/intel/elkhartlake/f... PS1, Line 63: if (CONFIG(PSE_IMAGE)) suspect code indent for conditional statements (8, 8)
https://review.coreboot.org/c/coreboot/+/47388/1/src/soc/intel/elkhartlake/f... PS1, Line 93: params->PchPseTgpio7PinMux= 0x8B82A40B; spaces required around that '=' (ctx:VxW)
https://review.coreboot.org/c/coreboot/+/47388/1/src/soc/intel/elkhartlake/f... PS1, Line 94: params->PchPseTgpio8PinMux= 0x8B80A607; spaces required around that '=' (ctx:VxW)
https://review.coreboot.org/c/coreboot/+/47388/1/src/soc/intel/elkhartlake/f... PS1, Line 95: params->PchPseTgpio9PinMux= 0x8B80A808; spaces required around that '=' (ctx:VxW)
https://review.coreboot.org/c/coreboot/+/47388/1/src/soc/intel/elkhartlake/f... PS1, Line 96: params->PchPseTgpio10PinMux= 0x8B86AA07; spaces required around that '=' (ctx:VxW)
https://review.coreboot.org/c/coreboot/+/47388/1/src/soc/intel/elkhartlake/f... PS1, Line 97: params->PchPseTgpio11PinMux= 0x8B86AC0B; spaces required around that '=' (ctx:VxW)
https://review.coreboot.org/c/coreboot/+/47388/1/src/soc/intel/elkhartlake/f... PS1, Line 98: params->PchPseTgpio12PinMux= 0x8B86AE13; spaces required around that '=' (ctx:VxW)
https://review.coreboot.org/c/coreboot/+/47388/1/src/soc/intel/elkhartlake/f... PS1, Line 99: params->PchPseTgpio13PinMux= 0x8B85B00C; spaces required around that '=' (ctx:VxW)
https://review.coreboot.org/c/coreboot/+/47388/1/src/soc/intel/elkhartlake/f... PS1, Line 100: params->PchPseTgpio14PinMux= 0x8B90B214; spaces required around that '=' (ctx:VxW)
https://review.coreboot.org/c/coreboot/+/47388/1/src/soc/intel/elkhartlake/f... PS1, Line 101: params->PchPseTgpio15PinMux= 0x8B90B403; spaces required around that '=' (ctx:VxW)
https://review.coreboot.org/c/coreboot/+/47388/1/src/soc/intel/elkhartlake/f... PS1, Line 102: params->PchPseTgpio16PinMux= 0x8B90B607; spaces required around that '=' (ctx:VxW)
https://review.coreboot.org/c/coreboot/+/47388/1/src/soc/intel/elkhartlake/f... PS1, Line 103: params->PchPseTgpio17PinMux= 0x8B90B80F; spaces required around that '=' (ctx:VxW)
https://review.coreboot.org/c/coreboot/+/47388/1/src/soc/intel/elkhartlake/f... PS1, Line 104: params->PchPseTgpio18PinMux= 0x8B90BA06; spaces required around that '=' (ctx:VxW)
https://review.coreboot.org/c/coreboot/+/47388/1/src/soc/intel/elkhartlake/f... PS1, Line 105: params->PchPseTgpio19PinMux= 0x8B8DBC01; spaces required around that '=' (ctx:VxW)
https://review.coreboot.org/c/coreboot/+/47388/1/src/soc/intel/elkhartlake/f... PS1, Line 108: params->PchPsePwmPinMux[8]= 0x7B706604; spaces required around that '=' (ctx:VxW)
https://review.coreboot.org/c/coreboot/+/47388/1/src/soc/intel/elkhartlake/f... PS1, Line 109: params->PchPsePwmPinMux[9]= 0x7B706805; spaces required around that '=' (ctx:VxW)
https://review.coreboot.org/c/coreboot/+/47388/1/src/soc/intel/elkhartlake/f... PS1, Line 110: params->PchPsePwmPinMux[10]= 0x7B706A06; spaces required around that '=' (ctx:VxW)
https://review.coreboot.org/c/coreboot/+/47388/1/src/soc/intel/elkhartlake/f... PS1, Line 111: params->PchPsePwmPinMux[11]= 0x7B706C11; spaces required around that '=' (ctx:VxW)
https://review.coreboot.org/c/coreboot/+/47388/1/src/soc/intel/elkhartlake/f... PS1, Line 112: params->PchPsePwmPinMux[12]= 0x7B706E12; spaces required around that '=' (ctx:VxW)
https://review.coreboot.org/c/coreboot/+/47388/1/src/soc/intel/elkhartlake/f... PS1, Line 113: params->PchPsePwmPinMux[13]= 0x7B707013; spaces required around that '=' (ctx:VxW)
https://review.coreboot.org/c/coreboot/+/47388/1/src/soc/intel/elkhartlake/f... PS1, Line 114: params->PchPsePwmPinMux[14]= 0x4B64720A; spaces required around that '=' (ctx:VxW)
https://review.coreboot.org/c/coreboot/+/47388/1/src/soc/intel/elkhartlake/f... PS1, Line 115: params->PchPsePwmPinMux[15]= 0x4B64740B; spaces required around that '=' (ctx:VxW)
https://review.coreboot.org/c/coreboot/+/47388/1/src/soc/intel/elkhartlake/f... PS1, Line 116: params->PchPseSpiMosiPinMux[1]= 0x4B852003; spaces required around that '=' (ctx:VxW)
https://review.coreboot.org/c/coreboot/+/47388/1/src/soc/intel/elkhartlake/f... PS1, Line 117: params->PchPseSpiMisoPinMux[1]= 0x4B853002; spaces required around that '=' (ctx:VxW)
https://review.coreboot.org/c/coreboot/+/47388/1/src/soc/intel/elkhartlake/f... PS1, Line 118: params->PchPseSpiClkPinMux[1]= 0x4B854001; spaces required around that '=' (ctx:VxW)
https://review.coreboot.org/c/coreboot/+/47388/1/src/soc/intel/elkhartlake/f... PS1, Line 119: params->PchPseSpiCs0PinMux[1]= 0x4B855000; spaces required around that '=' (ctx:VxW)
https://review.coreboot.org/c/coreboot/+/47388/1/src/soc/intel/elkhartlake/f... PS1, Line 120: params->PchPseI2sTxPinMux[0]= 0x1B702610; spaces required around that '=' (ctx:VxW)
https://review.coreboot.org/c/coreboot/+/47388/1/src/soc/intel/elkhartlake/f... PS1, Line 121: params->PchPseI2sRxPinMux[0]= 0x1B70160F; spaces required around that '=' (ctx:VxW)
https://review.coreboot.org/c/coreboot/+/47388/1/src/soc/intel/elkhartlake/f... PS1, Line 122: params->PchPseI2sSfrmPinMux[0]= 0x1B704614; spaces required around that '=' (ctx:VxW)
https://review.coreboot.org/c/coreboot/+/47388/1/src/soc/intel/elkhartlake/f... PS1, Line 123: params->PchPseI2sSclkPinMux[0]= 0x1B703615; spaces required around that '=' (ctx:VxW)
https://review.coreboot.org/c/coreboot/+/47388/1/src/soc/intel/elkhartlake/f... PS1, Line 126: params->EnableAllThermalFunctions =0x1; spaces required around that '=' (ctx:WxV)
https://review.coreboot.org/c/coreboot/+/47388/1/src/soc/intel/elkhartlake/f... PS1, Line 127: params->PchPseEcliteEnabled =0x0; spaces required around that '=' (ctx:WxV)
https://review.coreboot.org/c/coreboot/+/47388/1/src/soc/intel/elkhartlake/f... PS1, Line 129: if (CONFIG(ENABLE_TSN)){ suspect code indent for conditional statements (8, 8)
https://review.coreboot.org/c/coreboot/+/47388/1/src/soc/intel/elkhartlake/f... PS1, Line 129: if (CONFIG(ENABLE_TSN)){ space required before the open brace '{'
https://review.coreboot.org/c/coreboot/+/47388/1/src/soc/intel/elkhartlake/f... PS1, Line 130: params->PchPseGbeEnable[0]=config->PSE_TSN[0]; spaces required around that '=' (ctx:VxV)
https://review.coreboot.org/c/coreboot/+/47388/1/src/soc/intel/elkhartlake/f... PS1, Line 131: params->PchPseGbeEnable[1]=config->PSE_TSN[1]; spaces required around that '=' (ctx:VxV)
https://review.coreboot.org/c/coreboot/+/47388/1/src/soc/intel/elkhartlake/f... PS1, Line 132: trailing whitespace
https://review.coreboot.org/c/coreboot/+/47388/1/src/soc/intel/elkhartlake/f... PS1, Line 134: params->TsnMacAddrBase = (uint32_t)cbfs_boot_map_with_leak(\ Avoid unnecessary line continuations
https://review.coreboot.org/c/coreboot/+/47388/1/src/soc/intel/elkhartlake/f... PS1, Line 138: trailing whitespace
https://review.coreboot.org/c/coreboot/+/47388/1/src/soc/intel/elkhartlake/f... PS1, Line 139: params->TsnConfigBase = (uint32_t)cbfs_boot_map_with_leak(\ Avoid unnecessary line continuations
https://review.coreboot.org/c/coreboot/+/47388/1/src/soc/intel/elkhartlake/f... PS1, Line 144: params->PseTsnIpConfigBase = (uint32_t)cbfs_boot_map_with_leak(\ Avoid unnecessary line continuations
https://review.coreboot.org/c/coreboot/+/47388/1/src/soc/intel/elkhartlake/f... PS1, Line 149: params->PseTsnGbeSgmiiEnable[0]=0x1; spaces required around that '=' (ctx:VxV)
https://review.coreboot.org/c/coreboot/+/47388/1/src/soc/intel/elkhartlake/f... PS1, Line 150: params->PseTsnGbeSgmiiEnable[1]=0x1; spaces required around that '=' (ctx:VxV)
https://review.coreboot.org/c/coreboot/+/47388/1/src/soc/intel/elkhartlake/f... PS1, Line 151: params->PseTsnGbePhyInterfaceType[0]=0x1; spaces required around that '=' (ctx:VxV)
https://review.coreboot.org/c/coreboot/+/47388/1/src/soc/intel/elkhartlake/f... PS1, Line 152: params->PseTsnGbePhyInterfaceType[1]=0x1; spaces required around that '=' (ctx:VxV)
Hello build bot (Jenkins), Patrick Georgi, Martin Roth, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/47388
to look at the new patch set (#2).
Change subject: soc/intel/elkhartlake: Adding PSE TSN support & PSE UPDs configs ......................................................................
soc/intel/elkhartlake: Adding PSE TSN support & PSE UPDs configs
Enabled PSE TSN feature & set the PSE TSN ports as host owned. Added options for user to add PSE TSN related configuration blobs to be consumed by FSP-S. THis patch also added PSE UPD related default settings.
Signed-off-by: Tan, Lean Sheng lean.sheng.tan@intel.com Change-Id: I18ff0e7120358fa371c09a2c33bae602794c007b --- M src/soc/intel/elkhartlake/Kconfig M src/soc/intel/elkhartlake/Makefile.inc M src/soc/intel/elkhartlake/fsp_params.c 3 files changed, 139 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/88/47388/2
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47388 )
Change subject: soc/intel/elkhartlake: Adding PSE TSN support & PSE UPDs configs ......................................................................
Patch Set 2:
(49 comments)
https://review.coreboot.org/c/coreboot/+/47388/2/src/soc/intel/elkhartlake/K... File src/soc/intel/elkhartlake/Kconfig:
https://review.coreboot.org/c/coreboot/+/47388/2/src/soc/intel/elkhartlake/K... PS2, Line 236: string "TSN MAC adress binary path and filename" 'adress' may be misspelled - perhaps 'address'?
https://review.coreboot.org/c/coreboot/+/47388/2/src/soc/intel/elkhartlake/K... PS2, Line 239: The path and filename of the TSN mac adress binary. 'adress' may be misspelled - perhaps 'address'?
https://review.coreboot.org/c/coreboot/+/47388/2/src/soc/intel/elkhartlake/f... File src/soc/intel/elkhartlake/fsp_params.c:
https://review.coreboot.org/c/coreboot/+/47388/2/src/soc/intel/elkhartlake/f... PS2, Line 42: PSE_CONFIG_PSEowned =0x1, spaces required around that '=' (ctx:WxV)
https://review.coreboot.org/c/coreboot/+/47388/2/src/soc/intel/elkhartlake/f... PS2, Line 79: if (CONFIG(PSE_IMAGE)) that open brace { should be on the previous line
https://review.coreboot.org/c/coreboot/+/47388/2/src/soc/intel/elkhartlake/f... PS2, Line 79: if (CONFIG(PSE_IMAGE)) suspect code indent for conditional statements (8, 8)
https://review.coreboot.org/c/coreboot/+/47388/2/src/soc/intel/elkhartlake/f... PS2, Line 109: params->PchPseTgpio7PinMux= 0x8B82A40B; spaces required around that '=' (ctx:VxW)
https://review.coreboot.org/c/coreboot/+/47388/2/src/soc/intel/elkhartlake/f... PS2, Line 110: params->PchPseTgpio8PinMux= 0x8B80A607; spaces required around that '=' (ctx:VxW)
https://review.coreboot.org/c/coreboot/+/47388/2/src/soc/intel/elkhartlake/f... PS2, Line 111: params->PchPseTgpio9PinMux= 0x8B80A808; spaces required around that '=' (ctx:VxW)
https://review.coreboot.org/c/coreboot/+/47388/2/src/soc/intel/elkhartlake/f... PS2, Line 112: params->PchPseTgpio10PinMux= 0x8B86AA07; spaces required around that '=' (ctx:VxW)
https://review.coreboot.org/c/coreboot/+/47388/2/src/soc/intel/elkhartlake/f... PS2, Line 113: params->PchPseTgpio11PinMux= 0x8B86AC0B; spaces required around that '=' (ctx:VxW)
https://review.coreboot.org/c/coreboot/+/47388/2/src/soc/intel/elkhartlake/f... PS2, Line 114: params->PchPseTgpio12PinMux= 0x8B86AE13; spaces required around that '=' (ctx:VxW)
https://review.coreboot.org/c/coreboot/+/47388/2/src/soc/intel/elkhartlake/f... PS2, Line 115: params->PchPseTgpio13PinMux= 0x8B85B00C; spaces required around that '=' (ctx:VxW)
https://review.coreboot.org/c/coreboot/+/47388/2/src/soc/intel/elkhartlake/f... PS2, Line 116: params->PchPseTgpio14PinMux= 0x8B90B214; spaces required around that '=' (ctx:VxW)
https://review.coreboot.org/c/coreboot/+/47388/2/src/soc/intel/elkhartlake/f... PS2, Line 117: params->PchPseTgpio15PinMux= 0x8B90B403; spaces required around that '=' (ctx:VxW)
https://review.coreboot.org/c/coreboot/+/47388/2/src/soc/intel/elkhartlake/f... PS2, Line 118: params->PchPseTgpio16PinMux= 0x8B90B607; spaces required around that '=' (ctx:VxW)
https://review.coreboot.org/c/coreboot/+/47388/2/src/soc/intel/elkhartlake/f... PS2, Line 119: params->PchPseTgpio17PinMux= 0x8B90B80F; spaces required around that '=' (ctx:VxW)
https://review.coreboot.org/c/coreboot/+/47388/2/src/soc/intel/elkhartlake/f... PS2, Line 120: params->PchPseTgpio18PinMux= 0x8B90BA06; spaces required around that '=' (ctx:VxW)
https://review.coreboot.org/c/coreboot/+/47388/2/src/soc/intel/elkhartlake/f... PS2, Line 121: params->PchPseTgpio19PinMux= 0x8B8DBC01; spaces required around that '=' (ctx:VxW)
https://review.coreboot.org/c/coreboot/+/47388/2/src/soc/intel/elkhartlake/f... PS2, Line 124: params->PchPsePwmPinMux[8]= 0x7B706604; spaces required around that '=' (ctx:VxW)
https://review.coreboot.org/c/coreboot/+/47388/2/src/soc/intel/elkhartlake/f... PS2, Line 125: params->PchPsePwmPinMux[9]= 0x7B706805; spaces required around that '=' (ctx:VxW)
https://review.coreboot.org/c/coreboot/+/47388/2/src/soc/intel/elkhartlake/f... PS2, Line 126: params->PchPsePwmPinMux[10]= 0x7B706A06; spaces required around that '=' (ctx:VxW)
https://review.coreboot.org/c/coreboot/+/47388/2/src/soc/intel/elkhartlake/f... PS2, Line 127: params->PchPsePwmPinMux[11]= 0x7B706C11; spaces required around that '=' (ctx:VxW)
https://review.coreboot.org/c/coreboot/+/47388/2/src/soc/intel/elkhartlake/f... PS2, Line 128: params->PchPsePwmPinMux[12]= 0x7B706E12; spaces required around that '=' (ctx:VxW)
https://review.coreboot.org/c/coreboot/+/47388/2/src/soc/intel/elkhartlake/f... PS2, Line 129: params->PchPsePwmPinMux[13]= 0x7B707013; spaces required around that '=' (ctx:VxW)
https://review.coreboot.org/c/coreboot/+/47388/2/src/soc/intel/elkhartlake/f... PS2, Line 130: params->PchPsePwmPinMux[14]= 0x4B64720A; spaces required around that '=' (ctx:VxW)
https://review.coreboot.org/c/coreboot/+/47388/2/src/soc/intel/elkhartlake/f... PS2, Line 131: params->PchPsePwmPinMux[15]= 0x4B64740B; spaces required around that '=' (ctx:VxW)
https://review.coreboot.org/c/coreboot/+/47388/2/src/soc/intel/elkhartlake/f... PS2, Line 132: params->PchPseSpiMosiPinMux[1]= 0x4B852003; spaces required around that '=' (ctx:VxW)
https://review.coreboot.org/c/coreboot/+/47388/2/src/soc/intel/elkhartlake/f... PS2, Line 133: params->PchPseSpiMisoPinMux[1]= 0x4B853002; spaces required around that '=' (ctx:VxW)
https://review.coreboot.org/c/coreboot/+/47388/2/src/soc/intel/elkhartlake/f... PS2, Line 134: params->PchPseSpiClkPinMux[1]= 0x4B854001; spaces required around that '=' (ctx:VxW)
https://review.coreboot.org/c/coreboot/+/47388/2/src/soc/intel/elkhartlake/f... PS2, Line 135: params->PchPseSpiCs0PinMux[1]= 0x4B855000; spaces required around that '=' (ctx:VxW)
https://review.coreboot.org/c/coreboot/+/47388/2/src/soc/intel/elkhartlake/f... PS2, Line 136: params->PchPseI2sTxPinMux[0]= 0x1B702610; spaces required around that '=' (ctx:VxW)
https://review.coreboot.org/c/coreboot/+/47388/2/src/soc/intel/elkhartlake/f... PS2, Line 137: params->PchPseI2sRxPinMux[0]= 0x1B70160F; spaces required around that '=' (ctx:VxW)
https://review.coreboot.org/c/coreboot/+/47388/2/src/soc/intel/elkhartlake/f... PS2, Line 138: params->PchPseI2sSfrmPinMux[0]= 0x1B704614; spaces required around that '=' (ctx:VxW)
https://review.coreboot.org/c/coreboot/+/47388/2/src/soc/intel/elkhartlake/f... PS2, Line 139: params->PchPseI2sSclkPinMux[0]= 0x1B703615; spaces required around that '=' (ctx:VxW)
https://review.coreboot.org/c/coreboot/+/47388/2/src/soc/intel/elkhartlake/f... PS2, Line 142: params->EnableAllThermalFunctions =0x1; spaces required around that '=' (ctx:WxV)
https://review.coreboot.org/c/coreboot/+/47388/2/src/soc/intel/elkhartlake/f... PS2, Line 143: params->PchPseEcliteEnabled =0x0; spaces required around that '=' (ctx:WxV)
https://review.coreboot.org/c/coreboot/+/47388/2/src/soc/intel/elkhartlake/f... PS2, Line 145: if (CONFIG(ENABLE_TSN)){ suspect code indent for conditional statements (8, 8)
https://review.coreboot.org/c/coreboot/+/47388/2/src/soc/intel/elkhartlake/f... PS2, Line 145: if (CONFIG(ENABLE_TSN)){ space required before the open brace '{'
https://review.coreboot.org/c/coreboot/+/47388/2/src/soc/intel/elkhartlake/f... PS2, Line 146: params->PchPseGbeEnable[0]=config->PSE_TSN[0]; spaces required around that '=' (ctx:VxV)
https://review.coreboot.org/c/coreboot/+/47388/2/src/soc/intel/elkhartlake/f... PS2, Line 147: params->PchPseGbeEnable[1]=config->PSE_TSN[1]; spaces required around that '=' (ctx:VxV)
https://review.coreboot.org/c/coreboot/+/47388/2/src/soc/intel/elkhartlake/f... PS2, Line 148: trailing whitespace
https://review.coreboot.org/c/coreboot/+/47388/2/src/soc/intel/elkhartlake/f... PS2, Line 150: params->TsnMacAddrBase = (uint32_t)cbfs_boot_map_with_leak(\ Avoid unnecessary line continuations
https://review.coreboot.org/c/coreboot/+/47388/2/src/soc/intel/elkhartlake/f... PS2, Line 154: trailing whitespace
https://review.coreboot.org/c/coreboot/+/47388/2/src/soc/intel/elkhartlake/f... PS2, Line 155: params->TsnConfigBase = (uint32_t)cbfs_boot_map_with_leak(\ Avoid unnecessary line continuations
https://review.coreboot.org/c/coreboot/+/47388/2/src/soc/intel/elkhartlake/f... PS2, Line 160: params->PseTsnIpConfigBase = (uint32_t)cbfs_boot_map_with_leak(\ Avoid unnecessary line continuations
https://review.coreboot.org/c/coreboot/+/47388/2/src/soc/intel/elkhartlake/f... PS2, Line 165: params->PseTsnGbeSgmiiEnable[0]=0x1; spaces required around that '=' (ctx:VxV)
https://review.coreboot.org/c/coreboot/+/47388/2/src/soc/intel/elkhartlake/f... PS2, Line 166: params->PseTsnGbeSgmiiEnable[1]=0x1; spaces required around that '=' (ctx:VxV)
https://review.coreboot.org/c/coreboot/+/47388/2/src/soc/intel/elkhartlake/f... PS2, Line 167: params->PseTsnGbePhyInterfaceType[0]=0x1; spaces required around that '=' (ctx:VxV)
https://review.coreboot.org/c/coreboot/+/47388/2/src/soc/intel/elkhartlake/f... PS2, Line 168: params->PseTsnGbePhyInterfaceType[1]=0x1; spaces required around that '=' (ctx:VxV)
Hello build bot (Jenkins), Patrick Georgi, Martin Roth, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/47388
to look at the new patch set (#3).
Change subject: soc/intel/elkhartlake: Adding PSE TSN support & PSE UPDs configs ......................................................................
soc/intel/elkhartlake: Adding PSE TSN support & PSE UPDs configs
Enabled PSE TSN feature & set the PSE TSN ports as host owned. Added options for user to add PSE TSN related configuration blobs to be consumed by FSP-S. THis patch also added PSE UPD related default settings.
Signed-off-by: Tan, Lean Sheng lean.sheng.tan@intel.com Change-Id: I18ff0e7120358fa371c09a2c33bae602794c007b --- M src/soc/intel/elkhartlake/Kconfig M src/soc/intel/elkhartlake/Makefile.inc M src/soc/intel/elkhartlake/fsp_params.c 3 files changed, 97 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/88/47388/3
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47388 )
Change subject: soc/intel/elkhartlake: Adding PSE TSN support & PSE UPDs configs ......................................................................
Patch Set 3:
(10 comments)
https://review.coreboot.org/c/coreboot/+/47388/3/src/soc/intel/elkhartlake/K... File src/soc/intel/elkhartlake/Kconfig:
https://review.coreboot.org/c/coreboot/+/47388/3/src/soc/intel/elkhartlake/K... PS3, Line 236: string "TSN MAC adress binary path and filename" 'adress' may be misspelled - perhaps 'address'?
https://review.coreboot.org/c/coreboot/+/47388/3/src/soc/intel/elkhartlake/K... PS3, Line 239: The path and filename of the TSN mac adress binary. 'adress' may be misspelled - perhaps 'address'?
https://review.coreboot.org/c/coreboot/+/47388/3/src/soc/intel/elkhartlake/f... File src/soc/intel/elkhartlake/fsp_params.c:
https://review.coreboot.org/c/coreboot/+/47388/3/src/soc/intel/elkhartlake/f... PS3, Line 36: PSE_CONFIG_PSEowned =0x1, spaces required around that '=' (ctx:WxV)
https://review.coreboot.org/c/coreboot/+/47388/3/src/soc/intel/elkhartlake/f... PS3, Line 104: if (CONFIG(ENABLE_TSN)){ suspect code indent for conditional statements (8, 8)
https://review.coreboot.org/c/coreboot/+/47388/3/src/soc/intel/elkhartlake/f... PS3, Line 104: if (CONFIG(ENABLE_TSN)){ space required before the open brace '{'
https://review.coreboot.org/c/coreboot/+/47388/3/src/soc/intel/elkhartlake/f... PS3, Line 107: trailing whitespace
https://review.coreboot.org/c/coreboot/+/47388/3/src/soc/intel/elkhartlake/f... PS3, Line 109: params->TsnMacAddrBase = (uint32_t)cbfs_boot_map_with_leak(\ Avoid unnecessary line continuations
https://review.coreboot.org/c/coreboot/+/47388/3/src/soc/intel/elkhartlake/f... PS3, Line 113: trailing whitespace
https://review.coreboot.org/c/coreboot/+/47388/3/src/soc/intel/elkhartlake/f... PS3, Line 114: params->TsnConfigBase = (uint32_t)cbfs_boot_map_with_leak(\ Avoid unnecessary line continuations
https://review.coreboot.org/c/coreboot/+/47388/3/src/soc/intel/elkhartlake/f... PS3, Line 119: params->PseTsnIpConfigBase = (uint32_t)cbfs_boot_map_with_leak(\ Avoid unnecessary line continuations
Hello build bot (Jenkins), Patrick Georgi, Martin Roth, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/47388
to look at the new patch set (#4).
Change subject: soc/intel/elkhartlake: Adding PSE TSN support & PSE UPDs configs ......................................................................
soc/intel/elkhartlake: Adding PSE TSN support & PSE UPDs configs
Enabled PSE TSN feature & set the PSE TSN ports as host owned. Added options for user to add PSE TSN related configuration blobs to be consumed by FSP-S. THis patch also added PSE UPD related default settings.
Signed-off-by: Tan, Lean Sheng lean.sheng.tan@intel.com Change-Id: I18ff0e7120358fa371c09a2c33bae602794c007b --- M src/soc/intel/elkhartlake/Kconfig M src/soc/intel/elkhartlake/Makefile.inc M src/soc/intel/elkhartlake/fsp_params.c 3 files changed, 94 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/88/47388/4
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47388 )
Change subject: soc/intel/elkhartlake: Adding PSE TSN support & PSE UPDs configs ......................................................................
Patch Set 4:
(4 comments)
https://review.coreboot.org/c/coreboot/+/47388/4/src/soc/intel/elkhartlake/K... File src/soc/intel/elkhartlake/Kconfig:
https://review.coreboot.org/c/coreboot/+/47388/4/src/soc/intel/elkhartlake/K... PS4, Line 236: string "TSN MAC adress binary path and filename" 'adress' may be misspelled - perhaps 'address'?
https://review.coreboot.org/c/coreboot/+/47388/4/src/soc/intel/elkhartlake/K... PS4, Line 239: The path and filename of the TSN mac adress binary. 'adress' may be misspelled - perhaps 'address'?
https://review.coreboot.org/c/coreboot/+/47388/4/src/soc/intel/elkhartlake/f... File src/soc/intel/elkhartlake/fsp_params.c:
https://review.coreboot.org/c/coreboot/+/47388/4/src/soc/intel/elkhartlake/f... PS4, Line 104: if (CONFIG(ENABLE_TSN)){ suspect code indent for conditional statements (8, 8)
https://review.coreboot.org/c/coreboot/+/47388/4/src/soc/intel/elkhartlake/f... PS4, Line 104: if (CONFIG(ENABLE_TSN)){ space required before the open brace '{'
Hello build bot (Jenkins), Patrick Georgi, Martin Roth, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/47388
to look at the new patch set (#5).
Change subject: soc/intel/elkhartlake: Adding PSE TSN support & PSE UPDs configs ......................................................................
soc/intel/elkhartlake: Adding PSE TSN support & PSE UPDs configs
Enabled PSE TSN feature & set the PSE TSN ports as host owned. Added options for user to add PSE TSN related configuration blobs to be consumed by FSP-S. THis patch also added PSE UPD related default settings.
Signed-off-by: Tan, Lean Sheng lean.sheng.tan@intel.com Change-Id: I18ff0e7120358fa371c09a2c33bae602794c007b --- M src/soc/intel/elkhartlake/Kconfig M src/soc/intel/elkhartlake/Makefile.inc M src/soc/intel/elkhartlake/fsp_params.c 3 files changed, 106 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/88/47388/5
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47388 )
Change subject: soc/intel/elkhartlake: Adding PSE TSN support & PSE UPDs configs ......................................................................
Patch Set 5:
(4 comments)
https://review.coreboot.org/c/coreboot/+/47388/5/src/soc/intel/elkhartlake/K... File src/soc/intel/elkhartlake/Kconfig:
https://review.coreboot.org/c/coreboot/+/47388/5/src/soc/intel/elkhartlake/K... PS5, Line 236: string "TSN MAC adress binary path and filename" 'adress' may be misspelled - perhaps 'address'?
https://review.coreboot.org/c/coreboot/+/47388/5/src/soc/intel/elkhartlake/K... PS5, Line 239: The path and filename of the TSN mac adress binary. 'adress' may be misspelled - perhaps 'address'?
https://review.coreboot.org/c/coreboot/+/47388/5/src/soc/intel/elkhartlake/f... File src/soc/intel/elkhartlake/fsp_params.c:
https://review.coreboot.org/c/coreboot/+/47388/5/src/soc/intel/elkhartlake/f... PS5, Line 84: if (CONFIG(PSE_IMAGE)) { suspect code indent for conditional statements (8, 8)
https://review.coreboot.org/c/coreboot/+/47388/5/src/soc/intel/elkhartlake/f... PS5, Line 115: if (CONFIG(ENABLE_TSN)) { suspect code indent for conditional statements (8, 8)
Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47388 )
Change subject: soc/intel/elkhartlake: Adding PSE TSN support & PSE UPDs configs ......................................................................
Patch Set 5:
(5 comments)
https://review.coreboot.org/c/coreboot/+/47388/5//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/47388/5//COMMIT_MSG@2 PS5, Line 2: Tan, Lean Sheng First name/last name is more common: *Lean Sheng Tan*.
https://review.coreboot.org/c/coreboot/+/47388/5//COMMIT_MSG@7 PS5, Line 7: Adding Imperative mood: Add
https://review.coreboot.org/c/coreboot/+/47388/5//COMMIT_MSG@9 PS5, Line 9: Enabled Enable
https://review.coreboot.org/c/coreboot/+/47388/5//COMMIT_MSG@10 PS5, Line 10: Added Add
https://review.coreboot.org/c/coreboot/+/47388/5//COMMIT_MSG@12 PS5, Line 12: THis This
Attention is currently required from: Lean Sheng Tan. Werner Zeh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47388 )
Change subject: soc/intel/elkhartlake: Adding PSE TSN support & PSE UPDs configs ......................................................................
Patch Set 5:
(5 comments)
File src/soc/intel/elkhartlake/Makefile.inc:
https://review.coreboot.org/c/coreboot/+/47388/comment/3e05f32b_74844fa9 PS5, Line 66: tsnmac.bin Since you use this filename in the code to access it, would it make sense to have a common define for it? Maybe even a Kconfig entry?
https://review.coreboot.org/c/coreboot/+/47388/comment/058b539c_1d909c6c PS5, Line 71: tsnconfig.bin Same here.
https://review.coreboot.org/c/coreboot/+/47388/comment/774feaf1_28e3149e PS5, Line 76: psetsnipconfig.bin And here.
File src/soc/intel/elkhartlake/fsp_params.c:
https://review.coreboot.org/c/coreboot/+/47388/comment/345ca16a_a8155714 PS5, Line 30: /** PCH PSE ownership assignments Woukd it make sense to drop the PSE_CONFIG_ prefix as this is already defined by the enum type?
https://review.coreboot.org/c/coreboot/+/47388/comment/c7c89351_bf5b7d26 PS5, Line 47: TSN_PHY_SGMII = 0x2, Same question here.
Lean Sheng Tan has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/47388 )
Change subject: soc/intel/elkhartlake: Adding PSE TSN support & PSE UPDs configs ......................................................................
Abandoned
Will resubmit a new one
-
build bot (Jenkins) (Code Review) -
Lean Sheng Tan (Code Review)
-
Paul Menzel (Code Review)
-
Werner Zeh (Code Review)