Lean Sheng Tan has uploaded this change for review.
soc/intel/elkhartlake: Adding PSE TSN support & PSE UPDs configs
Enabled PSE TSN feature & set the PSE TSN ports as host owned.
Added options for user to add PSE TSN related configuration blobs
to be consumed by FSP-S.
THis patch also added PSE UPD related default settings.
Signed-off-by: Tan, Lean Sheng <lean.sheng.tan@intel.com>
Change-Id: I18ff0e7120358fa371c09a2c33bae602794c007b
---
M src/soc/intel/elkhartlake/Kconfig
M src/soc/intel/elkhartlake/Makefile.inc
M src/soc/intel/elkhartlake/fsp_params.c
3 files changed, 123 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/88/47388/1
diff --git a/src/soc/intel/elkhartlake/Kconfig b/src/soc/intel/elkhartlake/Kconfig
index 7fc2e5f..0b005cc 100644
--- a/src/soc/intel/elkhartlake/Kconfig
+++ b/src/soc/intel/elkhartlake/Kconfig
@@ -207,6 +207,11 @@
help
The path and filename of the PSE binary.
+config ENABLE_TSN
+ bool "Enable TSN ethernet"
+ help
+ Enable the initialization of PCH & PSE TSN ethernet.
+
config SOC_INTEL_ELKHARTLAKE_DEBUG_CONSENT
int "Debug Consent for EHL"
# USB DBC is more common for developers so make this default to 3 if
@@ -226,4 +231,22 @@
config PRERAM_CBMEM_CONSOLE_SIZE
hex
default 0x1400
+
+config TSN_MAC_ADDRESS_FILE
+ string "TSN MAC adress binary path and filename"
+ depends on ENABLE_TSN
+ help
+ The path and filename of the TSN mac adress binary.
+
+config TSN_CONFIG_FILE
+ string "TSN configuration binary path and filename"
+ depends on ENABLE_TSN
+ help
+ The path and filename of the TSN config file binary.
+
+config PSE_TSN_IP_FILE
+ string "PSE TSN configuration binary path and filename"
+ depends on ENABLE_TSN
+ help
+ The path and filename of the TSN config file binary.
endif
diff --git a/src/soc/intel/elkhartlake/Makefile.inc b/src/soc/intel/elkhartlake/Makefile.inc
index 9456d4e..2c02db4 100644
--- a/src/soc/intel/elkhartlake/Makefile.inc
+++ b/src/soc/intel/elkhartlake/Makefile.inc
@@ -63,4 +63,19 @@
pse.bin-align := 0x1000
pse.bin-compression := lzma
+cbfs-files-$(CONFIG_ENABLE_TSN) += tsnmac.bin
+tsnmac.bin-file := $(CONFIG_TSN_MAC_ADDRESS_FILE)
+tsnmac.bin-type := raw
+tsnmac.bin-align := 0x10
+
+cbfs-files-$(CONFIG_ENABLE_TSN) += tsnconfig.bin
+tsnconfig.bin-file := $(CONFIG_TSN_CONFIG_FILE)
+tsnconfig.bin-type := raw
+tsnconfig.bin-align := 0x10
+
+cbfs-files-$(CONFIG_ENABLE_TSN) += psetsnipconfig.bin
+psetsnipconfig.bin-file := $(CONFIG_PSE_TSN_IP_FILE)
+psetsnipconfig.bin-type := raw
+psetsnipconfig.bin-align := 0x10
+
endif
diff --git a/src/soc/intel/elkhartlake/fsp_params.c b/src/soc/intel/elkhartlake/fsp_params.c
index 4ec2cab..51c7d47 100644
--- a/src/soc/intel/elkhartlake/fsp_params.c
+++ b/src/soc/intel/elkhartlake/fsp_params.c
@@ -60,13 +60,97 @@
parse_devicetree(params);
- if (CONFIG(PSE_IMAGE)){
+ if (CONFIG(PSE_IMAGE))
+ {
//uint32_t psebase =0x0;
static char psefw[256 * KiB];
size_t psefwsize = cbfs_boot_load_file("pse.bin",
psefw, sizeof(psefw), CBFS_TYPE_RAW);
params->SiipRegionBase = (uint32_t)&psefw;
params->SiipRegionSize = psefwsize;
+ params->PchPseDmaEnable[0] = 0x1;
+ params->PchPseDmaEnable[1] = 0x1;
+ params->PchPseDmaEnable[2] = 0x1;
+ params->PchPseDmaSbInterruptEnable[0] = 0x0;
+ params->PchPseDmaSbInterruptEnable[1] = 0x1;
+ params->PchPseDmaSbInterruptEnable[2] = 0x1;
+ params->PchPseUartEnable[0] = 0x2;
+ params->PchPseUartEnable[1] = 0x1;
+ params->PchPseUartEnable[2] = 0x1;
+ params->PchPseHsuartEnable[0] = 0x1;
+ params->PchPseHsuartEnable[1] = 0x1;
+ params->PchPseHsuartEnable[2] = 0x1;
+ params->PchPseI2cEnable[2] = 0x1;
+ params->PchPseI2cEnable[7] = 0x1;
+ params->PchPseTimedGpioEnable[0] = 0x1;
+ params->PchPseTimedGpioEnable[1] = 0x1;
+ params->PchPseTimedGpioPinAllocation[0] = 0x0;
+ params->PchPseTimedGpioPinAllocation[1] = 0x0;
+ params->PchPseTimedGpioPinEnable[5] = 0x1;
+ params->PchPseTimedGpioPinEnable[6] = 0x1;
+ params->PchPseTimedGpioPinEnable[41] = 0x1;
+ params->PchPseTgpio6PinMux = 0x8B81A203;
+ params->PchPseTgpio7PinMux= 0x8B82A40B;
+ params->PchPseTgpio8PinMux= 0x8B80A607;
+ params->PchPseTgpio9PinMux= 0x8B80A808;
+ params->PchPseTgpio10PinMux= 0x8B86AA07;
+ params->PchPseTgpio11PinMux= 0x8B86AC0B;
+ params->PchPseTgpio12PinMux= 0x8B86AE13;
+ params->PchPseTgpio13PinMux= 0x8B85B00C;
+ params->PchPseTgpio14PinMux= 0x8B90B214;
+ params->PchPseTgpio15PinMux= 0x8B90B403;
+ params->PchPseTgpio16PinMux= 0x8B90B607;
+ params->PchPseTgpio17PinMux= 0x8B90B80F;
+ params->PchPseTgpio18PinMux= 0x8B90BA06;
+ params->PchPseTgpio19PinMux= 0x8B8DBC01;
+ params->PchPsePwmEnable = 0x1;
+ params->PchPsePwmPinEnable[15] = 0x0;
+ params->PchPsePwmPinMux[8]= 0x7B706604;
+ params->PchPsePwmPinMux[9]= 0x7B706805;
+ params->PchPsePwmPinMux[10]= 0x7B706A06;
+ params->PchPsePwmPinMux[11]= 0x7B706C11;
+ params->PchPsePwmPinMux[12]= 0x7B706E12;
+ params->PchPsePwmPinMux[13]= 0x7B707013;
+ params->PchPsePwmPinMux[14]= 0x4B64720A;
+ params->PchPsePwmPinMux[15]= 0x4B64740B;
+ params->PchPseSpiMosiPinMux[1]= 0x4B852003;
+ params->PchPseSpiMisoPinMux[1]= 0x4B853002;
+ params->PchPseSpiClkPinMux[1]= 0x4B854001;
+ params->PchPseSpiCs0PinMux[1]= 0x4B855000;
+ params->PchPseI2sTxPinMux[0]= 0x1B702610;
+ params->PchPseI2sRxPinMux[0]= 0x1B70160F;
+ params->PchPseI2sSfrmPinMux[0]= 0x1B704614;
+ params->PchPseI2sSclkPinMux[0]= 0x1B703615;
+ params->PchPseLh2PseSbInterruptEnable = 0x1;
+ params->PchPseLogOutputChannel = 0x3;
+ params->EnableAllThermalFunctions =0x1;
+ params->PchPseEcliteEnabled =0x0;
+ }
+ if (CONFIG(ENABLE_TSN)){
+ params->PchPseGbeEnable[0]=config->PSE_TSN[0];
+ params->PchPseGbeEnable[1]=config->PSE_TSN[1];
+
+ size_t sz;
+ params->TsnMacAddrBase = (uint32_t)cbfs_boot_map_with_leak(\
+ "tsnmac.bin", \
+ CBFS_TYPE_RAW, &sz);
+ params->TsnMacAddrSize = sz;
+
+ params->TsnConfigBase = (uint32_t)cbfs_boot_map_with_leak(\
+ "tsnconfig.bin", \
+ CBFS_TYPE_RAW, &sz);
+ params->TsnConfigSize = sz;
+
+ params->PseTsnIpConfigBase = (uint32_t)cbfs_boot_map_with_leak(\
+ "psetsnipconfig.bin", \
+ CBFS_TYPE_RAW, &sz);
+ params->PseTsnIpConfigSize = sz;
+ params->PchPseShellEnabled = 0x1;
+ params->PseTsnGbeSgmiiEnable[0]=0x1;
+ params->PseTsnGbeSgmiiEnable[1]=0x1;
+ params->PseTsnGbePhyInterfaceType[0]=0x1;
+ params->PseTsnGbePhyInterfaceType[1]=0x1;
+ }
/* Override/Fill FSP Silicon Param for mainboard */
mainboard_silicon_init_params(params);
}
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