Change in coreboot[master]: soc/intel/{apl,cnl,icl,skl,tgl}: Make above 4GB MMIO resource proper
Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38125 )
Change subject: soc/intel/{apl,cnl,icl,skl,tgl}: Make above 4GB MMIO resource proper ......................................................................
soc/intel/{apl,cnl,icl,skl,tgl}: Make above 4GB MMIO resource proper
This patch ensures coreboot is not publishing above 4GB mmio resource if soc common config "enable_above_4GB_mmio" not enable.
Publishing unnecessary 4GB above MMIO resource with wrong base and size is causing problem while working with discrete GPU.
Unable to boot with dGPU on IA platform with below error:
[ 2.297425] pcieport 0000:00:1c.0: PCI bridge to [bus 05] [ 2.302858] pcieport 0000:00:1c.0: bridge window [io 0x2000-0x2fff] [ 2.309427] pcieport 0000:00:1c.0: bridge window [mem 0xb2000000-0xb20fffff] [ 2.316679] pcieport 0000:00:1c.0: bridge window [mem 0x840000000-0x8c01fffff 64bit pref] [ 2.325072] pcieport 0000:00:1c.0: PCI bridge to [bus 05] [ 2.330502] pcieport 0000:00:1c.0: bridge window [io 0x2000-0x2fff] [ 2.337062] pcieport 0000:00:1c.0: bridge window [mem 0xb2000000-0xb20fffff] [ 2.344317] pcieport 0000:00:1c.0: bridge window [mem 0xa0000000-0xb01fffff 64bit pref] [ 2.352541] [drm] Not enough PCI address space for a large BAR.
Change-Id: I77b3a0e44582b047d7fbe679d3000d616f7e6111 Signed-off-by: Subrata Banik subrata.banik@intel.com --- M src/soc/intel/apollolake/acpi.c M src/soc/intel/apollolake/acpi/globalnvs.asl M src/soc/intel/apollolake/acpi/northbridge.asl M src/soc/intel/apollolake/include/soc/iomap.h M src/soc/intel/apollolake/include/soc/nvs.h M src/soc/intel/cannonlake/acpi.c M src/soc/intel/cannonlake/acpi/northbridge.asl M src/soc/intel/cannonlake/include/soc/iomap.h M src/soc/intel/common/block/acpi/acpi/globalnvs.asl M src/soc/intel/common/block/include/intelblocks/cfg.h M src/soc/intel/common/block/include/intelblocks/nvs.h M src/soc/intel/common/block/include/intelblocks/systemagent.h M src/soc/intel/common/block/systemagent/systemagent.c M src/soc/intel/icelake/acpi.c M src/soc/intel/icelake/acpi/northbridge.asl M src/soc/intel/icelake/include/soc/iomap.h M src/soc/intel/skylake/acpi.c M src/soc/intel/skylake/acpi/globalnvs.asl M src/soc/intel/skylake/acpi/systemagent.asl M src/soc/intel/skylake/include/soc/iomap.h M src/soc/intel/skylake/include/soc/nvs.h M src/soc/intel/tigerlake/acpi.c M src/soc/intel/tigerlake/acpi/northbridge.asl M src/soc/intel/tigerlake/include/soc/iomap.h 24 files changed, 139 insertions(+), 75 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/25/38125/1
diff --git a/src/soc/intel/apollolake/acpi.c b/src/soc/intel/apollolake/acpi.c index 7163884..ab1ef3c 100644 --- a/src/soc/intel/apollolake/acpi.c +++ b/src/soc/intel/apollolake/acpi.c @@ -127,6 +127,9 @@
if (CONFIG(SOC_INTEL_COMMON_BLOCK_SGX)) sgx_fill_gnvs(gnvs); + + /* Fill in Above 4GB MMIO resource */ + sa_fill_gnvs(gnvs); }
uint32_t acpi_fill_soc_wake(uint32_t generic_pm1_en, diff --git a/src/soc/intel/apollolake/acpi/globalnvs.asl b/src/soc/intel/apollolake/acpi/globalnvs.asl index 4aad29c..edba848 100644 --- a/src/soc/intel/apollolake/acpi/globalnvs.asl +++ b/src/soc/intel/apollolake/acpi/globalnvs.asl @@ -45,6 +45,9 @@ EPCS, 8, // 0x2C - SGX Enabled status EMNA, 64, // 0x2D - 0x34 EPC base address ELNG, 64, // 0x35 - 0x3C EPC Length + E4GM, 8, // 0x3D - Enable above 4GB MMIO Resource + A4GB, 64, // 0x3E - 0x45 Base of above 4GB MMIO Resource + A4GS, 64, // 0x46 - 0x4D Length of above 4GB MMIO Resource
/* ChromeOS stuff (0x100 -> 0xfff, size 0xeff) */ Offset (0x100), diff --git a/src/soc/intel/apollolake/acpi/northbridge.asl b/src/soc/intel/apollolake/acpi/northbridge.asl index 2f2a064..23597d8 100644 --- a/src/soc/intel/apollolake/acpi/northbridge.asl +++ b/src/soc/intel/apollolake/acpi/northbridge.asl @@ -114,18 +114,18 @@ Add(Subtract(GMAX, GMIN), 1, GLEN)
/* Patch PM02 range based on Memory Size */ - CreateQwordField (MCRS, ^PM02._MIN, MMIN) - CreateQwordField (MCRS, ^PM02._MAX, MMAX) - CreateQwordField (MCRS, ^PM02._LEN, MLEN) - - Store (^MCHC.TUUD, Local0) - - If (LLessEqual (Local0, 0x1000000000)) - { - Store (0, MMIN) - Store (0, MLEN) + If (LEqual (A4GS, 0)) { + CreateQwordField (^MCRS, ^PM02._LEN, MSEN) + Store (0, MSEN) + } Else { + CreateQwordField (^MCRS, ^PM02._MIN, MMIN) + CreateQwordField (^MCRS, ^PM02._MAX, MMAX) + CreateQwordField (^MCRS, ^PM02._LEN, MLEN) + /* Set 64bit MMIO resource base and length */ + Store (A4GS, MLEN) + Store (A4GB, MMIN) + Subtract (Add (MMIN, MLEN), 1, MMAX) } - Subtract (Add (MMIN, MLEN), 1, MMAX)
Return (MCRS) } diff --git a/src/soc/intel/apollolake/include/soc/iomap.h b/src/soc/intel/apollolake/include/soc/iomap.h index 3057fbe..22c982b 100644 --- a/src/soc/intel/apollolake/include/soc/iomap.h +++ b/src/soc/intel/apollolake/include/soc/iomap.h @@ -60,4 +60,7 @@ #define EARLY_I2C_BASE_ADDRESS 0xfe020000 #define EARLY_I2C_BASE(x) (EARLY_I2C_BASE_ADDRESS + (0x1000 * (x)))
+#define ABOVE_4GB_MEM_BASE_ADDRESS (128*GiB) +#define ABOVE_4GB_MEM_BASE_SIZE (64*GiB) + #endif /* _SOC_APOLLOLAKE_IOMAP_H_ */ diff --git a/src/soc/intel/apollolake/include/soc/nvs.h b/src/soc/intel/apollolake/include/soc/nvs.h index 6c37d59..5d9ac6a 100644 --- a/src/soc/intel/apollolake/include/soc/nvs.h +++ b/src/soc/intel/apollolake/include/soc/nvs.h @@ -47,7 +47,10 @@ uint8_t ecps; /* 0x2C - SGX Enabled status */ uint64_t emna; /* 0x2D - 0x34 EPC base address */ uint64_t elng; /* 0x35 - 0x3C EPC Length */ - uint8_t unused[195]; + uint8_t e4gm; /* 0x3D - Enable above 4GB MMIO Resource */ + uint64_t a4gb; /* 0x3E - 0x45 Base of above 4GB MMIO Resource */ + uint64_t a4gs; /* 0x46 - 0x4D Length of above 4GB MMIO Resource */ + uint8_t unused[178];
/* ChromeOS specific (0x100 - 0xfff) */ chromeos_acpi_t chromeos; diff --git a/src/soc/intel/cannonlake/acpi.c b/src/soc/intel/cannonlake/acpi.c index 6d1970b..a8add4d 100644 --- a/src/soc/intel/cannonlake/acpi.c +++ b/src/soc/intel/cannonlake/acpi.c @@ -231,6 +231,9 @@ /* Set USB2/USB3 wake enable bitmaps. */ gnvs->u2we = config->usb2_wake_enable_bitmap; gnvs->u3we = config->usb3_wake_enable_bitmap; + + /* Fill in Above 4GB MMIO resource */ + sa_fill_gnvs(gnvs); }
uint32_t acpi_fill_soc_wake(uint32_t generic_pm1_en, diff --git a/src/soc/intel/cannonlake/acpi/northbridge.asl b/src/soc/intel/cannonlake/acpi/northbridge.asl index 2529116..e778ae1 100644 --- a/src/soc/intel/cannonlake/acpi/northbridge.asl +++ b/src/soc/intel/cannonlake/acpi/northbridge.asl @@ -17,9 +17,6 @@
#include <soc/iomap.h>
-#define BASE_32GB 0x800000000 -#define SIZE_16GB 0x400000000 - Name (_HID, EisaId ("PNP0A08") /* PCI Express Bus */) // _HID: Hardware ID Name (_CID, EisaId ("PNP0A03") /* PCI Bus */) // _CID: Compatible ID Name (_SEG, Zero) // _SEG: PCI Segment @@ -205,20 +202,18 @@ Add (Subtract (PMAX, PMIN), 1, PLEN)
/* Patch PM02 range based on Memory Size */ - CreateQwordField (^MCRS, ^PM02._MIN, MMIN) - CreateQwordField (^MCRS, ^PM02._MAX, MMAX) - CreateQwordField (^MCRS, ^PM02._LEN, MLEN) - - Store (^MCHC.TUUD, Local0) - - If (LLessEqual (Local0, BASE_32GB)) { - Store (BASE_32GB, MMIN) - Store (SIZE_16GB, MLEN) + If (LEqual (A4GS, 0)) { + CreateQwordField (^MCRS, ^PM02._LEN, MSEN) + Store (0, MSEN) } Else { - Store (0, MMIN) - Store (0, MLEN) + CreateQwordField (^MCRS, ^PM02._MIN, MMIN) + CreateQwordField (^MCRS, ^PM02._MAX, MMAX) + CreateQwordField (^MCRS, ^PM02._LEN, MLEN) + /* Set 64bit MMIO resource base and length */ + Store (A4GS, MLEN) + Store (A4GB, MMIN) + Subtract (Add (MMIN, MLEN), 1, MMAX) } - Subtract (Add (MMIN, MLEN), 1, MMAX)
Return (^MCRS) } diff --git a/src/soc/intel/cannonlake/include/soc/iomap.h b/src/soc/intel/cannonlake/include/soc/iomap.h index 9cfb59e..a0a37d9 100644 --- a/src/soc/intel/cannonlake/include/soc/iomap.h +++ b/src/soc/intel/cannonlake/include/soc/iomap.h @@ -68,6 +68,9 @@
#define HECI1_BASE_ADDRESS 0xfeda2000
+#define ABOVE_4GB_MEM_BASE_ADDRESS 0x4000000000 +#define ABOVE_4GB_MEM_BASE_SIZE 0x4000000000 + /* PTT registers */ #define PTT_TXT_BASE_ADDRESS 0xfed30800 #define PTT_PRESENT 0x00070000 diff --git a/src/soc/intel/common/block/acpi/acpi/globalnvs.asl b/src/soc/intel/common/block/acpi/acpi/globalnvs.asl index 8e8241b..82c4c9e 100644 --- a/src/soc/intel/common/block/acpi/acpi/globalnvs.asl +++ b/src/soc/intel/common/block/acpi/acpi/globalnvs.asl @@ -47,6 +47,9 @@ U2WE, 16, // 0x2b - 0x2c USB2 Wake Enable Bitmap U3WE, 16, // 0x2d - 0x2e USB3 Wake Enable Bitmap UIOR, 8, // 0x2f - UART debug controller init on S3 resume + E4GM, 8, // 0x30 - Enable above 4GB MMIO Resource + A4GB, 64, // 0x31 - 0x38 Base of above 4GB MMIO Resource + A4GS, 64, // 0x39 - 0x40 Length of above 4GB MMIO Resource
/* ChromeOS specific */ Offset (0x100), diff --git a/src/soc/intel/common/block/include/intelblocks/cfg.h b/src/soc/intel/common/block/include/intelblocks/cfg.h index e7e381b..7c83b54 100644 --- a/src/soc/intel/common/block/include/intelblocks/cfg.h +++ b/src/soc/intel/common/block/include/intelblocks/cfg.h @@ -37,6 +37,7 @@ /* PCH Thermal Trip Temperature in deg C */ uint8_t pch_thermal_trip; struct mmc_dll_params emmc_dll; + int enable_above_4GB_mmio; };
/* This function to retrieve soc config structure required by common code */ diff --git a/src/soc/intel/common/block/include/intelblocks/nvs.h b/src/soc/intel/common/block/include/intelblocks/nvs.h index 5f367b6..ec8cdb3 100644 --- a/src/soc/intel/common/block/include/intelblocks/nvs.h +++ b/src/soc/intel/common/block/include/intelblocks/nvs.h @@ -38,7 +38,10 @@ u16 u2we; /* 0x2b - 0x2c USB2 Wake Enable Bitmap */ u16 u3we; /* 0x2d - 0x2e USB3 Wake Enable Bitmap */ u8 uior; /* 0x2f - UART debug controller init on S3 resume */ - u8 unused[208]; + u8 e4gm; /* 0x30 - Enable above 4GB MMIO Resource */ + u64 a4gb; /* 0x31 - 0x38 Base of above 4GB MMIO Resource */ + u64 a4gs; /* 0x39 - 0x40 Length of above 4GB MMIO Resource */ + u8 unused[191];
/* ChromeOS specific (0x100 - 0xfff) */ chromeos_acpi_t chromeos; diff --git a/src/soc/intel/common/block/include/intelblocks/systemagent.h b/src/soc/intel/common/block/include/intelblocks/systemagent.h index 163d97e..a018e55 100644 --- a/src/soc/intel/common/block/include/intelblocks/systemagent.h +++ b/src/soc/intel/common/block/include/intelblocks/systemagent.h @@ -18,6 +18,7 @@
#include <device/device.h> #include <soc/iomap.h> +#include <soc/nvs.h> #include <stddef.h>
/* Device 0:0.0 PCI configuration space */ @@ -82,6 +83,8 @@ uintptr_t sa_get_tseg_base(void); /* API to get TSEG size */ size_t sa_get_tseg_size(void); +/* Fill MMIO resource above 4GB into GNVS */ +void sa_fill_gnvs(global_nvs_t *gnvs); /* * SoC overrides * diff --git a/src/soc/intel/common/block/systemagent/systemagent.c b/src/soc/intel/common/block/systemagent/systemagent.c index 2019ef6..5a9c3a8 100644 --- a/src/soc/intel/common/block/systemagent/systemagent.c +++ b/src/soc/intel/common/block/systemagent/systemagent.c @@ -14,12 +14,14 @@ * GNU General Public License for more details. */
-#include <device/pci_ops.h> #include <cbmem.h> +#include <console/console.h> +#include <device/pci_ops.h> #include <device/device.h> #include <device/pci.h> #include <device/pci_ids.h> #include <intelblocks/acpi.h> +#include <intelblocks/cfg.h> #include <intelblocks/systemagent.h> #include <smbios.h> #include <soc/iomap.h> @@ -54,6 +56,34 @@ }
/* + * This function will get above 4GB mmio enable config specific to soc. + * + * Return values: + * 0 = Above 4GB memory is not enable + * 1 = Above 4GB memory is enable + */ +static int get_enable_above_4GB_mmio(void) +{ + const struct soc_intel_common_config *common_config; + common_config = chip_get_common_soc_structure(); + + return common_config->enable_above_4GB_mmio; +} + +/* Fill MMIO resource above 4GB into GNVS */ +void sa_fill_gnvs(global_nvs_t *gnvs) +{ + if (get_enable_above_4GB_mmio()) { + gnvs->e4gm = 1; + gnvs->a4gb = ABOVE_4GB_MEM_BASE_ADDRESS; + gnvs->a4gs = ABOVE_4GB_MEM_BASE_SIZE; + printk(BIOS_DEBUG, + "PCI space above 4GB MMIO is from 0x%llx to len = 0x%llx\n", + gnvs->a4gb, gnvs->a4gb); + } +} + +/* * Add all known fixed MMIO ranges that hang off the host bridge/memory * controller device. */ diff --git a/src/soc/intel/icelake/acpi.c b/src/soc/intel/icelake/acpi.c index 728cfb1..9610e9e 100644 --- a/src/soc/intel/icelake/acpi.c +++ b/src/soc/intel/icelake/acpi.c @@ -223,6 +223,9 @@ /* Set USB2/USB3 wake enable bitmaps. */ gnvs->u2we = config->usb2_wake_enable_bitmap; gnvs->u3we = config->usb3_wake_enable_bitmap; + + /* Fill in Above 4GB MMIO resource */ + sa_fill_gnvs(gnvs); }
uint32_t acpi_fill_soc_wake(uint32_t generic_pm1_en, diff --git a/src/soc/intel/icelake/acpi/northbridge.asl b/src/soc/intel/icelake/acpi/northbridge.asl index 68c7f9e..745660e 100644 --- a/src/soc/intel/icelake/acpi/northbridge.asl +++ b/src/soc/intel/icelake/acpi/northbridge.asl @@ -16,9 +16,6 @@
#include <soc/iomap.h>
-#define BASE_32GB 0x800000000 -#define SIZE_16GB 0x400000000 - Name (_HID, EisaId ("PNP0A08") /* PCI Express Bus */) // _HID: Hardware ID Name (_CID, EisaId ("PNP0A03") /* PCI Bus */) // _CID: Compatible ID Name (_SEG, Zero) // _SEG: PCI Segment @@ -206,20 +203,18 @@ Add (Subtract (PMAX, PMIN), 1, PLEN)
/* Patch PM02 range based on Memory Size */ - CreateQwordField (^MCRS, ^PM02._MIN, MMIN) - CreateQwordField (^MCRS, ^PM02._MAX, MMAX) - CreateQwordField (^MCRS, ^PM02._LEN, MLEN) - - Store (^MCHC.TUUD, Local0) - - If (LLessEqual (Local0, BASE_32GB)) { - Store (BASE_32GB, MMIN) - Store (SIZE_16GB, MLEN) + If (LEqual (A4GS, 0)) { + CreateQwordField (^MCRS, ^PM02._LEN, MSEN) + Store (0, MSEN) } Else { - Store (0, MMIN) - Store (0, MLEN) + CreateQwordField (^MCRS, ^PM02._MIN, MMIN) + CreateQwordField (^MCRS, ^PM02._MAX, MMAX) + CreateQwordField (^MCRS, ^PM02._LEN, MLEN) + /* Set 64bit MMIO resource base and length */ + Store (A4GS, MLEN) + Store (A4GB, MMIN) + Subtract (Add (MMIN, MLEN), 1, MMAX) } - Subtract (Add (MMIN, MLEN), 1, MMAX)
Return (^MCRS) } diff --git a/src/soc/intel/icelake/include/soc/iomap.h b/src/soc/intel/icelake/include/soc/iomap.h index 218b8bf..02f8a06 100644 --- a/src/soc/intel/icelake/include/soc/iomap.h +++ b/src/soc/intel/icelake/include/soc/iomap.h @@ -60,6 +60,10 @@
#define VTD_BASE_ADDRESS 0xFED90000 #define VTD_BASE_SIZE 0x00004000 + +#define ABOVE_4GB_MEM_BASE_ADDRESS (256*GiB) +#define ABOVE_4GB_MEM_BASE_SIZE (256*GiB) + /* * I/O port address space */ diff --git a/src/soc/intel/skylake/acpi.c b/src/soc/intel/skylake/acpi.c index 332f797..c200927 100644 --- a/src/soc/intel/skylake/acpi.c +++ b/src/soc/intel/skylake/acpi.c @@ -207,6 +207,9 @@
if (CONFIG(SOC_INTEL_COMMON_BLOCK_SGX_ENABLE)) sgx_fill_gnvs(gnvs); + + /* Fill in Above 4GB MMIO resource */ + sa_fill_gnvs(gnvs); }
unsigned long acpi_fill_mcfg(unsigned long current) diff --git a/src/soc/intel/skylake/acpi/globalnvs.asl b/src/soc/intel/skylake/acpi/globalnvs.asl index c4544e8..6c3e11a 100644 --- a/src/soc/intel/skylake/acpi/globalnvs.asl +++ b/src/soc/intel/skylake/acpi/globalnvs.asl @@ -70,6 +70,9 @@ EPCS, 8, // 0x43 - SGX Enabled status EMNA, 64, // 0x44 - 0x4B EPC base address ELNG, 64, // 0x4C - 0x53 EPC Length + E4GM, 8, // 0x54 - Enable above 4GB MMIO Resource + A4GB, 64, // 0x55 - 0x5C Base of above 4GB MMIO Resource + A4GS, 64, // 0x5D - 0x64 Length of above 4GB MMIO Resource
/* IGD OpRegion */ Offset (0xb4), diff --git a/src/soc/intel/skylake/acpi/systemagent.asl b/src/soc/intel/skylake/acpi/systemagent.asl index e7b2d90..d2141d5 100644 --- a/src/soc/intel/skylake/acpi/systemagent.asl +++ b/src/soc/intel/skylake/acpi/systemagent.asl @@ -17,9 +17,6 @@
#include <soc/iomap.h>
-#define BASE_32GB 0x800000000 -#define SIZE_16GB 0x400000000 - Name (_HID, EISAID ("PNP0A08")) /* PCIe */ Name (_CID, EISAID ("PNP0A03")) /* PCI */
@@ -219,20 +216,18 @@ Add (Subtract (PMAX, PMIN), 1, PLEN)
/* Patch PM02 range based on Memory Size */ - CreateQwordField (^MCRS, ^PM02._MIN, MMIN) - CreateQwordField (^MCRS, ^PM02._MAX, MMAX) - CreateQwordField (^MCRS, ^PM02._LEN, MLEN) - - Store (^MCHC.TUUD, Local0) - - If (LLessEqual (Local0, BASE_32GB)) { - Store (BASE_32GB, MMIN) - Store (SIZE_16GB, MLEN) + If (LEqual (A4GS, 0)) { + CreateQwordField (^MCRS, ^PM02._LEN, MSEN) + Store (0, MSEN) } Else { - Store (0, MMIN) - Store (0, MLEN) + CreateQwordField (^MCRS, ^PM02._MIN, MMIN) + CreateQwordField (^MCRS, ^PM02._MAX, MMAX) + CreateQwordField (^MCRS, ^PM02._LEN, MLEN) + /* Set 64bit MMIO resource base and length */ + Store (A4GS, MLEN) + Store (A4GB, MMIN) + Subtract (Add (MMIN, MLEN), 1, MMAX) } - Subtract (Add (MMIN, MLEN), 1, MMAX)
Return (^MCRS) } diff --git a/src/soc/intel/skylake/include/soc/iomap.h b/src/soc/intel/skylake/include/soc/iomap.h index c73d766..fc77d3d 100644 --- a/src/soc/intel/skylake/include/soc/iomap.h +++ b/src/soc/intel/skylake/include/soc/iomap.h @@ -72,6 +72,9 @@ #define PTT_TXT_BASE_ADDRESS 0xfed30800 #define PTT_PRESENT 0x00070000
+#define ABOVE_4GB_MEM_BASE_ADDRESS (128*GiB) +#define ABOVE_4GB_MEM_BASE_SIZE (64*GiB) + /* * I/O port address space */ diff --git a/src/soc/intel/skylake/include/soc/nvs.h b/src/soc/intel/skylake/include/soc/nvs.h index 72b1ac9..aa692c07 100644 --- a/src/soc/intel/skylake/include/soc/nvs.h +++ b/src/soc/intel/skylake/include/soc/nvs.h @@ -60,7 +60,10 @@ u8 ecps; /* 0x43 - SGX Enabled status */ u64 emna; /* 0x44 - 0x4B EPC base address */ u64 elng; /* 0x4C - 0x53 EPC Length */ - u8 rsvd[96]; + u8 e4gm; /* 0x54 - Enable above 4GB MMIO Resource */ + u64 a4gb; /* 0x55 - 0x5C Base of above 4GB MMIO Resource */ + u64 a4gs; /* 0x5D - 0x64 Length of above 4GB MMIO Resource */ + u8 rsvd[79];
/* IGD OpRegion */ u32 aslb; /* 0xb4 - IGD OpRegion Base Address */ diff --git a/src/soc/intel/tigerlake/acpi.c b/src/soc/intel/tigerlake/acpi.c index 5e04c9a..bbe8f73 100644 --- a/src/soc/intel/tigerlake/acpi.c +++ b/src/soc/intel/tigerlake/acpi.c @@ -223,6 +223,9 @@ /* Set USB2/USB3 wake enable bitmaps. */ gnvs->u2we = config->usb2_wake_enable_bitmap; gnvs->u3we = config->usb3_wake_enable_bitmap; + + /* Fill in Above 4GB MMIO resource */ + sa_fill_gnvs(gnvs); }
uint32_t acpi_fill_soc_wake(uint32_t generic_pm1_en, diff --git a/src/soc/intel/tigerlake/acpi/northbridge.asl b/src/soc/intel/tigerlake/acpi/northbridge.asl index d6c2d34..1038f25 100644 --- a/src/soc/intel/tigerlake/acpi/northbridge.asl +++ b/src/soc/intel/tigerlake/acpi/northbridge.asl @@ -16,9 +16,6 @@
#include <soc/iomap.h>
-#define BASE_32GB 0x800000000 -#define SIZE_16GB 0x400000000 - Name (_HID, EisaId ("PNP0A08") /* PCI Express Bus */) // _HID: Hardware ID Name (_CID, EisaId ("PNP0A03") /* PCI Bus */) // _CID: Compatible ID Name (_SEG, Zero) // _SEG: PCI Segment @@ -206,20 +203,18 @@ Add (Subtract (PMAX, PMIN), 1, PLEN)
/* Patch PM02 range based on Memory Size */ - CreateQwordField (MCRS, PM02._MIN, MMIN) - CreateQwordField (MCRS, PM02._MAX, MMAX) - CreateQwordField (MCRS, PM02._LEN, MLEN) - - Store (_SB.PCI0.MCHC.TUUD, Local0) - - If (LLessEqual (Local0, BASE_32GB)) { - Store (BASE_32GB, MMIN) - Store (SIZE_16GB, MLEN) + If (LEqual (A4GS, 0)) { + CreateQwordField (^MCRS, ^PM02._LEN, MSEN) + Store (0, MSEN) } Else { - Store (0, MMIN) - Store (0, MLEN) + CreateQwordField (^MCRS, ^PM02._MIN, MMIN) + CreateQwordField (^MCRS, ^PM02._MAX, MMAX) + CreateQwordField (^MCRS, ^PM02._LEN, MLEN) + /* Set 64bit MMIO resource base and length */ + Store (A4GS, MLEN) + Store (A4GB, MMIN) + Subtract (Add (MMIN, MLEN), 1, MMAX) } - Subtract (Add (MMIN, MLEN), 1, MMAX)
Return (MCRS) } diff --git a/src/soc/intel/tigerlake/include/soc/iomap.h b/src/soc/intel/tigerlake/include/soc/iomap.h index b3797c1..cfd958a 100644 --- a/src/soc/intel/tigerlake/include/soc/iomap.h +++ b/src/soc/intel/tigerlake/include/soc/iomap.h @@ -66,6 +66,10 @@
#define VTD_BASE_ADDRESS 0xFED90000 #define VTD_BASE_SIZE 0x00004000 + +#define ABOVE_4GB_MEM_BASE_ADDRESS (256*GiB) +#define ABOVE_4GB_MEM_BASE_SIZE (256*GiB) + /* * I/O port address space */
Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38125 )
Change subject: soc/intel/{apl,cnl,icl,skl,tgl}: Make above 4GB MMIO resource proper ......................................................................
Patch Set 1:
@Duncan: Do you recommend to use Kconfig instead of NVS ?
Hello Aaron Durbin, Patrick Rudolph, Arthur Heymans, Rizwan Qureshi, Duncan Laurie, V Sowmya, build bot (Jenkins), Furquan Shaikh,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/38125
to look at the new patch set (#2).
Change subject: soc/intel/{apl,cnl,icl,skl,tgl}: Make above 4GB MMIO resource proper ......................................................................
soc/intel/{apl,cnl,icl,skl,tgl}: Make above 4GB MMIO resource proper
This patch ensures coreboot is not publishing above 4GB mmio resource if soc common config "enable_above_4GB_mmio" not enable.
Publishing unnecessary 4GB above MMIO resource with wrong base and size is causing problem while working with discrete GPU.
Unable to boot with dGPU on IA platform with below error:
[ 2.297425] pcieport 0000:00:1c.0: PCI bridge to [bus 05] [ 2.302858] pcieport 0000:00:1c.0: bridge window [io 0x2000-0x2fff] [ 2.309427] pcieport 0000:00:1c.0: bridge window [mem 0xb2000000-0xb20fffff] [ 2.316679] pcieport 0000:00:1c.0: bridge window [mem 0x840000000-0x8c01fffff 64bit pref] [ 2.325072] pcieport 0000:00:1c.0: PCI bridge to [bus 05] [ 2.330502] pcieport 0000:00:1c.0: bridge window [io 0x2000-0x2fff] [ 2.337062] pcieport 0000:00:1c.0: bridge window [mem 0xb2000000-0xb20fffff] [ 2.344317] pcieport 0000:00:1c.0: bridge window [mem 0xa0000000-0xb01fffff 64bit pref] [ 2.352541] [drm] Not enough PCI address space for a large BAR.
Change-Id: I77b3a0e44582b047d7fbe679d3000d616f7e6111 Signed-off-by: Subrata Banik subrata.banik@intel.com --- M src/soc/intel/apollolake/acpi.c M src/soc/intel/apollolake/acpi/globalnvs.asl M src/soc/intel/apollolake/acpi/northbridge.asl M src/soc/intel/apollolake/include/soc/iomap.h M src/soc/intel/apollolake/include/soc/nvs.h M src/soc/intel/cannonlake/acpi.c M src/soc/intel/cannonlake/acpi/northbridge.asl M src/soc/intel/cannonlake/include/soc/iomap.h M src/soc/intel/common/block/acpi/acpi/globalnvs.asl M src/soc/intel/common/block/include/intelblocks/cfg.h M src/soc/intel/common/block/include/intelblocks/nvs.h M src/soc/intel/common/block/include/intelblocks/systemagent.h M src/soc/intel/common/block/systemagent/systemagent.c M src/soc/intel/icelake/acpi.c M src/soc/intel/icelake/acpi/northbridge.asl M src/soc/intel/icelake/include/soc/iomap.h M src/soc/intel/skylake/acpi.c M src/soc/intel/skylake/acpi/globalnvs.asl M src/soc/intel/skylake/acpi/systemagent.asl M src/soc/intel/skylake/include/soc/iomap.h M src/soc/intel/skylake/include/soc/nvs.h M src/soc/intel/tigerlake/acpi.c M src/soc/intel/tigerlake/acpi/northbridge.asl M src/soc/intel/tigerlake/include/soc/iomap.h 24 files changed, 141 insertions(+), 75 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/25/38125/2
Hello Aaron Durbin, Patrick Rudolph, Arthur Heymans, Rizwan Qureshi, Duncan Laurie, V Sowmya, build bot (Jenkins), Furquan Shaikh,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/38125
to look at the new patch set (#3).
Change subject: soc/intel/{apl,cnl,icl,skl,tgl}: Make above 4GB MMIO resource proper ......................................................................
soc/intel/{apl,cnl,icl,skl,tgl}: Make above 4GB MMIO resource proper
This patch ensures coreboot is not publishing above 4GB mmio resource if soc common config "enable_above_4GB_mmio" not enable.
Publishing unnecessary 4GB above MMIO resource with wrong base and size is causing problem while working with discrete GPU.
Unable to boot with dGPU on IA platform with below error:
[ 2.297425] pcieport 0000:00:1c.0: PCI bridge to [bus 05] [ 2.302858] pcieport 0000:00:1c.0: bridge window [io 0x2000-0x2fff] [ 2.309427] pcieport 0000:00:1c.0: bridge window [mem 0xb2000000-0xb20fffff] [ 2.316679] pcieport 0000:00:1c.0: bridge window [mem 0x840000000-0x8c01fffff 64bit pref] [ 2.325072] pcieport 0000:00:1c.0: PCI bridge to [bus 05] [ 2.330502] pcieport 0000:00:1c.0: bridge window [io 0x2000-0x2fff] [ 2.337062] pcieport 0000:00:1c.0: bridge window [mem 0xb2000000-0xb20fffff] [ 2.344317] pcieport 0000:00:1c.0: bridge window [mem 0xa0000000-0xb01fffff 64bit pref] [ 2.352541] [drm] Not enough PCI address space for a large BAR.
Change-Id: I77b3a0e44582b047d7fbe679d3000d616f7e6111 Signed-off-by: Subrata Banik subrata.banik@intel.com --- M src/soc/intel/apollolake/acpi.c M src/soc/intel/apollolake/acpi/globalnvs.asl M src/soc/intel/apollolake/acpi/northbridge.asl M src/soc/intel/apollolake/include/soc/iomap.h M src/soc/intel/apollolake/include/soc/nvs.h M src/soc/intel/cannonlake/acpi.c M src/soc/intel/cannonlake/acpi/northbridge.asl M src/soc/intel/cannonlake/include/soc/iomap.h M src/soc/intel/common/block/acpi/acpi/globalnvs.asl M src/soc/intel/common/block/include/intelblocks/cfg.h M src/soc/intel/common/block/include/intelblocks/nvs.h M src/soc/intel/common/block/include/intelblocks/systemagent.h M src/soc/intel/common/block/systemagent/systemagent.c M src/soc/intel/icelake/acpi.c M src/soc/intel/icelake/acpi/northbridge.asl M src/soc/intel/icelake/include/soc/iomap.h M src/soc/intel/skylake/acpi.c M src/soc/intel/skylake/acpi/globalnvs.asl M src/soc/intel/skylake/acpi/systemagent.asl M src/soc/intel/skylake/include/soc/iomap.h M src/soc/intel/skylake/include/soc/nvs.h M src/soc/intel/tigerlake/acpi.c M src/soc/intel/tigerlake/acpi/northbridge.asl M src/soc/intel/tigerlake/include/soc/iomap.h 24 files changed, 141 insertions(+), 75 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/25/38125/3
Hello Aaron Durbin, Patrick Rudolph, Arthur Heymans, Rizwan Qureshi, Duncan Laurie, V Sowmya, build bot (Jenkins), Furquan Shaikh,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/38125
to look at the new patch set (#4).
Change subject: soc/intel/{apl,cnl,icl,skl,tgl}: Make above 4GB MMIO resource proper ......................................................................
soc/intel/{apl,cnl,icl,skl,tgl}: Make above 4GB MMIO resource proper
This patch ensures coreboot is not publishing above 4GB mmio resource if soc common config "enable_above_4GB_mmio" not enable.
Publishing unnecessary 4GB above MMIO resource with wrong base and size is causing problem while working with discrete GPU.
Unable to boot with dGPU on IA platform with below error:
[ 2.297425] pcieport 0000:00:1c.0: PCI bridge to [bus 05] [ 2.302858] pcieport 0000:00:1c.0: bridge window [io 0x2000-0x2fff] [ 2.309427] pcieport 0000:00:1c.0: bridge window [mem 0xb2000000-0xb20fffff] [ 2.316679] pcieport 0000:00:1c.0: bridge window [mem 0x840000000-0x8c01fffff 64bit pref] [ 2.325072] pcieport 0000:00:1c.0: PCI bridge to [bus 05] [ 2.330502] pcieport 0000:00:1c.0: bridge window [io 0x2000-0x2fff] [ 2.337062] pcieport 0000:00:1c.0: bridge window [mem 0xb2000000-0xb20fffff] [ 2.344317] pcieport 0000:00:1c.0: bridge window [mem 0xa0000000-0xb01fffff 64bit pref] [ 2.352541] [drm] Not enough PCI address space for a large BAR.
Change-Id: I77b3a0e44582b047d7fbe679d3000d616f7e6111 Signed-off-by: Subrata Banik subrata.banik@intel.com --- M src/soc/intel/apollolake/acpi.c M src/soc/intel/apollolake/acpi/globalnvs.asl M src/soc/intel/apollolake/acpi/northbridge.asl M src/soc/intel/apollolake/include/soc/iomap.h M src/soc/intel/apollolake/include/soc/nvs.h M src/soc/intel/cannonlake/acpi.c M src/soc/intel/cannonlake/include/soc/iomap.h M src/soc/intel/common/block/acpi/acpi/globalnvs.asl M src/soc/intel/common/block/acpi/acpi/northbridge.asl M src/soc/intel/common/block/include/intelblocks/cfg.h M src/soc/intel/common/block/include/intelblocks/nvs.h M src/soc/intel/common/block/include/intelblocks/systemagent.h M src/soc/intel/common/block/systemagent/systemagent.c M src/soc/intel/icelake/acpi.c M src/soc/intel/icelake/include/soc/iomap.h M src/soc/intel/skylake/acpi.c M src/soc/intel/skylake/acpi/globalnvs.asl M src/soc/intel/skylake/acpi/systemagent.asl M src/soc/intel/skylake/include/soc/iomap.h M src/soc/intel/skylake/include/soc/nvs.h M src/soc/intel/tigerlake/acpi.c M src/soc/intel/tigerlake/include/soc/iomap.h 22 files changed, 121 insertions(+), 46 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/25/38125/4
Lance Zhao has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38125 )
Change subject: soc/intel/{apl,cnl,icl,skl,tgl}: Make above 4GB MMIO resource proper ......................................................................
Patch Set 4:
Is the addressed fixed? 128G~256GB and 256G~512GB?
Did we have to force such a huge resources to PCI MMIO but not based on the real usage?
Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38125 )
Change subject: soc/intel/{apl,cnl,icl,skl,tgl}: Make above 4GB MMIO resource proper ......................................................................
Patch Set 4:
Patch Set 4:
Is the addressed fixed? 128G~256GB and 256G~512GB?
Did we have to force such a huge resources to PCI MMIO but not based on the real usage?
Those values are based on Intel SOC reference code going to all IBV and OEM for each soc.
Lance Zhao has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38125 )
Change subject: soc/intel/{apl,cnl,icl,skl,tgl}: Make above 4GB MMIO resource proper ......................................................................
Patch Set 4:
Patch Set 4:
Patch Set 4:
Is the addressed fixed? 128G~256GB and 256G~512GB?
Did we have to force such a huge resources to PCI MMIO but not based on the real usage?
Those values are based on Intel SOC reference code going to all IBV and OEM for each soc.
Okay, so get forced in FSP side.
Lance Zhao has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38125 )
Change subject: soc/intel/{apl,cnl,icl,skl,tgl}: Make above 4GB MMIO resource proper ......................................................................
Patch Set 4: Code-Review+1
Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38125 )
Change subject: soc/intel/{apl,cnl,icl,skl,tgl}: Make above 4GB MMIO resource proper ......................................................................
Patch Set 4:
Patch Set 4:
Patch Set 4:
Patch Set 4:
Is the addressed fixed? 128G~256GB and 256G~512GB?
Did we have to force such a huge resources to PCI MMIO but not based on the real usage?
Those values are based on Intel SOC reference code going to all IBV and OEM for each soc.
Okay, so get forced in FSP side.
Yes Lance, logically having SOC ASL as part of FSP would have been a proper solution so we don't miss to port any ASL related changes from Reference code to Coreboot which is the case for all program.
Rizwan Qureshi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38125 )
Change subject: soc/intel/{apl,cnl,icl,skl,tgl}: Make above 4GB MMIO resource proper ......................................................................
Patch Set 4:
(4 comments)
https://review.coreboot.org/c/coreboot/+/38125/4/src/soc/intel/apollolake/in... File src/soc/intel/apollolake/include/soc/nvs.h:
https://review.coreboot.org/c/coreboot/+/38125/4/src/soc/intel/apollolake/in... PS4, Line 50: uint8_t e4gm; /* 0x3D - Enable above 4GB MMIO Resource */ : uint64_t a4gb; /* 0x3E - 0x45 Base of above 4GB MMIO Resource */ : uint64_t a4gs; /* 0x46 - 0x4D Length of above 4GB MMIO Resource */ Right now they are listed under "Miscellaneous" since these are specific to Intel SoCs, we probably have them in a separate section. OR may be a common NVS structure in intel/common and then SoCs can define any custom variables here.
https://review.coreboot.org/c/coreboot/+/38125/4/src/soc/intel/common/block/... File src/soc/intel/common/block/systemagent/systemagent.c:
https://review.coreboot.org/c/coreboot/+/38125/4/src/soc/intel/common/block/... PS4, Line 19: nclude <device/pci_ops.h> required?
https://review.coreboot.org/c/coreboot/+/38125/4/src/soc/intel/common/block/... PS4, Line 82: gnvs->a4gb should be gnvs->a4gs?
https://review.coreboot.org/c/coreboot/+/38125/4/src/soc/intel/skylake/inclu... File src/soc/intel/skylake/include/soc/iomap.h:
https://review.coreboot.org/c/coreboot/+/38125/4/src/soc/intel/skylake/inclu... PS4, Line 78: 0x2000000000 nit: 128*GiB here and everywhere would be nice
Hello Aaron Durbin, Patrick Rudolph, Arthur Heymans, Rizwan Qureshi, Duncan Laurie, Lance Zhao, V Sowmya, build bot (Jenkins), Furquan Shaikh,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/38125
to look at the new patch set (#5).
Change subject: soc/intel/{apl,cnl,icl,skl,tgl}: Make above 4GB MMIO resource proper ......................................................................
soc/intel/{apl,cnl,icl,skl,tgl}: Make above 4GB MMIO resource proper
This patch ensures coreboot is not publishing above 4GB mmio resource if soc common config "enable_above_4GB_mmio" not enable.
Publishing unnecessary 4GB above MMIO resource with wrong base and size is causing problem while working with discrete GPU.
Unable to boot with dGPU on IA platform with below error:
[ 2.297425] pcieport 0000:00:1c.0: PCI bridge to [bus 05] [ 2.302858] pcieport 0000:00:1c.0: bridge window [io 0x2000-0x2fff] [ 2.309427] pcieport 0000:00:1c.0: bridge window [mem 0xb2000000-0xb20fffff] [ 2.316679] pcieport 0000:00:1c.0: bridge window [mem 0x840000000-0x8c01fffff 64bit pref] [ 2.325072] pcieport 0000:00:1c.0: PCI bridge to [bus 05] [ 2.330502] pcieport 0000:00:1c.0: bridge window [io 0x2000-0x2fff] [ 2.337062] pcieport 0000:00:1c.0: bridge window [mem 0xb2000000-0xb20fffff] [ 2.344317] pcieport 0000:00:1c.0: bridge window [mem 0xa0000000-0xb01fffff 64bit pref] [ 2.352541] [drm] Not enough PCI address space for a large BAR.
Change-Id: I77b3a0e44582b047d7fbe679d3000d616f7e6111 Signed-off-by: Subrata Banik subrata.banik@intel.com --- M src/soc/intel/apollolake/acpi.c M src/soc/intel/apollolake/acpi/globalnvs.asl M src/soc/intel/apollolake/acpi/northbridge.asl M src/soc/intel/apollolake/include/soc/iomap.h M src/soc/intel/apollolake/include/soc/nvs.h M src/soc/intel/cannonlake/acpi.c M src/soc/intel/cannonlake/include/soc/iomap.h M src/soc/intel/common/block/acpi/acpi/globalnvs.asl M src/soc/intel/common/block/acpi/acpi/northbridge.asl M src/soc/intel/common/block/include/intelblocks/cfg.h M src/soc/intel/common/block/include/intelblocks/nvs.h M src/soc/intel/common/block/include/intelblocks/systemagent.h M src/soc/intel/common/block/systemagent/systemagent.c M src/soc/intel/icelake/acpi.c M src/soc/intel/icelake/include/soc/iomap.h M src/soc/intel/skylake/acpi.c M src/soc/intel/skylake/acpi/globalnvs.asl M src/soc/intel/skylake/acpi/systemagent.asl M src/soc/intel/skylake/include/soc/iomap.h M src/soc/intel/skylake/include/soc/nvs.h M src/soc/intel/tigerlake/acpi.c M src/soc/intel/tigerlake/include/soc/iomap.h 22 files changed, 120 insertions(+), 46 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/25/38125/5
Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38125 )
Change subject: soc/intel/{apl,cnl,icl,skl,tgl}: Make above 4GB MMIO resource proper ......................................................................
Patch Set 5:
(4 comments)
https://review.coreboot.org/c/coreboot/+/38125/4/src/soc/intel/apollolake/in... File src/soc/intel/apollolake/include/soc/nvs.h:
https://review.coreboot.org/c/coreboot/+/38125/4/src/soc/intel/apollolake/in... PS4, Line 50: uint8_t e4gm; /* 0x3D - Enable above 4GB MMIO Resource */ : uint64_t a4gb; /* 0x3E - 0x45 Base of above 4GB MMIO Resource */ : uint64_t a4gs; /* 0x46 - 0x4D Length of above 4GB MMIO Resource */
Right now they are listed under "Miscellaneous" since these are specific to Intel SoCs, we probably […]
Yes Rizwan, we already created common NVS structure since CNL onwards [https://review.coreboot.org/c/coreboot/+/38125/4/src/soc/intel/common/block/...]
making it common since SKL and APL is little difficult hence left it as is without adding into common part
https://review.coreboot.org/c/coreboot/+/38125/4/src/soc/intel/common/block/... File src/soc/intel/common/block/systemagent/systemagent.c:
https://review.coreboot.org/c/coreboot/+/38125/4/src/soc/intel/common/block/... PS4, Line 19: nclude <device/pci_ops.h>
required?
Done
https://review.coreboot.org/c/coreboot/+/38125/4/src/soc/intel/common/block/... PS4, Line 82: gnvs->a4gb
should be gnvs->a4gs?
Done
https://review.coreboot.org/c/coreboot/+/38125/4/src/soc/intel/skylake/inclu... File src/soc/intel/skylake/include/soc/iomap.h:
https://review.coreboot.org/c/coreboot/+/38125/4/src/soc/intel/skylake/inclu... PS4, Line 78: 0x2000000000
nit: 128*GiB here and everywhere would be nice
Yes, i also wished to do the same. But weird things happen and you can see compilation issue here, i believe its due to 32bit IASL compiler
https://qa.coreboot.org/job/coreboot-gerrit/113502/testReport/junit/board/ch...
Hello Aaron Durbin, Patrick Rudolph, Arthur Heymans, Rizwan Qureshi, Duncan Laurie, Lance Zhao, V Sowmya, build bot (Jenkins), Furquan Shaikh,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/38125
to look at the new patch set (#6).
Change subject: soc/intel/{apl,cnl,icl,skl,tgl}: Make above 4GB MMIO resource proper ......................................................................
soc/intel/{apl,cnl,icl,skl,tgl}: Make above 4GB MMIO resource proper
This patch ensures coreboot is not publishing above 4GB mmio resource if soc common config "enable_above_4GB_mmio" not enable.
Publishing unnecessary 4GB above MMIO resource with wrong base and size is causing problem while working with discrete GPU.
Unable to boot with dGPU on IA platform with below error:
[ 2.297425] pcieport 0000:00:1c.0: PCI bridge to [bus 05] [ 2.302858] pcieport 0000:00:1c.0: bridge window [io 0x2000-0x2fff] [ 2.309427] pcieport 0000:00:1c.0: bridge window [mem 0xb2000000-0xb20fffff] [ 2.316679] pcieport 0000:00:1c.0: bridge window [mem 0x840000000-0x8c01fffff 64bit pref] [ 2.325072] pcieport 0000:00:1c.0: PCI bridge to [bus 05] [ 2.330502] pcieport 0000:00:1c.0: bridge window [io 0x2000-0x2fff] [ 2.337062] pcieport 0000:00:1c.0: bridge window [mem 0xb2000000-0xb20fffff] [ 2.344317] pcieport 0000:00:1c.0: bridge window [mem 0xa0000000-0xb01fffff 64bit pref] [ 2.352541] [drm] Not enough PCI address space for a large BAR.
Change-Id: I77b3a0e44582b047d7fbe679d3000d616f7e6111 Signed-off-by: Subrata Banik subrata.banik@intel.com --- M src/soc/intel/apollolake/acpi.c M src/soc/intel/apollolake/acpi/globalnvs.asl M src/soc/intel/apollolake/acpi/northbridge.asl M src/soc/intel/apollolake/include/soc/iomap.h M src/soc/intel/apollolake/include/soc/nvs.h M src/soc/intel/cannonlake/acpi.c M src/soc/intel/cannonlake/include/soc/iomap.h M src/soc/intel/common/block/acpi/acpi/globalnvs.asl M src/soc/intel/common/block/acpi/acpi/northbridge.asl M src/soc/intel/common/block/include/intelblocks/cfg.h M src/soc/intel/common/block/include/intelblocks/nvs.h M src/soc/intel/common/block/include/intelblocks/systemagent.h M src/soc/intel/common/block/systemagent/systemagent.c M src/soc/intel/icelake/acpi.c M src/soc/intel/icelake/include/soc/iomap.h M src/soc/intel/skylake/acpi.c M src/soc/intel/skylake/acpi/globalnvs.asl M src/soc/intel/skylake/acpi/systemagent.asl M src/soc/intel/skylake/include/soc/iomap.h M src/soc/intel/skylake/include/soc/nvs.h M src/soc/intel/tigerlake/acpi.c M src/soc/intel/tigerlake/include/soc/iomap.h 22 files changed, 120 insertions(+), 46 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/25/38125/6
Hello Aaron Durbin, Patrick Rudolph, Arthur Heymans, Rizwan Qureshi, Duncan Laurie, Lance Zhao, V Sowmya, build bot (Jenkins), Furquan Shaikh,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/38125
to look at the new patch set (#7).
Change subject: soc/intel/{apl,cnl,icl,skl,tgl}: Make above 4GB MMIO resource proper ......................................................................
soc/intel/{apl,cnl,icl,skl,tgl}: Make above 4GB MMIO resource proper
This patch ensures coreboot is not publishing above 4GB mmio resource if soc common config "enable_above_4GB_mmio" not enable.
Publishing unnecessary 4GB above MMIO resource with wrong base and size is causing problem while working with discrete GPU.
Unable to boot with dGPU on IA platform with below error:
[ 2.297425] pcieport 0000:00:1c.0: PCI bridge to [bus 05] [ 2.302858] pcieport 0000:00:1c.0: bridge window [io 0x2000-0x2fff] [ 2.309427] pcieport 0000:00:1c.0: bridge window [mem 0xb2000000-0xb20fffff] [ 2.316679] pcieport 0000:00:1c.0: bridge window [mem 0x840000000-0x8c01fffff 64bit pref] [ 2.325072] pcieport 0000:00:1c.0: PCI bridge to [bus 05] [ 2.330502] pcieport 0000:00:1c.0: bridge window [io 0x2000-0x2fff] [ 2.337062] pcieport 0000:00:1c.0: bridge window [mem 0xb2000000-0xb20fffff] [ 2.344317] pcieport 0000:00:1c.0: bridge window [mem 0xa0000000-0xb01fffff 64bit pref] [ 2.352541] [drm] Not enough PCI address space for a large BAR.
Change-Id: I77b3a0e44582b047d7fbe679d3000d616f7e6111 Signed-off-by: Subrata Banik subrata.banik@intel.com --- M src/soc/intel/apollolake/acpi.c M src/soc/intel/apollolake/acpi/globalnvs.asl M src/soc/intel/apollolake/acpi/northbridge.asl M src/soc/intel/apollolake/include/soc/iomap.h M src/soc/intel/apollolake/include/soc/nvs.h M src/soc/intel/cannonlake/acpi.c M src/soc/intel/cannonlake/include/soc/iomap.h M src/soc/intel/common/block/acpi/acpi/globalnvs.asl M src/soc/intel/common/block/acpi/acpi/northbridge.asl M src/soc/intel/common/block/include/intelblocks/cfg.h M src/soc/intel/common/block/include/intelblocks/nvs.h M src/soc/intel/common/block/include/intelblocks/systemagent.h M src/soc/intel/common/block/systemagent/systemagent.c M src/soc/intel/icelake/acpi.c M src/soc/intel/icelake/include/soc/iomap.h M src/soc/intel/skylake/acpi.c M src/soc/intel/skylake/acpi/globalnvs.asl M src/soc/intel/skylake/acpi/systemagent.asl M src/soc/intel/skylake/include/soc/iomap.h M src/soc/intel/skylake/include/soc/nvs.h M src/soc/intel/tigerlake/acpi.c M src/soc/intel/tigerlake/include/soc/iomap.h 22 files changed, 120 insertions(+), 46 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/25/38125/7
Wonkyu Kim has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38125 )
Change subject: soc/intel/{apl,cnl,icl,skl,tgl}: Make above 4GB MMIO resource proper ......................................................................
Patch Set 7: Code-Review+1
Pratikkumar V Prajapati has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38125 )
Change subject: soc/intel/{apl,cnl,icl,skl,tgl}: Make above 4GB MMIO resource proper ......................................................................
Patch Set 7: Code-Review+1
(1 comment)
https://review.coreboot.org/c/coreboot/+/38125/7/src/soc/intel/common/block/... File src/soc/intel/common/block/systemagent/systemagent.c:
https://review.coreboot.org/c/coreboot/+/38125/7/src/soc/intel/common/block/... PS7, Line 4: 2017-2018 2020 in other files also!
Rizwan Qureshi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38125 )
Change subject: soc/intel/{apl,cnl,icl,skl,tgl}: Make above 4GB MMIO resource proper ......................................................................
Patch Set 7: Code-Review+2
Hello Pratikkumar V Prajapati, Aaron Durbin, Patrick Rudolph, Arthur Heymans, Wonkyu Kim, Rizwan Qureshi, Duncan Laurie, Lance Zhao, V Sowmya, build bot (Jenkins), Furquan Shaikh,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/38125
to look at the new patch set (#8).
Change subject: soc/intel/{apl,cnl,icl,skl,tgl}: Make above 4GB MMIO resource proper ......................................................................
soc/intel/{apl,cnl,icl,skl,tgl}: Make above 4GB MMIO resource proper
This patch ensures coreboot is not publishing above 4GB mmio resource if soc common config "enable_above_4GB_mmio" not enable.
Publishing unnecessary 4GB above MMIO resource with wrong base and size is causing problem while working with discrete GPU.
Unable to boot with dGPU on IA platform with below error:
[ 2.297425] pcieport 0000:00:1c.0: PCI bridge to [bus 05] [ 2.302858] pcieport 0000:00:1c.0: bridge window [io 0x2000-0x2fff] [ 2.309427] pcieport 0000:00:1c.0: bridge window [mem 0xb2000000-0xb20fffff] [ 2.316679] pcieport 0000:00:1c.0: bridge window [mem 0x840000000-0x8c01fffff 64bit pref] [ 2.325072] pcieport 0000:00:1c.0: PCI bridge to [bus 05] [ 2.330502] pcieport 0000:00:1c.0: bridge window [io 0x2000-0x2fff] [ 2.337062] pcieport 0000:00:1c.0: bridge window [mem 0xb2000000-0xb20fffff] [ 2.344317] pcieport 0000:00:1c.0: bridge window [mem 0xa0000000-0xb01fffff 64bit pref] [ 2.352541] [drm] Not enough PCI address space for a large BAR.
Change-Id: I77b3a0e44582b047d7fbe679d3000d616f7e6111 Signed-off-by: Subrata Banik subrata.banik@intel.com --- M src/soc/intel/apollolake/acpi.c M src/soc/intel/apollolake/acpi/globalnvs.asl M src/soc/intel/apollolake/acpi/northbridge.asl M src/soc/intel/apollolake/include/soc/iomap.h M src/soc/intel/apollolake/include/soc/nvs.h M src/soc/intel/cannonlake/acpi.c M src/soc/intel/cannonlake/include/soc/iomap.h M src/soc/intel/common/block/acpi/acpi/globalnvs.asl M src/soc/intel/common/block/acpi/acpi/northbridge.asl M src/soc/intel/common/block/include/intelblocks/cfg.h M src/soc/intel/common/block/include/intelblocks/nvs.h M src/soc/intel/common/block/include/intelblocks/systemagent.h M src/soc/intel/common/block/systemagent/systemagent.c M src/soc/intel/icelake/acpi.c M src/soc/intel/icelake/include/soc/iomap.h M src/soc/intel/skylake/acpi.c M src/soc/intel/skylake/acpi/globalnvs.asl M src/soc/intel/skylake/acpi/systemagent.asl M src/soc/intel/skylake/include/soc/iomap.h M src/soc/intel/skylake/include/soc/nvs.h M src/soc/intel/tigerlake/acpi.c M src/soc/intel/tigerlake/include/soc/iomap.h 22 files changed, 141 insertions(+), 65 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/25/38125/8
Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38125 )
Change subject: soc/intel/{apl,cnl,icl,skl,tgl}: Make above 4GB MMIO resource proper ......................................................................
Patch Set 8:
(1 comment)
https://review.coreboot.org/c/coreboot/+/38125/7/src/soc/intel/common/block/... File src/soc/intel/common/block/systemagent/systemagent.c:
https://review.coreboot.org/c/coreboot/+/38125/7/src/soc/intel/common/block/... PS7, Line 4: 2017-2018
2020 […]
Done
Pratikkumar V Prajapati has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38125 )
Change subject: soc/intel/{apl,cnl,icl,skl,tgl}: Make above 4GB MMIO resource proper ......................................................................
Patch Set 8:
(1 comment)
https://review.coreboot.org/c/coreboot/+/38125/8/src/soc/intel/common/block/... File src/soc/intel/common/block/systemagent/systemagent.c:
https://review.coreboot.org/c/coreboot/+/38125/8/src/soc/intel/common/block/... PS8, Line 4: * Copyright (C) 2017-2018 Intel Corporation. : * Copyright (C) 2019 Siemens AG : * Copyright (C) 2020 Intel Corporation. Only one line for Copyright of Intel. Same for at-least one more file.
Hello Pratikkumar V Prajapati, Aaron Durbin, Patrick Rudolph, Arthur Heymans, Wonkyu Kim, Rizwan Qureshi, Duncan Laurie, Lance Zhao, V Sowmya, build bot (Jenkins), Furquan Shaikh,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/38125
to look at the new patch set (#9).
Change subject: soc/intel/{apl,cnl,icl,skl,tgl}: Make above 4GB MMIO resource proper ......................................................................
soc/intel/{apl,cnl,icl,skl,tgl}: Make above 4GB MMIO resource proper
This patch ensures coreboot is not publishing above 4GB mmio resource if soc common config "enable_above_4GB_mmio" not enable.
Publishing unnecessary 4GB above MMIO resource with wrong base and size is causing problem while working with discrete GPU.
Unable to boot with dGPU on IA platform with below error:
[ 2.297425] pcieport 0000:00:1c.0: PCI bridge to [bus 05] [ 2.302858] pcieport 0000:00:1c.0: bridge window [io 0x2000-0x2fff] [ 2.309427] pcieport 0000:00:1c.0: bridge window [mem 0xb2000000-0xb20fffff] [ 2.316679] pcieport 0000:00:1c.0: bridge window [mem 0x840000000-0x8c01fffff 64bit pref] [ 2.325072] pcieport 0000:00:1c.0: PCI bridge to [bus 05] [ 2.330502] pcieport 0000:00:1c.0: bridge window [io 0x2000-0x2fff] [ 2.337062] pcieport 0000:00:1c.0: bridge window [mem 0xb2000000-0xb20fffff] [ 2.344317] pcieport 0000:00:1c.0: bridge window [mem 0xa0000000-0xb01fffff 64bit pref] [ 2.352541] [drm] Not enough PCI address space for a large BAR.
Change-Id: I77b3a0e44582b047d7fbe679d3000d616f7e6111 Signed-off-by: Subrata Banik subrata.banik@intel.com --- M src/soc/intel/apollolake/acpi.c M src/soc/intel/apollolake/acpi/globalnvs.asl M src/soc/intel/apollolake/acpi/northbridge.asl M src/soc/intel/apollolake/include/soc/iomap.h M src/soc/intel/apollolake/include/soc/nvs.h M src/soc/intel/cannonlake/acpi.c M src/soc/intel/cannonlake/include/soc/iomap.h M src/soc/intel/common/block/acpi/acpi/globalnvs.asl M src/soc/intel/common/block/acpi/acpi/northbridge.asl M src/soc/intel/common/block/include/intelblocks/cfg.h M src/soc/intel/common/block/include/intelblocks/nvs.h M src/soc/intel/common/block/include/intelblocks/systemagent.h M src/soc/intel/common/block/systemagent/systemagent.c M src/soc/intel/icelake/acpi.c M src/soc/intel/icelake/include/soc/iomap.h M src/soc/intel/skylake/acpi.c M src/soc/intel/skylake/acpi/globalnvs.asl M src/soc/intel/skylake/acpi/systemagent.asl M src/soc/intel/skylake/include/soc/iomap.h M src/soc/intel/skylake/include/soc/nvs.h M src/soc/intel/tigerlake/acpi.c M src/soc/intel/tigerlake/include/soc/iomap.h 22 files changed, 141 insertions(+), 67 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/25/38125/9
Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38125 )
Change subject: soc/intel/{apl,cnl,icl,skl,tgl}: Make above 4GB MMIO resource proper ......................................................................
Patch Set 8:
(1 comment)
https://review.coreboot.org/c/coreboot/+/38125/8/src/soc/intel/common/block/... File src/soc/intel/common/block/systemagent/systemagent.c:
https://review.coreboot.org/c/coreboot/+/38125/8/src/soc/intel/common/block/... PS8, Line 4: * Copyright (C) 2017-2018 Intel Corporation. : * Copyright (C) 2019 Siemens AG : * Copyright (C) 2020 Intel Corporation.
Only one line for Copyright of Intel. Same for at-least one more file.
Done
Rizwan Qureshi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38125 )
Change subject: soc/intel/{apl,cnl,icl,skl,tgl}: Make above 4GB MMIO resource proper ......................................................................
Patch Set 9: Code-Review+2
Pratikkumar V Prajapati has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38125 )
Change subject: soc/intel/{apl,cnl,icl,skl,tgl}: Make above 4GB MMIO resource proper ......................................................................
Patch Set 9: Code-Review+2
Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/38125 )
Change subject: soc/intel/{apl,cnl,icl,skl,tgl}: Make above 4GB MMIO resource proper ......................................................................
soc/intel/{apl,cnl,icl,skl,tgl}: Make above 4GB MMIO resource proper
This patch ensures coreboot is not publishing above 4GB mmio resource if soc common config "enable_above_4GB_mmio" not enable.
Publishing unnecessary 4GB above MMIO resource with wrong base and size is causing problem while working with discrete GPU.
Unable to boot with dGPU on IA platform with below error:
[ 2.297425] pcieport 0000:00:1c.0: PCI bridge to [bus 05] [ 2.302858] pcieport 0000:00:1c.0: bridge window [io 0x2000-0x2fff] [ 2.309427] pcieport 0000:00:1c.0: bridge window [mem 0xb2000000-0xb20fffff] [ 2.316679] pcieport 0000:00:1c.0: bridge window [mem 0x840000000-0x8c01fffff 64bit pref] [ 2.325072] pcieport 0000:00:1c.0: PCI bridge to [bus 05] [ 2.330502] pcieport 0000:00:1c.0: bridge window [io 0x2000-0x2fff] [ 2.337062] pcieport 0000:00:1c.0: bridge window [mem 0xb2000000-0xb20fffff] [ 2.344317] pcieport 0000:00:1c.0: bridge window [mem 0xa0000000-0xb01fffff 64bit pref] [ 2.352541] [drm] Not enough PCI address space for a large BAR.
Change-Id: I77b3a0e44582b047d7fbe679d3000d616f7e6111 Signed-off-by: Subrata Banik subrata.banik@intel.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/38125 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Rizwan Qureshi rizwan.qureshi@intel.com Reviewed-by: Pratikkumar V Prajapati pratikkumar.v.prajapati@intel.com --- M src/soc/intel/apollolake/acpi.c M src/soc/intel/apollolake/acpi/globalnvs.asl M src/soc/intel/apollolake/acpi/northbridge.asl M src/soc/intel/apollolake/include/soc/iomap.h M src/soc/intel/apollolake/include/soc/nvs.h M src/soc/intel/cannonlake/acpi.c M src/soc/intel/cannonlake/include/soc/iomap.h M src/soc/intel/common/block/acpi/acpi/globalnvs.asl M src/soc/intel/common/block/acpi/acpi/northbridge.asl M src/soc/intel/common/block/include/intelblocks/cfg.h M src/soc/intel/common/block/include/intelblocks/nvs.h M src/soc/intel/common/block/include/intelblocks/systemagent.h M src/soc/intel/common/block/systemagent/systemagent.c M src/soc/intel/icelake/acpi.c M src/soc/intel/icelake/include/soc/iomap.h M src/soc/intel/skylake/acpi.c M src/soc/intel/skylake/acpi/globalnvs.asl M src/soc/intel/skylake/acpi/systemagent.asl M src/soc/intel/skylake/include/soc/iomap.h M src/soc/intel/skylake/include/soc/nvs.h M src/soc/intel/tigerlake/acpi.c M src/soc/intel/tigerlake/include/soc/iomap.h 22 files changed, 141 insertions(+), 67 deletions(-)
Approvals: build bot (Jenkins): Verified Rizwan Qureshi: Looks good to me, approved Pratikkumar V Prajapati: Looks good to me, approved
diff --git a/src/soc/intel/apollolake/acpi.c b/src/soc/intel/apollolake/acpi.c index 7163884..46c7b6c 100644 --- a/src/soc/intel/apollolake/acpi.c +++ b/src/soc/intel/apollolake/acpi.c @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2016 Intel Corp. + * Copyright (C) 2016-2020 Intel Corp. * Copyright (C) 2017-2019 Siemens AG * (Written by Lance Zhao lijian.zhao@intel.com for Intel Corp.) * @@ -127,6 +127,9 @@
if (CONFIG(SOC_INTEL_COMMON_BLOCK_SGX)) sgx_fill_gnvs(gnvs); + + /* Fill in Above 4GB MMIO resource */ + sa_fill_gnvs(gnvs); }
uint32_t acpi_fill_soc_wake(uint32_t generic_pm1_en, diff --git a/src/soc/intel/apollolake/acpi/globalnvs.asl b/src/soc/intel/apollolake/acpi/globalnvs.asl index 4aad29c..1db373d 100644 --- a/src/soc/intel/apollolake/acpi/globalnvs.asl +++ b/src/soc/intel/apollolake/acpi/globalnvs.asl @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2016 Intel Corp. + * Copyright (C) 2016-2020 Intel Corp. * (Written by Alexandru Gagniuc alexandrux.gagniuc@intel.com for Intel Corp.) * * This program is free software; you can redistribute it and/or modify @@ -45,6 +45,9 @@ EPCS, 8, // 0x2C - SGX Enabled status EMNA, 64, // 0x2D - 0x34 EPC base address ELNG, 64, // 0x35 - 0x3C EPC Length + E4GM, 8, // 0x3D - Enable above 4GB MMIO Resource + A4GB, 64, // 0x3E - 0x45 Base of above 4GB MMIO Resource + A4GS, 64, // 0x46 - 0x4D Length of above 4GB MMIO Resource
/* ChromeOS stuff (0x100 -> 0xfff, size 0xeff) */ Offset (0x100), diff --git a/src/soc/intel/apollolake/acpi/northbridge.asl b/src/soc/intel/apollolake/acpi/northbridge.asl index 027e2a6..ff146ec 100644 --- a/src/soc/intel/apollolake/acpi/northbridge.asl +++ b/src/soc/intel/apollolake/acpi/northbridge.asl @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2016 Intel Corp. + * Copyright (C) 2016-2020 Intel Corp. * (Written by Lance Zhao lijian.zhao@intel.com for Intel Corp.) * * This program is free software; you can redistribute it and/or modify @@ -15,7 +15,6 @@ * GNU General Public License for more details. */
-#define BASE_64GB 0x1000000000
Name(_HID, EISAID("PNP0A08")) /* PCIe */ Name(_CID, EISAID("PNP0A03")) /* PCI */ @@ -115,18 +114,18 @@ Add(Subtract(GMAX, GMIN), 1, GLEN)
/* Patch PM02 range based on Memory Size */ - CreateQwordField (MCRS, PM02._MIN, MMIN) - CreateQwordField (MCRS, PM02._MAX, MMAX) - CreateQwordField (MCRS, PM02._LEN, MLEN) - - Store (_SB.PCI0.MCHC.TUUD, Local0) - - If (LLessEqual (Local0, BASE_64GB)) - { - Store (0, MMIN) - Store (0, MLEN) + If (LEqual (A4GS, 0)) { + CreateQwordField (MCRS, PM02._LEN, MSEN) + Store (0, MSEN) + } Else { + CreateQwordField (MCRS, PM02._MIN, MMIN) + CreateQwordField (MCRS, PM02._MAX, MMAX) + CreateQwordField (MCRS, PM02._LEN, MLEN) + /* Set 64bit MMIO resource base and length */ + Store (A4GS, MLEN) + Store (A4GB, MMIN) + Subtract (Add (MMIN, MLEN), 1, MMAX) } - Subtract (Add (MMIN, MLEN), 1, MMAX)
Return (MCRS) } diff --git a/src/soc/intel/apollolake/include/soc/iomap.h b/src/soc/intel/apollolake/include/soc/iomap.h index 3057fbe..e2fa462 100644 --- a/src/soc/intel/apollolake/include/soc/iomap.h +++ b/src/soc/intel/apollolake/include/soc/iomap.h @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2015 Intel Corp. + * Copyright (C) 2015-2020 Intel Corp. * (Written by Andrey Petrov andrey.petrov@intel.com for Intel Corp.) * * This program is free software; you can redistribute it and/or modify @@ -60,4 +60,7 @@ #define EARLY_I2C_BASE_ADDRESS 0xfe020000 #define EARLY_I2C_BASE(x) (EARLY_I2C_BASE_ADDRESS + (0x1000 * (x)))
+#define ABOVE_4GB_MEM_BASE_ADDRESS (128ULL * GiB) +#define ABOVE_4GB_MEM_BASE_SIZE (64ULL * GiB) + #endif /* _SOC_APOLLOLAKE_IOMAP_H_ */ diff --git a/src/soc/intel/apollolake/include/soc/nvs.h b/src/soc/intel/apollolake/include/soc/nvs.h index 6c37d59..9cdeee1 100644 --- a/src/soc/intel/apollolake/include/soc/nvs.h +++ b/src/soc/intel/apollolake/include/soc/nvs.h @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2015-2017 Intel Corp. + * Copyright (C) 2015-2020 Intel Corp. * (Written by Lance Zhao lijian.zhao@intel.com for Intel Corp.) * * This program is free software; you can redistribute it and/or modify @@ -47,7 +47,10 @@ uint8_t ecps; /* 0x2C - SGX Enabled status */ uint64_t emna; /* 0x2D - 0x34 EPC base address */ uint64_t elng; /* 0x35 - 0x3C EPC Length */ - uint8_t unused[195]; + uint8_t e4gm; /* 0x3D - Enable above 4GB MMIO Resource */ + uint64_t a4gb; /* 0x3E - 0x45 Base of above 4GB MMIO Resource */ + uint64_t a4gs; /* 0x46 - 0x4D Length of above 4GB MMIO Resource */ + uint8_t unused[178];
/* ChromeOS specific (0x100 - 0xfff) */ chromeos_acpi_t chromeos; diff --git a/src/soc/intel/cannonlake/acpi.c b/src/soc/intel/cannonlake/acpi.c index 6d1970b..2632ae0 100644 --- a/src/soc/intel/cannonlake/acpi.c +++ b/src/soc/intel/cannonlake/acpi.c @@ -3,7 +3,7 @@ * * Copyright (C) 2009 coresystems GmbH * Copyright (C) 2014 Google Inc. - * Copyright (C) 2017-2018 Intel Corporation. + * Copyright (C) 2017-2020 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -231,6 +231,9 @@ /* Set USB2/USB3 wake enable bitmaps. */ gnvs->u2we = config->usb2_wake_enable_bitmap; gnvs->u3we = config->usb3_wake_enable_bitmap; + + /* Fill in Above 4GB MMIO resource */ + sa_fill_gnvs(gnvs); }
uint32_t acpi_fill_soc_wake(uint32_t generic_pm1_en, diff --git a/src/soc/intel/cannonlake/include/soc/iomap.h b/src/soc/intel/cannonlake/include/soc/iomap.h index 9cfb59e..c66cde4 100644 --- a/src/soc/intel/cannonlake/include/soc/iomap.h +++ b/src/soc/intel/cannonlake/include/soc/iomap.h @@ -2,7 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2014 Google Inc. - * Copyright (C) 2017 Intel Corporation. + * Copyright (C) 2017-2020 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -68,6 +68,9 @@
#define HECI1_BASE_ADDRESS 0xfeda2000
+#define ABOVE_4GB_MEM_BASE_ADDRESS (256ULL * GiB) +#define ABOVE_4GB_MEM_BASE_SIZE (256ULL * GiB) + /* PTT registers */ #define PTT_TXT_BASE_ADDRESS 0xfed30800 #define PTT_PRESENT 0x00070000 diff --git a/src/soc/intel/common/block/acpi/acpi/globalnvs.asl b/src/soc/intel/common/block/acpi/acpi/globalnvs.asl index 8e8241b..e94c49f 100644 --- a/src/soc/intel/common/block/acpi/acpi/globalnvs.asl +++ b/src/soc/intel/common/block/acpi/acpi/globalnvs.asl @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2019 Intel Corporation. + * Copyright (C) 2019-2020 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -47,6 +47,9 @@ U2WE, 16, // 0x2b - 0x2c USB2 Wake Enable Bitmap U3WE, 16, // 0x2d - 0x2e USB3 Wake Enable Bitmap UIOR, 8, // 0x2f - UART debug controller init on S3 resume + E4GM, 8, // 0x30 - Enable above 4GB MMIO Resource + A4GB, 64, // 0x31 - 0x38 Base of above 4GB MMIO Resource + A4GS, 64, // 0x39 - 0x40 Length of above 4GB MMIO Resource
/* ChromeOS specific */ Offset (0x100), diff --git a/src/soc/intel/common/block/acpi/acpi/northbridge.asl b/src/soc/intel/common/block/acpi/acpi/northbridge.asl index 2372e79..d271dda 100644 --- a/src/soc/intel/common/block/acpi/acpi/northbridge.asl +++ b/src/soc/intel/common/block/acpi/acpi/northbridge.asl @@ -16,9 +16,6 @@
#include <soc/iomap.h>
-#define BASE_32GB 0x800000000 -#define SIZE_16GB 0x400000000 - Name (_HID, EisaId ("PNP0A08") /* PCI Express Bus */) // _HID: Hardware ID Name (_CID, EisaId ("PNP0A03") /* PCI Bus */) // _CID: Compatible ID Name (_SEG, Zero) // _SEG: PCI Segment @@ -204,20 +201,18 @@ Add (Subtract (PMAX, PMIN), 1, PLEN)
/* Patch PM02 range based on Memory Size */ - CreateQwordField (MCRS, PM02._MIN, MMIN) - CreateQwordField (MCRS, PM02._MAX, MMAX) - CreateQwordField (MCRS, PM02._LEN, MLEN) - - Store (_SB.PCI0.MCHC.TUUD, Local0) - - If (LLessEqual (Local0, BASE_32GB)) { - Store (BASE_32GB, MMIN) - Store (SIZE_16GB, MLEN) + If (LEqual (A4GS, 0)) { + CreateQwordField (MCRS, PM02._LEN, MSEN) + Store (0, MSEN) } Else { - Store (0, MMIN) - Store (0, MLEN) + CreateQwordField (MCRS, PM02._MIN, MMIN) + CreateQwordField (MCRS, PM02._MAX, MMAX) + CreateQwordField (MCRS, PM02._LEN, MLEN) + /* Set 64bit MMIO resource base and length */ + Store (A4GS, MLEN) + Store (A4GB, MMIN) + Subtract (Add (MMIN, MLEN), 1, MMAX) } - Subtract (Add (MMIN, MLEN), 1, MMAX)
Return (MCRS) } diff --git a/src/soc/intel/common/block/include/intelblocks/cfg.h b/src/soc/intel/common/block/include/intelblocks/cfg.h index e7e381b..d907147 100644 --- a/src/soc/intel/common/block/include/intelblocks/cfg.h +++ b/src/soc/intel/common/block/include/intelblocks/cfg.h @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2018 Intel Corporation. + * Copyright (C) 2018-2020 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -37,6 +37,7 @@ /* PCH Thermal Trip Temperature in deg C */ uint8_t pch_thermal_trip; struct mmc_dll_params emmc_dll; + int enable_above_4GB_mmio; };
/* This function to retrieve soc config structure required by common code */ diff --git a/src/soc/intel/common/block/include/intelblocks/nvs.h b/src/soc/intel/common/block/include/intelblocks/nvs.h index 5f367b6..30502f1 100644 --- a/src/soc/intel/common/block/include/intelblocks/nvs.h +++ b/src/soc/intel/common/block/include/intelblocks/nvs.h @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2019 Intel Corporation. + * Copyright (C) 2019-2020 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -38,7 +38,10 @@ u16 u2we; /* 0x2b - 0x2c USB2 Wake Enable Bitmap */ u16 u3we; /* 0x2d - 0x2e USB3 Wake Enable Bitmap */ u8 uior; /* 0x2f - UART debug controller init on S3 resume */ - u8 unused[208]; + u8 e4gm; /* 0x30 - Enable above 4GB MMIO Resource */ + u64 a4gb; /* 0x31 - 0x38 Base of above 4GB MMIO Resource */ + u64 a4gs; /* 0x39 - 0x40 Length of above 4GB MMIO Resource */ + u8 unused[191];
/* ChromeOS specific (0x100 - 0xfff) */ chromeos_acpi_t chromeos; diff --git a/src/soc/intel/common/block/include/intelblocks/systemagent.h b/src/soc/intel/common/block/include/intelblocks/systemagent.h index 163d97e..c605958 100644 --- a/src/soc/intel/common/block/include/intelblocks/systemagent.h +++ b/src/soc/intel/common/block/include/intelblocks/systemagent.h @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright 2017 Intel Corporation. + * Copyright 2017-2020 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -18,6 +18,7 @@
#include <device/device.h> #include <soc/iomap.h> +#include <soc/nvs.h> #include <stddef.h>
/* Device 0:0.0 PCI configuration space */ @@ -82,6 +83,8 @@ uintptr_t sa_get_tseg_base(void); /* API to get TSEG size */ size_t sa_get_tseg_size(void); +/* Fill MMIO resource above 4GB into GNVS */ +void sa_fill_gnvs(global_nvs_t *gnvs); /* * SoC overrides * diff --git a/src/soc/intel/common/block/systemagent/systemagent.c b/src/soc/intel/common/block/systemagent/systemagent.c index 2da3992..0fab7d9 100644 --- a/src/soc/intel/common/block/systemagent/systemagent.c +++ b/src/soc/intel/common/block/systemagent/systemagent.c @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2017-2018 Intel Corporation. + * Copyright (C) 2017-2020 Intel Corporation. * Copyright (C) 2019 Siemens AG * * This program is free software; you can redistribute it and/or modify @@ -14,12 +14,13 @@ * GNU General Public License for more details. */
-#include <device/pci_ops.h> #include <cbmem.h> +#include <console/console.h> #include <device/device.h> #include <device/pci.h> #include <device/pci_ids.h> #include <intelblocks/acpi.h> +#include <intelblocks/cfg.h> #include <intelblocks/systemagent.h> #include <smbios.h> #include <soc/iomap.h> @@ -54,6 +55,34 @@ }
/* + * This function will get above 4GB mmio enable config specific to soc. + * + * Return values: + * 0 = Above 4GB memory is not enable + * 1 = Above 4GB memory is enable + */ +static int get_enable_above_4GB_mmio(void) +{ + const struct soc_intel_common_config *common_config; + common_config = chip_get_common_soc_structure(); + + return common_config->enable_above_4GB_mmio; +} + +/* Fill MMIO resource above 4GB into GNVS */ +void sa_fill_gnvs(global_nvs_t *gnvs) +{ + if (get_enable_above_4GB_mmio()) { + gnvs->e4gm = 1; + gnvs->a4gb = ABOVE_4GB_MEM_BASE_ADDRESS; + gnvs->a4gs = ABOVE_4GB_MEM_BASE_SIZE; + printk(BIOS_DEBUG, + "PCI space above 4GB MMIO is from 0x%llx to len = 0x%llx\n", + gnvs->a4gb, gnvs->a4gs); + } +} + +/* * Add all known fixed MMIO ranges that hang off the host bridge/memory * controller device. */ diff --git a/src/soc/intel/icelake/acpi.c b/src/soc/intel/icelake/acpi.c index 728cfb1..a2ed8d9 100644 --- a/src/soc/intel/icelake/acpi.c +++ b/src/soc/intel/icelake/acpi.c @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2018 Intel Corp. + * Copyright (C) 2018-2020 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -28,6 +28,7 @@ #include <soc/pci_devs.h> #include <soc/pm.h> #include <soc/soc_chip.h> +#include <soc/systemagent.h> #include <string.h> #include <vendorcode/google/chromeos/gnvs.h> #include <wrdd.h> @@ -223,6 +224,9 @@ /* Set USB2/USB3 wake enable bitmaps. */ gnvs->u2we = config->usb2_wake_enable_bitmap; gnvs->u3we = config->usb3_wake_enable_bitmap; + + /* Fill in Above 4GB MMIO resource */ + sa_fill_gnvs(gnvs); }
uint32_t acpi_fill_soc_wake(uint32_t generic_pm1_en, diff --git a/src/soc/intel/icelake/include/soc/iomap.h b/src/soc/intel/icelake/include/soc/iomap.h index 218b8bf..50ba005 100644 --- a/src/soc/intel/icelake/include/soc/iomap.h +++ b/src/soc/intel/icelake/include/soc/iomap.h @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2018 Intel Corporation. + * Copyright (C) 2018-2020 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -60,6 +60,10 @@
#define VTD_BASE_ADDRESS 0xFED90000 #define VTD_BASE_SIZE 0x00004000 + +#define ABOVE_4GB_MEM_BASE_ADDRESS (256ULL * GiB) +#define ABOVE_4GB_MEM_BASE_SIZE (256ULL * GiB) + /* * I/O port address space */ diff --git a/src/soc/intel/skylake/acpi.c b/src/soc/intel/skylake/acpi.c index 332f797..bf54854 100644 --- a/src/soc/intel/skylake/acpi.c +++ b/src/soc/intel/skylake/acpi.c @@ -3,7 +3,7 @@ * * Copyright (C) 2009 coresystems GmbH * Copyright (C) 2014 Google Inc. - * Copyright (C) 2015-2019 Intel Corporation. + * Copyright (C) 2015-2020 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -207,6 +207,9 @@
if (CONFIG(SOC_INTEL_COMMON_BLOCK_SGX_ENABLE)) sgx_fill_gnvs(gnvs); + + /* Fill in Above 4GB MMIO resource */ + sa_fill_gnvs(gnvs); }
unsigned long acpi_fill_mcfg(unsigned long current) diff --git a/src/soc/intel/skylake/acpi/globalnvs.asl b/src/soc/intel/skylake/acpi/globalnvs.asl index c4544e8..b2467f9 100644 --- a/src/soc/intel/skylake/acpi/globalnvs.asl +++ b/src/soc/intel/skylake/acpi/globalnvs.asl @@ -3,7 +3,7 @@ * * Copyright (C) 2007-2009 coresystems GmbH * Copyright (C) 2014 Google Inc. - * Copyright (C) 2015 Intel Corporation. + * Copyright (C) 2015-2020 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -70,6 +70,9 @@ EPCS, 8, // 0x43 - SGX Enabled status EMNA, 64, // 0x44 - 0x4B EPC base address ELNG, 64, // 0x4C - 0x53 EPC Length + E4GM, 8, // 0x54 - Enable above 4GB MMIO Resource + A4GB, 64, // 0x55 - 0x5C Base of above 4GB MMIO Resource + A4GS, 64, // 0x5D - 0x64 Length of above 4GB MMIO Resource
/* IGD OpRegion */ Offset (0xb4), diff --git a/src/soc/intel/skylake/acpi/systemagent.asl b/src/soc/intel/skylake/acpi/systemagent.asl index 589fcc1..89380aa 100644 --- a/src/soc/intel/skylake/acpi/systemagent.asl +++ b/src/soc/intel/skylake/acpi/systemagent.asl @@ -3,7 +3,7 @@ * * Copyright (C) 2007-2009 coresystems GmbH * Copyright (C) 2015 Google Inc. - * Copyright (C) 2015 Intel Corporation. + * Copyright (C) 2015-2020 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -17,9 +17,6 @@
#include <soc/iomap.h>
-#define BASE_32GB 0x800000000 -#define SIZE_16GB 0x400000000 - Name (_HID, EISAID ("PNP0A08")) /* PCIe */ Name (_CID, EISAID ("PNP0A03")) /* PCI */
@@ -214,20 +211,18 @@ Add (Subtract (PMAX, PMIN), 1, PLEN)
/* Patch PM02 range based on Memory Size */ - CreateQwordField (MCRS, PM02._MIN, MMIN) - CreateQwordField (MCRS, PM02._MAX, MMAX) - CreateQwordField (MCRS, PM02._LEN, MLEN) - - Store (_SB.PCI0.MCHC.TUUD, Local0) - - If (LLessEqual (Local0, BASE_32GB)) { - Store (BASE_32GB, MMIN) - Store (SIZE_16GB, MLEN) + If (LEqual (A4GS, 0)) { + CreateQwordField (MCRS, PM02._LEN, MSEN) + Store (0, MSEN) } Else { - Store (0, MMIN) - Store (0, MLEN) + CreateQwordField (MCRS, PM02._MIN, MMIN) + CreateQwordField (MCRS, PM02._MAX, MMAX) + CreateQwordField (MCRS, PM02._LEN, MLEN) + /* Set 64bit MMIO resource base and length */ + Store (A4GS, MLEN) + Store (A4GB, MMIN) + Subtract (Add (MMIN, MLEN), 1, MMAX) } - Subtract (Add (MMIN, MLEN), 1, MMAX)
Return (MCRS) } diff --git a/src/soc/intel/skylake/include/soc/iomap.h b/src/soc/intel/skylake/include/soc/iomap.h index 814dd94..b447d79 100644 --- a/src/soc/intel/skylake/include/soc/iomap.h +++ b/src/soc/intel/skylake/include/soc/iomap.h @@ -2,7 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2014 Google Inc. - * Copyright (C) 2015 Intel Corporation. + * Copyright (C) 2015-2020 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -75,6 +75,9 @@ #define PTT_TXT_BASE_ADDRESS 0xfed30800 #define PTT_PRESENT 0x00070000
+#define ABOVE_4GB_MEM_BASE_ADDRESS (128ULL * GiB) +#define ABOVE_4GB_MEM_BASE_SIZE (64ULL * GiB) + /* * I/O port address space */ diff --git a/src/soc/intel/skylake/include/soc/nvs.h b/src/soc/intel/skylake/include/soc/nvs.h index 72b1ac9..d5f62f6 100644 --- a/src/soc/intel/skylake/include/soc/nvs.h +++ b/src/soc/intel/skylake/include/soc/nvs.h @@ -3,7 +3,7 @@ * * Copyright (C) 2008-2009 coresystems GmbH * Copyright (C) 2014 Google Inc. - * Copyright (C) 2015 Intel Corporation. + * Copyright (C) 2015-2020 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -60,7 +60,10 @@ u8 ecps; /* 0x43 - SGX Enabled status */ u64 emna; /* 0x44 - 0x4B EPC base address */ u64 elng; /* 0x4C - 0x53 EPC Length */ - u8 rsvd[96]; + u8 e4gm; /* 0x54 - Enable above 4GB MMIO Resource */ + u64 a4gb; /* 0x55 - 0x5C Base of above 4GB MMIO Resource */ + u64 a4gs; /* 0x5D - 0x64 Length of above 4GB MMIO Resource */ + u8 rsvd[79];
/* IGD OpRegion */ u32 aslb; /* 0xb4 - IGD OpRegion Base Address */ diff --git a/src/soc/intel/tigerlake/acpi.c b/src/soc/intel/tigerlake/acpi.c index 5e04c9a..b9cae3c 100644 --- a/src/soc/intel/tigerlake/acpi.c +++ b/src/soc/intel/tigerlake/acpi.c @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2019 Intel Corp. + * Copyright (C) 2019-2020 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -28,6 +28,7 @@ #include <soc/pci_devs.h> #include <soc/pm.h> #include <soc/soc_chip.h> +#include <soc/systemagent.h> #include <string.h> #include <wrdd.h>
@@ -223,6 +224,9 @@ /* Set USB2/USB3 wake enable bitmaps. */ gnvs->u2we = config->usb2_wake_enable_bitmap; gnvs->u3we = config->usb3_wake_enable_bitmap; + + /* Fill in Above 4GB MMIO resource */ + sa_fill_gnvs(gnvs); }
uint32_t acpi_fill_soc_wake(uint32_t generic_pm1_en, diff --git a/src/soc/intel/tigerlake/include/soc/iomap.h b/src/soc/intel/tigerlake/include/soc/iomap.h index b3797c1..72ac25f 100644 --- a/src/soc/intel/tigerlake/include/soc/iomap.h +++ b/src/soc/intel/tigerlake/include/soc/iomap.h @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2019 Intel Corporation. + * Copyright (C) 2019-2020 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -66,6 +66,10 @@
#define VTD_BASE_ADDRESS 0xFED90000 #define VTD_BASE_SIZE 0x00004000 + +#define ABOVE_4GB_MEM_BASE_ADDRESS (256ULL * GiB) +#define ABOVE_4GB_MEM_BASE_SIZE (256ULL * GiB) + /* * I/O port address space */
Aaron Durbin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38125 )
Change subject: soc/intel/{apl,cnl,icl,skl,tgl}: Make above 4GB MMIO resource proper ......................................................................
Patch Set 10:
(2 comments)
https://review.coreboot.org/c/coreboot/+/38125/10//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/38125/10//COMMIT_MSG@25 PS10, Line 25: [ 2.352541] [drm] Not enough PCI address space for a large BAR. This commit description could have been clearer. I'm not exactly sure what the problem was...
1. What range was the discrete gpu's BAR getting assigned with coreboot? 2. It seems those 64-bit BARs were being assigned by the kernel. Not coreboot. Is that true? 3. Or was the big one assigned a smaller BAR? Though, I'm not sure how since there's a single address. 4. What is the PM02 field supposed to represent?
https://review.coreboot.org/c/coreboot/+/38125/10/src/soc/intel/apollolake/i... File src/soc/intel/apollolake/include/soc/iomap.h:
https://review.coreboot.org/c/coreboot/+/38125/10/src/soc/intel/apollolake/i... PS10, Line 63: #define ABOVE_4GB_MEM_BASE_ADDRESS (128ULL * GiB) There is no comment as to what this supposed to mean. Is this the base address of physical address space that will be decoded as MMIO? And the size (64 GiB) is the length? So the range is [2^37 : 2^37 + 2^36) ?
Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38125 )
Change subject: soc/intel/{apl,cnl,icl,skl,tgl}: Make above 4GB MMIO resource proper ......................................................................
Patch Set 10:
(2 comments)
https://review.coreboot.org/c/coreboot/+/38125/10//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/38125/10//COMMIT_MSG@25 PS10, Line 25: [ 2.352541] [drm] Not enough PCI address space for a large BAR.
This commit description could have been clearer. I'm not exactly sure what the problem was...
- What range was the discrete gpu's BAR getting assigned with coreboot?
[Subrata] Coreboot is assigning the resources between TOLUD memory address as below
PCI: 00:1c.0 child on link 0 PCI: 05:00.0 PCI: 00:1c.0 resource base 2000 size 1000 align 12 gran 12 limit 2fff flags 60080102 index 1c PCI: 00:1c.0 resource base 80000000 size 10200000 align 28 gran 20 limit 901fffff flags 60081202 index 24 PCI: 00:1c.0 resource base b2000000 size 100000 align 20 gran 20 limit b20fffff flags 60080202 index 20 PCI: 05:00.0 PCI: 05:00.0 resource base 80000000 size 10000000 align 28 gran 28 limit 8fffffff flags 60001201 index 10 PCI: 05:00.0 resource base 90000000 size 200000 align 21 gran 21 limit 901fffff flags 60001201 index 18 PCI: 05:00.0 resource base 2000 size 100 align 8 gran 8 limit 20ff flags 60000100 index 20 PCI: 05:00.0 resource base b2000000 size 40000 align 18 gran 18 limit b203ffff flags 60000200 index 24 PCI: 05:00.0 resource base b2040000 size 20000 align 17 gran 17 limit b205ffff flags 60002200 index 30
- It seems those 64-bit BARs were being assigned by the kernel. Not coreboot. Is that true?
[Subrata] As Coreboot is broadcasting above 4GB (TOUUD + memory) range, then kernel tries to reassign PCIE and DGPU BAR with above 4GB resources as below and it complained about not enough memory available.
[ 8.744719] pcieport 0000:00:1c.0: bridge window [mem 0x840000000-0x8c01fffff 64bit pref] [ 8.744719] pcieport 0000:00:1c.0: bridge window [mem 0x840000000-0x8c01fffff 64bit pref] [ 8.761505] pcieport 0000:00:1c.0: PCI bridge to [bus 05] [ 8.761505] pcieport 0000:00:1c.0: PCI bridge to [bus 05] [ 8.772339] pcieport 0000:00:1c.0: bridge window [io 0x2000-0x2fff] [ 8.772339] pcieport 0000:00:1c.0: bridge window [io 0x2000-0x2fff] [ 8.785464] pcieport 0000:00:1c.0: bridge window [mem 0xb2000000-0xb20fffff] [ 8.785464] pcieport 0000:00:1c.0: bridge window [mem 0xb2000000-0xb20fffff] [ 8.799972] pcieport 0000:00:1c.0: bridge window [mem 0x80000000-0x901fffff 64bit pref] [ 8.799972] pcieport 0000:00:1c.0: bridge window [mem 0x80000000-0x901fffff 64bit pref] [ 8.816412] [drm] Not enough PCI address space for a large BAR. [ 8.816412] [drm] Not enough PCI address space for a large BAR. [ 8.816415] amdgpu 0000:05:00.0: BAR 0: assigned [mem 0x80000000-0x8fffffff 64bit pref] [ 8.816415] amdgpu 0000:05:00.0: BAR 0: assigned [mem 0x80000000-0x8fffffff 64bit pref] [ 34.388444] watchdog: BUG: soft lockup - CPU#3 stuck for 23s! [swapper/0:1] [ 34.388444] watchdog: BUG: soft lockup - CPU#3 stuck for 23s! [swapper/0:1] [ 34.814531] Kernel panic - not syncing: softlockup: hung tasks [ 34.814531] Kernel panic - not syncing: softlockup: hung tasks [ 34.814531] ACPI MEMORY or I/O RESET_REG. [ 34.814531] ACPI MEMORY or I/O RESET_REG.
- Or was the big one assigned a smaller BAR? Though, I'm not sure how since there's a single address.
[Subrata] Not enough memory to allocate above 4GB resource for DGPU. This is what i see when i have enable above 4GB resource in coreboot using config variable with DGPU connected.
4.089259] amdgpu 0000:ad:00.0: BAR 2: releasing [mem 0x50000000-0x501fffff 64bit pref] [ 4.097356] amdgpu 0000:ad:00.0: BAR 0: releasing [mem 0x40000000-0x4fffffff 64bit pref] [ 4.105483] pcieport 0000:00:1c.0: BAR 9: releasing [mem 0x40000000-0x501fffff 64bit pref] [ 4.113769] pcieport 0000:00:1c.0: BAR 9: assigned [mem 0x4080000000-0x41001fffff 64bit pref] [ 4.122309] amdgpu 0000:ad:00.0: BAR 0: assigned [mem 0x4080000000-0x40ffffffff 64bit pref] [ 4.130686] amdgpu 0000:ad:00.0: BAR 2: assigned [mem 0x4100000000-0x41001fffff 64bit pref] [ 4.139064] pcieport 0000:00:1c.0: PCI bridge to [bus ad] [ 4.144476] pcieport 0000:00:1c.0: bridge window [io 0x3000-0x3fff] [ 4.151021] pcieport 0000:00:1c.0: bridge window [mem 0x88200000-0x882fffff] [ 4.158258] pcieport 0000:00:1c.0: bridge window [mem 0x4080000000-0x41001fffff 64bit pref] [ 4.166813] amdgpu 0000:ad:00.0: VRAM: 2048M 0x000000F400000000 - 0x000000F47FFFFFFF (2048M used) [ 4.175697] amdgpu 0000:ad:00.0: GART: 256M 0x000000FF00000000 - 0x000000FF0FFFFFFF
- What is the PM02 field supposed to represent?
PM02 is to override TOUUD base and size
/* PCI Memory Region (TUUD - (TUUD + ABOVE_4G_MMIO_SIZE)) */ QWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite, 0x00000000, 0x10000, 0x1ffff, 0x00000000, 0x10000,,, PM02)
https://review.coreboot.org/c/coreboot/+/38125/10/src/soc/intel/apollolake/i... File src/soc/intel/apollolake/include/soc/iomap.h:
https://review.coreboot.org/c/coreboot/+/38125/10/src/soc/intel/apollolake/i... PS10, Line 63: #define ABOVE_4GB_MEM_BASE_ADDRESS (128ULL * GiB)
There is no comment as to what this supposed to mean. […]
i will add comment section
Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38125 )
Change subject: soc/intel/{apl,cnl,icl,skl,tgl}: Make above 4GB MMIO resource proper ......................................................................
Patch Set 10:
(1 comment)
https://review.coreboot.org/c/coreboot/+/38125/10/src/soc/intel/apollolake/i... File src/soc/intel/apollolake/include/soc/iomap.h:
https://review.coreboot.org/c/coreboot/+/38125/10/src/soc/intel/apollolake/i... PS10, Line 63: #define ABOVE_4GB_MEM_BASE_ADDRESS (128ULL * GiB)
i will add comment section
Please review https://review.coreboot.org/c/coreboot/+/38388/1
Aaron Durbin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38125 )
Change subject: soc/intel/{apl,cnl,icl,skl,tgl}: Make above 4GB MMIO resource proper ......................................................................
Patch Set 10:
(1 comment)
https://review.coreboot.org/c/coreboot/+/38125/10/src/soc/intel/skylake/acpi... File src/soc/intel/skylake/acpi/systemagent.asl:
https://review.coreboot.org/c/coreboot/+/38125/10/src/soc/intel/skylake/acpi... PS10, Line 223: Store (A4GB, MMIN) So it looks like we always setting the same fixed physical window for this resource? Correct?
-
Aaron Durbin (Code Review) -
Lance Zhao (Code Review)
-
Pratikkumar V Prajapati (Code Review)
-
Rizwan Qureshi (Code Review)
-
Subrata Banik (Code Review)
-
Wonkyu Kim (Code Review)