Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38125 )
Change subject: soc/intel/{apl,cnl,icl,skl,tgl}: Make above 4GB MMIO resource proper ......................................................................
Patch Set 10:
(2 comments)
https://review.coreboot.org/c/coreboot/+/38125/10//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/38125/10//COMMIT_MSG@25 PS10, Line 25: [ 2.352541] [drm] Not enough PCI address space for a large BAR.
This commit description could have been clearer. I'm not exactly sure what the problem was...
- What range was the discrete gpu's BAR getting assigned with coreboot?
[Subrata] Coreboot is assigning the resources between TOLUD memory address as below
PCI: 00:1c.0 child on link 0 PCI: 05:00.0 PCI: 00:1c.0 resource base 2000 size 1000 align 12 gran 12 limit 2fff flags 60080102 index 1c PCI: 00:1c.0 resource base 80000000 size 10200000 align 28 gran 20 limit 901fffff flags 60081202 index 24 PCI: 00:1c.0 resource base b2000000 size 100000 align 20 gran 20 limit b20fffff flags 60080202 index 20 PCI: 05:00.0 PCI: 05:00.0 resource base 80000000 size 10000000 align 28 gran 28 limit 8fffffff flags 60001201 index 10 PCI: 05:00.0 resource base 90000000 size 200000 align 21 gran 21 limit 901fffff flags 60001201 index 18 PCI: 05:00.0 resource base 2000 size 100 align 8 gran 8 limit 20ff flags 60000100 index 20 PCI: 05:00.0 resource base b2000000 size 40000 align 18 gran 18 limit b203ffff flags 60000200 index 24 PCI: 05:00.0 resource base b2040000 size 20000 align 17 gran 17 limit b205ffff flags 60002200 index 30
- It seems those 64-bit BARs were being assigned by the kernel. Not coreboot. Is that true?
[Subrata] As Coreboot is broadcasting above 4GB (TOUUD + memory) range, then kernel tries to reassign PCIE and DGPU BAR with above 4GB resources as below and it complained about not enough memory available.
[ 8.744719] pcieport 0000:00:1c.0: bridge window [mem 0x840000000-0x8c01fffff 64bit pref] [ 8.744719] pcieport 0000:00:1c.0: bridge window [mem 0x840000000-0x8c01fffff 64bit pref] [ 8.761505] pcieport 0000:00:1c.0: PCI bridge to [bus 05] [ 8.761505] pcieport 0000:00:1c.0: PCI bridge to [bus 05] [ 8.772339] pcieport 0000:00:1c.0: bridge window [io 0x2000-0x2fff] [ 8.772339] pcieport 0000:00:1c.0: bridge window [io 0x2000-0x2fff] [ 8.785464] pcieport 0000:00:1c.0: bridge window [mem 0xb2000000-0xb20fffff] [ 8.785464] pcieport 0000:00:1c.0: bridge window [mem 0xb2000000-0xb20fffff] [ 8.799972] pcieport 0000:00:1c.0: bridge window [mem 0x80000000-0x901fffff 64bit pref] [ 8.799972] pcieport 0000:00:1c.0: bridge window [mem 0x80000000-0x901fffff 64bit pref] [ 8.816412] [drm] Not enough PCI address space for a large BAR. [ 8.816412] [drm] Not enough PCI address space for a large BAR. [ 8.816415] amdgpu 0000:05:00.0: BAR 0: assigned [mem 0x80000000-0x8fffffff 64bit pref] [ 8.816415] amdgpu 0000:05:00.0: BAR 0: assigned [mem 0x80000000-0x8fffffff 64bit pref] [ 34.388444] watchdog: BUG: soft lockup - CPU#3 stuck for 23s! [swapper/0:1] [ 34.388444] watchdog: BUG: soft lockup - CPU#3 stuck for 23s! [swapper/0:1] [ 34.814531] Kernel panic - not syncing: softlockup: hung tasks [ 34.814531] Kernel panic - not syncing: softlockup: hung tasks [ 34.814531] ACPI MEMORY or I/O RESET_REG. [ 34.814531] ACPI MEMORY or I/O RESET_REG.
- Or was the big one assigned a smaller BAR? Though, I'm not sure how since there's a single address.
[Subrata] Not enough memory to allocate above 4GB resource for DGPU. This is what i see when i have enable above 4GB resource in coreboot using config variable with DGPU connected.
4.089259] amdgpu 0000:ad:00.0: BAR 2: releasing [mem 0x50000000-0x501fffff 64bit pref] [ 4.097356] amdgpu 0000:ad:00.0: BAR 0: releasing [mem 0x40000000-0x4fffffff 64bit pref] [ 4.105483] pcieport 0000:00:1c.0: BAR 9: releasing [mem 0x40000000-0x501fffff 64bit pref] [ 4.113769] pcieport 0000:00:1c.0: BAR 9: assigned [mem 0x4080000000-0x41001fffff 64bit pref] [ 4.122309] amdgpu 0000:ad:00.0: BAR 0: assigned [mem 0x4080000000-0x40ffffffff 64bit pref] [ 4.130686] amdgpu 0000:ad:00.0: BAR 2: assigned [mem 0x4100000000-0x41001fffff 64bit pref] [ 4.139064] pcieport 0000:00:1c.0: PCI bridge to [bus ad] [ 4.144476] pcieport 0000:00:1c.0: bridge window [io 0x3000-0x3fff] [ 4.151021] pcieport 0000:00:1c.0: bridge window [mem 0x88200000-0x882fffff] [ 4.158258] pcieport 0000:00:1c.0: bridge window [mem 0x4080000000-0x41001fffff 64bit pref] [ 4.166813] amdgpu 0000:ad:00.0: VRAM: 2048M 0x000000F400000000 - 0x000000F47FFFFFFF (2048M used) [ 4.175697] amdgpu 0000:ad:00.0: GART: 256M 0x000000FF00000000 - 0x000000FF0FFFFFFF
- What is the PM02 field supposed to represent?
PM02 is to override TOUUD base and size
/* PCI Memory Region (TUUD - (TUUD + ABOVE_4G_MMIO_SIZE)) */ QWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite, 0x00000000, 0x10000, 0x1ffff, 0x00000000, 0x10000,,, PM02)
https://review.coreboot.org/c/coreboot/+/38125/10/src/soc/intel/apollolake/i... File src/soc/intel/apollolake/include/soc/iomap.h:
https://review.coreboot.org/c/coreboot/+/38125/10/src/soc/intel/apollolake/i... PS10, Line 63: #define ABOVE_4GB_MEM_BASE_ADDRESS (128ULL * GiB)
There is no comment as to what this supposed to mean. […]
i will add comment section