Aaron Durbin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38125 )
Change subject: soc/intel/{apl,cnl,icl,skl,tgl}: Make above 4GB MMIO resource proper ......................................................................
Patch Set 10:
(2 comments)
https://review.coreboot.org/c/coreboot/+/38125/10//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/38125/10//COMMIT_MSG@25 PS10, Line 25: [ 2.352541] [drm] Not enough PCI address space for a large BAR. This commit description could have been clearer. I'm not exactly sure what the problem was...
1. What range was the discrete gpu's BAR getting assigned with coreboot? 2. It seems those 64-bit BARs were being assigned by the kernel. Not coreboot. Is that true? 3. Or was the big one assigned a smaller BAR? Though, I'm not sure how since there's a single address. 4. What is the PM02 field supposed to represent?
https://review.coreboot.org/c/coreboot/+/38125/10/src/soc/intel/apollolake/i... File src/soc/intel/apollolake/include/soc/iomap.h:
https://review.coreboot.org/c/coreboot/+/38125/10/src/soc/intel/apollolake/i... PS10, Line 63: #define ABOVE_4GB_MEM_BASE_ADDRESS (128ULL * GiB) There is no comment as to what this supposed to mean. Is this the base address of physical address space that will be decoded as MMIO? And the size (64 GiB) is the length? So the range is [2^37 : 2^37 + 2^36) ?