Christoph Pomaska has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38920 )
Change subject: mb/gigabyte: Add Gigabyte Z170X-Gaming 7 ......................................................................
mb/gigabyte: Add Gigabyte Z170X-Gaming 7
Change-Id: Ib2c69bddd22cbd8f797dbb57370a4d8e5afa63bc --- A src/mainboard/gigabyte/ga-z170x-gaming7/Kconfig A src/mainboard/gigabyte/ga-z170x-gaming7/Kconfig.name A src/mainboard/gigabyte/ga-z170x-gaming7/Makefile.inc A src/mainboard/gigabyte/ga-z170x-gaming7/acpi/dptf.asl A src/mainboard/gigabyte/ga-z170x-gaming7/acpi/ec.asl A src/mainboard/gigabyte/ga-z170x-gaming7/acpi/mainboard.asl A src/mainboard/gigabyte/ga-z170x-gaming7/acpi/superio.asl A src/mainboard/gigabyte/ga-z170x-gaming7/board_info.txt A src/mainboard/gigabyte/ga-z170x-gaming7/cmos.default A src/mainboard/gigabyte/ga-z170x-gaming7/cmos.layout A src/mainboard/gigabyte/ga-z170x-gaming7/devicetree.cb A src/mainboard/gigabyte/ga-z170x-gaming7/dsdt.asl A src/mainboard/gigabyte/ga-z170x-gaming7/gma-mainboard.ads A src/mainboard/gigabyte/ga-z170x-gaming7/gpio.h A src/mainboard/gigabyte/ga-z170x-gaming7/hda_verb.c A src/mainboard/gigabyte/ga-z170x-gaming7/include/gpio.h A src/mainboard/gigabyte/ga-z170x-gaming7/mainboard.c A src/mainboard/gigabyte/ga-z170x-gaming7/ramstage.c A src/mainboard/gigabyte/ga-z170x-gaming7/romstage.c 19 files changed, 1,704 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/20/38920/1
diff --git a/src/mainboard/gigabyte/ga-z170x-gaming7/Kconfig b/src/mainboard/gigabyte/ga-z170x-gaming7/Kconfig new file mode 100644 index 0000000..3218b39 --- /dev/null +++ b/src/mainboard/gigabyte/ga-z170x-gaming7/Kconfig @@ -0,0 +1,49 @@ +if BOARD_GIGABYTE_GA_Z170X_GAMING_7 + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select BOARD_ROMSIZE_KB_16384 + select HAVE_ACPI_RESUME + select HAVE_ACPI_TABLES + select HAVE_OPTION_TABLE + select HAVE_CMOS_DEFAULT + select INTEL_GMA_HAVE_VBT + select INTEL_INT15 + select SOC_INTEL_KABYLAKE + select SKYLAKE_SOC_PCH_H + select SUPERIO_ITE_IT8528E # board has actually IT8628E + +config IRQ_SLOT_COUNT + int + default 18 + +config MAINBOARD_DIR + string + default "gigabyte/ga-z170x-gaming7" + +config MAINBOARD_PART_NUMBER + string + default "Z170X-Gaming 7" + +config MAX_CPUS + int + default 8 + +config DEVICETREE + string + default "devicetree.cb" + +config PRERAM_CBMEM_CONSOLE_SIZE + hex + default 0xd00 + +config DIMM_SPD_SIZE + int + default 512 #DDR4 + +# This is overridden if CMOS is used for configuration values. +config MAINBOARD_POWER_ON_AFTER_POWER_FAIL + bool + default n + +endif diff --git a/src/mainboard/gigabyte/ga-z170x-gaming7/Kconfig.name b/src/mainboard/gigabyte/ga-z170x-gaming7/Kconfig.name new file mode 100644 index 0000000..a0ff2d5 --- /dev/null +++ b/src/mainboard/gigabyte/ga-z170x-gaming7/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_GIGABYTE_Z170X_GAMING_7 + bool "GA-Z170X-Gaming 7" diff --git a/src/mainboard/gigabyte/ga-z170x-gaming7/Makefile.inc b/src/mainboard/gigabyte/ga-z170x-gaming7/Makefile.inc new file mode 100644 index 0000000..223820e --- /dev/null +++ b/src/mainboard/gigabyte/ga-z170x-gaming7/Makefile.inc @@ -0,0 +1,20 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2013 Google Inc. +## Copyright (C) 2016 Intel Corporation. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +ramstage-y += mainboard.c +ramstage-y += ramstage.c +ramstage-y += hda_verb.c +ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads diff --git a/src/mainboard/gigabyte/ga-z170x-gaming7/acpi/dptf.asl b/src/mainboard/gigabyte/ga-z170x-gaming7/acpi/dptf.asl new file mode 100644 index 0000000..4453f3b --- /dev/null +++ b/src/mainboard/gigabyte/ga-z170x-gaming7/acpi/dptf.asl @@ -0,0 +1,54 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Google Inc. + * Copyright (C) 2015 Intel Corporation. + * Copyright (C) 2019 Maxim Polyakov max.senia.poliak@gmail.com + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#define DPTF_CPU_PASSIVE 98 +#define DPTF_CPU_CRITICAL 125 +#define DPTF_CPU_ACTIVE_AC0 91 +#define DPTF_CPU_ACTIVE_AC1 85 +#define DPTF_CPU_ACTIVE_AC2 83 +#define DPTF_CPU_ACTIVE_AC3 80 +#define DPTF_CPU_ACTIVE_AC4 75 + +Name (DTRT, Package () { + /* CPU Throttle Effect on CPU */ + Package () { _SB.PCI0.B0D4, _SB.PCI0.B0D4, 100, 50, 0, 0, 0, 0 }, + +}) + +Name (MPPC, Package () +{ + 0x2, /* Revision */ + Package () { /* Power Limit 1 */ + 0, /* PowerLimitIndex, 0 for Power Limit 1 */ + 10000, /* PowerLimitMinimum */ + 31000, /* PowerLimitMaximum */ + 28000, /* TimeWindowMinimum */ + 28000, /* TimeWindowMaximum */ + 100 /* StepSize */ + }, + Package () { /* Power Limit 2 */ + 1, /* PowerLimitIndex, 1 for Power Limit 2 */ + 15000, /* PowerLimitMinimum */ + 65000, /* PowerLimitMaximum */ + 28000, /* TimeWindowMinimum */ + 28000, /* TimeWindowMaximum */ + 100 /* StepSize */ + } +}) + +/* Include DPTF */ +#include <soc/intel/skylake/acpi/dptf/dptf.asl> diff --git a/src/mainboard/gigabyte/ga-z170x-gaming7/acpi/ec.asl b/src/mainboard/gigabyte/ga-z170x-gaming7/acpi/ec.asl new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/src/mainboard/gigabyte/ga-z170x-gaming7/acpi/ec.asl diff --git a/src/mainboard/gigabyte/ga-z170x-gaming7/acpi/mainboard.asl b/src/mainboard/gigabyte/ga-z170x-gaming7/acpi/mainboard.asl new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/src/mainboard/gigabyte/ga-z170x-gaming7/acpi/mainboard.asl diff --git a/src/mainboard/gigabyte/ga-z170x-gaming7/acpi/superio.asl b/src/mainboard/gigabyte/ga-z170x-gaming7/acpi/superio.asl new file mode 100644 index 0000000..8b13789 --- /dev/null +++ b/src/mainboard/gigabyte/ga-z170x-gaming7/acpi/superio.asl @@ -0,0 +1 @@ + diff --git a/src/mainboard/gigabyte/ga-z170x-gaming7/board_info.txt b/src/mainboard/gigabyte/ga-z170x-gaming7/board_info.txt new file mode 100644 index 0000000..c6b7655 --- /dev/null +++ b/src/mainboard/gigabyte/ga-z170x-gaming7/board_info.txt @@ -0,0 +1,7 @@ +Category: desktop +Board URL: https://www.gigabyte.com/Motherboard/GA-Z170X-Gaming-7-rev-10 +ROM package: SOIC-8 +ROM protocol: SPI +ROM socketed: n +Flashrom support: y +Release year: 2015 diff --git a/src/mainboard/gigabyte/ga-z170x-gaming7/cmos.default b/src/mainboard/gigabyte/ga-z170x-gaming7/cmos.default new file mode 100644 index 0000000..3296093 --- /dev/null +++ b/src/mainboard/gigabyte/ga-z170x-gaming7/cmos.default @@ -0,0 +1,4 @@ +boot_option=Fallback +debug_level=Debug +power_on_after_fail=Disable +nmi=Enable diff --git a/src/mainboard/gigabyte/ga-z170x-gaming7/cmos.layout b/src/mainboard/gigabyte/ga-z170x-gaming7/cmos.layout new file mode 100644 index 0000000..916db62 --- /dev/null +++ b/src/mainboard/gigabyte/ga-z170x-gaming7/cmos.layout @@ -0,0 +1,125 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2007-2008 coresystems GmbH +## Copyright (C) 2016 Intel Corporation. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +# ----------------------------------------------------------------- +entries + +#start-bit length config config-ID name +#0 8 r 0 seconds +#8 8 r 0 alarm_seconds +#16 8 r 0 minutes +#24 8 r 0 alarm_minutes +#32 8 r 0 hours +#40 8 r 0 alarm_hours +#48 8 r 0 day_of_week +#56 8 r 0 day_of_month +#64 8 r 0 month +#72 8 r 0 year +# ----------------------------------------------------------------- +# Status Register A +#80 4 r 0 rate_select +#84 3 r 0 REF_Clock +#87 1 r 0 UIP +# ----------------------------------------------------------------- +# Status Register B +#88 1 r 0 auto_switch_DST +#89 1 r 0 24_hour_mode +#90 1 r 0 binary_values_enable +#91 1 r 0 square-wave_out_enable +#92 1 r 0 update_finished_enable +#93 1 r 0 alarm_interrupt_enable +#94 1 r 0 periodic_interrupt_enable +#95 1 r 0 disable_clock_updates +# ----------------------------------------------------------------- +# Status Register C +#96 4 r 0 status_c_rsvd +#100 1 r 0 uf_flag +#101 1 r 0 af_flag +#102 1 r 0 pf_flag +#103 1 r 0 irqf_flag +# ----------------------------------------------------------------- +# Status Register D +#104 7 r 0 status_d_rsvd +#111 1 r 0 valid_cmos_ram +# ----------------------------------------------------------------- +# Diagnostic Status Register +#112 8 r 0 diag_rsvd1 + +# ----------------------------------------------------------------- +0 120 r 0 reserved_memory +#120 264 r 0 unused + +# ----------------------------------------------------------------- +# RTC_BOOT_BYTE (coreboot hardcoded) +384 1 e 4 boot_option +388 4 h 0 reboot_counter +#390 2 r 0 unused? + +# ----------------------------------------------------------------- +# coreboot config options: console +#392 3 r 0 unused +395 4 e 6 debug_level +#399 1 r 0 unused + +# coreboot config options: cpu +400 1 e 2 hyper_threading +#401 7 r 0 unused + +# coreboot config options: southbridge +408 1 e 1 nmi +409 2 e 7 power_on_after_fail +#411 5 r 0 unused + +# coreboot config options: bootloader +#Used by ChromeOS: +416 128 r 0 vbnv +#544 440 r 0 unused + +# SandyBridge MRC Scrambler Seed values +896 32 r 0 mrc_scrambler_seed +928 32 r 0 mrc_scrambler_seed_s3 + +# coreboot config options: check sums +984 16 h 0 check_sum +#1000 24 r 0 amd_reserved + +# ----------------------------------------------------------------- + +enumerations + +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +6 0 Emergency +6 1 Alert +6 2 Critical +6 3 Error +6 4 Warning +6 5 Notice +6 6 Info +6 7 Debug +6 8 Spew +7 0 Disable +7 1 Enable +7 2 Keep +# ----------------------------------------------------------------- +checksums + +checksum 392 415 984 diff --git a/src/mainboard/gigabyte/ga-z170x-gaming7/devicetree.cb b/src/mainboard/gigabyte/ga-z170x-gaming7/devicetree.cb new file mode 100644 index 0000000..29fbd71 --- /dev/null +++ b/src/mainboard/gigabyte/ga-z170x-gaming7/devicetree.cb @@ -0,0 +1,439 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2017 Intel Corporation. +## Copyright (C) 2019 Maxim Polyakov max.senia.poliak@gmail.com +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +chip soc/intel/skylake + + register "deep_s3_enable_ac" = "0" + register "deep_s3_enable_dc" = "0" + register "deep_s5_enable_ac" = "0" + register "deep_s5_enable_dc" = "0" + register "deep_sx_config" = "DSX_EN_WAKE_PIN" + + register "eist_enable" = "1" + + # GPE configuration + # Note that GPE events called out in ASL code rely on this + # route. i.e. If this route changes then the affected GPE + # offset bits also need to be changed. + register "gpe0_dw0" = "GPP_B" + register "gpe0_dw1" = "GPP_D" + register "gpe0_dw2" = "GPP_E" + + # Set @0x280-0x2ff I/O Range for SuperIO HWM + register "gen1_dec" = "0x00fc0201" + register "gen2_dec" = "0x007c0a01" + register "gen3_dec" = "0x000c0081" + + # Enable "Intel Speed Shift Technology" + register "speed_shift_enable" = "1" + + # Enable DPTF + register "dptf_enable" = "1" + + # FSP Configuration + register "SmbusEnable" = "1" + register "ScsEmmcEnabled" = "0" + register "ScsEmmcHs400Enabled" = "0" + register "ScsSdCardEnabled" = "0" + register "HeciEnabled" = "0" + register "SkipExtGfxScan" = "0" + register "PrimaryDisplay" = "Display_PEG" + register "Device4Enable" = "1" + register "SaGv" = "SaGv_Enabled" + register "PmTimerDisabled" = "0" + register "EnableAzalia" = "1" + register "DspEnable" = "0" + register "PchHdaVcType" = "Vc1" + + register "pirqa_routing" = "PCH_IRQ11" + register "pirqb_routing" = "PCH_IRQ10" + register "pirqc_routing" = "PCH_IRQ11" + register "pirqd_routing" = "PCH_IRQ11" + register "pirqe_routing" = "PCH_IRQ11" + register "pirqf_routing" = "PCH_IRQ11" + register "pirqg_routing" = "PCH_IRQ11" + register "pirqh_routing" = "PCH_IRQ11" + + # Set LPC Serial IRQ mode + register "serirq_mode" = "SERIRQ_CONTINUOUS" + + # Enabling SLP_S3#, SLP_S4#, SLP_SUS and SLP_A Stretch + # SLP_S3 Minimum Assertion Width. Values 0: 60us, 1: 1ms, 2: 50ms, 3: 2s + register "PmConfigSlpS3MinAssert" = "0x02" + + # SLP_S4 Minimum Assertion Width. Values 0: default, 1: 1s, 2: 2s, 3: 3s, 4: 4s + register "PmConfigSlpS4MinAssert" = "0x04" + + # SLP_SUS Minimum Assertion Width. Values 0: 0ms, 1: 500ms, 2: 1s, 3: 4s + register "PmConfigSlpSusMinAssert" = "0x03" + + # SLP_A Minimum Assertion Width. Values 0: 0ms, 1: 4s, 2: 98ms, 3: 2s + register "PmConfigSlpAMinAssert" = "0x03" + + # VR Settings Configuration + #+----------------+-------+-------+-------------+-------+ + #| Domain/Setting | SA | IA | GT Unsliced | GT | + #+----------------+-------+-------+-------------+-------+ + #| Psi1Threshold | 20A | 20A | 20A | 20A | + #| Psi2Threshold | 4A | 5A | 5A | 5A | + #| Psi3Threshold | 1A | 1A | 1A | 1A | + #| Psi3Enable | 1 | 1 | 1 | 1 | + #| Psi4Enable | 1 | 1 | 1 | 1 | + #| ImonSlope | 0 | 0 | 0 | 0 | + #| ImonOffset | 0 | 0 | 0 | 0 | + #| IccMax* | 0 | 0 | 0 | 0 | + #| VrVoltageLimit | 1.52V | 1.52V | 1.52V | 1.52V | + #+----------------+-------+-------+-------------+-------+ + # * - is set automatically in the vr_config.c + register "domain_vr_config[VR_SYSTEM_AGENT]" = "{ + .vr_config_enable = 1, \ + .psi1threshold = VR_CFG_AMP(20), \ + .psi2threshold = VR_CFG_AMP(4), \ + .psi3threshold = VR_CFG_AMP(1), \ + .psi3enable = 1, \ + .psi4enable = 1, \ + .imon_slope = 0x0, \ + .imon_offset = 0x0, \ + .icc_max = 0x0, \ + .voltage_limit = 1520 \ + }" + + register "domain_vr_config[VR_IA_CORE]" = "{ + .vr_config_enable = 1, \ + .psi1threshold = VR_CFG_AMP(20), \ + .psi2threshold = VR_CFG_AMP(5), \ + .psi3threshold = VR_CFG_AMP(1), \ + .psi3enable = 1, \ + .psi4enable = 1, \ + .imon_slope = 0x0, \ + .imon_offset = 0x0, \ + .icc_max = 0x0, \ + .voltage_limit = 1520 \ + }" + + register "domain_vr_config[VR_GT_UNSLICED]" = "{ + .vr_config_enable = 1, \ + .psi1threshold = VR_CFG_AMP(20), \ + .psi2threshold = VR_CFG_AMP(5), \ + .psi3threshold = VR_CFG_AMP(1), \ + .psi3enable = 1, \ + .psi4enable = 1, \ + .imon_slope = 0x0, \ + .imon_offset = 0x0, \ + .icc_max = 0x0 ,\ + .voltage_limit = 1520 \ + }" + + register "domain_vr_config[VR_GT_SLICED]" = "{ + .vr_config_enable = 1, \ + .psi1threshold = VR_CFG_AMP(20), \ + .psi2threshold = VR_CFG_AMP(5), \ + .psi3threshold = VR_CFG_AMP(1), \ + .psi3enable = 1, \ + .psi4enable = 1, \ + .imon_slope = 0x0, \ + .imon_offset = 0x0, \ + .icc_max = 0x0, \ + .voltage_limit = 1520 \ + }" + + register "EnableLan" = "1" + register "PmTimerDisabled" = "0" + + # USB + register "usb2_ports[0]" = "USB2_PORT_MID(OC0)" + register "usb2_ports[1]" = "USB2_PORT_MID(OC0)" + register "usb2_ports[2]" = "USB2_PORT_MID(OC4)" + register "usb2_ports[3]" = "USB2_PORT_MID(OC4)" + register "usb2_ports[4]" = "USB2_PORT_MID(OC2)" + register "usb2_ports[5]" = "USB2_PORT_MID(OC2)" + register "usb2_ports[6]" = "USB2_PORT_MID(OC0)" + register "usb2_ports[7]" = "USB2_PORT_MID(OC0)" + register "usb2_ports[8]" = "USB2_PORT_MID(OC0)" + register "usb2_ports[9]" = "USB2_PORT_MID(OC0)" + register "usb2_ports[10]" = "USB2_PORT_MID(OC1)" + register "usb2_ports[11]" = "USB2_PORT_MID(OC1)" + register "usb2_ports[12]" = "USB2_PORT_MID(OC_SKIP)" + register "usb2_ports[13]" = "USB2_PORT_MID(OC_SKIP)" + register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)" + register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC0)" + register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC3)" + register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC3)" + register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC1)" + register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC1)" + register "usb3_ports[6]" = "USB3_PORT_DEFAULT(OC_SKIP)" + register "usb3_ports[7]" = "USB3_PORT_DEFAULT(OC_SKIP)" + register "usb3_ports[8]" = "USB3_PORT_DEFAULT(OC_SKIP)" + register "usb3_ports[9]" = "USB3_PORT_DEFAULT(OC_SKIP)" + + # SATA + register "EnableSata" = "1" + register "SataSalpSupport" = "1" + register "SataPortsEnable" = "{ \ + [0] = 1, \ + [1] = 1, \ + [2] = 1, \ + [3] = 1, \ + [4] = 0, \ + [5] = 0, \ + }" + # SATA4 and SATA5 are located in the lower right corner + # of the board, but there is no connector for this + + # PCH UART, SPI, I2C + register "SerialIoDevMode" = "{ \ + [PchSerialIoIndexI2C0] = PchSerialIoDisabled, \ + [PchSerialIoIndexI2C1] = PchSerialIoDisabled, \ + [PchSerialIoIndexI2C2] = PchSerialIoDisabled, \ + [PchSerialIoIndexI2C3] = PchSerialIoDisabled, \ + [PchSerialIoIndexI2C4] = PchSerialIoDisabled, \ + [PchSerialIoIndexI2C5] = PchSerialIoDisabled, \ + [PchSerialIoIndexSpi0] = PchSerialIoDisabled, \ + [PchSerialIoIndexSpi1] = PchSerialIoDisabled, \ + [PchSerialIoIndexUart0] = PchSerialIoDisabled, \ + [PchSerialIoIndexUart1] = PchSerialIoDisabled, \ + [PchSerialIoIndexUart2] = PchSerialIoDisabled, \ + }" + + # Set params for PEG 0:1:0 + register "Peg0MaxLinkWidth" = "Peg0_x16" + # Configure PCIe clockgen in PCH + # PEG0 uses SRCCLKREQ0 and CLKSRC0 + register "PcieRpClkReqSupport[0]" = "1" + register "PcieRpClkReqNumber[0]" = "0" + register "PcieRpClkSrcNumber[0]" = "0" + + # Enable Root port 6(x1) for LAN. + register "PcieRpEnable[5]" = "1" + # Disable CLKREQ#, since onboard LAN is always present + register "PcieRpClkReqSupport[5]" = "0" + # Enable Advanced Error Reporting + register "PcieRpAdvancedErrorReporting[5]" = "1" + # Enable Latency Tolerance Reporting Mechanism + register "PcieRpLtrEnable[5]" = "1" + # Use CLK SRC 1 + register "PcieRpClkSrcNumber[5]" = "1" + + # Enable Root port 5 (x1) for PCIE slot. + register "PcieRpEnable[4]" = "1" + # Enable CLKREQ# + register "PcieRpClkReqSupport[4]" = "1" + # Use SRCCLKREQ2# + register "PcieRpClkReqNumber[4]" = "2" + # Enable Advanced Error Reporting + register "PcieRpAdvancedErrorReporting[4]" = "1" + # Enable Latency Tolerance Reporting Mechanism + register "PcieRpLtrEnable[4]" = "1" + # Use CLK SRC 2 + register "PcieRpClkSrcNumber[4]" = "2" + # Use Hot Plug subsystem + register "PcieRpHotPlug[4]" = "1" + + # Enable Root port 7(x1) for PCIE slot. + register "PcieRpEnable[6]" = "1" + # Enable CLKREQ# + register "PcieRpClkReqSupport[6]" = "1" + # Use SRCCLKREQ3# + register "PcieRpClkReqNumber[6]" = "3" + # Enable Advanced Error Reporting + register "PcieRpAdvancedErrorReporting[6]" = "1" + # Enable Latency Tolerance Reporting Mechanism + register "PcieRpLtrEnable[6]" = "1" + # Use CLK SRC 3 + register "PcieRpClkSrcNumber[6]" = "3" + # Use Hot Plug subsystem + register "PcieRpHotPlug[6]" = "1" + + # PL2 override 95W + register "tdp_pl2_override" = "95" + + # Send an extra VR mailbox command for the PS4 exit issue + register "SendVrMbxCmd" = "2" + + device cpu_cluster 0 on + device lapic 0 on end + end + device domain 0 on + device pci 00.0 on # Host Bridge + subsystemid 0x1849 0x191f + end + device pci 01.0 on # PEG + subsystemid 0x1849 0x1901 + end + device pci 02.0 on # Integrated Graphics Device + subsystemid 0x1849 0x1912 + end + device pci 14.0 on # USB xHCI + subsystemid 0x1849 0xa131 + end + device pci 14.1 off end # USB xDCI (OTG) + device pci 14.2 off # Thermal Subsystem + #subsystemid 0x1849 0xa131 + end + device pci 15.0 off end # I2C #0 + device pci 15.1 off end # I2C #1 + device pci 15.2 off end # I2C #2 + device pci 15.3 off end # I2C #3 + device pci 16.0 on # Management Engine Interface 1 + subsystemid 0x1849 0xa131 + end + device pci 16.1 off end # Management Engine Interface 2 + device pci 16.2 off end # Management Engine IDE-R + device pci 16.3 off end # Management Engine KT Redirection + device pci 16.4 off end # Management Engine Interface 3 + device pci 17.0 on # SATA + subsystemid 0x1b21 0x0612 + end + device pci 19.0 off end # UART #2 + device pci 19.1 off end # I2C #5 + device pci 19.2 off end # I2C #4 + device pci 1c.0 on end # PCI Express Port 1 + device pci 1c.1 on end # PCI Express Port 2 + device pci 1c.2 on # Qualcomm Atheros Killer E2400 Gigabit Ethernet Controller + subsystemid 0x1969 0xe0a1 + off + device pci 1c.3 off end # PCI Express Port 4 + device pci 1c.4 on end # PCI Express Port 5 + device pci 1c.5 off end # PCI Express Port 6 + device pci 1c.6 off end # PCI Express Port 7 + device pci 1c.7 off end # PCI Express Port 8 + device pci 1d.0 off end # PCI Express Port 9 + device pci 1d.1 off end # PCI Express Port 10 + device pci 1d.2 off end # PCI Express Port 11 + device pci 1d.3 off end # PCI Express Port 12 + device pci 1e.0 off end # UART #0 + device pci 1e.1 off end # UART #1 + device pci 1e.2 off end # GSPI #0 + device pci 1e.3 off end # GSPI #1 + device pci 1e.4 off end # eMMC + device pci 1e.5 off end # SDIO + device pci 1e.6 off end # SDCard + device pci 1f.0 on # LPC bridge + subsystemid 0x1849 0x1a43 + + chip superio/common + device pnp 2e.0 on # passes SIO base addr to SSDT gen + + chip superio/nuvoton/nct6791d + device pnp 2e.1 on + # Global Control Registers + # Device IRQ Polarity + irq 0x13 = 0x00 + irq 0x14 = 0x00 + # Global Option + irq 0x24 = 0xfb + irq 0x27 = 0x10 + # Multi Function + irq 0x1a = 0xb0 + irq 0x1b = 0xe6 + irq 0x2a = 0x04 + irq 0x2c = 0x40 + irq 0x2d = 0x03 + + # Parallel Port + io 0x60 = 0x0378 + irq 0x70 = 7 + drq 0x74 = 4 # No DMA + irq 0xf0 = 0x3c # Printer mode + end + device pnp 2e.2 on # UART A + io 0x60 = 0x03f8 + irq 0x70 = 4 + end + device pnp 2e.3 on # IR + io 0x60 = 0x02f8 + irq 0x70 = 3 + end + device pnp 2e.5 on # PS/2 KBC + io 0x60 = 0x0060 + io 0x62 = 0x0064 + irq 0x70 = 1 # Keyboard + irq 0x72 = 12 # Mouse + end + device pnp 2e.6 off end # CIR + device pnp 2e.7 on # GPIO6 + irq 0xf6 = 0xff + irq 0xf7 = 0xff + irq 0xf8 = 0xff + end + device pnp 2e.107 on # GPIO7 + irq 0xe0 = 0x7f + irq 0xe1 = 0x0d + end + device pnp 2e.207 on # GPIO8 + irq 0xe6 = 0xff + irq 0xe7 = 0xff + irq 0xed = 0xff + end + device pnp 2e.8 off end # WDT + device pnp 2e.108 on end # GPIO0 + device pnp 2e.308 off end # GPIO base + device pnp 2e.408 off end # WDTMEM + device pnp 2e.708 on end # GPIO1 + device pnp 2e.9 on end # GPIO2 + device pnp 2e.109 on # GPIO3 + irq 0xe4 = 0x7b + irq 0xe5 = 0x02 + irq 0xea = 0x04 + end + device pnp 2e.209 on # GPIO4 + irq 0xf0 = 0x7f + irq 0xf1 = 0x80 + end + device pnp 2e.309 on # GPIO5 + irq 0xf4 = 0xdf + irq 0xf5 = 0xd5 + end + device pnp 2e.a on + # Power RAM in S3 and let the PCH + # handle power failure actions + irq 0xe4 = 0x70 + # Set HWM reset source to LRESET# + irq 0xe7 = 0x01 + end # ACPI + device pnp 2e.b on # HWM, LED + io 0x60 = 0x0290 + io 0x62 = 0 + irq 0x70 = 0 + end + device pnp 2e.d off end # BCLK, WDT2, WDT_MEM + device pnp 2e.e off end # CIR wake-up + device pnp 2e.f off end # GPIO PP/OD + device pnp 2e.14 off end # SVID, Port 80 UART + device pnp 2e.16 off end # DS5 + device pnp 2e.116 off end # DS3 + device pnp 2e.316 on end # PCHDSW + device pnp 2e.416 off end # DSWWOPT + device pnp 2e.516 on end # DS3OPT + device pnp 2e.616 on end # DSDSS + device pnp 2e.716 off end # DSPU + end # chip superio/nuvoton/nct6791d + + end # device pnp 2e.0 + end # chip superio/common + + chip drivers/pc80/tpm + device pnp 4e.0 on end # TPM module + end + end # LPC Interface + device pci 1f.1 off end + device pci 1f.2 on end # Power Management Controller + device pci 1f.3 on end # Intel HDA + device pci 1f.4 on end # SMBus + device pci 1f.5 on end # PCH SPI + device pci 1f.6 on end # GbE + end +end diff --git a/src/mainboard/gigabyte/ga-z170x-gaming7/dsdt.asl b/src/mainboard/gigabyte/ga-z170x-gaming7/dsdt.asl new file mode 100644 index 0000000..1f3537e --- /dev/null +++ b/src/mainboard/gigabyte/ga-z170x-gaming7/dsdt.asl @@ -0,0 +1,54 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2015 Google Inc. + * Copyright (C) 2016 Intel Corporation + * Copyright (C) 2019 Maxim Polyakov max.senia.poliak@gmail.com + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/acpi.h> +DefinitionBlock( + "dsdt.aml", + "DSDT", + 0x02, // DSDT revision: ACPI v2.0 and up + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20110725 // OEM revision +) +{ + #include <soc/intel/skylake/acpi/platform.asl> + + // global NVS and variables + #include <soc/intel/skylake/acpi/globalnvs.asl> + + // CPU + #include <cpu/intel/common/acpi/cpu.asl> + + Scope (_SB) { + Device (PCI0) + { + /* Image processing unit */ + #include <soc/intel/skylake/acpi/ipu.asl> + #include <soc/intel/skylake/acpi/systemagent.asl> + #include <soc/intel/skylake/acpi/pch.asl> + } + + // Dynamic Platform Thermal Framework + #include "acpi/dptf.asl" + } + + #include <southbridge/intel/common/acpi/sleepstates.asl> + + // Mainboard specific + #include "acpi/mainboard.asl" +} diff --git a/src/mainboard/gigabyte/ga-z170x-gaming7/gma-mainboard.ads b/src/mainboard/gigabyte/ga-z170x-gaming7/gma-mainboard.ads new file mode 100644 index 0000000..86a3a62 --- /dev/null +++ b/src/mainboard/gigabyte/ga-z170x-gaming7/gma-mainboard.ads @@ -0,0 +1,32 @@ +-- +-- This file is part of the coreboot project. +-- +-- Copyright (C) 2018 Tristan Corrick tristan@corrick.kiwi +-- Copyright (C) 2019 Maxim Polyakov max.senia.poliak@gmail.com +-- +-- This program is free software: you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation, either version 2 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- + +with HW.GFX.GMA; +with HW.GFX.GMA.Display_Probing; + +use HW.GFX.GMA; +use HW.GFX.GMA.Display_Probing; + +private package GMA.Mainboard is + + ports : constant Port_List := + (HDMI1, -- mainboard DVI port + HDMI3, -- mainboard HDMI port + Analog, + others => Disabled); + +end GMA.Mainboard; diff --git a/src/mainboard/gigabyte/ga-z170x-gaming7/gpio.h b/src/mainboard/gigabyte/ga-z170x-gaming7/gpio.h new file mode 100644 index 0000000..8417dee --- /dev/null +++ b/src/mainboard/gigabyte/ga-z170x-gaming7/gpio.h @@ -0,0 +1,235 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2020 Christoph Pomaska + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the + * GNU General Public License for more details. + */ + +#ifndef MAINBOARD_GPIO_H +#define MAINBOARD_GPIO_H + +#include <soc/gpe.h> +#include <soc/gpio.h> + +#ifndef __ACPI__ + +/* Pad configuration in ramstage. */ +static const struct pad_config gpio_table[] = { + PAD_CFG_NF(GPD0, NONE, PWROK, NF1), + PAD_CFG_TERM_GPO(GPD1, 0, NONE, PWROK), + _PAD_CFG_STRUCT(GPD2, 0x00080500, 0x3c00), + PAD_CFG_NF(GPD3, UP_20K, PWROK, NF1), + PAD_CFG_NF(GPD4, NONE, PWROK, NF1), + PAD_CFG_NF(GPD5, NONE, PWROK, NF1), + PAD_CFG_NF(GPD6, NONE, PWROK, NF1), + PAD_CFG_TERM_GPO(GPD7, 1, NONE, PWROK), + PAD_CFG_NF(GPD8, NONE, PWROK, NF1), + PAD_CFG_NF(GPD9, NONE, PWROK, NF1), + PAD_CFG_NF(GPD10, NONE, PWROK, NF1), + PAD_CFG_NF(GPD11, NONE, PWROK, NF1), + PAD_CFG_NF(GPP_A0, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_A1, NATIVE, DEEP, NF1), + PAD_CFG_NF(GPP_A2, NATIVE, DEEP, NF1), + PAD_CFG_NF(GPP_A3, NATIVE, DEEP, NF1), + PAD_CFG_NF(GPP_A4, NATIVE, DEEP, NF1), + PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_A7, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_A8, NONE, PLTRST, NF1), + PAD_CFG_NF(GPP_A9, DN_20K, DEEP, NF1), + PAD_CFG_NF(GPP_A10, DN_20K, PLTRST, NF1), + PAD_CFG_NF(GPP_A11, UP_20K, DEEP, NF1), + PAD_CFG_NF(GPP_A12, NONE, DEEP, NF3), + PAD_CFG_NF(GPP_A13, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_A14, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_A15, UP_20K, DEEP, NF1), + PAD_NC(GPP_A16, NONE), + PAD_NC(GPP_A17, NONE), + PAD_CFG_NF(GPP_A18, NONE, PLTRST, NF1), + PAD_CFG_NF(GPP_A19, NONE, PLTRST, NF1), + PAD_NC(GPP_A20, NONE), + PAD_CFG_TERM_GPO(GPP_A21, 1, NONE, DEEP), + PAD_CFG_TERM_GPO(GPP_A22, 1, NONE, DEEP), + _PAD_CFG_STRUCT(GPP_A23, 0x40100100, 0x0000), + PAD_CFG_TERM_GPO(GPP_B0, 0, NONE, DEEP), + PAD_CFG_TERM_GPO(GPP_B1, 0, NONE, DEEP), + PAD_NC(GPP_B2, NONE), + PAD_NC(GPP_B3, NONE), + PAD_CFG_TERM_GPO(GPP_B4, 0, NONE, PLTRST), + PAD_NC(GPP_B5, NONE), + PAD_NC(GPP_B6, NONE), + PAD_NC(GPP_B7, NONE), + PAD_NC(GPP_B8, NONE), + PAD_NC(GPP_B9, NONE), + PAD_NC(GPP_B10, NONE), + PAD_CFG_TERM_GPO(GPP_B11, 0, NONE, DEEP), + PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_B14, DN_20K, PLTRST, NF1), + PAD_CFG_TERM_GPO(GPP_B15, 0, NONE, PLTRST), + PAD_NC(GPP_B16, NONE), + PAD_CFG_TERM_GPO(GPP_B17, 1, NONE, DEEP), + PAD_CFG_TERM_GPO(GPP_B18, 0, NONE, DEEP), + PAD_CFG_TERM_GPO(GPP_B19, 0, NONE, PLTRST), + PAD_CFG_NF(GPP_B20, DN_20K, PLTRST, NF1), + PAD_CFG_NF(GPP_B21, DN_20K, PLTRST, NF1), + PAD_CFG_NF(GPP_B22, DN_20K, PLTRST, NF1), + _PAD_CFG_STRUCT(GPP_B23, 0x84000a01, 0x1000), + PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), + PAD_CFG_TERM_GPO(GPP_C2, 1, NONE, DEEP), + PAD_CFG_NF(GPP_C3, DN_20K, DEEP, NF1), + PAD_CFG_NF(GPP_C4, NONE, DEEP, NF1), + PAD_CFG_TERM_GPO(GPP_C5, 0, NONE, DEEP), + _PAD_CFG_STRUCT(GPP_C6, 0xfffffffd, 0xffffff00), + _PAD_CFG_STRUCT(GPP_C7, 0xfffffffd, 0xffffff00), + PAD_NC(GPP_C8, NONE), + PAD_NC(GPP_C9, NONE), + PAD_NC(GPP_C10, NONE), + PAD_NC(GPP_C11, NONE), + PAD_NC(GPP_C12, NONE), + PAD_NC(GPP_C13, NONE), + PAD_NC(GPP_C14, NONE), + PAD_NC(GPP_C15, NONE), + PAD_NC(GPP_C16, NONE), + PAD_NC(GPP_C17, NONE), + PAD_NC(GPP_C18, NONE), + PAD_CFG_TERM_GPO(GPP_C19, 0, NONE, PWROK), + PAD_CFG_TERM_GPO(GPP_C20, 0, NONE, PWROK), + PAD_CFG_TERM_GPO(GPP_C21, 0, NONE, PWROK), + _PAD_CFG_STRUCT(GPP_C22, 0x42840101, 0x0000), + PAD_NC(GPP_C23, NONE), + PAD_CFG_TERM_GPO(GPP_D0, 0, NONE, PWROK), + PAD_CFG_TERM_GPO(GPP_D1, 1, NONE, PWROK), + PAD_CFG_TERM_GPO(GPP_D2, 0, NONE, PWROK), + _PAD_CFG_STRUCT(GPP_D3, 0x82880101, 0x1000), + _PAD_CFG_STRUCT(GPP_D4, 0x42840101, 0x0000), + PAD_CFG_NF(GPP_D5, NONE, PLTRST, NF1), + PAD_CFG_TERM_GPO(GPP_D6, 0, NONE, PLTRST), + PAD_CFG_NF(GPP_D7, NONE, PLTRST, NF1), + PAD_CFG_NF(GPP_D8, NONE, PLTRST, NF1), + PAD_CFG_TERM_GPO(GPP_D9, 0, NONE, PWROK), + PAD_NC(GPP_D10, NONE), + PAD_NC(GPP_D11, NONE), + PAD_NC(GPP_D12, NONE), + PAD_NC(GPP_D13, NONE), + PAD_NC(GPP_D14, NONE), + PAD_NC(GPP_D15, NONE), + PAD_NC(GPP_D16, NONE), + PAD_CFG_NF(GPP_D17, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_D18, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_D20, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_D21, NONE, PLTRST, NF1), + PAD_CFG_NF(GPP_D22, NONE, PLTRST, NF1), + PAD_NC(GPP_D23, NONE), + PAD_CFG_NF(GPP_E0, UP_20K, PLTRST, NF1), + PAD_CFG_NF(GPP_E1, UP_20K, PLTRST, NF1), + PAD_CFG_NF(GPP_E2, UP_20K, PLTRST, NF1), + PAD_NC(GPP_E3, NONE), + PAD_NC(GPP_E4, NONE), + _PAD_CFG_STRUCT(GPP_E5, 0x04000601, 0x0000), + PAD_CFG_NF(GPP_E6, NONE, PWROK, NF1), + PAD_NC(GPP_E7, NONE), + PAD_CFG_NF(GPP_E8, NONE, PLTRST, NF1), + PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_E10, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_E11, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_E12, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_F0, UP_20K, PLTRST, NF1), + PAD_CFG_NF(GPP_F1, UP_20K, PLTRST, NF1), + PAD_CFG_NF(GPP_F2, UP_20K, PLTRST, NF1), + PAD_NC(GPP_F3, NONE), + PAD_NC(GPP_F4, NONE), + PAD_CFG_TERM_GPO(GPP_F5, 1, NONE, PLTRST), + PAD_CFG_NF(GPP_F6, NONE, PWROK, NF1), + PAD_NC(GPP_F7, NONE), + PAD_NC(GPP_F8, NONE), + PAD_NC(GPP_F9, NONE), + PAD_CFG_GPI(GPP_F10, NONE, PLTRST), + PAD_NC(GPP_F11, NONE), + _PAD_CFG_STRUCT(GPP_F12, 0x80900100, 0x0000), + _PAD_CFG_STRUCT(GPP_F13, 0x80100100, 0x0000), + _PAD_CFG_STRUCT(GPP_F14, 0x40900100, 0x0000), + PAD_CFG_NF(GPP_F15, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_F16, NONE, DEEP, NF1), + PAD_NC(GPP_F17, NONE), + PAD_CFG_TERM_GPO(GPP_F18, 1, NONE, PLTRST), + PAD_CFG_NF(GPP_F19, NONE, PLTRST, NF1), + PAD_CFG_NF(GPP_F20, NONE, PLTRST, NF1), + PAD_CFG_NF(GPP_F21, NONE, PLTRST, NF1), + PAD_CFG_TERM_GPO(GPP_F22, 1, NONE, PLTRST), + PAD_CFG_TERM_GPO(GPP_F23, 1, NONE, PLTRST), + _PAD_CFG_STRUCT(GPP_G0, 0x84000101, 0x0000), + _PAD_CFG_STRUCT(GPP_G1, 0x84000101, 0x0000), + PAD_CFG_TERM_GPO(GPP_G2, 1, NONE, PLTRST), + PAD_NC(GPP_G3, NONE), + PAD_NC(GPP_G4, NONE), + PAD_CFG_TERM_GPO(GPP_G5, 1, NONE, PLTRST), + PAD_CFG_TERM_GPO(GPP_G6, 1, NONE, PLTRST), + PAD_CFG_TERM_GPO(GPP_G7, 1, NONE, DEEP), + PAD_CFG_NF(GPP_G8, NONE, DEEP, NF1), + PAD_CFG_GPI(GPP_G9, NONE, PLTRST), + PAD_CFG_GPI(GPP_G10, NONE, PLTRST), + PAD_CFG_NF(GPP_G11, NONE, DEEP, NF1), + PAD_CFG_TERM_GPO(GPP_G12, 1, NONE, PLTRST), + PAD_NC(GPP_G13, NONE), + PAD_CFG_TERM_GPO(GPP_G14, 1, NONE, PLTRST), + PAD_CFG_TERM_GPO(GPP_G15, 1, NONE, PLTRST), + PAD_CFG_TERM_GPO(GPP_G16, 0, DN_20K, PLTRST), + PAD_NC(GPP_G17, NONE), + PAD_CFG_TERM_GPO(GPP_G18, 1, NONE, PLTRST), + PAD_CFG_TERM_GPO(GPP_G19, 1, NONE, PLTRST), + PAD_CFG_TERM_GPO(GPP_G20, 1, NONE, PLTRST), + PAD_CFG_TERM_GPO(GPP_G21, 1, NONE, PLTRST), + PAD_CFG_TERM_GPO(GPP_G22, 1, NONE, PLTRST), + PAD_CFG_TERM_GPO(GPP_G23, 1, NONE, PLTRST), + PAD_NC(GPP_H0, NONE), + PAD_NC(GPP_H1, NONE), + PAD_NC(GPP_H2, NONE), + PAD_NC(GPP_H3, NONE), + PAD_NC(GPP_H4, NONE), + PAD_NC(GPP_H5, NONE), + PAD_NC(GPP_H6, NONE), + PAD_NC(GPP_H7, NONE), + PAD_NC(GPP_H8, NONE), + PAD_NC(GPP_H9, NONE), + PAD_NC(GPP_H10, NONE), + PAD_NC(GPP_H11, NONE), + PAD_CFG_TERM_GPO(GPP_H12, 0, NONE, DEEP), + _PAD_CFG_STRUCT(GPP_H13, 0x80100100, 0x0000), + _PAD_CFG_STRUCT(GPP_H14, 0x80100100, 0x0000), + _PAD_CFG_STRUCT(GPP_H15, 0x80100100, 0x0000), + PAD_CFG_TERM_GPO(GPP_H16, 1, NONE, PLTRST), + PAD_CFG_TERM_GPO(GPP_H17, 1, NONE, PLTRST), + PAD_NC(GPP_H18, NONE), + PAD_CFG_NF(GPP_H19, NONE, PLTRST, NF1), + PAD_CFG_NF(GPP_H20, NONE, PLTRST, NF1), + PAD_NC(GPP_H21, NONE), + PAD_NC(GPP_H22, NONE), + PAD_CFG_TERM_GPO(GPP_H23, 0, NONE, DEEP), + PAD_CFG_NF(GPP_I0, NONE, PLTRST, NF1), + PAD_CFG_NF(GPP_I1, NONE, PLTRST, NF1), + PAD_CFG_NF(GPP_I2, NONE, PLTRST, NF1), + PAD_CFG_NF(GPP_I3, NONE, PLTRST, NF1), + PAD_CFG_NF(GPP_I4, NONE, PLTRST, NF1), + PAD_CFG_NF(GPP_I5, NONE, PLTRST, NF1), + PAD_CFG_NF(GPP_I6, DN_20K, PLTRST, NF1), + PAD_CFG_NF(GPP_I7, NONE, PLTRST, NF1), + PAD_CFG_NF(GPP_I8, DN_20K, PLTRST, NF1), + PAD_CFG_NF(GPP_I9, NONE, PLTRST, NF1), + PAD_CFG_NF(GPP_I10, DN_20K, PLTRST, NF1), +}; + +#endif + +#endif + diff --git a/src/mainboard/gigabyte/ga-z170x-gaming7/hda_verb.c b/src/mainboard/gigabyte/ga-z170x-gaming7/hda_verb.c new file mode 100644 index 0000000..940c8fb --- /dev/null +++ b/src/mainboard/gigabyte/ga-z170x-gaming7/hda_verb.c @@ -0,0 +1,51 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Christoph Pomaska + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the + * GNU General Public License for more details. + */ + +#ifndef HDA_VERB_H +#define HDA_VERB_H + +#include <device/azalia_device.h> + +const u32 cim_verb_data[] = { + /* Creative, Recon3Di */ + 0x11020011, /* Vendor ID */ + 0x1458a036, /* Subsystem ID */ + 11, /* Number of entries */ + AZALIA_SUBVENDOR(0, 0x1458a036), + AZALIA_PIN_CFG(0, 0x0b, 0x01014010), + AZALIA_PIN_CFG(0, 0x0c, 0x014580f0), + AZALIA_PIN_CFG(0, 0x0d, 0x014570f0), + AZALIA_PIN_CFG(0, 0x0e, 0x01c530f0), + AZALIA_PIN_CFG(0, 0x0f, 0x0221401f), + AZALIA_PIN_CFG(0, 0x10, 0x02216011), + AZALIA_PIN_CFG(0, 0x11, 0x02012014), + AZALIA_PIN_CFG(0, 0x12, 0x37a791f0), + AZALIA_PIN_CFG(0, 0x13, 0x908700f0), + AZALIA_PIN_CFG(0, 0x18, 0x500000f0), + /* Intel, SkylakeHDMI */ + 0x80862809, /* Vendor ID */ + 0x80860101, /* Subsystem ID */ + 4, /* Number of entries */ + AZALIA_SUBVENDOR(2, 0x80860101), + AZALIA_PIN_CFG(2, 0x05, 0x18560010), + AZALIA_PIN_CFG(2, 0x06, 0x18560010), + AZALIA_PIN_CFG(2, 0x07, 0x18560010), +}; + +const u32 pc_beep_verbs[] = {}; + +AZALIA_ARRAY_SIZES; + +#endif diff --git a/src/mainboard/gigabyte/ga-z170x-gaming7/include/gpio.h b/src/mainboard/gigabyte/ga-z170x-gaming7/include/gpio.h new file mode 100644 index 0000000..0b33078 --- /dev/null +++ b/src/mainboard/gigabyte/ga-z170x-gaming7/include/gpio.h @@ -0,0 +1,508 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Maxim Polyakov max.senia.poliak@gmail.com + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the + * GNU General Public License for more details. + */ + +#ifndef _PCH_GPIO_H +#define _PCH_GPIO_H + +#include <soc/gpe.h> +#include <soc/gpio.h> + +/* Pad configuration in ramstage */ +static const struct pad_config gpio_table[] = { + /* ------- GPIO Group GPP_A ------- */ + /* GPP_A0 - RCIN# */ + PAD_CFG_NF_BUF_TRIG(GPP_A0, NONE, PLTRST, NF1, TX_DISABLE, OFF), + /* GPP_A1 - LAD0 */ + PAD_CFG_NF_BUF_TRIG(GPP_A1, 20K_PU, PLTRST, NF1, NO_DISABLE, OFF), + /* GPP_A2 - LAD1 */ + PAD_CFG_NF_BUF_TRIG(GPP_A2, 20K_PU, PLTRST, NF1, NO_DISABLE, OFF), + /* GPP_A3 - LAD2 */ + PAD_CFG_NF_BUF_TRIG(GPP_A3, 20K_PU, PLTRST, NF1, NO_DISABLE, OFF), + /* GPP_A4 - LAD3 */ + PAD_CFG_NF_BUF_TRIG(GPP_A4, 20K_PU, PLTRST, NF1, NO_DISABLE, OFF), + /* GPP_A5 - LFRAME# */ + PAD_CFG_NF_BUF_TRIG(GPP_A5, NONE, PLTRST, NF1, RX_DISABLE, OFF), + /* GPP_A6 - SERIRQ */ + PAD_CFG_NF_BUF_TRIG(GPP_A6, NONE, PLTRST, NF1, NO_DISABLE, OFF), + /* GPP_A7 - GPIO */ + PAD_CFG_GPI_INT(GPP_A7, NONE, PLTRST, OFF), + /* GPP_A8 - CLKRUN# */ + PAD_CFG_NF_BUF_TRIG(GPP_A8, NONE, PLTRST, NF1, TX_DISABLE, OFF), + /* GPP_A9 - CLKOUT_LPC0 */ + PAD_CFG_NF_BUF_TRIG(GPP_A9, 20K_PD, PLTRST, NF1, RX_DISABLE, OFF), + /* GPP_A10 - CLKOUT_LPC1 */ + PAD_CFG_NF_BUF_TRIG(GPP_A10, 20K_PD, PLTRST, NF1, RX_DISABLE, OFF), + /* GPP_A11 - GPIO */ + PAD_CFG_GPI_INT(GPP_A11, NONE, PLTRST, OFF), + /* GPP_A12 - GPIO */ + PAD_CFG_GPI_INT(GPP_A12, NONE, PLTRST, OFF), + /* GPP_A13 - SUSWARN#/SUSPWRDNACK */ + PAD_CFG_NF_BUF_TRIG(GPP_A13, NONE, DEEP, NF1, RX_DISABLE, OFF), + /* GPP_A14 - SUS_STAT# */ + PAD_CFG_NF_BUF_TRIG(GPP_A14, NONE, DEEP, NF1, RX_DISABLE, OFF), + /* GPP_A15 - SUS_ACK# */ + PAD_CFG_NF_BUF_TRIG(GPP_A15, 20K_PU, DEEP, NF1, TX_DISABLE, OFF), + /* GPP_A16 - GPIO */ + PAD_CFG_GPI_INT(GPP_A16, NONE, PLTRST, OFF), + /* GPP_A17 - GPIO */ + PAD_CFG_GPI_INT(GPP_A17, NONE, PLTRST, OFF), + /* GPP_A18 - GPIO */ + PAD_CFG_GPI_INT(GPP_A18, NONE, PLTRST, OFF), + /* GPP_A19 - GPIO */ + PAD_CFG_GPI_INT(GPP_A19, NONE, PLTRST, OFF), + /* GPP_A20 - GPIO */ + PAD_CFG_GPI_INT(GPP_A20, NONE, PLTRST, OFF), + /* GPP_A21 - GPIO */ + PAD_CFG_GPI_INT(GPP_A21, NONE, PLTRST, OFF), + /* GPP_A22 - GPIO */ + PAD_CFG_GPI_INT(GPP_A22, NONE, PLTRST, OFF), + /* GPP_A23 - GPIO */ + PAD_CFG_GPI_INT(GPP_A23, NONE, PLTRST, OFF), + + /* ------- GPIO Group GPP_B ------- */ + /* GPP_B0 - GPIO */ + PAD_CFG_GPI_INT(GPP_B0, NONE, PLTRST, OFF), + /* GPP_B1 - GPIO */ + PAD_CFG_GPI_INT(GPP_B1, NONE, PLTRST, OFF), + /* GPP_B2 - GPIO */ + PAD_CFG_GPI_INT(GPP_B2, NONE, PLTRST, OFF), + /* GPP_B3 - GPIO */ + PAD_CFG_GPO(GPP_B3, 1, DEEP), + /* GPP_B4 - CPU_GP3 */ + PAD_CFG_NF_BUF_TRIG(GPP_B4, NONE, PLTRST, NF1, TX_DISABLE, OFF), + /* GPP_B5 - GPIO */ + PAD_CFG_GPI_INT(GPP_B5, NONE, PLTRST, OFF), + /* GPP_B6 - GPIO */ + PAD_CFG_GPI_INT(GPP_B6, NONE, PLTRST, OFF), + /* GPP_B7 - NC */ + PAD_NC(GPP_B7, NONE), + /* GPP_B8 - GPIO */ + PAD_CFG_GPI_INT(GPP_B8, 5K_PU, PLTRST, OFF), + /* GPP_B9 - GPIO */ + PAD_CFG_GPI_INT(GPP_B9, NONE, PLTRST, OFF), + /* GPP_B10 - GPIO */ + PAD_CFG_GPI_INT(GPP_B10, NONE, PLTRST, OFF), + /* GPP_B11 - GPIO */ + _PAD_CFG_STRUCT(GPP_B11, + PAD_FUNC(GPIO) | PAD_RESET(PWROK) | + PAD_CFG0_TRIG_OFF | PAD_CFG0_RX_POL_NONE | + PAD_BUF(NO_DISABLE), + PAD_PULL(NONE)), + /* GPP_B12 - SLP_S0# */ + PAD_CFG_NF_BUF_TRIG(GPP_B12, NONE, DEEP, NF1, RX_DISABLE, OFF), + /* GPP_B13 - PLTRST# */ + PAD_CFG_NF_BUF_TRIG(GPP_B13, NONE, DEEP, NF1, RX_DISABLE, OFF), + /* GPP_B14 - SPKR */ + PAD_CFG_NF_BUF_TRIG(GPP_B14, 20K_PD, PLTRST, NF1, RX_DISABLE, OFF), + /* GPP_B15 - GPIO */ + PAD_CFG_GPI_INT(GPP_B15, NONE, PLTRST, OFF), + /* GPP_B16 - GPIO */ + PAD_CFG_GPI_INT(GPP_B16, NONE, PLTRST, OFF), + /* GPP_B17 - GPIO */ + PAD_CFG_GPO(GPP_B17, 1, DEEP), + /* GPP_B18 - GPIO */ + PAD_CFG_GPI_INT(GPP_B18, NONE, PLTRST, OFF), + /* GPP_B19 - GPIO */ + PAD_CFG_GPI_INT(GPP_B19, NONE, PLTRST, OFF), + /* GPP_B20 - GPIO */ + PAD_CFG_GPI_INT(GPP_B20, NONE, PLTRST, OFF), + /* GPP_B21 - GPIO */ + PAD_CFG_GPI_INT(GPP_B21, NONE, PLTRST, OFF), + /* GPP_B22 - GPIO */ + PAD_CFG_GPI_INT(GPP_B22, NONE, PLTRST, OFF), + /* GPP_B23 - PCHHOT# */ + _PAD_CFG_STRUCT(GPP_B23, + PAD_FUNC(NF2) | PAD_RESET(PLTRST) | + PAD_CFG0_TRIG_OFF | PAD_CFG0_RX_POL_NONE | + PAD_BUF(RX_DISABLE) | 1, + PAD_PULL(20K_PD)), + + /* ------- GPIO Group GPP_C ------- */ + /* GPP_C0 - SMBCLK */ + PAD_CFG_NF_BUF_TRIG(GPP_C0, NONE, DEEP, NF1, TX_DISABLE, OFF), + /* GPP_C1 - SMBDATA */ + PAD_CFG_NF_BUF_TRIG(GPP_C1, NONE, DEEP, NF1, TX_DISABLE, OFF), + /* GPP_C2 - GPIO */ + PAD_CFG_GPO(GPP_C2, 1, DEEP), + /* GPP_C3 - SML0CLK */ + PAD_CFG_NF_BUF_TRIG(GPP_C3, NONE, DEEP, NF1, TX_DISABLE, OFF), + /* GPP_C4 - SML0DATA */ + PAD_CFG_NF_BUF_TRIG(GPP_C4, NONE, DEEP, NF1, TX_DISABLE, OFF), + /* GPP_C5 - GPIO */ + PAD_CFG_GPI_INT(GPP_C5, NONE, PLTRST, OFF), + /* GPP_C6 - RESERVED */ + /* GPP_C7 - RESERVED */ + /* GPP_C8 - UART0_RXD */ + PAD_CFG_NF_BUF_TRIG(GPP_C8, NONE, PLTRST, NF1, TX_DISABLE, OFF), + /* GPP_C9 - UART0_TXD */ + PAD_CFG_NF_BUF_TRIG(GPP_C9, NONE, PLTRST, NF1, RX_DISABLE, OFF), + /* GPP_C10 - UART0_RTS# */ + PAD_CFG_NF_BUF_TRIG(GPP_C10, NONE, PLTRST, NF1, RX_DISABLE, OFF), + /* GPP_C11 - UART0_CTS# */ + PAD_CFG_NF_BUF_TRIG(GPP_C11, NONE, PLTRST, NF1, TX_DISABLE, OFF), + /* GPP_C12 - GPIO */ + PAD_CFG_GPI_INT(GPP_C12, NONE, PLTRST, OFF), + /* GPP_C13 - GPIO */ + PAD_CFG_GPI_INT(GPP_C13, NONE, PLTRST, OFF), + /* GPP_C14 - GPIO */ + PAD_CFG_GPI_INT(GPP_C14, NONE, PLTRST, OFF), + /* GPP_C15 - GPIO */ + PAD_CFG_GPI_INT(GPP_C15, NONE, PLTRST, OFF), + /* GPP_C16 - GPIO */ + PAD_CFG_GPI_INT(GPP_C16, NONE, PLTRST, OFF), + /* GPP_C17 - GPIO */ + PAD_CFG_GPI_INT(GPP_C17, NONE, PLTRST, OFF), + /* GPP_C18 - GPIO */ + PAD_CFG_GPI_INT(GPP_C18, NONE, PLTRST, OFF), + /* GPP_C19 - GPIO */ + PAD_CFG_GPI_INT(GPP_C19, NONE, PLTRST, OFF), + /* GPP_C20 - UART2_RXD */ + PAD_CFG_NF_BUF_TRIG(GPP_C20, NONE, PLTRST, NF1, TX_DISABLE, OFF), + /* GPP_C21 - UART2_TXD */ + PAD_CFG_NF_BUF_TRIG(GPP_C21, NONE, PLTRST, NF1, RX_DISABLE, OFF), + /* GPP_C22 - UART2_RTS# */ + PAD_CFG_NF_BUF_TRIG(GPP_C22, NONE, PLTRST, NF1, RX_DISABLE, OFF), + /* GPP_C23 - GPIO */ + PAD_CFG_GPI_SCI(GPP_C23, NONE, DEEP, LEVEL, YES), + + /* ------- GPIO Group GPP_D ------- */ + /* GPP_D0 - GPIO */ + PAD_CFG_GPI_INT(GPP_D0, NONE, PLTRST, OFF), + /* GPP_D1 - GPIO */ + PAD_CFG_GPI_INT(GPP_D1, NONE, PLTRST, OFF), + /* GPP_D2 - GPIO */ + PAD_CFG_GPI_INT(GPP_D2, NONE, PLTRST, OFF), + /* GPP_D3 - GPIO */ + PAD_CFG_GPI_INT(GPP_D3, NONE, PLTRST, OFF), + /* GPP_D4 - GPIO */ + PAD_CFG_GPI_INT(GPP_D4, NONE, PLTRST, OFF), + /* GPP_D5 - I2S_SFRM */ + PAD_CFG_NF_BUF_TRIG(GPP_D5, NONE, PLTRST, NF1, NO_DISABLE, OFF), + /* GPP_D6 - I2S_TXD */ + PAD_CFG_NF_BUF_TRIG(GPP_D6, NONE, PLTRST, NF1, RX_DISABLE, OFF), + /* GPP_D7 - I2S_RXD */ + PAD_CFG_NF_BUF_TRIG(GPP_D7, NONE, PLTRST, NF1, TX_DISABLE, OFF), + /* GPP_D8 - I2S_SCLK */ + PAD_CFG_NF_BUF_TRIG(GPP_D8, NONE, PLTRST, NF1, NO_DISABLE, OFF), + /* GPP_D9 - GPIO */ + PAD_CFG_GPI_INT(GPP_D9, NONE, PLTRST, OFF), + /* GPP_D10 - GPIO */ + PAD_CFG_GPI_INT(GPP_D10, NONE, PLTRST, OFF), + /* GPP_D11 - GPIO */ + PAD_CFG_GPI_INT(GPP_D11, NONE, PLTRST, OFF), + /* GPP_D12 - GPIO */ + PAD_CFG_GPI_INT(GPP_D12, NONE, PLTRST, OFF), + /* GPP_D13 - GPIO */ + PAD_CFG_GPI_INT(GPP_D13, NONE, PLTRST, OFF), + /* GPP_D14 - GPIO */ + PAD_CFG_GPI_INT(GPP_D14, NONE, PLTRST, OFF), + /* GPP_D15 - GPIO */ + PAD_CFG_GPI_INT(GPP_D15, NONE, PLTRST, OFF), + /* GPP_D16 - GPIO */ + PAD_CFG_GPI_INT(GPP_D16, NONE, PLTRST, OFF), + /* GPP_D17 - GPIO */ + PAD_CFG_GPI_INT(GPP_D17, NONE, PLTRST, OFF), + /* GPP_D18 - GPIO */ + PAD_CFG_GPI_INT(GPP_D18, NONE, PLTRST, OFF), + /* GPP_D19 - DMIC_CLK0 */ + PAD_CFG_NF_BUF_TRIG(GPP_D19, 20K_PU, PLTRST, NF1, TX_DISABLE, OFF), + /* GPP_D20 - DMIC_DATA0 */ + PAD_CFG_NF_BUF_TRIG(GPP_D20, 20K_PU, PLTRST, NF1, TX_DISABLE, OFF), + /* GPP_D21 - GPIO */ + PAD_CFG_GPI_INT(GPP_D21, NONE, PLTRST, OFF), + /* GPP_D22 - GPIO */ + PAD_CFG_GPI_INT(GPP_D22, NONE, PLTRST, OFF), + /* GPP_D23 - GPIO */ + PAD_CFG_GPI_INT(GPP_D23, NONE, PLTRST, OFF), + + /* ------- GPIO Group GPP_E ------- */ + /* GPP_E0 - SATAXPCIE0 */ + PAD_CFG_NF_BUF_TRIG(GPP_E0, 20K_PU, PLTRST, NF1, TX_DISABLE, OFF), + /* GPP_E1 - SATAXPCIE1 */ + PAD_CFG_NF_BUF_TRIG(GPP_E1, 20K_PU, PLTRST, NF1, TX_DISABLE, OFF), + /* GPP_E2 - SATAXPCIE2 */ + PAD_CFG_NF_BUF_TRIG(GPP_E2, 20K_PU, PLTRST, NF1, TX_DISABLE, OFF), + /* GPP_E3 - CPU_GP0 */ + PAD_CFG_NF_BUF_TRIG(GPP_E3, NONE, PLTRST, NF1, TX_DISABLE, OFF), + /* GPP_E4 - SATA_DEVSLP0 */ + PAD_CFG_NF_BUF_TRIG(GPP_E4, NONE, PLTRST, NF1, TX_DISABLE, OFF), + /* GPP_E5 - SATA_DEVSLP1 */ + PAD_CFG_NF_BUF_TRIG(GPP_E5, NONE, PLTRST, NF1, TX_DISABLE, OFF), + /* GPP_E6 - SATA_DEVSLP2 */ + PAD_CFG_NF_BUF_TRIG(GPP_E6, NONE, PLTRST, NF1, TX_DISABLE, OFF), + /* GPP_E7 - GPIO */ + PAD_CFG_GPI_INT(GPP_E7, NONE, PLTRST, OFF), + /* GPP_E8 - SATA_LED# */ + PAD_CFG_NF_BUF_TRIG(GPP_E8, NONE, PLTRST, NF1, RX_DISABLE, OFF), + /* GPP_E9 - USB_OC0# */ + PAD_CFG_NF_BUF_TRIG(GPP_E9, NONE, DEEP, NF1, TX_DISABLE, OFF), + /* GPP_E10 - USB_OC1# */ + PAD_CFG_NF_BUF_TRIG(GPP_E10, NONE, DEEP, NF1, TX_DISABLE, OFF), + /* GPP_E11 - USB_OC2# */ + PAD_CFG_NF_BUF_TRIG(GPP_E11, NONE, DEEP, NF1, TX_DISABLE, OFF), + /* GPP_E12 - USB_OC3# */ + PAD_CFG_NF_BUF_TRIG(GPP_E12, NONE, DEEP, NF1, TX_DISABLE, OFF), + + /* ------- GPIO Group GPP_F ------- */ + /* GPP_F0 - GPIO */ + PAD_CFG_GPI_INT(GPP_F0, NONE, PLTRST, OFF), + /* GPP_F1 - SATAXPCIE4 */ + PAD_CFG_NF_BUF_TRIG(GPP_F1, 20K_PU, PLTRST, NF1, TX_DISABLE, OFF), + /* GPP_F2 - GPIO */ + PAD_NC(GPP_F2, NONE), + /* GPP_F3 - GPIO */ + PAD_CFG_GPI_INT(GPP_F3, NONE, PLTRST, OFF), + /* GPP_F4 - GPIO */ + PAD_CFG_GPI_INT(GPP_F4, NONE, PLTRST, OFF), + /* GPP_F5 - GPIO */ + PAD_CFG_GPI_INT(GPP_F5, NONE, PLTRST, OFF), + /* GPP_F6 - GPIO */ + PAD_CFG_GPI_INT(GPP_F6, NONE, PLTRST, OFF), + /* GPP_F7 - GPIO */ + PAD_CFG_GPI_INT(GPP_F7, NONE, PLTRST, OFF), + /* GPP_F8 - GPIO */ + PAD_CFG_GPI_INT(GPP_F8, NONE, PLTRST, OFF), + /* GPP_F9 - GPIO */ + PAD_CFG_GPI_INT(GPP_F9, NONE, PLTRST, OFF), + /* GPP_F10 - GPIO */ + PAD_CFG_GPI_APIC(GPP_F10, NONE, PLTRST), + /* GPP_F11 - GPIO */ + PAD_CFG_GPI_INT(GPP_F11, NONE, PLTRST, OFF), + /* GPP_F12 - GPIO */ + PAD_CFG_GPI_APIC_INVERT(GPP_F12, NONE, PLTRST), + /* GPP_F13 - GPIO */ + PAD_CFG_GPI_APIC(GPP_F13, NONE, PLTRST), + /* GPP_F14 - GPIO */ + PAD_CFG_GPI_APIC_INVERT(GPP_F14, NONE, DEEP), + /* GPP_F15 - USB_OC4# */ + PAD_CFG_NF_BUF_TRIG(GPP_F15, NONE, DEEP, NF1, TX_DISABLE, OFF), + /* GPP_F16 - USB_OC5# */ + PAD_CFG_NF_BUF_TRIG(GPP_F16, NONE, DEEP, NF1, TX_DISABLE, OFF), + /* GPP_F17 - USB_OC6# */ + PAD_CFG_NF_BUF_TRIG(GPP_F17, NONE, DEEP, NF1, TX_DISABLE, OFF), + /* GPP_F18 - GPIO */ + PAD_CFG_GPO(GPP_F18, 1, PLTRST), + /* GPP_F19 - GPIO */ + PAD_CFG_GPI_INT(GPP_F19, NONE, PLTRST, OFF), + /* GPP_F20 - GPIO */ + PAD_CFG_GPI_INT(GPP_F20, NONE, PLTRST, OFF), + /* GPP_F21 - GPIO */ + PAD_CFG_GPI_INT(GPP_F21, NONE, PLTRST, OFF), + /* GPP_F22 - GPIO */ + PAD_CFG_GPI_INT(GPP_F22, NONE, PLTRST, OFF), + /* GPP_F23 - GPIO */ + PAD_CFG_GPI_INT(GPP_F23, NONE, PLTRST, OFF), + + /* ------- GPIO Group GPP_G ------- */ + /* GPP_G0 - GPIO */ + PAD_CFG_GPI_INT(GPP_G0, NONE, PWROK, OFF), + /* GPP_G1 - GPIO */ + PAD_CFG_GPI_INT(GPP_G1, NONE, PWROK, OFF), + /* GPP_G2 - GPIO */ + PAD_CFG_GPI_INT(GPP_G2, NONE, PWROK, OFF), + /* GPP_G3 - GPIO */ + PAD_CFG_GPI_INT(GPP_G3, NONE, PWROK, OFF), + /* GPP_G4 - GPIO */ + PAD_CFG_GPO(GPP_G4, 0, DEEP), + /* GPP_G5 - GPIO */ + PAD_CFG_GPI_INT(GPP_G5, NONE, PWROK, OFF), + /* GPP_G6 - GPIO */ + _PAD_CFG_STRUCT(GPP_G6, + PAD_FUNC(GPIO) | PAD_RESET(PWROK) | + PAD_CFG0_TRIG_LEVEL | PAD_CFG0_RX_POL_YES | + PAD_BUF(TX_DISABLE), + PAD_PULL(NONE)), + /* GPP_G7 - GPIO */ + PAD_CFG_GPI_INT(GPP_G7, NONE, PWROK, OFF), + /* GPP_G8 - GPIO */ + PAD_CFG_GPI_INT(GPP_G8, NONE, PLTRST, OFF), + /* GPP_G9 - GPIO */ + PAD_CFG_GPI_INT(GPP_G9, NONE, PLTRST, OFF), + /* GPP_G10 - GPIO */ + PAD_CFG_GPI_INT(GPP_G10, NONE, PLTRST, OFF), + /* GPP_G11 - GPIO */ + PAD_CFG_GPI_INT(GPP_G11, NONE, PLTRST, OFF), + /* GPP_G12 - GPIO */ + _PAD_CFG_STRUCT(GPP_G12, + PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | + PAD_CFG0_TRIG_LEVEL | PAD_CFG0_RX_POL_YES | + PAD_BUF(TX_DISABLE), + PAD_PULL(NONE)), + /* GPP_G13 - GPIO */ + PAD_CFG_GPO(GPP_G13, 1, PLTRST), + /* GPP_G14 - GPIO */ + _PAD_CFG_STRUCT(GPP_G14, + PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | + PAD_CFG0_TRIG_LEVEL | PAD_CFG0_RX_POL_YES | + PAD_BUF(TX_DISABLE), + PAD_PULL(NONE)), + /* GPP_G15 - GPIO */ + PAD_CFG_GPO(GPP_G15, 0, PLTRST), + /* GPP_G16 - GPIO */ + PAD_CFG_TERM_GPO(GPP_G16, 1, 20K_PD, PLTRST), + /* GPP_G17 - GPIO */ + PAD_CFG_GPI_INT(GPP_G17, NONE, PLTRST, OFF), + /* GPP_G18 - GPIO */ + PAD_CFG_GPI_APIC(GPP_G18, NONE, PLTRST), + /* GPP_G19 - SMI# */ + PAD_CFG_NF_BUF_TRIG(GPP_G19, NONE, PLTRST, NF1, TX_DISABLE, OFF), + /* GPP_G20 - GPIO */ + PAD_CFG_GPI_INT(GPP_G20, NONE, PLTRST, OFF), + /* GPP_G21 - GPIO */ + PAD_CFG_GPI_INT(GPP_G21, NONE, PLTRST, OFF), + /* GPP_G22 - GPIO */ + PAD_CFG_GPI_INT(GPP_G22, NONE, PLTRST, OFF), + /* GPP_G23 - GPIO */ + PAD_CFG_GPI_INT(GPP_G23, NONE, PLTRST, OFF), + + /* ------- GPIO Group GPP_H ------- */ + /* GPP_H0 - GPIO */ + PAD_CFG_GPI_INT(GPP_H0, NONE, PLTRST, OFF), + /* GPP_H1 - GPIO */ + PAD_NC(GPP_H1, NONE), + /* GPP_H2 - GPIO */ + PAD_CFG_GPI_INT(GPP_H2, NONE, PLTRST, OFF), + /* GPP_H3 - GPIO */ + PAD_CFG_GPI_INT(GPP_H3, NONE, PLTRST, OFF), + /* GPP_H4 - GPIO */ + PAD_CFG_GPI_INT(GPP_H4, NONE, PLTRST, OFF), + /* GPP_H5 - GPIO */ + PAD_CFG_GPI_INT(GPP_H5, NONE, PLTRST, OFF), + /* GPP_H6 - GPIO */ + PAD_CFG_GPI_INT(GPP_H6, NONE, PLTRST, OFF), + /* GPP_H7 - GPIO */ + PAD_CFG_GPI_INT(GPP_H7, NONE, PLTRST, OFF), + /* GPP_H8 - GPIO */ + PAD_CFG_GPI_INT(GPP_H8, NONE, PLTRST, OFF), + /* GPP_H9 - GPIO */ + PAD_CFG_GPI_INT(GPP_H9, NONE, PLTRST, OFF), + /* GPP_H10 - GPIO */ + PAD_CFG_GPI_INT(GPP_H10, NONE, PLTRST, OFF), + /* GPP_H11 - GPIO */ + PAD_CFG_GPI_INT(GPP_H11, NONE, PLTRST, OFF), + /* GPP_H12 - GPIO */ + PAD_CFG_GPI_INT(GPP_H12, NONE, PLTRST, OFF), + /* GPP_H13 - GPIO */ + PAD_CFG_GPI_APIC(GPP_H13, NONE, PLTRST), + /* GPP_H14 - GPIO */ + PAD_CFG_GPI_APIC(GPP_H14, NONE, PLTRST), + /* GPP_H15 - GPIO */ + PAD_CFG_GPI_APIC(GPP_H15, NONE, PLTRST), + /* GPP_H16 - GPIO */ + PAD_CFG_GPI(GPP_H16, NONE, PLTRST), + /* GPP_H17 - GPIO */ + PAD_CFG_GPO(GPP_H17, 1, PLTRST), + /* GPP_H18 - GPIO */ + PAD_CFG_GPI_INT(GPP_H18, NONE, PLTRST, OFF), + /* GPP_H19 - GPIO */ + PAD_CFG_GPI_INT(GPP_H19, NONE, PLTRST, OFF), + /* GPP_H20 - GPIO */ + PAD_CFG_GPI_INT(GPP_H20, NONE, PLTRST, OFF), + /* GPP_H21 - GPIO */ + PAD_CFG_GPI_INT(GPP_H21, NONE, PLTRST, OFF), + /* GPP_H22 - GPIO */ + PAD_CFG_GPI_INT(GPP_H22, NONE, PLTRST, OFF), + /* GPP_H23 - GPIO */ + PAD_CFG_GPI_INT(GPP_H23, NONE, PWROK, OFF), + + /* -------- GPIO Group GPD -------- */ + /* GPD0 - GPIO */ + PAD_CFG_GPI_INT(GPD0, NONE, PLTRST, OFF), + /* GPD1 - GPIO */ + PAD_CFG_GPO(GPD1, 0, PWROK), + /* GPD2 - LAN_WAKE# */ + PAD_CFG_NF_BUF_TRIG(GPD2, NATIVE, PWROK, NF1, RX_DISABLE, LEVEL), + /* GPD3 - PWRBTN# */ + PAD_CFG_NF_BUF_TRIG(GPD3, 20K_PU, PWROK, NF1, TX_DISABLE, OFF), + /* GPD4 - SLP_S3# */ + PAD_CFG_NF_BUF_TRIG(GPD4, NONE, PWROK, NF1, RX_DISABLE, OFF), + /* GPD5 - SLP_S4# */ + PAD_CFG_NF_BUF_TRIG(GPD5, NONE, PWROK, NF1, RX_DISABLE, OFF), + /* GPD6 - GPIO */ + PAD_CFG_GPI_INT(GPD6, NONE, PLTRST, OFF), + /* GPD7 - GPIO */ + _PAD_CFG_STRUCT(GPD7, + PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | + PAD_CFG0_TRIG_OFF | PAD_CFG0_RX_POL_NONE | + PAD_BUF(TX_DISABLE) | 1, + PAD_PULL(NONE)), + /* GPD8 - SUSCLK */ + PAD_CFG_NF_BUF_TRIG(GPD8, NONE, PWROK, NF1, RX_DISABLE, OFF), + /* GPD9 - SLP_WLAN# */ + PAD_CFG_NF_BUF_TRIG(GPD9, NONE, PWROK, NF1, RX_DISABLE, OFF), + /* GPD10 - SLP_S5# */ + PAD_CFG_NF_BUF_TRIG(GPD10, NONE, PWROK, NF1, RX_DISABLE, OFF), + /* GPD11 - GPIO */ + PAD_CFG_GPO(GPD11, 0, PWROK), + + /* ------- GPIO Group GPP_I ------- */ + /* GPP_I0 - DDPB_HPD0 */ + PAD_CFG_NF_BUF_TRIG(GPP_I0, NONE, PLTRST, NF1, TX_DISABLE, OFF), + /* GPP_I1 - DDPC_HPD1 */ + PAD_CFG_NF_BUF_TRIG(GPP_I1, NONE, PLTRST, NF1, TX_DISABLE, OFF), + /* GPP_I2 - DDPD_HPD2 */ + PAD_CFG_NF_BUF_TRIG(GPP_I2, NONE, PLTRST, NF1, TX_DISABLE, OFF), + /* GPP_I3 - DDPE_HPD3 */ + PAD_CFG_NF_BUF_TRIG(GPP_I3, NONE, PLTRST, NF1, TX_DISABLE, OFF), + /* GPP_I4 - GPIO */ + PAD_CFG_GPI_INT(GPP_I4, NONE, PLTRST, OFF), + /* GPP_I5 - DDPB_CTRLCLK */ + PAD_CFG_NF_BUF_TRIG(GPP_I5, NONE, PLTRST, NF1, TX_DISABLE, OFF), + /* GPP_I6 - DDPB_CTRLDATA */ + PAD_CFG_NF_BUF_TRIG(GPP_I6, 20K_PD, PLTRST, NF1, TX_DISABLE, OFF), + /* GPP_I7 - DDPC_CTRLCLK */ + PAD_CFG_NF_BUF_TRIG(GPP_I7, NONE, PLTRST, NF1, TX_DISABLE, OFF), + /* GPP_I8 - DDPC_CTRLDATA */ + PAD_CFG_NF_BUF_TRIG(GPP_I8, 20K_PD, PLTRST, NF1, TX_DISABLE, OFF), + /* GPP_I9 - DDPD_CTRLCLK */ + PAD_CFG_NF_BUF_TRIG(GPP_I9, NONE, PLTRST, NF1, TX_DISABLE, OFF), + /* GPP_I10 - DDPD_CTRLDATA */ + PAD_CFG_NF_BUF_TRIG(GPP_I10, 20K_PD, PLTRST, NF1, TX_DISABLE, OFF), +}; + +/* Early pad configuration in romstage */ +static const struct pad_config early_gpio_table[] = { + /* ------- GPIO Group GPP_A ------- */ + /* GPP_A0 - RCIN# */ + PAD_CFG_NF_BUF_TRIG(GPP_A0, NONE, PLTRST, NF1, TX_DISABLE, OFF), + /* GPP_A1 - LAD0 */ + PAD_CFG_NF_BUF_TRIG(GPP_A1, 20K_PU, PLTRST, NF1, NO_DISABLE, OFF), + /* GPP_A2 - LAD1 */ + PAD_CFG_NF_BUF_TRIG(GPP_A2, 20K_PU, PLTRST, NF1, NO_DISABLE, OFF), + /* GPP_A3 - LAD2 */ + PAD_CFG_NF_BUF_TRIG(GPP_A3, 20K_PU, PLTRST, NF1, NO_DISABLE, OFF), + /* GPP_A4 - LAD3 */ + PAD_CFG_NF_BUF_TRIG(GPP_A4, 20K_PU, PLTRST, NF1, NO_DISABLE, OFF), + /* GPP_A5 - LFRAME# */ + PAD_CFG_NF_BUF_TRIG(GPP_A5, NONE, PLTRST, NF1, RX_DISABLE, OFF), + /* GPP_A6 - SERIRQ */ + PAD_CFG_NF_BUF_TRIG(GPP_A6, NONE, PLTRST, NF1, NO_DISABLE, OFF), + + /* GPP_A8 - CLKRUN# */ + PAD_CFG_NF_BUF_TRIG(GPP_A8, NONE, PLTRST, NF1, TX_DISABLE, OFF), + /* GPP_A9 - CLKOUT_LPC0 */ + PAD_CFG_NF_BUF_TRIG(GPP_A9, 20K_PD, PLTRST, NF1, RX_DISABLE, OFF), + /* GPP_A10 - CLKOUT_LPC1 */ + PAD_CFG_NF_BUF_TRIG(GPP_A10, 20K_PD, PLTRST, NF1, RX_DISABLE, OFF), + + /* GPP_A13 - SUSWARN#/SUSPWRDNACK */ + PAD_CFG_NF_BUF_TRIG(GPP_A13, NONE, DEEP, NF1, RX_DISABLE, OFF), + /* GPP_A14 - SUS_STAT# */ + PAD_CFG_NF_BUF_TRIG(GPP_A14, NONE, DEEP, NF1, RX_DISABLE, OFF), + /* GPP_A15 - SUS_ACK# */ + PAD_CFG_NF_BUF_TRIG(GPP_A15, 20K_PU, DEEP, NF1, TX_DISABLE, OFF), +}; + +#endif diff --git a/src/mainboard/gigabyte/ga-z170x-gaming7/mainboard.c b/src/mainboard/gigabyte/ga-z170x-gaming7/mainboard.c new file mode 100644 index 0000000..4c1c6cd --- /dev/null +++ b/src/mainboard/gigabyte/ga-z170x-gaming7/mainboard.c @@ -0,0 +1,30 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018 Tristan Corrick tristan@corrick.kiwi + * Copyright (C) 2019 Maxim Polyakov max.senia.poliak@gmail.com + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <device/device.h> +#include <drivers/intel/gma/int15.h> + +static void mainboard_enable(struct device *dev) +{ + install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_NONE, + GMA_INT15_PANEL_FIT_DEFAULT, + GMA_INT15_BOOT_DISPLAY_DEFAULT, 0); +} + +struct chip_operations mainboard_ops = { + .enable_dev = mainboard_enable, +}; diff --git a/src/mainboard/gigabyte/ga-z170x-gaming7/ramstage.c b/src/mainboard/gigabyte/ga-z170x-gaming7/ramstage.c new file mode 100644 index 0000000..a247b72 --- /dev/null +++ b/src/mainboard/gigabyte/ga-z170x-gaming7/ramstage.c @@ -0,0 +1,27 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Intel Corporation + * Copyright (C) 2019 Maxim Polyakov max.senia.poliak@gmail.com + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <soc/ramstage.h> +#include "include/gpio.h" + +void mainboard_silicon_init_params(FSP_SIL_UPD *params) +{ + /* Configure pads prior to SiliconInit() in case there's any + * dependencies during hardware initialization. */ + gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table)); + + params->CdClock = 3; +} diff --git a/src/mainboard/gigabyte/ga-z170x-gaming7/romstage.c b/src/mainboard/gigabyte/ga-z170x-gaming7/romstage.c new file mode 100644 index 0000000..0c0371b --- /dev/null +++ b/src/mainboard/gigabyte/ga-z170x-gaming7/romstage.c @@ -0,0 +1,66 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Intel Corporation. + * Copyright (C) 2019 Maxim Polyakov max.senia.poliak@gmail.com + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <soc/romstage.h> +#include <string.h> +#include <spd_bin.h> + +static void mainboard_fill_rcomp_res_data(void *rcomp_ptr) +{ + /* Rcomp resistor */ + const u16 RcompResistor[3] = { 200, 81, 162 }; + memcpy(rcomp_ptr, RcompResistor, + sizeof(RcompResistor)); +} + +static void mainboard_fill_rcomp_strength_data(void *rcomp_strength_ptr) +{ + /* Rcomp target */ + static const u16 RcompTarget[5] = { + 100, 40, 40, 23, 40 }; + memcpy(rcomp_strength_ptr, RcompTarget, sizeof(RcompTarget)); +} + +void mainboard_memory_init_params(FSPM_UPD *mupd) +{ + FSP_M_CONFIG *mem_cfg; + struct spd_block blk = { + .addr_map = { 0x50, 0x51, 0x52, 0x53, }, + }; + + mem_cfg = &mupd->FspmConfig; + mainboard_fill_dq_map_data(&mem_cfg->DqByteMapCh0, + &mem_cfg->DqByteMapCh1); + mainboard_fill_dqs_map_data(&mem_cfg->DqsMapCpu2DramCh0, + &mem_cfg->DqsMapCpu2DramCh1); + mainboard_fill_rcomp_res_data(&mem_cfg->RcompResistor); + mainboard_fill_rcomp_strength_data(&mem_cfg->RcompTarget); + + mem_cfg->DqPinsInterleaved = 1; + get_spd_smbus(&blk); + mem_cfg->MemorySpdDataLen = blk.len; + mem_cfg->MemorySpdPtr00 = (uintptr_t)blk.spd_array[0]; + mem_cfg->MemorySpdPtr10 = (uintptr_t)blk.spd_array[2]; + mem_cfg->MemorySpdPtr01 = (uintptr_t)blk.spd_array[1]; + mem_cfg->MemorySpdPtr11 = (uintptr_t)blk.spd_array[3]; + dump_spd_info(&blk); + + /* use virtual channel 1 for the dmi interface of the PCH */ + mupd->FspmTestConfig.DmiVc1 = 1; + + /* desktop type */ + mem_cfg->UserBd = BOARD_TYPE_DESKTOP; +}
Hello build bot (Jenkins), Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/38920
to look at the new patch set (#2).
Change subject: [WIP] mb/gigabyte: Add Gigabyte Z170X-Gaming 7 ......................................................................
[WIP] mb/gigabyte: Add Gigabyte Z170X-Gaming 7
Change-Id: Ib2c69bddd22cbd8f797dbb57370a4d8e5afa63bc --- A src/mainboard/gigabyte/ga-z170x-gaming7/Kconfig A src/mainboard/gigabyte/ga-z170x-gaming7/Kconfig.name A src/mainboard/gigabyte/ga-z170x-gaming7/Makefile.inc A src/mainboard/gigabyte/ga-z170x-gaming7/acpi/dptf.asl A src/mainboard/gigabyte/ga-z170x-gaming7/acpi/ec.asl A src/mainboard/gigabyte/ga-z170x-gaming7/acpi/mainboard.asl A src/mainboard/gigabyte/ga-z170x-gaming7/acpi/superio.asl A src/mainboard/gigabyte/ga-z170x-gaming7/board_info.txt A src/mainboard/gigabyte/ga-z170x-gaming7/cmos.default A src/mainboard/gigabyte/ga-z170x-gaming7/cmos.layout A src/mainboard/gigabyte/ga-z170x-gaming7/devicetree.cb A src/mainboard/gigabyte/ga-z170x-gaming7/dsdt.asl A src/mainboard/gigabyte/ga-z170x-gaming7/gma-mainboard.ads A src/mainboard/gigabyte/ga-z170x-gaming7/gpio.h A src/mainboard/gigabyte/ga-z170x-gaming7/hda_verb.c A src/mainboard/gigabyte/ga-z170x-gaming7/include/gpio.h A src/mainboard/gigabyte/ga-z170x-gaming7/mainboard.c A src/mainboard/gigabyte/ga-z170x-gaming7/ramstage.c A src/mainboard/gigabyte/ga-z170x-gaming7/romstage.c 19 files changed, 1,704 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/20/38920/2
Pavel Sayekat has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38920 )
Change subject: [WIP] mb/gigabyte: Add Gigabyte Z170X-Gaming 7 ......................................................................
Patch Set 2:
(1 comment)
.
https://review.coreboot.org/c/coreboot/+/38920/2/src/mainboard/gigabyte/ga-z... File src/mainboard/gigabyte/ga-z170x-gaming7/Kconfig.name:
https://review.coreboot.org/c/coreboot/+/38920/2/src/mainboard/gigabyte/ga-z... PS2, Line 2: bool "GA-Z170X-Gaming 7" I think it should match with your Kconfig's MAINBOARD_PART_NUMBER's default value? Like only "Z170X-Gaming 7".
Pavel Sayekat has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38920 )
Change subject: [WIP] mb/gigabyte: Add Gigabyte Z170X-Gaming 7 ......................................................................
Patch Set 2:
(1 comment)
.
https://review.coreboot.org/c/coreboot/+/38920/2/src/mainboard/gigabyte/ga-z... File src/mainboard/gigabyte/ga-z170x-gaming7/Kconfig:
https://review.coreboot.org/c/coreboot/+/38920/2/src/mainboard/gigabyte/ga-z... PS2, Line 1: if BOARD_GIGABYTE_GA_Z170X_GAMING_7 It doesn't match with the board name defined in your Kconfig.name.
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38920 )
Change subject: [WIP] mb/gigabyte: Add Gigabyte Z170X-Gaming 7 ......................................................................
Patch Set 2:
(13 comments)
https://review.coreboot.org/c/coreboot/+/38920/2/src/mainboard/gigabyte/ga-z... File src/mainboard/gigabyte/ga-z170x-gaming7/Kconfig:
https://review.coreboot.org/c/coreboot/+/38920/2/src/mainboard/gigabyte/ga-z... PS2, Line 14: SUPERIO_ITE_IT8528E You're better off selecting IT8728E, really. IT8528E is an EC for laptops and such.
https://review.coreboot.org/c/coreboot/+/38920/2/src/mainboard/gigabyte/ga-z... PS2, Line 32: config DEVICETREE : string : default "devicetree.cb" That's the default
https://review.coreboot.org/c/coreboot/+/38920/2/src/mainboard/gigabyte/ga-z... File src/mainboard/gigabyte/ga-z170x-gaming7/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/38920/2/src/mainboard/gigabyte/ga-z... PS2, Line 190: [4] = 0, \ : [5] = 0, \ Enable these
https://review.coreboot.org/c/coreboot/+/38920/2/src/mainboard/gigabyte/ga-z... PS2, Line 193: # SATA4 and SATA5 are located in the lower right corner : # of the board, but there is no connector for this Smells like copypasta
https://review.coreboot.org/c/coreboot/+/38920/2/src/mainboard/gigabyte/ga-z... PS2, Line 211: # Set params for PEG 0:1:0 Check schematics for PCIe port routing
https://review.coreboot.org/c/coreboot/+/38920/2/src/mainboard/gigabyte/ga-z... PS2, Line 330: chip superio/nuvoton/nct6791d Not at all!
https://review.coreboot.org/c/coreboot/+/38920/2/src/mainboard/gigabyte/ga-z... File src/mainboard/gigabyte/ga-z170x-gaming7/dsdt.asl:
https://review.coreboot.org/c/coreboot/+/38920/2/src/mainboard/gigabyte/ga-z... PS2, Line 34: // CPU Please drop, it does not provide any value.
https://review.coreboot.org/c/coreboot/+/38920/2/src/mainboard/gigabyte/ga-z... File src/mainboard/gigabyte/ga-z170x-gaming7/gma-mainboard.ads:
https://review.coreboot.org/c/coreboot/+/38920/2/src/mainboard/gigabyte/ga-z... PS2, Line 26: ports : constant Port_List := The rest of Ada code is indented with three spaces
https://review.coreboot.org/c/coreboot/+/38920/2/src/mainboard/gigabyte/ga-z... File src/mainboard/gigabyte/ga-z170x-gaming7/gpio.h:
PS2: This should be a gpio.c instead
https://review.coreboot.org/c/coreboot/+/38920/2/src/mainboard/gigabyte/ga-z... PS2, Line 25: static const struct pad_config gpio_table[] = { Are these correct?
https://review.coreboot.org/c/coreboot/+/38920/2/src/mainboard/gigabyte/ga-z... File src/mainboard/gigabyte/ga-z170x-gaming7/hda_verb.c:
https://review.coreboot.org/c/coreboot/+/38920/2/src/mainboard/gigabyte/ga-z... PS2, Line 37: /* Intel, SkylakeHDMI */ Add a blank line between codecs for clarity
https://review.coreboot.org/c/coreboot/+/38920/2/src/mainboard/gigabyte/ga-z... File src/mainboard/gigabyte/ga-z170x-gaming7/include/gpio.h:
PS2: why two gpio.h ?
https://review.coreboot.org/c/coreboot/+/38920/2/src/mainboard/gigabyte/ga-z... File src/mainboard/gigabyte/ga-z170x-gaming7/mainboard.c:
PS2: This should not be necessary at all for SKL.
Hello Angel Pons, build bot (Jenkins), Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/38920
to look at the new patch set (#3).
Change subject: [WIP] mb/gigabyte: Add Gigabyte Z170X-Gaming 7 ......................................................................
[WIP] mb/gigabyte: Add Gigabyte Z170X-Gaming 7
THIS IS UNTESTED SO FAR
The board has Boot guard enabled but is still in manufacturing mode. As far as the intel tools guide me there is no key burned yet.
Change-Id: Ib2c69bddd22cbd8f797dbb57370a4d8e5afa63bc --- A src/mainboard/gigabyte/ga-z170x-gaming7/Kconfig A src/mainboard/gigabyte/ga-z170x-gaming7/Kconfig.name A src/mainboard/gigabyte/ga-z170x-gaming7/Makefile.inc A src/mainboard/gigabyte/ga-z170x-gaming7/acpi/dptf.asl A src/mainboard/gigabyte/ga-z170x-gaming7/acpi/ec.asl A src/mainboard/gigabyte/ga-z170x-gaming7/acpi/mainboard.asl A src/mainboard/gigabyte/ga-z170x-gaming7/acpi/superio.asl A src/mainboard/gigabyte/ga-z170x-gaming7/board_info.txt A src/mainboard/gigabyte/ga-z170x-gaming7/cmos.default A src/mainboard/gigabyte/ga-z170x-gaming7/cmos.layout A src/mainboard/gigabyte/ga-z170x-gaming7/data.vbt A src/mainboard/gigabyte/ga-z170x-gaming7/devicetree.cb A src/mainboard/gigabyte/ga-z170x-gaming7/dsdt.asl A src/mainboard/gigabyte/ga-z170x-gaming7/gma-mainboard.ads A src/mainboard/gigabyte/ga-z170x-gaming7/gpio.h A src/mainboard/gigabyte/ga-z170x-gaming7/hda_verb.c A src/mainboard/gigabyte/ga-z170x-gaming7/include/gpio.h A src/mainboard/gigabyte/ga-z170x-gaming7/mainboard.c A src/mainboard/gigabyte/ga-z170x-gaming7/ramstage.c A src/mainboard/gigabyte/ga-z170x-gaming7/romstage.c 20 files changed, 1,626 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/20/38920/3
Hello Angel Pons, build bot (Jenkins), Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/38920
to look at the new patch set (#4).
Change subject: [WIP] mb/gigabyte: Add Gigabyte Z170X-Gaming 7 ......................................................................
[WIP] mb/gigabyte: Add Gigabyte Z170X-Gaming 7
THIS IS UNTESTED SO FAR
The board has Boot guard enabled but is still in manufacturing mode. As far as the intel tools guide me there is no key burned yet.
Change-Id: Ib2c69bddd22cbd8f797dbb57370a4d8e5afa63bc --- A src/mainboard/gigabyte/ga-z170x-gaming7/Kconfig A src/mainboard/gigabyte/ga-z170x-gaming7/Kconfig.name A src/mainboard/gigabyte/ga-z170x-gaming7/Makefile.inc A src/mainboard/gigabyte/ga-z170x-gaming7/acpi/dptf.asl A src/mainboard/gigabyte/ga-z170x-gaming7/acpi/ec.asl A src/mainboard/gigabyte/ga-z170x-gaming7/acpi/mainboard.asl A src/mainboard/gigabyte/ga-z170x-gaming7/acpi/superio.asl A src/mainboard/gigabyte/ga-z170x-gaming7/board_info.txt A src/mainboard/gigabyte/ga-z170x-gaming7/cmos.default A src/mainboard/gigabyte/ga-z170x-gaming7/cmos.layout A src/mainboard/gigabyte/ga-z170x-gaming7/data.vbt A src/mainboard/gigabyte/ga-z170x-gaming7/devicetree.cb A src/mainboard/gigabyte/ga-z170x-gaming7/dsdt.asl A src/mainboard/gigabyte/ga-z170x-gaming7/gma-mainboard.ads A src/mainboard/gigabyte/ga-z170x-gaming7/gpio.h A src/mainboard/gigabyte/ga-z170x-gaming7/hda_verb.c A src/mainboard/gigabyte/ga-z170x-gaming7/include/gpio.h A src/mainboard/gigabyte/ga-z170x-gaming7/mainboard.c A src/mainboard/gigabyte/ga-z170x-gaming7/ramstage.c A src/mainboard/gigabyte/ga-z170x-gaming7/romstage.c 20 files changed, 1,622 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/20/38920/4
Christoph Pomaska has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38920 )
Change subject: [WIP] mb/gigabyte: Add Gigabyte Z170X-Gaming 7 ......................................................................
Patch Set 4:
(6 comments)
https://review.coreboot.org/c/coreboot/+/38920/2/src/mainboard/gigabyte/ga-z... File src/mainboard/gigabyte/ga-z170x-gaming7/Kconfig:
https://review.coreboot.org/c/coreboot/+/38920/2/src/mainboard/gigabyte/ga-z... PS2, Line 1: if BOARD_GIGABYTE_GA_Z170X_GAMING_7
It doesn't match with the board name defined in your Kconfig.name.
Done
https://review.coreboot.org/c/coreboot/+/38920/2/src/mainboard/gigabyte/ga-z... PS2, Line 14: SUPERIO_ITE_IT8528E
You're better off selecting IT8728E, really. IT8528E is an EC for laptops and such.
Done
https://review.coreboot.org/c/coreboot/+/38920/2/src/mainboard/gigabyte/ga-z... PS2, Line 32: config DEVICETREE : string : default "devicetree.cb"
That's the default
Done
https://review.coreboot.org/c/coreboot/+/38920/2/src/mainboard/gigabyte/ga-z... File src/mainboard/gigabyte/ga-z170x-gaming7/Kconfig.name:
https://review.coreboot.org/c/coreboot/+/38920/2/src/mainboard/gigabyte/ga-z... PS2, Line 2: bool "GA-Z170X-Gaming 7"
I think it should match with your Kconfig's MAINBOARD_PART_NUMBER's default value? Like only "Z170X- […]
Done
https://review.coreboot.org/c/coreboot/+/38920/2/src/mainboard/gigabyte/ga-z... File src/mainboard/gigabyte/ga-z170x-gaming7/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/38920/2/src/mainboard/gigabyte/ga-z... PS2, Line 190: [4] = 0, \ : [5] = 0, \
Enable these
Done
https://review.coreboot.org/c/coreboot/+/38920/2/src/mainboard/gigabyte/ga-z... PS2, Line 193: # SATA4 and SATA5 are located in the lower right corner : # of the board, but there is no connector for this
Smells like copypasta
Done
Hello Angel Pons, build bot (Jenkins), Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/38920
to look at the new patch set (#5).
Change subject: [WIP] mb/gigabyte: Add Gigabyte Z170X-Gaming 7 ......................................................................
[WIP] mb/gigabyte: Add Gigabyte Z170X-Gaming 7
THIS IS UNTESTED SO FAR
The board has Boot guard enabled but is still in manufacturing mode. As far as the intel tools guide me there is no key burned yet.
Change-Id: Ib2c69bddd22cbd8f797dbb57370a4d8e5afa63bc Signed-off-by: Christoph Pomaska coreboot@slrie.de --- A src/mainboard/gigabyte/ga-z170x-gaming7/Kconfig A src/mainboard/gigabyte/ga-z170x-gaming7/Kconfig.name A src/mainboard/gigabyte/ga-z170x-gaming7/Makefile.inc A src/mainboard/gigabyte/ga-z170x-gaming7/acpi/dptf.asl A src/mainboard/gigabyte/ga-z170x-gaming7/acpi/ec.asl A src/mainboard/gigabyte/ga-z170x-gaming7/acpi/mainboard.asl A src/mainboard/gigabyte/ga-z170x-gaming7/acpi/superio.asl A src/mainboard/gigabyte/ga-z170x-gaming7/board_info.txt A src/mainboard/gigabyte/ga-z170x-gaming7/cmos.default A src/mainboard/gigabyte/ga-z170x-gaming7/cmos.layout A src/mainboard/gigabyte/ga-z170x-gaming7/data.vbt A src/mainboard/gigabyte/ga-z170x-gaming7/devicetree.cb A src/mainboard/gigabyte/ga-z170x-gaming7/dsdt.asl A src/mainboard/gigabyte/ga-z170x-gaming7/gma-mainboard.ads A src/mainboard/gigabyte/ga-z170x-gaming7/gpio.h A src/mainboard/gigabyte/ga-z170x-gaming7/hda_verb.c A src/mainboard/gigabyte/ga-z170x-gaming7/include/gpio.h A src/mainboard/gigabyte/ga-z170x-gaming7/mainboard.c A src/mainboard/gigabyte/ga-z170x-gaming7/ramstage.c A src/mainboard/gigabyte/ga-z170x-gaming7/romstage.c 20 files changed, 1,622 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/20/38920/5
Hello Angel Pons, build bot (Jenkins), Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/38920
to look at the new patch set (#6).
Change subject: [WIP] mb/gigabyte: Add Gigabyte Z170X-Gaming 7 ......................................................................
[WIP] mb/gigabyte: Add Gigabyte Z170X-Gaming 7
THIS IS UNTESTED SO FAR
The board has Boot guard enabled but is still in manufacturing mode. As far as the intel tools guide me there is no key burned yet.
Change-Id: Ib2c69bddd22cbd8f797dbb57370a4d8e5afa63bc Signed-off-by: Christoph Pomaska coreboot@slrie.de --- A src/mainboard/gigabyte/ga-z170x-gaming7/Kconfig A src/mainboard/gigabyte/ga-z170x-gaming7/Kconfig.name A src/mainboard/gigabyte/ga-z170x-gaming7/Makefile.inc A src/mainboard/gigabyte/ga-z170x-gaming7/acpi/dptf.asl A src/mainboard/gigabyte/ga-z170x-gaming7/acpi/ec.asl A src/mainboard/gigabyte/ga-z170x-gaming7/acpi/mainboard.asl A src/mainboard/gigabyte/ga-z170x-gaming7/acpi/superio.asl A src/mainboard/gigabyte/ga-z170x-gaming7/board_info.txt A src/mainboard/gigabyte/ga-z170x-gaming7/cmos.default A src/mainboard/gigabyte/ga-z170x-gaming7/cmos.layout A src/mainboard/gigabyte/ga-z170x-gaming7/data.vbt A src/mainboard/gigabyte/ga-z170x-gaming7/devicetree.cb A src/mainboard/gigabyte/ga-z170x-gaming7/dsdt.asl A src/mainboard/gigabyte/ga-z170x-gaming7/gma-mainboard.ads A src/mainboard/gigabyte/ga-z170x-gaming7/gpio.h A src/mainboard/gigabyte/ga-z170x-gaming7/hda_verb.c A src/mainboard/gigabyte/ga-z170x-gaming7/include/gpio.h A src/mainboard/gigabyte/ga-z170x-gaming7/mainboard.c A src/mainboard/gigabyte/ga-z170x-gaming7/ramstage.c A src/mainboard/gigabyte/ga-z170x-gaming7/romstage.c 20 files changed, 1,622 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/20/38920/6
Christoph Pomaska has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38920 )
Change subject: [WIP] mb/gigabyte: Add Gigabyte Z170X-Gaming 7 ......................................................................
Patch Set 6:
(6 comments)
https://review.coreboot.org/c/coreboot/+/38920/2/src/mainboard/gigabyte/ga-z... File src/mainboard/gigabyte/ga-z170x-gaming7/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/38920/2/src/mainboard/gigabyte/ga-z... PS2, Line 190: [4] = 0, \ : [5] = 0, \
Done
Done
https://review.coreboot.org/c/coreboot/+/38920/2/src/mainboard/gigabyte/ga-z... PS2, Line 193: # SATA4 and SATA5 are located in the lower right corner : # of the board, but there is no connector for this
Done
Done
https://review.coreboot.org/c/coreboot/+/38920/2/src/mainboard/gigabyte/ga-z... PS2, Line 330: chip superio/nuvoton/nct6791d
Not at all!
Done
https://review.coreboot.org/c/coreboot/+/38920/2/src/mainboard/gigabyte/ga-z... File src/mainboard/gigabyte/ga-z170x-gaming7/dsdt.asl:
https://review.coreboot.org/c/coreboot/+/38920/2/src/mainboard/gigabyte/ga-z... PS2, Line 34: // CPU
Please drop, it does not provide any value.
Just the comment or the include aswell?
https://review.coreboot.org/c/coreboot/+/38920/2/src/mainboard/gigabyte/ga-z... File src/mainboard/gigabyte/ga-z170x-gaming7/gma-mainboard.ads:
https://review.coreboot.org/c/coreboot/+/38920/2/src/mainboard/gigabyte/ga-z... PS2, Line 26: ports : constant Port_List :=
The rest of Ada code is indented with three spaces
Done
https://review.coreboot.org/c/coreboot/+/38920/2/src/mainboard/gigabyte/ga-z... File src/mainboard/gigabyte/ga-z170x-gaming7/gpio.h:
https://review.coreboot.org/c/coreboot/+/38920/2/src/mainboard/gigabyte/ga-z... PS2, Line 25: static const struct pad_config gpio_table[] = {
Are these correct?
The values have been retrieved from the board.
Hello Angel Pons, build bot (Jenkins), Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/38920
to look at the new patch set (#7).
Change subject: [WIP] mb/gigabyte: Add Gigabyte Z170X-Gaming 7 ......................................................................
[WIP] mb/gigabyte: Add Gigabyte Z170X-Gaming 7
THIS IS UNTESTED SO FAR
The board has Boot guard enabled but is still in manufacturing mode. As far as the intel tools guide me there is no key burned yet.
Change-Id: Ib2c69bddd22cbd8f797dbb57370a4d8e5afa63bc Signed-off-by: Christoph Pomaska coreboot@slrie.de --- A src/mainboard/gigabyte/ga-z170x-gaming7/Kconfig A src/mainboard/gigabyte/ga-z170x-gaming7/Kconfig.name A src/mainboard/gigabyte/ga-z170x-gaming7/Makefile.inc A src/mainboard/gigabyte/ga-z170x-gaming7/acpi/dptf.asl A src/mainboard/gigabyte/ga-z170x-gaming7/acpi/ec.asl A src/mainboard/gigabyte/ga-z170x-gaming7/acpi/mainboard.asl A src/mainboard/gigabyte/ga-z170x-gaming7/acpi/superio.asl A src/mainboard/gigabyte/ga-z170x-gaming7/board_info.txt A src/mainboard/gigabyte/ga-z170x-gaming7/cmos.default A src/mainboard/gigabyte/ga-z170x-gaming7/cmos.layout A src/mainboard/gigabyte/ga-z170x-gaming7/data.vbt A src/mainboard/gigabyte/ga-z170x-gaming7/devicetree.cb A src/mainboard/gigabyte/ga-z170x-gaming7/dsdt.asl A src/mainboard/gigabyte/ga-z170x-gaming7/gma-mainboard.ads A src/mainboard/gigabyte/ga-z170x-gaming7/gpio.c A src/mainboard/gigabyte/ga-z170x-gaming7/hda_verb.c A src/mainboard/gigabyte/ga-z170x-gaming7/mainboard.c A src/mainboard/gigabyte/ga-z170x-gaming7/ramstage.c A src/mainboard/gigabyte/ga-z170x-gaming7/romstage.c 19 files changed, 1,113 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/20/38920/7
Christoph Pomaska has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38920 )
Change subject: [WIP] mb/gigabyte: Add Gigabyte Z170X-Gaming 7 ......................................................................
Patch Set 7:
(2 comments)
https://review.coreboot.org/c/coreboot/+/38920/2/src/mainboard/gigabyte/ga-z... File src/mainboard/gigabyte/ga-z170x-gaming7/gpio.h:
PS2:
This should be a gpio. […]
Done
https://review.coreboot.org/c/coreboot/+/38920/2/src/mainboard/gigabyte/ga-z... File src/mainboard/gigabyte/ga-z170x-gaming7/include/gpio.h:
PS2:
why two gpio. […]
copypasta leftover.
Hello Angel Pons, build bot (Jenkins), Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/38920
to look at the new patch set (#8).
Change subject: [WIP] mb/gigabyte: Add Gigabyte Z170X-Gaming 7 ......................................................................
[WIP] mb/gigabyte: Add Gigabyte Z170X-Gaming 7
THIS IS UNTESTED SO FAR
The board has Boot guard enabled but is still in manufacturing mode. As far as the intel tools guide me there is no key burned yet.
Change-Id: Ib2c69bddd22cbd8f797dbb57370a4d8e5afa63bc Signed-off-by: Christoph Pomaska coreboot@slrie.de --- A src/mainboard/gigabyte/ga-z170x-gaming7/Kconfig A src/mainboard/gigabyte/ga-z170x-gaming7/Kconfig.name A src/mainboard/gigabyte/ga-z170x-gaming7/Makefile.inc A src/mainboard/gigabyte/ga-z170x-gaming7/acpi/dptf.asl A src/mainboard/gigabyte/ga-z170x-gaming7/acpi/ec.asl A src/mainboard/gigabyte/ga-z170x-gaming7/acpi/mainboard.asl A src/mainboard/gigabyte/ga-z170x-gaming7/acpi/superio.asl A src/mainboard/gigabyte/ga-z170x-gaming7/board_info.txt A src/mainboard/gigabyte/ga-z170x-gaming7/cmos.default A src/mainboard/gigabyte/ga-z170x-gaming7/cmos.layout A src/mainboard/gigabyte/ga-z170x-gaming7/data.vbt A src/mainboard/gigabyte/ga-z170x-gaming7/devicetree.cb A src/mainboard/gigabyte/ga-z170x-gaming7/dsdt.asl A src/mainboard/gigabyte/ga-z170x-gaming7/gma-mainboard.ads A src/mainboard/gigabyte/ga-z170x-gaming7/gpio.c A src/mainboard/gigabyte/ga-z170x-gaming7/hda_verb.c A src/mainboard/gigabyte/ga-z170x-gaming7/ramstage.c A src/mainboard/gigabyte/ga-z170x-gaming7/romstage.c 18 files changed, 1,083 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/20/38920/8
Christoph Pomaska has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38920 )
Change subject: [WIP] mb/gigabyte: Add Gigabyte Z170X-Gaming 7 ......................................................................
Patch Set 8:
(2 comments)
https://review.coreboot.org/c/coreboot/+/38920/2/src/mainboard/gigabyte/ga-z... File src/mainboard/gigabyte/ga-z170x-gaming7/hda_verb.c:
https://review.coreboot.org/c/coreboot/+/38920/2/src/mainboard/gigabyte/ga-z... PS2, Line 37: /* Intel, SkylakeHDMI */
Add a blank line between codecs for clarity
Done
https://review.coreboot.org/c/coreboot/+/38920/2/src/mainboard/gigabyte/ga-z... File src/mainboard/gigabyte/ga-z170x-gaming7/mainboard.c:
PS2:
This should not be necessary at all for SKL.
Done
Hello Angel Pons, build bot (Jenkins), Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/38920
to look at the new patch set (#9).
Change subject: [WIP] mb/gigabyte: Add Gigabyte Z170X-Gaming 7 ......................................................................
[WIP] mb/gigabyte: Add Gigabyte Z170X-Gaming 7
THIS IS UNTESTED SO FAR
The board has Boot guard enabled but is still in manufacturing mode. As far as the intel tools guide me there is no key burned yet.
Change-Id: Ib2c69bddd22cbd8f797dbb57370a4d8e5afa63bc Signed-off-by: Christoph Pomaska coreboot@slrie.de --- A src/mainboard/gigabyte/ga-z170x-gaming7/Kconfig A src/mainboard/gigabyte/ga-z170x-gaming7/Kconfig.name A src/mainboard/gigabyte/ga-z170x-gaming7/Makefile.inc A src/mainboard/gigabyte/ga-z170x-gaming7/acpi/dptf.asl A src/mainboard/gigabyte/ga-z170x-gaming7/acpi/ec.asl A src/mainboard/gigabyte/ga-z170x-gaming7/acpi/mainboard.asl A src/mainboard/gigabyte/ga-z170x-gaming7/acpi/superio.asl A src/mainboard/gigabyte/ga-z170x-gaming7/board_info.txt A src/mainboard/gigabyte/ga-z170x-gaming7/cmos.default A src/mainboard/gigabyte/ga-z170x-gaming7/cmos.layout A src/mainboard/gigabyte/ga-z170x-gaming7/data.vbt A src/mainboard/gigabyte/ga-z170x-gaming7/devicetree.cb A src/mainboard/gigabyte/ga-z170x-gaming7/dsdt.asl A src/mainboard/gigabyte/ga-z170x-gaming7/gma-mainboard.ads A src/mainboard/gigabyte/ga-z170x-gaming7/gpio.c A src/mainboard/gigabyte/ga-z170x-gaming7/hda_verb.c A src/mainboard/gigabyte/ga-z170x-gaming7/ramstage.c A src/mainboard/gigabyte/ga-z170x-gaming7/romstage.c 18 files changed, 1,083 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/20/38920/9
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38920 )
Change subject: [WIP] mb/gigabyte: Add Gigabyte Z170X-Gaming 7 ......................................................................
Patch Set 9:
(1 comment)
https://review.coreboot.org/c/coreboot/+/38920/9/src/mainboard/gigabyte/ga-z... File src/mainboard/gigabyte/ga-z170x-gaming7/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/38920/9/src/mainboard/gigabyte/ga-z... PS9, Line 354: end one tab too much (is the end of "chip superio/ite/it8728f")
Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38920 )
Change subject: [WIP] mb/gigabyte: Add Gigabyte Z170X-Gaming 7 ......................................................................
Patch Set 9:
(2 comments)
https://review.coreboot.org/c/coreboot/+/38920/9/src/mainboard/gigabyte/ga-z... File src/mainboard/gigabyte/ga-z170x-gaming7/romstage.c:
https://review.coreboot.org/c/coreboot/+/38920/9/src/mainboard/gigabyte/ga-z... PS9, Line 24: const u16 RcompResistor[3] = { 200, 81, 162 }; 121, 75, 100
(actually, it's unclear if these are configurable for desktop CPUs at all)
https://review.coreboot.org/c/coreboot/+/38920/9/src/mainboard/gigabyte/ga-z... PS9, Line 33: 100, 40, 40, 23, 40 }; 60, 26, 20, 20, 26
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38920 )
Change subject: [WIP] mb/gigabyte: Add Gigabyte Z170X-Gaming 7 ......................................................................
Patch Set 9:
(1 comment)
https://review.coreboot.org/c/coreboot/+/38920/9/src/mainboard/gigabyte/ga-z... File src/mainboard/gigabyte/ga-z170x-gaming7/romstage.c:
https://review.coreboot.org/c/coreboot/+/38920/9/src/mainboard/gigabyte/ga-z... PS9, Line 24: const u16 RcompResistor[3] = { 200, 81, 162 };
121, 75, 100 […]
They don't exist at all.
Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38920 )
Change subject: [WIP] mb/gigabyte: Add Gigabyte Z170X-Gaming 7 ......................................................................
Patch Set 9:
(1 comment)
https://review.coreboot.org/c/coreboot/+/38920/9/src/mainboard/gigabyte/ga-z... File src/mainboard/gigabyte/ga-z170x-gaming7/romstage.c:
https://review.coreboot.org/c/coreboot/+/38920/9/src/mainboard/gigabyte/ga-z... PS9, Line 24: const u16 RcompResistor[3] = { 200, 81, 162 };
They don't exist at all.
Not on the mainboard, but there are resistors in the CPU package. Question remains if FSP handles it automatically for SKL-S (or the hardware ignores FSP) or needs some reasonable numbers.
Christoph Pomaska has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38920 )
Change subject: [WIP] mb/gigabyte: Add Gigabyte Z170X-Gaming 7 ......................................................................
Patch Set 9:
(3 comments)
https://review.coreboot.org/c/coreboot/+/38920/2/src/mainboard/gigabyte/ga-z... File src/mainboard/gigabyte/ga-z170x-gaming7/gpio.h:
https://review.coreboot.org/c/coreboot/+/38920/2/src/mainboard/gigabyte/ga-z... PS2, Line 25: static const struct pad_config gpio_table[] = {
The values have been retrieved from the board.
Done
https://review.coreboot.org/c/coreboot/+/38920/9/src/mainboard/gigabyte/ga-z... File src/mainboard/gigabyte/ga-z170x-gaming7/romstage.c:
https://review.coreboot.org/c/coreboot/+/38920/9/src/mainboard/gigabyte/ga-z... PS9, Line 24: const u16 RcompResistor[3] = { 200, 81, 162 };
They don't exist at all.
So I could remove the constant entirely?
https://review.coreboot.org/c/coreboot/+/38920/9/src/mainboard/gigabyte/ga-z... PS9, Line 33: 100, 40, 40, 23, 40 };
60, 26, 20, 20, 26
What about this one?
Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38920 )
Change subject: [WIP] mb/gigabyte: Add Gigabyte Z170X-Gaming 7 ......................................................................
Patch Set 9:
(2 comments)
https://review.coreboot.org/c/coreboot/+/38920/9/src/mainboard/gigabyte/ga-z... File src/mainboard/gigabyte/ga-z170x-gaming7/romstage.c:
https://review.coreboot.org/c/coreboot/+/38920/9/src/mainboard/gigabyte/ga-z... PS9, Line 24: const u16 RcompResistor[3] = { 200, 81, 162 };
121, 75, 100
Just take these numbers. Intel secret documents list them for SKL-H and CML-S, plus Angel confirmed that the resistors on the bottom of a SKL-S CPU match.
https://review.coreboot.org/c/coreboot/+/38920/9/src/mainboard/gigabyte/ga-z... PS9, Line 33: 100, 40, 40, 23, 40 };
What about this one?
Same here.
Hello Angel Pons, build bot (Jenkins), Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/38920
to look at the new patch set (#10).
Change subject: [WIP] mb/gigabyte: Add Gigabyte Z170X-Gaming 7 ......................................................................
[WIP] mb/gigabyte: Add Gigabyte Z170X-Gaming 7
THIS IS UNTESTED SO FAR
The board has Boot guard enabled but is still in manufacturing mode. As far as the intel tools guide me there is no key burned yet.
Change-Id: Ib2c69bddd22cbd8f797dbb57370a4d8e5afa63bc Signed-off-by: Christoph Pomaska coreboot@slrie.de --- A src/mainboard/gigabyte/ga-z170x-gaming7/Kconfig A src/mainboard/gigabyte/ga-z170x-gaming7/Kconfig.name A src/mainboard/gigabyte/ga-z170x-gaming7/Makefile.inc A src/mainboard/gigabyte/ga-z170x-gaming7/acpi/dptf.asl A src/mainboard/gigabyte/ga-z170x-gaming7/acpi/ec.asl A src/mainboard/gigabyte/ga-z170x-gaming7/acpi/mainboard.asl A src/mainboard/gigabyte/ga-z170x-gaming7/acpi/superio.asl A src/mainboard/gigabyte/ga-z170x-gaming7/board_info.txt A src/mainboard/gigabyte/ga-z170x-gaming7/cmos.default A src/mainboard/gigabyte/ga-z170x-gaming7/cmos.layout A src/mainboard/gigabyte/ga-z170x-gaming7/data.vbt A src/mainboard/gigabyte/ga-z170x-gaming7/devicetree.cb A src/mainboard/gigabyte/ga-z170x-gaming7/dsdt.asl A src/mainboard/gigabyte/ga-z170x-gaming7/gma-mainboard.ads A src/mainboard/gigabyte/ga-z170x-gaming7/gpio.c A src/mainboard/gigabyte/ga-z170x-gaming7/hda_verb.c A src/mainboard/gigabyte/ga-z170x-gaming7/ramstage.c A src/mainboard/gigabyte/ga-z170x-gaming7/romstage.c 18 files changed, 1,093 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/20/38920/10
Christoph Pomaska has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38920 )
Change subject: [WIP] mb/gigabyte: Add Gigabyte Z170X-Gaming 7 ......................................................................
Patch Set 10:
(2 comments)
https://review.coreboot.org/c/coreboot/+/38920/9/src/mainboard/gigabyte/ga-z... File src/mainboard/gigabyte/ga-z170x-gaming7/romstage.c:
https://review.coreboot.org/c/coreboot/+/38920/9/src/mainboard/gigabyte/ga-z... PS9, Line 24: const u16 RcompResistor[3] = { 200, 81, 162 };
121, 75, 100 […]
Done
https://review.coreboot.org/c/coreboot/+/38920/9/src/mainboard/gigabyte/ga-z... PS9, Line 33: 100, 40, 40, 23, 40 };
Same here.
Done
Hello Angel Pons, build bot (Jenkins), Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/38920
to look at the new patch set (#11).
Change subject: [WIP] mb/gigabyte: Add Gigabyte Z170X-Gaming 7 ......................................................................
[WIP] mb/gigabyte: Add Gigabyte Z170X-Gaming 7
At the current state of this commit the board does not go beyond romstage. (At least it does not brick the board though.)
The board has Boot guard enabled but is still in manufacturing mode. As far as the intel tools guide me there is no key burned yet.
Change-Id: Ib2c69bddd22cbd8f797dbb57370a4d8e5afa63bc Signed-off-by: Christoph Pomaska coreboot@slrie.de --- A src/mainboard/gigabyte/ga-z170x-gaming7/Kconfig A src/mainboard/gigabyte/ga-z170x-gaming7/Kconfig.name A src/mainboard/gigabyte/ga-z170x-gaming7/Makefile.inc A src/mainboard/gigabyte/ga-z170x-gaming7/acpi/dptf.asl A src/mainboard/gigabyte/ga-z170x-gaming7/acpi/ec.asl A src/mainboard/gigabyte/ga-z170x-gaming7/acpi/mainboard.asl A src/mainboard/gigabyte/ga-z170x-gaming7/acpi/superio.asl A src/mainboard/gigabyte/ga-z170x-gaming7/board_info.txt A src/mainboard/gigabyte/ga-z170x-gaming7/cmos.default A src/mainboard/gigabyte/ga-z170x-gaming7/cmos.layout A src/mainboard/gigabyte/ga-z170x-gaming7/data.vbt A src/mainboard/gigabyte/ga-z170x-gaming7/devicetree.cb A src/mainboard/gigabyte/ga-z170x-gaming7/dsdt.asl A src/mainboard/gigabyte/ga-z170x-gaming7/gma-mainboard.ads A src/mainboard/gigabyte/ga-z170x-gaming7/gpio.c A src/mainboard/gigabyte/ga-z170x-gaming7/hda_verb.c A src/mainboard/gigabyte/ga-z170x-gaming7/ramstage.c A src/mainboard/gigabyte/ga-z170x-gaming7/romstage.c 18 files changed, 1,093 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/20/38920/11
Hello build bot (Jenkins), Patrick Georgi, Martin Roth, Angel Pons,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/38920
to look at the new patch set (#12).
Change subject: [WIP] mb/gigabyte: Add Gigabyte Z170X-Gaming 7 ......................................................................
[WIP] mb/gigabyte: Add Gigabyte Z170X-Gaming 7
At the current state of this commit the board does not go beyond ramstage.
The board has Boot guard enabled but is still in manufacturing mode. As far as the intel tools guide me there is no key burned yet.
Change-Id: Ib2c69bddd22cbd8f797dbb57370a4d8e5afa63bc Signed-off-by: Christoph Pomaska coreboot@slrie.de --- A src/mainboard/gigabyte/ga-z170x-gaming7/Kconfig A src/mainboard/gigabyte/ga-z170x-gaming7/Kconfig.name A src/mainboard/gigabyte/ga-z170x-gaming7/Makefile.inc A src/mainboard/gigabyte/ga-z170x-gaming7/acpi/dptf.asl A src/mainboard/gigabyte/ga-z170x-gaming7/acpi/ec.asl A src/mainboard/gigabyte/ga-z170x-gaming7/acpi/mainboard.asl A src/mainboard/gigabyte/ga-z170x-gaming7/acpi/superio.asl A src/mainboard/gigabyte/ga-z170x-gaming7/board_info.txt A src/mainboard/gigabyte/ga-z170x-gaming7/cmos.default A src/mainboard/gigabyte/ga-z170x-gaming7/cmos.layout A src/mainboard/gigabyte/ga-z170x-gaming7/data.vbt A src/mainboard/gigabyte/ga-z170x-gaming7/devicetree.cb A src/mainboard/gigabyte/ga-z170x-gaming7/dsdt.asl A src/mainboard/gigabyte/ga-z170x-gaming7/gma-mainboard.ads A src/mainboard/gigabyte/ga-z170x-gaming7/gpio.c A src/mainboard/gigabyte/ga-z170x-gaming7/hda_verb.c A src/mainboard/gigabyte/ga-z170x-gaming7/ramstage.c A src/mainboard/gigabyte/ga-z170x-gaming7/romstage.c 18 files changed, 1,124 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/20/38920/12
Hello build bot (Jenkins), Patrick Georgi, Martin Roth, Angel Pons,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/38920
to look at the new patch set (#13).
Change subject: [WIP] mb/gigabyte: Add Gigabyte Z170X-Gaming 7 ......................................................................
[WIP] mb/gigabyte: Add Gigabyte Z170X-Gaming 7
At the current state of this commit the board does not go beyond ramstage.
The board has Boot guard enabled but is still in manufacturing mode. As far as the intel tools guide me there is no key burned yet.
Change-Id: Ib2c69bddd22cbd8f797dbb57370a4d8e5afa63bc Signed-off-by: Christoph Pomaska coreboot@slrie.de --- A src/mainboard/gigabyte/ga-z170x-gaming7/Kconfig A src/mainboard/gigabyte/ga-z170x-gaming7/Kconfig.name A src/mainboard/gigabyte/ga-z170x-gaming7/Makefile.inc A src/mainboard/gigabyte/ga-z170x-gaming7/acpi/dptf.asl A src/mainboard/gigabyte/ga-z170x-gaming7/acpi/ec.asl A src/mainboard/gigabyte/ga-z170x-gaming7/acpi/mainboard.asl A src/mainboard/gigabyte/ga-z170x-gaming7/acpi/superio.asl A src/mainboard/gigabyte/ga-z170x-gaming7/board_info.txt A src/mainboard/gigabyte/ga-z170x-gaming7/cmos.default A src/mainboard/gigabyte/ga-z170x-gaming7/cmos.layout A src/mainboard/gigabyte/ga-z170x-gaming7/data.vbt A src/mainboard/gigabyte/ga-z170x-gaming7/devicetree.cb A src/mainboard/gigabyte/ga-z170x-gaming7/dsdt.asl A src/mainboard/gigabyte/ga-z170x-gaming7/gma-mainboard.ads A src/mainboard/gigabyte/ga-z170x-gaming7/gpio.c A src/mainboard/gigabyte/ga-z170x-gaming7/hda_verb.c A src/mainboard/gigabyte/ga-z170x-gaming7/ramstage.c A src/mainboard/gigabyte/ga-z170x-gaming7/romstage.c 18 files changed, 1,124 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/20/38920/13
Christoph Pomaska has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38920 )
Change subject: [WIP] mb/gigabyte: Add Gigabyte Z170X-Gaming 7 ......................................................................
Patch Set 13:
(1 comment)
https://review.coreboot.org/c/coreboot/+/38920/9/src/mainboard/gigabyte/ga-z... File src/mainboard/gigabyte/ga-z170x-gaming7/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/38920/9/src/mainboard/gigabyte/ga-z... PS9, Line 354: end
one tab too much (is the end of "chip superio/ite/it8728f")
Done
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38920 )
Change subject: [WIP] mb/gigabyte: Add Gigabyte Z170X-Gaming 7 ......................................................................
Patch Set 13:
(9 comments)
https://review.coreboot.org/c/coreboot/+/38920/13/src/mainboard/gigabyte/ga-... File src/mainboard/gigabyte/ga-z170x-gaming7/acpi/dptf.asl:
PS13: /* SPDX-License-Identifier: GPL-2.0-only */ /* This file is part of the coreboot project. */
https://review.coreboot.org/c/coreboot/+/38920/13/src/mainboard/gigabyte/ga-... File src/mainboard/gigabyte/ga-z170x-gaming7/cmos.layout:
PS13: ## SPDX-License-Identifier: GPL-2.0-only ## This file is part of the coreboot project.
https://review.coreboot.org/c/coreboot/+/38920/13/src/mainboard/gigabyte/ga-... File src/mainboard/gigabyte/ga-z170x-gaming7/devicetree.cb:
PS13: ## SPDX-License-Identifier: GPL-2.0-only ## This file is part of the coreboot project.
https://review.coreboot.org/c/coreboot/+/38920/13/src/mainboard/gigabyte/ga-... PS13, Line 43: # Enable DPTF : register "dptf_enable" = "1" Disable DPTF
https://review.coreboot.org/c/coreboot/+/38920/13/src/mainboard/gigabyte/ga-... PS13, Line 53: Display_PEG Why? No onboard video?
https://review.coreboot.org/c/coreboot/+/38920/13/src/mainboard/gigabyte/ga-... File src/mainboard/gigabyte/ga-z170x-gaming7/dsdt.asl:
https://review.coreboot.org/c/coreboot/+/38920/13/src/mainboard/gigabyte/ga-... PS13, Line 34: // CPU No need for this
https://review.coreboot.org/c/coreboot/+/38920/13/src/mainboard/gigabyte/ga-... PS13, Line 40: /* Image processing unit */ : #include <soc/intel/skylake/acpi/ipu.asl> Nope
https://review.coreboot.org/c/coreboot/+/38920/13/src/mainboard/gigabyte/ga-... PS13, Line 46: // Dynamic Platform Thermal Framework : #include "acpi/dptf.asl" Not needed for now
https://review.coreboot.org/c/coreboot/+/38920/13/src/mainboard/gigabyte/ga-... File src/mainboard/gigabyte/ga-z170x-gaming7/gma-mainboard.ads:
https://review.coreboot.org/c/coreboot/+/38920/13/src/mainboard/gigabyte/ga-... PS13, Line 29: DP2, -- The board's HDMI port You need HDMI1 and HDMI2
Christoph Pomaska has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38920 )
Change subject: [WIP] mb/gigabyte: Add Gigabyte Z170X-Gaming 7 ......................................................................
Patch Set 13:
(2 comments)
https://review.coreboot.org/c/coreboot/+/38920/13/src/mainboard/gigabyte/ga-... File src/mainboard/gigabyte/ga-z170x-gaming7/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/38920/13/src/mainboard/gigabyte/ga-... PS13, Line 43: # Enable DPTF : register "dptf_enable" = "1"
Disable DPTF
Done
https://review.coreboot.org/c/coreboot/+/38920/13/src/mainboard/gigabyte/ga-... PS13, Line 53: Display_PEG
Why? No onboard video?
Couldnt find any entries that give another sample on what to put into that field so I just removed it entirely.
Maxim Polyakov has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38920 )
Change subject: [WIP] mb/gigabyte: Add Gigabyte Z170X-Gaming 7 ......................................................................
Patch Set 13:
(5 comments)
https://review.coreboot.org/c/coreboot/+/38920/13/src/mainboard/gigabyte/ga-... File src/mainboard/gigabyte/ga-z170x-gaming7/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/38920/13/src/mainboard/gigabyte/ga-... PS13, Line 35: @0x280-0x2ff Please correct this I/O range in the comment and add here all the ranges that you use.
https://review.coreboot.org/c/coreboot/+/38920/13/src/mainboard/gigabyte/ga-... PS13, Line 43: # Enable DPTF : register "dptf_enable" = "1"
Done
Why should this be disabled?
https://review.coreboot.org/c/coreboot/+/38920/13/src/mainboard/gigabyte/ga-... PS13, Line 53: Display_PEG
Couldnt find any entries that give another sample on what to put into that field so I just removed i […]
Display_PEG means that if you use an external graphics card on your board and it is inserted into the PEG slot, the video will be output through it. If you disconnect the graphics card, the video will be output through IGD.
This option sets only priority, however, if you set Display_IGD here, only this device will be used, regardless of the external gfx.
https://review.coreboot.org/c/coreboot/+/38920/13/src/mainboard/gigabyte/ga-... PS13, Line 243: Root port 7(x1) I see much more PCIe slots on the "Z170X-Gaming 7" motherboard (https://thunderbolttechnology.net/sites/default/files/imagecache/product-det...). Will you add them later?
https://review.coreboot.org/c/coreboot/+/38920/13/src/mainboard/gigabyte/ga-... File src/mainboard/gigabyte/ga-z170x-gaming7/gma-mainboard.ads:
https://review.coreboot.org/c/coreboot/+/38920/13/src/mainboard/gigabyte/ga-... PS13, Line 29: DP2, -- The board's HDMI port
You need HDMI1 and HDMI2
One of them is DP. https://www.gigabyte.com/FileUpload/Product/2/5481/20150722181813_src.png
Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38920 )
Change subject: [WIP] mb/gigabyte: Add Gigabyte Z170X-Gaming 7 ......................................................................
Patch Set 13:
(2 comments)
https://review.coreboot.org/c/coreboot/+/38920/13/src/mainboard/gigabyte/ga-... File src/mainboard/gigabyte/ga-z170x-gaming7/Kconfig:
https://review.coreboot.org/c/coreboot/+/38920/13/src/mainboard/gigabyte/ga-... PS13, Line 17: select FSP_USE_REPO Remove, since this is enabled by default.
https://review.coreboot.org/c/coreboot/+/38920/13/src/mainboard/gigabyte/ga-... PS13, Line 31: config MAX_CPUS : int : default 8 Useless, since 8 is the default.
Christoph Pomaska has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38920 )
Change subject: [WIP] mb/gigabyte: Add Gigabyte Z170X-Gaming 7 ......................................................................
Patch Set 13:
(1 comment)
https://review.coreboot.org/c/coreboot/+/38920/13/src/mainboard/gigabyte/ga-... File src/mainboard/gigabyte/ga-z170x-gaming7/gma-mainboard.ads:
https://review.coreboot.org/c/coreboot/+/38920/13/src/mainboard/gigabyte/ga-... PS13, Line 29: DP2, -- The board's HDMI port
One of them is DP. […]
in vendor firmware under linux they both showed up as DP output for some reason, thats why I did it like that.
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38920 )
Change subject: [WIP] mb/gigabyte: Add Gigabyte Z170X-Gaming 7 ......................................................................
Patch Set 13:
(3 comments)
https://review.coreboot.org/c/coreboot/+/38920/13/src/mainboard/gigabyte/ga-... File src/mainboard/gigabyte/ga-z170x-gaming7/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/38920/13/src/mainboard/gigabyte/ga-... PS13, Line 43: # Enable DPTF : register "dptf_enable" = "1"
Why should this be disabled?
DPTF support can be added once the board boots (I don't think it's really useful on a desktop anyway)
https://review.coreboot.org/c/coreboot/+/38920/13/src/mainboard/gigabyte/ga-... PS13, Line 53: Display_PEG
Display_PEG means that if you use an external graphics card on your board and it is inserted into th […]
Uh, then this should indeed be Display_PEG
https://review.coreboot.org/c/coreboot/+/38920/13/src/mainboard/gigabyte/ga-... File src/mainboard/gigabyte/ga-z170x-gaming7/gma-mainboard.ads:
https://review.coreboot.org/c/coreboot/+/38920/13/src/mainboard/gigabyte/ga-... PS13, Line 29: DP2, -- The board's HDMI port
in vendor firmware under linux they both showed up as DP output for some reason, thats why I did it […]
@Maxim the passive DP-to-HDMI converters need HDMI to be enabled here.
Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38920 )
Change subject: [WIP] mb/gigabyte: Add Gigabyte Z170X-Gaming 7 ......................................................................
Patch Set 13:
(1 comment)
https://review.coreboot.org/c/coreboot/+/38920/13/src/mainboard/gigabyte/ga-... File src/mainboard/gigabyte/ga-z170x-gaming7/gma-mainboard.ads:
https://review.coreboot.org/c/coreboot/+/38920/13/src/mainboard/gigabyte/ga-... PS13, Line 29: DP2, -- The board's HDMI port
@Maxim the passive DP-to-HDMI converters need HDMI to be enabled here.
It's advertised as HDMI 2.0, Intel can't do it so there will be an active converter on DP2.
If a passive adapter can be used without trying is hard to tell. They'd have to have the GMBUS pins connected. The VBT can give a hint, though. It has flags for the connection types per port.
Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38920 )
Change subject: [WIP] mb/gigabyte: Add Gigabyte Z170X-Gaming 7 ......................................................................
Patch Set 13:
(1 comment)
https://review.coreboot.org/c/coreboot/+/38920/13/src/mainboard/gigabyte/ga-... File src/mainboard/gigabyte/ga-z170x-gaming7/gma-mainboard.ads:
https://review.coreboot.org/c/coreboot/+/38920/13/src/mainboard/gigabyte/ga-... PS13, Line 29: DP2, -- The board's HDMI port
If a passive adapter can be used without trying is hard to tell. They'd have to have the GMBUS pins connected. The VBT can give a hint, though. It has flags for the connection types per port.
That ^ was for DP1 (just to be clear).
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38920 )
Change subject: [WIP] mb/gigabyte: Add Gigabyte Z170X-Gaming 7 ......................................................................
Patch Set 13:
(1 comment)
https://review.coreboot.org/c/coreboot/+/38920/13/src/mainboard/gigabyte/ga-... File src/mainboard/gigabyte/ga-z170x-gaming7/gma-mainboard.ads:
https://review.coreboot.org/c/coreboot/+/38920/13/src/mainboard/gigabyte/ga-... PS13, Line 29: DP2, -- The board's HDMI port
If a passive adapter can be used without trying is hard to tell. They'd have to have the […]
Wait, I have the schematics, why am I wasting my time not checking them? So, they say:
DDI1 => DP connector DDI2 => MCDP2800 IC => HDMI connector DDI3 => DSL6540 Alpine Ridge
As Nico said, there is an active DP-to-HDMI converter on DP2. However, DP1 could also work with a passive adapter (although not HDMI 2.0). The schematics mention that it is DP + HDMI.
Also, don't forget about the TBT controller! It probably doesn't work, but it should be enabled.
Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38920 )
Change subject: [WIP] mb/gigabyte: Add Gigabyte Z170X-Gaming 7 ......................................................................
Patch Set 13:
(1 comment)
https://review.coreboot.org/c/coreboot/+/38920/13/src/mainboard/gigabyte/ga-... File src/mainboard/gigabyte/ga-z170x-gaming7/gma-mainboard.ads:
https://review.coreboot.org/c/coreboot/+/38920/13/src/mainboard/gigabyte/ga-... PS13, Line 29: DP2, -- The board's HDMI port
Wait, I have the schematics, why am I wasting my time not checking them? So, they say: […]
Anything about DDPB_CTRLCTL/_CTRLDATA?
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38920 )
Change subject: [WIP] mb/gigabyte: Add Gigabyte Z170X-Gaming 7 ......................................................................
Patch Set 13:
(1 comment)
https://review.coreboot.org/c/coreboot/+/38920/13/src/mainboard/gigabyte/ga-... File src/mainboard/gigabyte/ga-z170x-gaming7/gma-mainboard.ads:
https://review.coreboot.org/c/coreboot/+/38920/13/src/mainboard/gigabyte/ga-... PS13, Line 29: DP2, -- The board's HDMI port
Anything about DDPB_CTRLCTL/_CTRLDATA?
They are pulled high with two resistors, and that's it.
Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38920 )
Change subject: [WIP] mb/gigabyte: Add Gigabyte Z170X-Gaming 7 ......................................................................
Patch Set 13:
(18 comments)
https://review.coreboot.org/c/coreboot/+/38920/13/src/mainboard/gigabyte/ga-... File src/mainboard/gigabyte/ga-z170x-gaming7/Kconfig:
https://review.coreboot.org/c/coreboot/+/38920/13/src/mainboard/gigabyte/ga-... PS13, Line 5: select BOARD_ROMSIZE_KB_16384 : select HAVE_ACPI_RESUME : select HAVE_ACPI_TABLES : select HAVE_OPTION_TABLE : select HAVE_CMOS_DEFAULT : select INTEL_GMA_HAVE_VBT : select INTEL_INT15 : select SOC_INTEL_KABYLAKE : select SKYLAKE_SOC_PCH_H : select MAINBOARD_HAS_LIBGFXINIT : select SUPERIO_ITE_IT8728F # board has actually IT8628E : select MAINBOARD_USES_IFD_GBE_REGION Reorder alphabetically
https://review.coreboot.org/c/coreboot/+/38920/13/src/mainboard/gigabyte/ga-... File src/mainboard/gigabyte/ga-z170x-gaming7/acpi/dptf.asl:
PS13:
/* SPDX-License-Identifier: GPL-2.0-only */ […]
Done
https://review.coreboot.org/c/coreboot/+/38920/13/src/mainboard/gigabyte/ga-... PS13, Line 1: /* : * This file is part of the coreboot project. : * : * Copyright (C) 2014 Google Inc. : * Copyright (C) 2015 Intel Corporation. : * Copyright (C) 2019 Maxim Polyakov max.senia.poliak@gmail.com : * : * This program is free software; you can redistribute it and/or modify : * it under the terms of the GNU General Public License as published by : * the Free Software Foundation; version 2 of the License. : * : * This program is distributed in the hope that it will be useful, : * but WITHOUT ANY WARRANTY; without even the implied warranty of : * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the : * GNU General Public License for more details. : */ Replace with .. /* SPDX-License-Identifier: GPL-2.0-only */
https://review.coreboot.org/c/coreboot/+/38920/13/src/mainboard/gigabyte/ga-... File src/mainboard/gigabyte/ga-z170x-gaming7/board_info.txt:
https://review.coreboot.org/c/coreboot/+/38920/13/src/mainboard/gigabyte/ga-... PS13, Line 2: Board URL: https://www.gigabyte.com/Motherboard/GA-Z170X-Gaming-7-rev-10 Add these .. Vendor name: Gigabyte Board name: GA Z170X Gaming 7 rev. 1.0
https://review.coreboot.org/c/coreboot/+/38920/13/src/mainboard/gigabyte/ga-... File src/mainboard/gigabyte/ga-z170x-gaming7/cmos.layout:
PS13:
## SPDX-License-Identifier: GPL-2.0-only […]
Done
https://review.coreboot.org/c/coreboot/+/38920/13/src/mainboard/gigabyte/ga-... PS13, Line 1: ## : ## This file is part of the coreboot project. : ## : ## Copyright (C) 2007-2008 coresystems GmbH : ## Copyright (C) 2016 Intel Corporation. : ## : ## This program is free software; you can redistribute it and/or modify : ## it under the terms of the GNU General Public License as published by : ## the Free Software Foundation; version 2 of the License. : ## : ## This program is distributed in the hope that it will be useful, : ## but WITHOUT ANY WARRANTY; without even the implied warranty of : ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the : ## GNU General Public License for more details. : ## Replace with .. GA-Z170X-Gaming-7-rev-10
https://review.coreboot.org/c/coreboot/+/38920/13/src/mainboard/gigabyte/ga-... File src/mainboard/gigabyte/ga-z170x-gaming7/devicetree.cb:
PS13:
## SPDX-License-Identifier: GPL-2.0-only […]
Done
https://review.coreboot.org/c/coreboot/+/38920/13/src/mainboard/gigabyte/ga-... PS13, Line 19: register "deep_s3_enable_ac" = "0" : register "deep_s3_enable_dc" = "0" : register "deep_s5_enable_ac" = "0" : register "deep_s5_enable_dc" = "0" Remove, because all 0
https://review.coreboot.org/c/coreboot/+/38920/13/src/mainboard/gigabyte/ga-... PS13, Line 267: device domain 0 on Add the following below this line .. subsystemid 0x1849 0x1912 inherit and replace every occurrence of .. subsystemid 0x1849 0x1912
https://review.coreboot.org/c/coreboot/+/38920/13/src/mainboard/gigabyte/ga-... File src/mainboard/gigabyte/ga-z170x-gaming7/dsdt.asl:
https://review.coreboot.org/c/coreboot/+/38920/13/src/mainboard/gigabyte/ga-... PS13, Line 1: /* : * This file is part of the coreboot project. : * : * Copyright (C) 2007-2009 coresystems GmbH : * Copyright (C) 2015 Google Inc. : * Copyright (C) 2016 Intel Corporation : * Copyright (C) 2019 Maxim Polyakov max.senia.poliak@gmail.com : * : * This program is free software; you can redistribute it and/or modify : * it under the terms of the GNU General Public License as published by : * the Free Software Foundation; version 2 of the License. : * : * This program is distributed in the hope that it will be useful, : * but WITHOUT ANY WARRANTY; without even the implied warranty of : * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the : * GNU General Public License for more details. : */ Replace with .. /* SPDX-License-Identifier: GPL-2.0-only */
https://review.coreboot.org/c/coreboot/+/38920/13/src/mainboard/gigabyte/ga-... PS13, Line 23: 0x02 Replace 0x02 by ACPI_DSDT_REV_2
https://review.coreboot.org/c/coreboot/+/38920/13/src/mainboard/gigabyte/ga-... PS13, Line 23: // DSDT revision: ACPI v2.0 and up Remove
https://review.coreboot.org/c/coreboot/+/38920/13/src/mainboard/gigabyte/ga-... File src/mainboard/gigabyte/ga-z170x-gaming7/gpio.c:
https://review.coreboot.org/c/coreboot/+/38920/13/src/mainboard/gigabyte/ga-... PS13, Line 1: /* : * This file is part of the coreboot project. : * : * This program is free software; you can redistribute it and/or : * modify it under the terms of the GNU General Public License as : * published by the Free Software Foundation; version 2 of : * the License. : * : * This program is distributed in the hope that it will be useful, : * but WITHOUT ANY WARRANTY; without even the implied warranty of : * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the : * GNU General Public License for more details. : */ Replace with .. /* SPDX-License-Identifier: GPL-2.0-only */
https://review.coreboot.org/c/coreboot/+/38920/13/src/mainboard/gigabyte/ga-... PS13, Line 15: #ifndef CFG_GPIO_H : #define CFG_GPIO_H No guards necessary here
https://review.coreboot.org/c/coreboot/+/38920/13/src/mainboard/gigabyte/ga-... PS13, Line 265: #endif /* CFG_GPIO_H */ Remove
https://review.coreboot.org/c/coreboot/+/38920/13/src/mainboard/gigabyte/ga-... File src/mainboard/gigabyte/ga-z170x-gaming7/hda_verb.c:
https://review.coreboot.org/c/coreboot/+/38920/13/src/mainboard/gigabyte/ga-... PS13, Line 1: /* : * This file is part of the coreboot project. : * : * Copyright (C) 2019 Christoph Pomaska : * : * This program is free software; you can redistribute it and/or modify : * it under the terms of the GNU General Public License as published by : * the Free Software Foundation; version 2 of the License. : * : * This program is distributed in the hope that it will be useful, : * but WITHOUT ANY WARRANTY; without even the implied warranty of : * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the : * GNU General Public License for more details. : */ Replace with .. /* SPDX-License-Identifier: GPL-2.0-only */
https://review.coreboot.org/c/coreboot/+/38920/13/src/mainboard/gigabyte/ga-... File src/mainboard/gigabyte/ga-z170x-gaming7/ramstage.c:
https://review.coreboot.org/c/coreboot/+/38920/13/src/mainboard/gigabyte/ga-... PS13, Line 1: /* : * This file is part of the coreboot project. : * : * Copyright (C) 2016 Intel Corporation : * Copyright (C) 2019 Maxim Polyakov max.senia.poliak@gmail.com : * : * This program is free software; you can redistribute it and/or modify : * it under the terms of the GNU General Public License as published by : * the Free Software Foundation; version 2 of the License. : * : * This program is distributed in the hope that it will be useful, : * but WITHOUT ANY WARRANTY; without even the implied warranty of : * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the : * GNU General Public License for more details. : */ Replace with .. /* SPDX-License-Identifier: GPL-2.0-only */
https://review.coreboot.org/c/coreboot/+/38920/13/src/mainboard/gigabyte/ga-... File src/mainboard/gigabyte/ga-z170x-gaming7/romstage.c:
https://review.coreboot.org/c/coreboot/+/38920/13/src/mainboard/gigabyte/ga-... PS13, Line 1: /* : * This file is part of the coreboot project. : * : * Copyright (C) 2016 Intel Corporation. : * Copyright (C) 2019 Maxim Polyakov max.senia.poliak@gmail.com : * : * This program is free software; you can redistribute it and/or modify : * it under the terms of the GNU General Public License as published by : * the Free Software Foundation; version 2 of the License. : * : * This program is distributed in the hope that it will be useful, : * but WITHOUT ANY WARRANTY; without even the implied warranty of : * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the : * GNU General Public License for more details. : */ Replace with .. /* SPDX-License-Identifier: GPL-2.0-only */
Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38920 )
Change subject: [WIP] mb/gigabyte: Add Gigabyte Z170X-Gaming 7 ......................................................................
Patch Set 13:
(8 comments)
These changes make your mainboard using the variant mechanism, but I suggest you get the other changes done first.
https://review.coreboot.org/c/coreboot/+/38920/13/src/mainboard/gigabyte/ga-... File src/mainboard/gigabyte/ga-z170x-gaming7/Kconfig:
https://review.coreboot.org/c/coreboot/+/38920/13/src/mainboard/gigabyte/ga-... PS13, Line 18: Add this config DEVICETREE string default "variant/$(VARIANT_DIR)/devicetree.cb"
https://review.coreboot.org/c/coreboot/+/38920/13/src/mainboard/gigabyte/ga-... PS13, Line 26: Add this config VARIANT_DIR string default "ga-z170x-gaming7" if BOARD_GIGABYTE_GA_Z170X_GAMING_7
and create this directory variant/ga-z170x-gaming7
https://review.coreboot.org/c/coreboot/+/38920/13/src/mainboard/gigabyte/ga-... File src/mainboard/gigabyte/ga-z170x-gaming7/Makefile.inc:
https://review.coreboot.org/c/coreboot/+/38920/13/src/mainboard/gigabyte/ga-... PS13, Line 18: hda_verb.c Replace with .. variant/$(VARIANT_DIR)/hda_verb.c
https://review.coreboot.org/c/coreboot/+/38920/13/src/mainboard/gigabyte/ga-... PS13, Line 19: gma-mainboard.ads Replace with .. variant/$(VARIANT_DIR)/gma-mainboard.ads
https://review.coreboot.org/c/coreboot/+/38920/13/src/mainboard/gigabyte/ga-... File src/mainboard/gigabyte/ga-z170x-gaming7/devicetree.cb:
PS13: Move this file to variant/ga-z170x-gaming7
https://review.coreboot.org/c/coreboot/+/38920/13/src/mainboard/gigabyte/ga-... File src/mainboard/gigabyte/ga-z170x-gaming7/gma-mainboard.ads:
PS13: Move this file to variant/ga-z170x-gaming7
https://review.coreboot.org/c/coreboot/+/38920/13/src/mainboard/gigabyte/ga-... File src/mainboard/gigabyte/ga-z170x-gaming7/gpio.c:
PS13: Move this file to variant/ga-z170x-gaming7
https://review.coreboot.org/c/coreboot/+/38920/13/src/mainboard/gigabyte/ga-... File src/mainboard/gigabyte/ga-z170x-gaming7/hda_verb.c:
PS13: Move this file to variant/ga-z170x-gaming7
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38920 )
Change subject: [WIP] mb/gigabyte: Add Gigabyte Z170X-Gaming 7 ......................................................................
Patch Set 13:
Patch Set 13:
(8 comments)
These changes make your mainboard using the variant mechanism, but I suggest you get the other changes done first.
I'd prefer to not switch to variants until required. Without another board, there's no reference to discern what is variant-specific.
Hello Felix Singer, build bot (Jenkins), Patrick Georgi, Martin Roth, Angel Pons, Felix Held,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/38920
to look at the new patch set (#14).
Change subject: [WIP] mb/gigabyte: Add Gigabyte Z170X-Gaming 7 ......................................................................
[WIP] mb/gigabyte: Add Gigabyte Z170X-Gaming 7
At the current state of this commit the board does not go beyond romstage. (At least it does not brick the board though.)
The board has Boot guard enabled but is still in manufacturing mode. As far as the intel tools guide me there is no key burned yet.
Change-Id: Ib2c69bddd22cbd8f797dbb57370a4d8e5afa63bc Signed-off-by: Christoph Pomaska coreboot@slrie.de --- A src/mainboard/gigabyte/ga-z170x-gaming7/Kconfig A src/mainboard/gigabyte/ga-z170x-gaming7/Kconfig.name A src/mainboard/gigabyte/ga-z170x-gaming7/Makefile.inc A src/mainboard/gigabyte/ga-z170x-gaming7/acpi/ec.asl A src/mainboard/gigabyte/ga-z170x-gaming7/acpi/superio.asl A src/mainboard/gigabyte/ga-z170x-gaming7/board_info.txt A src/mainboard/gigabyte/ga-z170x-gaming7/bootblock.c A src/mainboard/gigabyte/ga-z170x-gaming7/cmos.default A src/mainboard/gigabyte/ga-z170x-gaming7/cmos.layout A src/mainboard/gigabyte/ga-z170x-gaming7/data.vbt A src/mainboard/gigabyte/ga-z170x-gaming7/devicetree.cb A src/mainboard/gigabyte/ga-z170x-gaming7/dsdt.asl A src/mainboard/gigabyte/ga-z170x-gaming7/gma-mainboard.ads A src/mainboard/gigabyte/ga-z170x-gaming7/gpio.c A src/mainboard/gigabyte/ga-z170x-gaming7/hda_verb.c A src/mainboard/gigabyte/ga-z170x-gaming7/include/mainboard/gpio.h A src/mainboard/gigabyte/ga-z170x-gaming7/ramstage.c A src/mainboard/gigabyte/ga-z170x-gaming7/romstage.c 18 files changed, 788 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/20/38920/14
Attention is currently required from: Angel Pons, Christoph Pomaska. Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38920 )
Change subject: [WIP] mb/gigabyte: Add Gigabyte Z170X-Gaming 7 ......................................................................
Patch Set 14:
(25 comments)
File src/mainboard/gigabyte/ga-z170x-gaming7/Kconfig:
https://review.coreboot.org/c/coreboot/+/38920/comment/ae720440_c1ec2d6c PS13, Line 5: select BOARD_ROMSIZE_KB_16384 : select HAVE_ACPI_RESUME : select HAVE_ACPI_TABLES : select HAVE_OPTION_TABLE : select HAVE_CMOS_DEFAULT : select INTEL_GMA_HAVE_VBT : select INTEL_INT15 : select SOC_INTEL_KABYLAKE : select SKYLAKE_SOC_PCH_H : select MAINBOARD_HAS_LIBGFXINIT : select SUPERIO_ITE_IT8728F # board has actually IT8628E : select MAINBOARD_USES_IFD_GBE_REGION
Reorder alphabetically
Done
https://review.coreboot.org/c/coreboot/+/38920/comment/60f39d8c_e979e449 PS13, Line 17: select FSP_USE_REPO
Remove, since this is enabled by default.
Done
https://review.coreboot.org/c/coreboot/+/38920/comment/31ace47d_62946998 PS13, Line 18:
Add this […]
Done
https://review.coreboot.org/c/coreboot/+/38920/comment/f9c99eca_7eb1d09a PS13, Line 26:
Add this […]
Done
File src/mainboard/gigabyte/ga-z170x-gaming7/Makefile.inc:
https://review.coreboot.org/c/coreboot/+/38920/comment/c5c7f2ca_22027301 PS13, Line 18: hda_verb.c
Replace with .. […]
Done
https://review.coreboot.org/c/coreboot/+/38920/comment/9f910611_353bff94 PS13, Line 19: gma-mainboard.ads
Replace with .. […]
Done
File src/mainboard/gigabyte/ga-z170x-gaming7/acpi/dptf.asl:
https://review.coreboot.org/c/coreboot/+/38920/comment/9bde58f3_a4e6a67d PS13, Line 1: /* : * This file is part of the coreboot project. : * : * Copyright (C) 2014 Google Inc. : * Copyright (C) 2015 Intel Corporation. : * Copyright (C) 2019 Maxim Polyakov max.senia.poliak@gmail.com : * : * This program is free software; you can redistribute it and/or modify : * it under the terms of the GNU General Public License as published by : * the Free Software Foundation; version 2 of the License. : * : * This program is distributed in the hope that it will be useful, : * but WITHOUT ANY WARRANTY; without even the implied warranty of : * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the : * GNU General Public License for more details. : */
Replace with .. […]
Done
File src/mainboard/gigabyte/ga-z170x-gaming7/devicetree.cb:
PS13:
Move this file to variant/ga-z170x-gaming7
Done
https://review.coreboot.org/c/coreboot/+/38920/comment/7ea53e04_0246e8fc PS13, Line 19: register "deep_s3_enable_ac" = "0" : register "deep_s3_enable_dc" = "0" : register "deep_s5_enable_ac" = "0" : register "deep_s5_enable_dc" = "0"
Remove, because all 0
Done
File src/mainboard/gigabyte/ga-z170x-gaming7/dsdt.asl:
https://review.coreboot.org/c/coreboot/+/38920/comment/824abe6e_e0910530 PS2, Line 34: // CPU
Just the comment or the include aswell?
Done
File src/mainboard/gigabyte/ga-z170x-gaming7/dsdt.asl:
https://review.coreboot.org/c/coreboot/+/38920/comment/4f5da9ff_c732a345 PS13, Line 1: /* : * This file is part of the coreboot project. : * : * Copyright (C) 2007-2009 coresystems GmbH : * Copyright (C) 2015 Google Inc. : * Copyright (C) 2016 Intel Corporation : * Copyright (C) 2019 Maxim Polyakov max.senia.poliak@gmail.com : * : * This program is free software; you can redistribute it and/or modify : * it under the terms of the GNU General Public License as published by : * the Free Software Foundation; version 2 of the License. : * : * This program is distributed in the hope that it will be useful, : * but WITHOUT ANY WARRANTY; without even the implied warranty of : * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the : * GNU General Public License for more details. : */
Replace with .. […]
Done
https://review.coreboot.org/c/coreboot/+/38920/comment/89626536_f5e6b9eb PS13, Line 23: // DSDT revision: ACPI v2.0 and up
Remove
Done
https://review.coreboot.org/c/coreboot/+/38920/comment/e4ec0df5_9e5324b5 PS13, Line 23: 0x02
Replace 0x02 by ACPI_DSDT_REV_2
Done
https://review.coreboot.org/c/coreboot/+/38920/comment/0bda88df_be45564e PS13, Line 34: // CPU
No need for this
Done
https://review.coreboot.org/c/coreboot/+/38920/comment/09a34978_17b52762 PS13, Line 40: /* Image processing unit */ : #include <soc/intel/skylake/acpi/ipu.asl>
Nope
Done
https://review.coreboot.org/c/coreboot/+/38920/comment/507f639f_a8218b68 PS13, Line 46: // Dynamic Platform Thermal Framework : #include "acpi/dptf.asl"
Not needed for now
Done
File src/mainboard/gigabyte/ga-z170x-gaming7/gma-mainboard.ads:
PS13:
Move this file to variant/ga-z170x-gaming7
Done
File src/mainboard/gigabyte/ga-z170x-gaming7/gpio.c:
PS13:
Move this file to variant/ga-z170x-gaming7
Done
https://review.coreboot.org/c/coreboot/+/38920/comment/14d4df7d_f4fe0121 PS13, Line 1: /* : * This file is part of the coreboot project. : * : * This program is free software; you can redistribute it and/or : * modify it under the terms of the GNU General Public License as : * published by the Free Software Foundation; version 2 of : * the License. : * : * This program is distributed in the hope that it will be useful, : * but WITHOUT ANY WARRANTY; without even the implied warranty of : * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the : * GNU General Public License for more details. : */
Replace with .. […]
Done
https://review.coreboot.org/c/coreboot/+/38920/comment/0f5d8982_1c29ce96 PS13, Line 15: #ifndef CFG_GPIO_H : #define CFG_GPIO_H
No guards necessary here
Done
https://review.coreboot.org/c/coreboot/+/38920/comment/b9fc83e5_6682e26f PS13, Line 265: #endif /* CFG_GPIO_H */
Remove
Done
File src/mainboard/gigabyte/ga-z170x-gaming7/hda_verb.c:
PS13:
Move this file to variant/ga-z170x-gaming7
Done
https://review.coreboot.org/c/coreboot/+/38920/comment/c8c49b8d_5beb2275 PS13, Line 1: /* : * This file is part of the coreboot project. : * : * Copyright (C) 2019 Christoph Pomaska : * : * This program is free software; you can redistribute it and/or modify : * it under the terms of the GNU General Public License as published by : * the Free Software Foundation; version 2 of the License. : * : * This program is distributed in the hope that it will be useful, : * but WITHOUT ANY WARRANTY; without even the implied warranty of : * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the : * GNU General Public License for more details. : */
Replace with .. […]
Done
File src/mainboard/gigabyte/ga-z170x-gaming7/ramstage.c:
https://review.coreboot.org/c/coreboot/+/38920/comment/f009283f_d81503da PS13, Line 1: /* : * This file is part of the coreboot project. : * : * Copyright (C) 2016 Intel Corporation : * Copyright (C) 2019 Maxim Polyakov max.senia.poliak@gmail.com : * : * This program is free software; you can redistribute it and/or modify : * it under the terms of the GNU General Public License as published by : * the Free Software Foundation; version 2 of the License. : * : * This program is distributed in the hope that it will be useful, : * but WITHOUT ANY WARRANTY; without even the implied warranty of : * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the : * GNU General Public License for more details. : */
Replace with .. […]
Done
File src/mainboard/gigabyte/ga-z170x-gaming7/romstage.c:
https://review.coreboot.org/c/coreboot/+/38920/comment/60f5ef91_0fbe2f1b PS13, Line 1: /* : * This file is part of the coreboot project. : * : * Copyright (C) 2016 Intel Corporation. : * Copyright (C) 2019 Maxim Polyakov max.senia.poliak@gmail.com : * : * This program is free software; you can redistribute it and/or modify : * it under the terms of the GNU General Public License as published by : * the Free Software Foundation; version 2 of the License. : * : * This program is distributed in the hope that it will be useful, : * but WITHOUT ANY WARRANTY; without even the implied warranty of : * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the : * GNU General Public License for more details. : */
Replace with .. […]
Done
Attention is currently required from: Felix Singer, Nico Huber, Maxim Polyakov, Angel Pons.
Christoph Pomaska has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38920 )
Change subject: [WIP] mb/gigabyte: Add Gigabyte Z170X-Gaming 7 ......................................................................
Patch Set 15:
(7 comments)
File src/mainboard/gigabyte/ga-z170x-gaming7/Kconfig:
https://review.coreboot.org/c/coreboot/+/38920/comment/d090dc0f_0877733b PS13, Line 31: config MAX_CPUS : int : default 8
Useless, since 8 is the default.
Done
File src/mainboard/gigabyte/ga-z170x-gaming7/board_info.txt:
https://review.coreboot.org/c/coreboot/+/38920/comment/476970d9_a8763266 PS13, Line 2: Board URL: https://www.gigabyte.com/Motherboard/GA-Z170X-Gaming-7-rev-10
Add these .. […]
Done
File src/mainboard/gigabyte/ga-z170x-gaming7/cmos.layout:
https://review.coreboot.org/c/coreboot/+/38920/comment/cd8db8ff_e48a08c1 PS13, Line 1: ## : ## This file is part of the coreboot project. : ## : ## Copyright (C) 2007-2008 coresystems GmbH : ## Copyright (C) 2016 Intel Corporation. : ## : ## This program is free software; you can redistribute it and/or modify : ## it under the terms of the GNU General Public License as published by : ## the Free Software Foundation; version 2 of the License. : ## : ## This program is distributed in the hope that it will be useful, : ## but WITHOUT ANY WARRANTY; without even the implied warranty of : ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the : ## GNU General Public License for more details. : ##
Replace with .. […]
Done
File src/mainboard/gigabyte/ga-z170x-gaming7/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/38920/comment/c7b687a7_4ce915ff PS13, Line 53: Display_PEG
Uh, then this should indeed be Display_PEG
Added it again.
https://review.coreboot.org/c/coreboot/+/38920/comment/f228f5bc_52a57bd4 PS13, Line 243: Root port 7(x1)
I see much more PCIe slots on the "Z170X-Gaming 7" motherboard (https://thunderbolttechnology. […]
Sure, but I'll try to make the board boot first.
https://review.coreboot.org/c/coreboot/+/38920/comment/9c2b30e8_4fe53242 PS13, Line 267: device domain 0 on
Add the following below this line .. […]
Done
File src/mainboard/gigabyte/ga-z170x-gaming7/gma-mainboard.ads:
https://review.coreboot.org/c/coreboot/+/38920/comment/2028d895_0a7a7863 PS13, Line 29: DP2, -- The board's HDMI port
They are pulled high with two resistors, and that's it.
Unfortunately I'm not sure what to conclude from here. My assumption would be that the approach to list them as DP is correct but that I'm still missing something for the passive DP-to-HDMI converter and the Thunderbolt controller.
What I take from here is that I have to connect a monitor via the USB-C/tbt port to check how it is recognized. Unfortunately I am missing the hardware (a monitor that I can connect to the tbt port directly) to check. The only adapters that I have most likely have their own converter, is that an issue? I'd figure that I'll postpone the thunderbolt controller for later until I have made progress in successfully booting the board.
Attention is currently required from: Felix Singer, Nico Huber, Maxim Polyakov, Angel Pons.
Hello Felix Singer, build bot (Jenkins), Martin L Roth, Angel Pons, Felix Held,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/38920
to look at the new patch set (#16).
Change subject: [WIP] mb/gigabyte: Add Gigabyte Z170X-Gaming 7 ......................................................................
[WIP] mb/gigabyte: Add Gigabyte Z170X-Gaming 7
At the current state of this commit the board does not go beyond romstage. (At least it does not brick the board though.)
The board has Boot guard enabled but is still in manufacturing mode. As far as the intel tools guide me there is no key burned yet.
Change-Id: Ib2c69bddd22cbd8f797dbb57370a4d8e5afa63bc Signed-off-by: Christoph Pomaska coreboot@slrie.de --- A src/mainboard/gigabyte/ga-z170x-gaming7/Kconfig A src/mainboard/gigabyte/ga-z170x-gaming7/Kconfig.name A src/mainboard/gigabyte/ga-z170x-gaming7/Makefile.inc A src/mainboard/gigabyte/ga-z170x-gaming7/acpi/ec.asl A src/mainboard/gigabyte/ga-z170x-gaming7/acpi/superio.asl A src/mainboard/gigabyte/ga-z170x-gaming7/board_info.txt A src/mainboard/gigabyte/ga-z170x-gaming7/bootblock.c A src/mainboard/gigabyte/ga-z170x-gaming7/cmos.default A src/mainboard/gigabyte/ga-z170x-gaming7/cmos.layout A src/mainboard/gigabyte/ga-z170x-gaming7/data.vbt A src/mainboard/gigabyte/ga-z170x-gaming7/devicetree.cb A src/mainboard/gigabyte/ga-z170x-gaming7/dsdt.asl A src/mainboard/gigabyte/ga-z170x-gaming7/gma-mainboard.ads A src/mainboard/gigabyte/ga-z170x-gaming7/gpio.c A src/mainboard/gigabyte/ga-z170x-gaming7/hda_verb.c A src/mainboard/gigabyte/ga-z170x-gaming7/include/mainboard/gpio.h A src/mainboard/gigabyte/ga-z170x-gaming7/ramstage.c A src/mainboard/gigabyte/ga-z170x-gaming7/romstage.c 18 files changed, 800 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/20/38920/16
Attention is currently required from: Nico Huber, Maxim Polyakov, Angel Pons, Christoph Pomaska.
Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38920 )
Change subject: [WIP] mb/gigabyte: Add Gigabyte Z170X-Gaming 7 ......................................................................
Patch Set 16:
(15 comments)
File src/mainboard/gigabyte/ga-z170x-gaming7/Kconfig:
PS16: ## SPDX-License-Identifier: GPL-2.0-or-later
File src/mainboard/gigabyte/ga-z170x-gaming7/Kconfig.name:
PS16: ## SPDX-License-Identifier: GPL-2.0-or-later
File src/mainboard/gigabyte/ga-z170x-gaming7/Makefile.inc:
PS16: ## SPDX-License-Identifier: GPL-2.0-or-later
File src/mainboard/gigabyte/ga-z170x-gaming7/acpi/ec.asl:
https://review.coreboot.org/c/coreboot/+/38920/comment/6f89fc15_c663ba48 PS16, Line 1: /* SPDX-License-Identifier: GPL-2.0-only */ /* SPDX-License-Identifier: GPL-2.0-or-later */
File src/mainboard/gigabyte/ga-z170x-gaming7/acpi/superio.asl:
https://review.coreboot.org/c/coreboot/+/38920/comment/f3cd98c6_ad6d2aae PS16, Line 1: /* SPDX-License-Identifier: GPL-2.0-only */ /* SPDX-License-Identifier: GPL-2.0-or-later */
File src/mainboard/gigabyte/ga-z170x-gaming7/bootblock.c:
https://review.coreboot.org/c/coreboot/+/38920/comment/6753b82f_1e5ca492 PS16, Line 1: /* SPDX-License-Identifier: GPL-2.0-only */ /* SPDX-License-Identifier: GPL-2.0-or-later */
File src/mainboard/gigabyte/ga-z170x-gaming7/cmos.layout:
https://review.coreboot.org/c/coreboot/+/38920/comment/218f1980_2bdf35bd PS16, Line 1: ## : ## This file is part of the coreboot project. : ## : ## Copyright (C) 2007-2008 coresystems GmbH : ## Copyright (C) 2016 Intel Corporation. : ## : ## This program is free software; you can redistribute it and/or modify : ## it under the terms of the GNU General Public License as published by : ## the Free Software Foundation; version 2 of the License. : ## : ## This program is distributed in the hope that it will be useful, : ## but WITHOUT ANY WARRANTY; without even the implied warranty of : ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the : ## GNU General Public License for more details. : ## GA-Z170X-Gaming-7-rev-10 ## SPDX-License-Identifier: GPL-2.0-or-later
File src/mainboard/gigabyte/ga-z170x-gaming7/devicetree.cb:
PS16: ## SPDX-License-Identifier: GPL-2.0-or-later
File src/mainboard/gigabyte/ga-z170x-gaming7/dsdt.asl:
https://review.coreboot.org/c/coreboot/+/38920/comment/2a25fb8c_dfe50276 PS16, Line 1: /* SPDX-License-Identifier: GPL-2.0-only */ /* SPDX-License-Identifier: GPL-2.0-or-later */
https://review.coreboot.org/c/coreboot/+/38920/comment/011d65d6_464548bf PS16, Line 10: // OEM revision Remove the comment
File src/mainboard/gigabyte/ga-z170x-gaming7/gpio.c:
https://review.coreboot.org/c/coreboot/+/38920/comment/e732b9d8_20c02792 PS16, Line 1: /* SPDX-License-Identifier: GPL-2.0-only */ /* SPDX-License-Identifier: GPL-2.0-or-later */
File src/mainboard/gigabyte/ga-z170x-gaming7/hda_verb.c:
https://review.coreboot.org/c/coreboot/+/38920/comment/19176a10_4c3f922a PS16, Line 1: /* SPDX-License-Identifier: GPL-2.0-only */ /* SPDX-License-Identifier: GPL-2.0-or-later */
File src/mainboard/gigabyte/ga-z170x-gaming7/include/mainboard/gpio.h:
https://review.coreboot.org/c/coreboot/+/38920/comment/ef073da5_b2cd2794 PS16, Line 1: /* SPDX-License-Identifier: GPL-2.0-only */ /* SPDX-License-Identifier: GPL-2.0-or-later */
File src/mainboard/gigabyte/ga-z170x-gaming7/ramstage.c:
https://review.coreboot.org/c/coreboot/+/38920/comment/10d2ad08_162080bc PS16, Line 1: /* SPDX-License-Identifier: GPL-2.0-only */ /* SPDX-License-Identifier: GPL-2.0-or-later */
File src/mainboard/gigabyte/ga-z170x-gaming7/romstage.c:
https://review.coreboot.org/c/coreboot/+/38920/comment/3edd8faf_19abae80 PS16, Line 1: /* SPDX-License-Identifier: GPL-2.0-only */ /* SPDX-License-Identifier: GPL-2.0-or-later */
Attention is currently required from: Nico Huber, Maxim Polyakov, Angel Pons, Christoph Pomaska.
Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38920 )
Change subject: [WIP] mb/gigabyte: Add Gigabyte Z170X-Gaming 7 ......................................................................
Patch Set 16:
(5 comments)
File src/mainboard/gigabyte/ga-z170x-gaming7/Kconfig:
https://review.coreboot.org/c/coreboot/+/38920/comment/5d4dfdd4_d6437d45 PS16, Line 19: string Remove data type
https://review.coreboot.org/c/coreboot/+/38920/comment/eaf1d7e6_983d9a05 PS16, Line 23: string Remove data type
https://review.coreboot.org/c/coreboot/+/38920/comment/104688de_2d506a6e PS16, Line 27: hex Remove data type
https://review.coreboot.org/c/coreboot/+/38920/comment/996501f2_81fc9be4 PS16, Line 31: int Remove data type
https://review.coreboot.org/c/coreboot/+/38920/comment/3f0a64bf_60f19053 PS16, Line 32: #DDR4 Remove comment
Attention is currently required from: Felix Singer, Nico Huber, Maxim Polyakov, Angel Pons.
Christoph Pomaska has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38920 )
Change subject: [WIP] mb/gigabyte: Add Gigabyte Z170X-Gaming 7 ......................................................................
Patch Set 16:
(15 comments)
File src/mainboard/gigabyte/ga-z170x-gaming7/Kconfig:
PS16:
## SPDX-License-Identifier: GPL-2. […]
Done
File src/mainboard/gigabyte/ga-z170x-gaming7/Kconfig.name:
PS16:
## SPDX-License-Identifier: GPL-2. […]
Done
File src/mainboard/gigabyte/ga-z170x-gaming7/Makefile.inc:
PS16:
## SPDX-License-Identifier: GPL-2. […]
Done
File src/mainboard/gigabyte/ga-z170x-gaming7/acpi/ec.asl:
https://review.coreboot.org/c/coreboot/+/38920/comment/ad369976_8b90d894 PS16, Line 1: /* SPDX-License-Identifier: GPL-2.0-only */
/* SPDX-License-Identifier: GPL-2. […]
Done
File src/mainboard/gigabyte/ga-z170x-gaming7/acpi/superio.asl:
https://review.coreboot.org/c/coreboot/+/38920/comment/cdff9623_2960e378 PS16, Line 1: /* SPDX-License-Identifier: GPL-2.0-only */
/* SPDX-License-Identifier: GPL-2. […]
Done
File src/mainboard/gigabyte/ga-z170x-gaming7/bootblock.c:
https://review.coreboot.org/c/coreboot/+/38920/comment/400c230f_95c2c9a7 PS16, Line 1: /* SPDX-License-Identifier: GPL-2.0-only */
/* SPDX-License-Identifier: GPL-2. […]
Done
File src/mainboard/gigabyte/ga-z170x-gaming7/cmos.layout:
https://review.coreboot.org/c/coreboot/+/38920/comment/b1163026_e4daf8f2 PS16, Line 1: ## : ## This file is part of the coreboot project. : ## : ## Copyright (C) 2007-2008 coresystems GmbH : ## Copyright (C) 2016 Intel Corporation. : ## : ## This program is free software; you can redistribute it and/or modify : ## it under the terms of the GNU General Public License as published by : ## the Free Software Foundation; version 2 of the License. : ## : ## This program is distributed in the hope that it will be useful, : ## but WITHOUT ANY WARRANTY; without even the implied warranty of : ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the : ## GNU General Public License for more details. : ## GA-Z170X-Gaming-7-rev-10
## SPDX-License-Identifier: GPL-2. […]
Done
File src/mainboard/gigabyte/ga-z170x-gaming7/devicetree.cb:
PS16:
## SPDX-License-Identifier: GPL-2. […]
Done
File src/mainboard/gigabyte/ga-z170x-gaming7/dsdt.asl:
https://review.coreboot.org/c/coreboot/+/38920/comment/6cb9c84a_e4556f47 PS16, Line 1: /* SPDX-License-Identifier: GPL-2.0-only */
/* SPDX-License-Identifier: GPL-2. […]
Done
https://review.coreboot.org/c/coreboot/+/38920/comment/e0024996_15212ec5 PS16, Line 10: // OEM revision
Remove the comment
Done
File src/mainboard/gigabyte/ga-z170x-gaming7/gpio.c:
https://review.coreboot.org/c/coreboot/+/38920/comment/9da09ce6_4e9cecba PS16, Line 1: /* SPDX-License-Identifier: GPL-2.0-only */
/* SPDX-License-Identifier: GPL-2. […]
Done
File src/mainboard/gigabyte/ga-z170x-gaming7/hda_verb.c:
https://review.coreboot.org/c/coreboot/+/38920/comment/7796bd24_004c8a5c PS16, Line 1: /* SPDX-License-Identifier: GPL-2.0-only */
/* SPDX-License-Identifier: GPL-2. […]
Done
File src/mainboard/gigabyte/ga-z170x-gaming7/include/mainboard/gpio.h:
https://review.coreboot.org/c/coreboot/+/38920/comment/ef569c57_fb59b4c0 PS16, Line 1: /* SPDX-License-Identifier: GPL-2.0-only */
/* SPDX-License-Identifier: GPL-2. […]
Done
File src/mainboard/gigabyte/ga-z170x-gaming7/ramstage.c:
https://review.coreboot.org/c/coreboot/+/38920/comment/5264f2bd_b031e5cf PS16, Line 1: /* SPDX-License-Identifier: GPL-2.0-only */
/* SPDX-License-Identifier: GPL-2. […]
Done
File src/mainboard/gigabyte/ga-z170x-gaming7/romstage.c:
https://review.coreboot.org/c/coreboot/+/38920/comment/6e977192_0687b882 PS16, Line 1: /* SPDX-License-Identifier: GPL-2.0-only */
/* SPDX-License-Identifier: GPL-2. […]
Done
Attention is currently required from: Felix Singer, Nico Huber, Maxim Polyakov, Angel Pons.
Christoph Pomaska has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38920 )
Change subject: [WIP] mb/gigabyte: Add Gigabyte Z170X-Gaming 7 ......................................................................
Patch Set 16:
(5 comments)
File src/mainboard/gigabyte/ga-z170x-gaming7/Kconfig:
https://review.coreboot.org/c/coreboot/+/38920/comment/8b28cb89_d85cf229 PS16, Line 19: string
Remove data type
Done
https://review.coreboot.org/c/coreboot/+/38920/comment/fac1177f_cb73341c PS16, Line 23: string
Remove data type
Done
https://review.coreboot.org/c/coreboot/+/38920/comment/fb36b145_4ffec4f9 PS16, Line 27: hex
Remove data type
Done
https://review.coreboot.org/c/coreboot/+/38920/comment/93c0583b_ab1604ea PS16, Line 31: int
Remove data type
Done
https://review.coreboot.org/c/coreboot/+/38920/comment/e2af93d4_7135638e PS16, Line 32: #DDR4
Remove comment
Done
Attention is currently required from: Felix Singer, Nico Huber, Maxim Polyakov, Angel Pons.
Hello Felix Singer, build bot (Jenkins), Martin L Roth, Angel Pons, Felix Held,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/38920
to look at the new patch set (#17).
Change subject: [WIP] mb/gigabyte: Add Gigabyte Z170X-Gaming 7 ......................................................................
[WIP] mb/gigabyte: Add Gigabyte Z170X-Gaming 7
At the current state of this commit the board does not go beyond romstage. (At least it does not brick the board though.)
The board has Boot guard enabled but is still in manufacturing mode. As far as the intel tools guide me there is no key burned yet.
Change-Id: Ib2c69bddd22cbd8f797dbb57370a4d8e5afa63bc Signed-off-by: Christoph Pomaska coreboot@slrie.de --- A src/mainboard/gigabyte/ga-z170x-gaming7/Kconfig A src/mainboard/gigabyte/ga-z170x-gaming7/Kconfig.name A src/mainboard/gigabyte/ga-z170x-gaming7/Makefile.inc A src/mainboard/gigabyte/ga-z170x-gaming7/acpi/ec.asl A src/mainboard/gigabyte/ga-z170x-gaming7/acpi/superio.asl A src/mainboard/gigabyte/ga-z170x-gaming7/board_info.txt A src/mainboard/gigabyte/ga-z170x-gaming7/bootblock.c A src/mainboard/gigabyte/ga-z170x-gaming7/cmos.default A src/mainboard/gigabyte/ga-z170x-gaming7/cmos.layout A src/mainboard/gigabyte/ga-z170x-gaming7/data.vbt A src/mainboard/gigabyte/ga-z170x-gaming7/devicetree.cb A src/mainboard/gigabyte/ga-z170x-gaming7/dsdt.asl A src/mainboard/gigabyte/ga-z170x-gaming7/gma-mainboard.ads A src/mainboard/gigabyte/ga-z170x-gaming7/gpio.c A src/mainboard/gigabyte/ga-z170x-gaming7/hda_verb.c A src/mainboard/gigabyte/ga-z170x-gaming7/include/mainboard/gpio.h A src/mainboard/gigabyte/ga-z170x-gaming7/ramstage.c A src/mainboard/gigabyte/ga-z170x-gaming7/romstage.c 18 files changed, 795 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/20/38920/17
Attention is currently required from: Nico Huber, Maxim Polyakov, Angel Pons, Christoph Pomaska.
Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38920 )
Change subject: [WIP] mb/gigabyte: Add Gigabyte Z170X-Gaming 7 ......................................................................
Patch Set 17:
(1 comment)
File src/mainboard/gigabyte/ga-z170x-gaming7/romstage.c:
https://review.coreboot.org/c/coreboot/+/38920/comment/17d09f4e_f3a3ad5a PS17, Line 7: static void mainboard_fill_rcomp_res_data(void *rcomp_ptr) : { : const u16 RcompResistor[3] = { 121, 75, 100 }; : memcpy(rcomp_ptr, RcompResistor, sizeof(RcompResistor)); : } : : static void mainboard_fill_rcomp_strength_data(void *rcomp_strength_ptr) : { : static const u16 RcompTarget[5] = { 60, 26, 20, 20, 26 }; : memcpy(rcomp_strength_ptr, RcompTarget, sizeof(RcompTarget)); : } See if any of these configurations work:
From intel/saddlebrook/spd/spd_util.c ``` RcompResistor[3] = { 121, 81, 100 }; RcompTarget[5] = { 100, 40, 20, 20, 26 }; ```
From intel/kblrvp/spd/spd_util.c ``` RcompResistor[3] = { 200, 81, 162 }; RcompTarget[5] = { 100, 40, 40, 23, 40 }; ```
Attention is currently required from: Felix Singer, Maxim Polyakov, Angel Pons, Christoph Pomaska.
Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38920 )
Change subject: [WIP] mb/gigabyte: Add Gigabyte Z170X-Gaming 7 ......................................................................
Patch Set 17:
(1 comment)
File src/mainboard/gigabyte/ga-z170x-gaming7/romstage.c:
https://review.coreboot.org/c/coreboot/+/38920/comment/7f4d2962_ec86b3ad PS17, Line 7: static void mainboard_fill_rcomp_res_data(void *rcomp_ptr) : { : const u16 RcompResistor[3] = { 121, 75, 100 }; : memcpy(rcomp_ptr, RcompResistor, sizeof(RcompResistor)); : } : : static void mainboard_fill_rcomp_strength_data(void *rcomp_strength_ptr) : { : static const u16 RcompTarget[5] = { 60, 26, 20, 20, 26 }; : memcpy(rcomp_strength_ptr, RcompTarget, sizeof(RcompTarget)); : }
See if any of these configurations work: […]
Anything wrong with the current numbers (I suggested them based on Intel docs). Also, why guess?
Attention is currently required from: Felix Singer, Maxim Polyakov, Angel Pons, Christoph Pomaska.
Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38920 )
Change subject: [WIP] mb/gigabyte: Add Gigabyte Z170X-Gaming 7 ......................................................................
Patch Set 17:
(1 comment)
File src/mainboard/gigabyte/ga-z170x-gaming7/gma-mainboard.ads:
https://review.coreboot.org/c/coreboot/+/38920/comment/1181c8ea_5a379c44 PS13, Line 29: DP2, -- The board's HDMI port
Unfortunately I'm not sure what to conclude from here. […]
HDMI1 would require DDPB_CTRLCTL/_CTRLDATA to be connected via a mux to the DP port. If Angel was right, that is not the case, so *no* HDMI1.
I'd say either
(DP1, DP2, others => Disabled)
or
(DP1, DP2, DP3, -- untested TBT connection others => Disabled)
Marking as resolved as the code already does the first thing.
Attention is currently required from: Felix Singer, Maxim Polyakov, Angel Pons, Christoph Pomaska.
Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38920 )
Change subject: [WIP] mb/gigabyte: Add Gigabyte Z170X-Gaming 7 ......................................................................
Patch Set 17:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/38920/comment/fc007d7c_04811591 PS17, Line 10: romstage. (At least it does not brick the board though.) Does it pass raminit?
Attention is currently required from: Felix Singer, Nico Huber, Maxim Polyakov, Christoph Pomaska.
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38920 )
Change subject: [WIP] mb/gigabyte: Add Gigabyte Z170X-Gaming 7 ......................................................................
Patch Set 17:
(3 comments)
File src/mainboard/gigabyte/ga-z170x-gaming7/gma-mainboard.ads:
https://review.coreboot.org/c/coreboot/+/38920/comment/36c9a7b4_b2632fbd PS13, Line 29: DP2, -- The board's HDMI port
HDMI1 would require DDPB_CTRLCTL/_CTRLDATA to be connected via a mux to the DP […]
DDPB_CTRL{CLK,DATA} are only connected to pull-up resistors, so no HDMI1: https://imgur.com/UWoon2Z.png
MCDP2800 is the MegaChips LSPCON. We use PCON mode in coreboot/libgfxinit, so no HDMI2.
Might be good to mention that DP3 for TBT is untested, otherwise looks good.
File src/mainboard/gigabyte/ga-z170x-gaming7/romstage.c:
https://review.coreboot.org/c/coreboot/+/38920/comment/da56ca94_3bb97890 PS17, Line 7: static void mainboard_fill_rcomp_res_data(void *rcomp_ptr) : { : const u16 RcompResistor[3] = { 121, 75, 100 }; : memcpy(rcomp_ptr, RcompResistor, sizeof(RcompResistor)); : } : : static void mainboard_fill_rcomp_strength_data(void *rcomp_strength_ptr) : { : static const u16 RcompTarget[5] = { 60, 26, 20, 20, 26 }; : memcpy(rcomp_strength_ptr, RcompTarget, sizeof(RcompTarget)); : }
Anything wrong with the current numbers (I suggested them based on Intel docs). […]
Felix, the values for Saddle Brook are for ULT with DDR4 (CB:38978 uses the same values) and the values in KBLRVP are only used for KBLRVP3, which is ULT with LPDDR3.
For Rcomp resistors, the values match those from hp/280_g2, which we actually confirmed by desoldering and measuring the three memory Rcomp resistors on an i5-6400 CPU.
As for Rcomp targets, they match the values for prodrive/hermes (which is Coffee Lake but has a very similar memory controller). hp/280_g2 has a different value for RdOdt (first value, it has 50 instead of 60) because it only supports one DIMM per channel, whereas prodrive/hermes and this board support two DIMMs per channel.
TL;DR: Current Rcomp values *are* correct.
https://review.coreboot.org/c/coreboot/+/38920/comment/372ec496_1699478d PS17, Line 29: mem_cfg->DqPinsInterleaved = 1; Add:
mem_cfg->CaVrefConfig = 2;
It's not super important (boards still boot fine with the wrong value), but it's correct as per schematics (channel A goes to DDR_VREF_CA, channel B goes to DDR1_VREF_DQ). See CB:57262 and https://review.coreboot.org/c/coreboot/+/52110/1..2//COMMIT_MSG#b9 for a very in-depth explanation of this setting.
TL;DR: schematics say you should use CaVrefConfig = 2.
-
Angel Pons (Code Review) -
Christoph Pomaska (Code Review)
-
Felix Singer (Code Review)
-
Maxim Polyakov (Code Review)
-
Nico Huber (Code Review)
-
Pavel Sayekat (Code Review)