Attention is currently required from: Felix Singer, Nico Huber, Maxim Polyakov, Christoph Pomaska.

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3 comments:

• File src/mainboard/gigabyte/ga-z170x-gaming7/gma-mainboard.ads:

  • Patch Set #13, Line 29: DP2, -- The board's HDMI port

    HDMI1 would require DDPB_CTRLCTL/_CTRLDATA to be connected via a mux to the DP […]

    DDPB_CTRL{CLK,DATA} are only connected to pull-up resistors, so no HDMI1: https://imgur.com/UWoon2Z.png

    MCDP2800 is the MegaChips LSPCON. We use PCON mode in coreboot/libgfxinit, so no HDMI2.

    Might be good to mention that DP3 for TBT is untested, otherwise looks good.

• File src/mainboard/gigabyte/ga-z170x-gaming7/romstage.c:

  • Patch Set #17, Line 7:

    static void mainboard_fill_rcomp_res_data(void *rcomp_ptr)
    {
    	const u16 RcompResistor[3] = { 121, 75, 100 };
    	memcpy(rcomp_ptr, RcompResistor, sizeof(RcompResistor));
    }
    
    static void mainboard_fill_rcomp_strength_data(void *rcomp_strength_ptr)
    {
    	static const u16 RcompTarget[5] = { 60, 26, 20, 20, 26 };
    	memcpy(rcomp_strength_ptr, RcompTarget, sizeof(RcompTarget));
    }
    

    Anything wrong with the current numbers (I suggested them based on Intel docs). […]

    Felix, the values for Saddle Brook are for ULT with DDR4 (CB:38978 uses the same values) and the values in KBLRVP are only used for KBLRVP3, which is ULT with LPDDR3.

    For Rcomp resistors, the values match those from hp/280_g2, which we actually confirmed by desoldering and measuring the three memory Rcomp resistors on an i5-6400 CPU.

    As for Rcomp targets, they match the values for prodrive/hermes (which is Coffee Lake but has a very similar memory controller). hp/280_g2 has a different value for RdOdt (first value, it has 50 instead of 60) because it only supports one DIMM per channel, whereas prodrive/hermes and this board support two DIMMs per channel.

    TL;DR: Current Rcomp values *are* correct.

  • Patch Set #17, Line 29: mem_cfg->DqPinsInterleaved = 1;

    Add:

     mem_cfg->CaVrefConfig = 2;

    It's not super important (boards still boot fine with the wrong value), but it's correct as per schematics (channel A goes to DDR_VREF_CA, channel B goes to DDR1_VREF_DQ). See CB:57262 and https://review.coreboot.org/c/coreboot/+/52110/1..2//COMMIT_MSG#b9 for a very in-depth explanation of this setting.

    TL;DR: schematics say you should use CaVrefConfig = 2.

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