Ricardo Ribalda has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46962 )
Change subject: mb/google/hatch/jinlon: Describe the privacy_gpio ......................................................................
mb/google/hatch/jinlon: Describe the privacy_gpio
Add information regarding the privacy pin on the overridetree and gpio.
Change-Id: Ifa628dda03f3f65976850aeabaf516f528a921b7 Signed-off-by: Ricardo Ribalda ribalda@chromium.org --- M src/mainboard/google/hatch/variants/jinlon/gpio.c M src/mainboard/google/hatch/variants/jinlon/overridetree.cb 2 files changed, 12 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/62/46962/1
diff --git a/src/mainboard/google/hatch/variants/jinlon/gpio.c b/src/mainboard/google/hatch/variants/jinlon/gpio.c index 88f0092..3b6a76f 100644 --- a/src/mainboard/google/hatch/variants/jinlon/gpio.c +++ b/src/mainboard/google/hatch/variants/jinlon/gpio.c @@ -18,6 +18,8 @@ * using this pin, expose this pin to driver. */ PAD_CFG_GPO(GPP_C15, 1, DEEP), + /* D4 : Camera Privacy Status */ + PAD_CFG_GPI(GPP_D4, NONE, DEEP), /* E0 : View Angle Management */ PAD_CFG_GPO(GPP_E0, 0, DEEP), /* F3 : MEM_STRAP_3 */ diff --git a/src/mainboard/google/hatch/variants/jinlon/overridetree.cb b/src/mainboard/google/hatch/variants/jinlon/overridetree.cb index fc3bb85..22cc5d3 100644 --- a/src/mainboard/google/hatch/variants/jinlon/overridetree.cb +++ b/src/mainboard/google/hatch/variants/jinlon/overridetree.cb @@ -80,6 +80,16 @@ device generic 0 on end end end # Integrated Graphics Device + device pci 14.0 on + chip drivers/usb/acpi + device usb 0.0 on + chip drivers/usb/acpi + register "privacy_gpio" = "ACPI_GPIO_INPUT_ACTIVE_LOW(GPP_D4)" + device usb 2.6 on end + end + end + end + end # USB xHCI device pci 15.0 on chip drivers/i2c/generic register "hid" = ""ELAN0000""
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46962 )
Change subject: mb/google/hatch/jinlon: Describe the privacy_gpio ......................................................................
Patch Set 1:
(1 comment)
https://review.coreboot.org/c/coreboot/+/46962/1/src/mainboard/google/hatch/... File src/mainboard/google/hatch/variants/jinlon/overridetree.cb:
https://review.coreboot.org/c/coreboot/+/46962/1/src/mainboard/google/hatch/... PS1, Line 86: chip drivers/usb/acpi why are there two nested `chip drivers/usb/acpi` lines?
Ricardo Ribalda has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46962 )
Change subject: mb/google/hatch/jinlon: Describe the privacy_gpio ......................................................................
Patch Set 1:
(1 comment)
https://review.coreboot.org/c/coreboot/+/46962/1/src/mainboard/google/hatch/... File src/mainboard/google/hatch/variants/jinlon/overridetree.cb:
https://review.coreboot.org/c/coreboot/+/46962/1/src/mainboard/google/hatch/... PS1, Line 86: chip drivers/usb/acpi
why are there two nested `chip drivers/usb/acpi` lines?
I tried removing the first
`chip drivers/usb/acpi`
and then the field is not created in the acpi table.
I think we need co have all the chip "headers" on the overridetree
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46962 )
Change subject: mb/google/hatch/jinlon: Describe the privacy_gpio ......................................................................
Patch Set 1: Code-Review+1
(1 comment)
https://review.coreboot.org/c/coreboot/+/46962/1/src/mainboard/google/hatch/... File src/mainboard/google/hatch/variants/jinlon/overridetree.cb:
https://review.coreboot.org/c/coreboot/+/46962/1/src/mainboard/google/hatch/... PS1, Line 86: chip drivers/usb/acpi
I tried removing the first […]
Ah, it probably placed the privacy_gpio on the `_SB.PCI0.XHCI.RHUB` scope instead of the USB port's scope.
Hello build bot (Jenkins), Furquan Shaikh, Angel Pons,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/46962
to look at the new patch set (#2).
Change subject: mb/google/hatch/jinlon: Describe the privacy_gpio ......................................................................
mb/google/hatch/jinlon: Describe the privacy_gpio
Add information regarding the privacy pin on the overridetree and gpio.
Change-Id: Ifa628dda03f3f65976850aeabaf516f528a921b7 Signed-off-by: Ricardo Ribalda ribalda@chromium.org --- M src/mainboard/google/hatch/variants/jinlon/gpio.c M src/mainboard/google/hatch/variants/jinlon/overridetree.cb 2 files changed, 10 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/62/46962/2
Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46962 )
Change subject: mb/google/hatch/jinlon: Describe the privacy_gpio ......................................................................
Patch Set 2:
(2 comments)
https://review.coreboot.org/c/coreboot/+/46962/1/src/mainboard/google/hatch/... File src/mainboard/google/hatch/variants/jinlon/overridetree.cb:
https://review.coreboot.org/c/coreboot/+/46962/1/src/mainboard/google/hatch/... PS1, Line 86: chip drivers/usb/acpi
Ah, it probably placed the privacy_gpio on the `_SB.PCI0.XHCI. […]
Yep, you need to keep the existing hierarchy (which has the RHUB under the controller)
https://review.coreboot.org/c/coreboot/+/46962/2/src/mainboard/google/hatch/... File src/mainboard/google/hatch/variants/jinlon/overridetree.cb:
https://review.coreboot.org/c/coreboot/+/46962/2/src/mainboard/google/hatch/... PS2, Line 86: ACPI_GPIO_INPUT_ACTIVE_LOW My (limited) understanding is that this is an IRQ, would a GpioInterrupt be more appropriate?
Ricardo Ribalda has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46962 )
Change subject: mb/google/hatch/jinlon: Describe the privacy_gpio ......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/c/coreboot/+/46962/2/src/mainboard/google/hatch/... File src/mainboard/google/hatch/variants/jinlon/overridetree.cb:
https://review.coreboot.org/c/coreboot/+/46962/2/src/mainboard/google/hatch/... PS2, Line 86: ACPI_GPIO_INPUT_ACTIVE_LOW
My (limited) understanding is that this is an IRQ, would a GpioInterrupt be more appropriate?
I though that too. but then I had a nice conversation with Andy Shevchenko. If you want to read an irq pin, you have to declare it as GpioIo(), not as GpioInt().
https://lore.kernel.org/linux-gpio/CAHp75Vd7D7gArrgAWJ-e=u-KeGiQ5Ouj94YGfRmL...
https://lore.kernel.org/linux-gpio/CAHp75VdZiOnQdUirEM1BG27kV=htNX95Ar6eJ8LA...
Also there is no way (and kernel upstream do not want) to define a GpioInt() as EDGE and BOTH and ACTIVE_LOW().
Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46962 )
Change subject: mb/google/hatch/jinlon: Describe the privacy_gpio ......................................................................
Patch Set 2:
(2 comments)
https://review.coreboot.org/c/coreboot/+/46962/2/src/mainboard/google/hatch/... File src/mainboard/google/hatch/variants/jinlon/gpio.c:
https://review.coreboot.org/c/coreboot/+/46962/2/src/mainboard/google/hatch/... PS2, Line 22: PAD_CFG_GPI Then shouldn't this be `PAD_CFG_GPI_INT(GPP_D4, NONE, PLTRST, EDGE_BOTH)` ? or does the kernel reconfigure the pad?
https://review.coreboot.org/c/coreboot/+/46962/2/src/mainboard/google/hatch/... File src/mainboard/google/hatch/variants/jinlon/overridetree.cb:
https://review.coreboot.org/c/coreboot/+/46962/2/src/mainboard/google/hatch/... PS2, Line 86: ACPI_GPIO_INPUT_ACTIVE_LOW
I though that too. but then I had a nice conversation with Andy Shevchenko. […]
Hm, I see, that's odd.
Hello build bot (Jenkins), Furquan Shaikh, Angel Pons,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/46962
to look at the new patch set (#3).
Change subject: mb/google/hatch/jinlon: Describe the privacy_gpio ......................................................................
mb/google/hatch/jinlon: Describe the privacy_gpio
Add information regarding the privacy pin on the overridetree and gpio.
Change-Id: Ifa628dda03f3f65976850aeabaf516f528a921b7 Signed-off-by: Ricardo Ribalda ribalda@chromium.org --- M src/mainboard/google/hatch/variants/jinlon/gpio.c M src/mainboard/google/hatch/variants/jinlon/overridetree.cb 2 files changed, 10 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/62/46962/3
Ricardo Ribalda has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46962 )
Change subject: mb/google/hatch/jinlon: Describe the privacy_gpio ......................................................................
Patch Set 3:
(1 comment)
https://review.coreboot.org/c/coreboot/+/46962/2/src/mainboard/google/hatch/... File src/mainboard/google/hatch/variants/jinlon/gpio.c:
https://review.coreboot.org/c/coreboot/+/46962/2/src/mainboard/google/hatch/... PS2, Line 22: PAD_CFG_GPI
Then shouldn't this be `PAD_CFG_GPI_INT(GPP_D4, NONE, PLTRST, EDGE_BOTH)` ? or does the kernel recon […]
Good catch!! For some reason I lost that change when moving from my chromeos test to review.
Thanks!
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46962 )
Change subject: mb/google/hatch/jinlon: Describe the privacy_gpio ......................................................................
Patch Set 3:
(1 comment)
https://review.coreboot.org/c/coreboot/+/46962/2/src/mainboard/google/hatch/... File src/mainboard/google/hatch/variants/jinlon/overridetree.cb:
https://review.coreboot.org/c/coreboot/+/46962/2/src/mainboard/google/hatch/... PS2, Line 86: ACPI_GPIO_INPUT_ACTIVE_LOW
Hm, I see, that's odd.
I think what you care about is reading the state of the signal when IRQ is triggered. And the driver wants to know the polarity because the signal could be active high or active low in hardware.
Wouldn't it make sense to apply the inversion at the pad and then use GpioInt() with both-edge trigger here? That will ensure - Signal is inverted at the pad rx and interrupt is triggered for both edges. And when the driver reads the state of the signal, it will always have to check for 1 instead of caring for the polarity.
Ricardo Ribalda has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46962 )
Change subject: mb/google/hatch/jinlon: Describe the privacy_gpio ......................................................................
Patch Set 3:
(1 comment)
https://review.coreboot.org/c/coreboot/+/46962/2/src/mainboard/google/hatch/... File src/mainboard/google/hatch/variants/jinlon/overridetree.cb:
https://review.coreboot.org/c/coreboot/+/46962/2/src/mainboard/google/hatch/... PS2, Line 86: ACPI_GPIO_INPUT_ACTIVE_LOW
I think what you care about is reading the state of the signal when IRQ is triggered. […]
I tried setting PAD_RX_POL(INVERT) on an EDGE_BOTH and it had no effect (check the attached patch). So it is either not possible, or I do not know how to it properly. (most likely the second :P )
Also by the conversation with Andy Shevchenko, seems that if you plan to read the value of a pin you should not set it as GpioInt(). https://lore.kernel.org/linux-gpio/CAHp75VdZiOnQdUirEM1BG27kV=htNX95Ar6eJ8LA...
I thought that gpiod_to_irq will not work unless it was a GpioInt() but it works fine. So in this case I will just convert it to that.
It's actually that gpio_to_irq() is solely for GPIOs which initially are not IRQs.
Could we say that doing gpiod_get_value() from a GpioInt() is always wrong?
But it's not wrong. Some cases simply make little or no sense, but in principal why not? Yes, it may be fragile or too much customized.
diff --git a/src/mainboard/google/hatch/variants/jinlon/gpio.c b/src/mainboard/google/hatch/variants/jinlon/gpio.c index 4029f062db..326e84d748 100644 --- a/src/mainboard/google/hatch/variants/jinlon/gpio.c +++ b/src/mainboard/google/hatch/variants/jinlon/gpio.c @@ -19,7 +19,7 @@ static const struct pad_config gpio_table[] = { */ PAD_CFG_GPO(GPP_C15, 1, DEEP), /* D4 : Camera Privacy Status */ - PAD_CFG_GPI_INT(GPP_D4, NONE, PLTRST, EDGE_BOTH), + PAD_CFG_GPI_INT_INVERTED(GPP_D4, NONE, PLTRST, EDGE_BOTH), /* E0 : View Angle Management */ PAD_CFG_GPO(GPP_E0, 0, DEEP), /* F3 : MEM_STRAP_3 */ diff --git a/src/soc/intel/common/block/include/intelblocks/gpio_defs.h b/src/soc/intel/common/block/include/intelblocks/gpio_defs.h index 31bbde0ce2..10fb8ece09 100644 --- a/src/soc/intel/common/block/include/intelblocks/gpio_defs.h +++ b/src/soc/intel/common/block/include/intelblocks/gpio_defs.h @@ -265,10 +265,10 @@ * General purpose input. The following macro sets the * Host Software Pad Ownership to GPIO Driver mode. */ -#define PAD_CFG_GPI_TRIG_OWN(pad, pull, rst, trig, own) \ +#define PAD_CFG_GPI_TRIG_OWN(pad, pull, rst, trig, own, inv) \ _PAD_CFG_STRUCT(pad, \ PAD_FUNC(GPIO) | PAD_RESET(rst) | \ - PAD_TRIG(trig) | PAD_RX_POL(NONE) | PAD_BUF(TX_DISABLE), \ + PAD_TRIG(trig) | PAD_RX_POL(inv) | PAD_BUF(TX_DISABLE), \ PAD_PULL(pull) | PAD_CFG_OWN_GPIO(own))
#define PAD_CFG_GPI_GPIO_DRIVER(pad, pull, rst) \ @@ -289,7 +289,10 @@
/* GPIO Interrupt */ #define PAD_CFG_GPI_INT(pad, pull, rst, trig) \ - PAD_CFG_GPI_TRIG_OWN(pad, pull, rst, trig, DRIVER) + PAD_CFG_GPI_TRIG_OWN(pad, pull, rst, trig, DRIVER, NONE) + +#define PAD_CFG_GPI_INT_INVERTED(pad, pull, rst, trig) \ + PAD_CFG_GPI_TRIG_OWN(pad, pull, rst, trig, DRIVER, INVERT)
/* * No Connect configuration for unused pad.
Hello build bot (Jenkins), Furquan Shaikh, Angel Pons,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/46962
to look at the new patch set (#4).
Change subject: mb/google/hatch/jinlon: Describe the privacy_gpio ......................................................................
mb/google/hatch/jinlon: Describe the privacy_gpio
Add information regarding the privacy pin on the overridetree and gpio.
Change-Id: Ifa628dda03f3f65976850aeabaf516f528a921b7 Signed-off-by: Ricardo Ribalda ribalda@chromium.org --- M src/mainboard/google/hatch/variants/jinlon/gpio.c M src/mainboard/google/hatch/variants/jinlon/overridetree.cb 2 files changed, 12 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/62/46962/4
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46962 )
Change subject: mb/google/hatch/jinlon: Describe the privacy_gpio ......................................................................
Patch Set 4:
(3 comments)
https://review.coreboot.org/c/coreboot/+/46962/2/src/mainboard/google/hatch/... File src/mainboard/google/hatch/variants/jinlon/overridetree.cb:
https://review.coreboot.org/c/coreboot/+/46962/2/src/mainboard/google/hatch/... PS2, Line 86: ACPI_GPIO_INPUT_ACTIVE_LOW
I tried setting PAD_RX_POL(INVERT) on an EDGE_BOTH and it had no effect (check the attached patch). […]
Thanks for the pointers Ricardo. It is definitely an interesting case. As for why the above diff did not work, I think the kernel is reconfiguring the pad based on the information passed in ACPI. That is probably why it doesn't work. If interested, you can dump the configuration registers in coreboot and kernel to see if they change later on. Anyways, we can go ahead with the change you have in the latest patchset. Thanks for trying this out! :)
https://review.coreboot.org/c/coreboot/+/46962/4/src/mainboard/google/hatch/... File src/mainboard/google/hatch/variants/jinlon/overridetree.cb:
https://review.coreboot.org/c/coreboot/+/46962/4/src/mainboard/google/hatch/... PS4, Line 83: Can you please use tabs instead of spaces here and for the lines below like the rest of the entries in this file?
https://review.coreboot.org/c/coreboot/+/46962/4/src/mainboard/google/hatch/... PS4, Line 87: ACPI_GPIO_INPUT_ACTIVE_LOW Can you please add a comment here explaining why this is being configured as GPIO instead of GPIO_IRQ? It would be good to have the context here so that it isn't accidentally changed later on and also helps if anyone decides to copy-paste.
Hello build bot (Jenkins), Furquan Shaikh, Angel Pons,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/46962
to look at the new patch set (#5).
Change subject: mb/google/hatch/jinlon: Describe the privacy_gpio ......................................................................
mb/google/hatch/jinlon: Describe the privacy_gpio
Add information regarding the privacy pin on the overridetree and gpio.
Change-Id: Ifa628dda03f3f65976850aeabaf516f528a921b7 Signed-off-by: Ricardo Ribalda ribalda@chromium.org --- M src/mainboard/google/hatch/variants/jinlon/gpio.c M src/mainboard/google/hatch/variants/jinlon/overridetree.cb 2 files changed, 15 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/62/46962/5
Ricardo Ribalda has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46962 )
Change subject: mb/google/hatch/jinlon: Describe the privacy_gpio ......................................................................
Patch Set 5:
(2 comments)
https://review.coreboot.org/c/coreboot/+/46962/4/src/mainboard/google/hatch/... File src/mainboard/google/hatch/variants/jinlon/overridetree.cb:
https://review.coreboot.org/c/coreboot/+/46962/4/src/mainboard/google/hatch/... PS4, Line 83:
Can you please use tabs instead of spaces here and for the lines below like the rest of the entries […]
Done
https://review.coreboot.org/c/coreboot/+/46962/4/src/mainboard/google/hatch/... PS4, Line 87: ACPI_GPIO_INPUT_ACTIVE_LOW
Can you please add a comment here explaining why this is being configured as GPIO instead of GPIO_IR […]
Done
Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46962 )
Change subject: mb/google/hatch/jinlon: Describe the privacy_gpio ......................................................................
Patch Set 6: Code-Review+2
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46962 )
Change subject: mb/google/hatch/jinlon: Describe the privacy_gpio ......................................................................
Patch Set 6:
(1 comment)
https://review.coreboot.org/c/coreboot/+/46962/6/src/mainboard/google/hatch/... File src/mainboard/google/hatch/variants/jinlon/overridetree.cb:
https://review.coreboot.org/c/coreboot/+/46962/6/src/mainboard/google/hatch/... PS6, Line 87: BOTH_LEVEL BOTH_EDGE?
Ricardo Ribalda has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46962 )
Change subject: mb/google/hatch/jinlon: Describe the privacy_gpio ......................................................................
Patch Set 6:
(1 comment)
https://review.coreboot.org/c/coreboot/+/46962/6/src/mainboard/google/hatch/... File src/mainboard/google/hatch/variants/jinlon/overridetree.cb:
https://review.coreboot.org/c/coreboot/+/46962/6/src/mainboard/google/hatch/... PS6, Line 87: BOTH_LEVEL
BOTH_EDGE?
Done
Hello build bot (Jenkins), Furquan Shaikh, Tim Wawrzynczak, Angel Pons,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/46962
to look at the new patch set (#7).
Change subject: mb/google/hatch/jinlon: Describe the privacy_gpio ......................................................................
mb/google/hatch/jinlon: Describe the privacy_gpio
Add information regarding the privacy pin on the overridetree and gpio.
BUG=b:169840271
Change-Id: Ifa628dda03f3f65976850aeabaf516f528a921b7 Signed-off-by: Ricardo Ribalda ribalda@chromium.org --- M src/mainboard/google/hatch/variants/jinlon/gpio.c M src/mainboard/google/hatch/variants/jinlon/overridetree.cb 2 files changed, 15 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/62/46962/7
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46962 )
Change subject: mb/google/hatch/jinlon: Describe the privacy_gpio ......................................................................
Patch Set 7: Code-Review+2
Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/46962 )
Change subject: mb/google/hatch/jinlon: Describe the privacy_gpio ......................................................................
mb/google/hatch/jinlon: Describe the privacy_gpio
Add information regarding the privacy pin on the overridetree and gpio.
BUG=b:169840271
Change-Id: Ifa628dda03f3f65976850aeabaf516f528a921b7 Signed-off-by: Ricardo Ribalda ribalda@chromium.org Reviewed-on: https://review.coreboot.org/c/coreboot/+/46962 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Furquan Shaikh furquan@google.com --- M src/mainboard/google/hatch/variants/jinlon/gpio.c M src/mainboard/google/hatch/variants/jinlon/overridetree.cb 2 files changed, 15 insertions(+), 0 deletions(-)
Approvals: build bot (Jenkins): Verified Furquan Shaikh: Looks good to me, approved
diff --git a/src/mainboard/google/hatch/variants/jinlon/gpio.c b/src/mainboard/google/hatch/variants/jinlon/gpio.c index 88f0092..4029f06 100644 --- a/src/mainboard/google/hatch/variants/jinlon/gpio.c +++ b/src/mainboard/google/hatch/variants/jinlon/gpio.c @@ -18,6 +18,8 @@ * using this pin, expose this pin to driver. */ PAD_CFG_GPO(GPP_C15, 1, DEEP), + /* D4 : Camera Privacy Status */ + PAD_CFG_GPI_INT(GPP_D4, NONE, PLTRST, EDGE_BOTH), /* E0 : View Angle Management */ PAD_CFG_GPO(GPP_E0, 0, DEEP), /* F3 : MEM_STRAP_3 */ diff --git a/src/mainboard/google/hatch/variants/jinlon/overridetree.cb b/src/mainboard/google/hatch/variants/jinlon/overridetree.cb index fc3bb85..f042401 100644 --- a/src/mainboard/google/hatch/variants/jinlon/overridetree.cb +++ b/src/mainboard/google/hatch/variants/jinlon/overridetree.cb @@ -80,6 +80,19 @@ device generic 0 on end end end # Integrated Graphics Device + device pci 14.0 on + chip drivers/usb/acpi + device usb 0.0 on + chip drivers/usb/acpi + # The Linux Kernel does not allow an inverted BOTH_EDGE irq + # So we need to use GpioIO() instead of GpioInt() + # https://www.kernel.org/doc/Documentation/acpi/gpio-properties.txt + register "privacy_gpio" = "ACPI_GPIO_INPUT_ACTIVE_LOW(GPP_D4)" + device usb 2.6 on end + end + end + end + end # USB xHCI device pci 15.0 on chip drivers/i2c/generic register "hid" = ""ELAN0000""
-
Angel Pons (Code Review) -
Furquan Shaikh (Code Review)
-
Patrick Georgi (Code Review)
-
Ricardo Ribalda (Code Review)
-
Tim Wawrzynczak (Code Review)