Change in coreboot[master]: soc/intel/common/block/cpu: Introduce USE_CAR_NEM_ENHANCED_V3 Kconfig
Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48344 )
Change subject: soc/intel/common/block/cpu: Introduce USE_CAR_NEM_ENHANCED_V3 Kconfig ......................................................................
soc/intel/common/block/cpu: Introduce USE_CAR_NEM_ENHANCED_V3 Kconfig
List of changes: 1. Default select USE_CAR_NEM_ENHANCED_V1 to use the existing algorithm 2. Select COS_MAPPED_TO_MSB 3. Add new MSR 0xc85 IA32_YMM 4. a. Update eNEM init flow:
- Set MSR 0x1891 IA32_CR_SF_QOS_MASK_1 = 0xFFFFF - (2^(non-eviction mask)-1) - Set MSR 0x1892 IA32_CR_SF_QOS_MASK_2 = (2^(non-eviction mask)-1) - Set MSR 0xC85 L3_Protected_ways = (2^(no. of ways)-1)
b. Update eNEM teardown flow: - Set MSR 0xC85 L3_Protected_ways = 0x00000
This new eNEM flow can be used for ADL SoC.
Change-Id: Idb5a9ec74c50bda371c30e13aeadbb4326887fd6 Signed-off-by: Subrata Banik subrata.banik@intel.com --- M src/include/cpu/x86/msr.h M src/soc/intel/common/block/cpu/Kconfig M src/soc/intel/common/block/cpu/car/cache_as_ram.S M src/soc/intel/common/block/cpu/car/exit_car.S 4 files changed, 52 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/44/48344/1
diff --git a/src/include/cpu/x86/msr.h b/src/include/cpu/x86/msr.h index 5ae3ddf..1b089c0 100644 --- a/src/include/cpu/x86/msr.h +++ b/src/include/cpu/x86/msr.h @@ -85,6 +85,7 @@ #define IA32_HWP_CAPABILITIES 0x771 #define IA32_HWP_REQUEST 0x774 #define IA32_HWP_STATUS 0x777 +#define IA32_YMM 0xc85 #define IA32_PQR_ASSOC 0xc8f /* MSR bits 33:32 encode slot number 0-3 */ #define IA32_PQR_ASSOC_MASK (1 << 0 | 1 << 1) diff --git a/src/soc/intel/common/block/cpu/Kconfig b/src/soc/intel/common/block/cpu/Kconfig index 9023b58..7af664d 100644 --- a/src/soc/intel/common/block/cpu/Kconfig +++ b/src/soc/intel/common/block/cpu/Kconfig @@ -66,6 +66,14 @@ This config supports INTEL_CAR_NEM_ENHANCED mode on TGL platform.
+config USE_CAR_NEM_ENHANCED_V3 + bool + select USE_CAR_NEM_ENHANCED_V1 + select COS_MAPPED_TO_MSB + help + This config supports INTEL_CAR_NEM_ENHANCED mode on + ADL platform. + config COS_MAPPED_TO_MSB bool depends on INTEL_CAR_NEM_ENHANCED diff --git a/src/soc/intel/common/block/cpu/car/cache_as_ram.S b/src/soc/intel/common/block/cpu/car/cache_as_ram.S index 167342f..371ac73 100644 --- a/src/soc/intel/common/block/cpu/car/cache_as_ram.S +++ b/src/soc/intel/common/block/cpu/car/cache_as_ram.S @@ -413,7 +413,11 @@
set_eviction_mask: mov %ebx, %ecx /* back up the number of ways */ - mov %eax, %ebx /* back up the non-eviction mask*/ + mov %eax, %ebx /* back up the non-eviction mask */ +#if CONFIG(USE_CAR_NEM_ENHANCED_V3) + movd %ecx, %mm3 /* Store the number of ways in mm3 for later use */ + movd %ebx, %mm4 /* Store the non-eviction mask in mm4 for later use */ +#endif /* * Set MSR 0xC91 IA32_L3_MASK_1 or MSR 0x1891 IA32_CR_SF_QOS_MASK_1 * This MSR contain one bit per each way of LLC @@ -450,6 +454,37 @@ #endif xorl %edx, %edx wrmsr + +#if CONFIG(USE_CAR_NEM_ENHANCED_V3) + /* Set MSR 0x1891 IA32_CR_SF_QOS_MASK_1 = 0xFFFFF - (2^(non-eviction mask) - 1) */ + movd %mm4, %ecx + movl $0x01, %eax + shl %cl, %eax + subl $0x01, %eax + mov %eax, %ebx + mov $0xFFFFF, %eax + subl %ebx, %eax + xorl %edx, %edx + mov $IA32_CR_SF_QOS_MASK_1, %ecx + wrmsr + + /* Set MSR 0x1892 IA32_CR_SF_QOS_MASK_2 = (2^(non-eviction mask) - 1) */ + movd %mm4, %ecx + movl $0x01, %eax + shl %cl, %eax + subl $0x01, %eax + xorl %edx, %edx + mov $IA32_CR_SF_QOS_MASK_2, %ecx + wrmsr + + /* Set MSR 0xC85 L3_Protected_ways = (2^(no. of ways) - 1) */ + movd %mm3, %ecx + shl %cl, %eax + subl $0x01, %eax + xorl %edx, %edx + mov $IA32_YMM, %ecx + wrmsr +#endif /* * Set IA32_PQR_ASSOC * diff --git a/src/soc/intel/common/block/cpu/car/exit_car.S b/src/soc/intel/common/block/cpu/car/exit_car.S index 191232a..568a502 100644 --- a/src/soc/intel/common/block/cpu/car/exit_car.S +++ b/src/soc/intel/common/block/cpu/car/exit_car.S @@ -96,6 +96,13 @@ rdmsr and $~IA32_PQR_ASSOC_MASK, %edx wrmsr +#if CONFIG(USE_CAR_NEM_ENHANCED_V3) + /* Set MSR 0xC85 L3_Protected_ways = 0x00000 */ + mov $IA32_YMM, %ecx + mov $0x00000, %eax + xorl %edx, %edx + wrmsr +#endif #endif
/* Return to caller. */
Hello Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/48344
to look at the new patch set (#2).
Change subject: soc/intel/common/block/cpu: Introduce USE_CAR_NEM_ENHANCED_V3 Kconfig ......................................................................
soc/intel/common/block/cpu: Introduce USE_CAR_NEM_ENHANCED_V3 Kconfig
List of changes: 1. Default select USE_CAR_NEM_ENHANCED_V1 to use the existing algorithm 2. Select COS_MAPPED_TO_MSB 3. Add new MSR 0xc85 IA32_YMM 4. a. Update eNEM init flow:
- Set MSR 0x1891 IA32_CR_SF_QOS_MASK_1 = 0xFFFFF - (2^(non-eviction mask)-1) - Set MSR 0x1892 IA32_CR_SF_QOS_MASK_2 = (2^(non-eviction mask)-1) - Set MSR 0xC85 L3_Protected_ways = (2^(no. of ways)-1)
b. Update eNEM teardown flow: - Set MSR 0xC85 L3_Protected_ways = 0x00000
This new eNEM flow can be used for ADL SoC.
Change-Id: Idb5a9ec74c50bda371c30e13aeadbb4326887fd6 Signed-off-by: Subrata Banik subrata.banik@intel.com --- M src/include/cpu/x86/msr.h M src/soc/intel/common/block/cpu/Kconfig M src/soc/intel/common/block/cpu/car/cache_as_ram.S M src/soc/intel/common/block/cpu/car/exit_car.S 4 files changed, 52 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/44/48344/2
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48344 )
Change subject: soc/intel/common/block/cpu: Introduce USE_CAR_NEM_ENHANCED_V3 Kconfig ......................................................................
Patch Set 2:
Some of TGL related CAR support is being fixed as part of CB:48286. I would like to understand and ensure we do this correctly for ADL too.
Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48344 )
Change subject: soc/intel/common/block/cpu: Introduce USE_CAR_NEM_ENHANCED_V3 Kconfig ......................................................................
Patch Set 2:
Patch Set 2:
Some of TGL related CAR support is being fixed as part of CB:48286. I would like to understand and ensure we do this correctly for ADL too.
ADL eNEM flow would be different than TGL, working on doc part
Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48344 )
Change subject: soc/intel/common/block/cpu: Introduce USE_CAR_NEM_ENHANCED_V3 Kconfig ......................................................................
Patch Set 2:
(1 comment)
Patchset:
PS2: @Furquan, Tim, can we review this and make it ready, later we can select eNEM from SoC ?
Attention is currently required from: Subrata Banik. Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48344 )
Change subject: soc/intel/common/block/cpu: Introduce USE_CAR_NEM_ENHANCED_V3 Kconfig ......................................................................
Patch Set 2:
(2 comments)
Patchset:
PS2:
@Furquan, Tim, can we review this and make it ready, later we can select eNEM from SoC ?
Please see my comments on the bug.
File src/soc/intel/common/block/cpu/car/cache_as_ram.S:
https://review.coreboot.org/c/coreboot/+/48344/comment/6f4c101a_6c4eac3c PS2, Line 417: USE_CAR_NEM_ENHANCED_V3 There is no _V1/_V2 anymore. I think what is different for ADL is just the 0xc85 register. It is still not clear to me what role it plays in NEM. Please see my questions on the bug.
Attention is currently required from: Furquan Shaikh, Subrata Banik. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48344 )
Change subject: soc/intel/common/block/cpu: Introduce USE_CAR_NEM_ENHANCED_V3 Kconfig ......................................................................
Patch Set 2:
(1 comment)
File src/soc/intel/common/block/cpu/car/cache_as_ram.S:
https://review.coreboot.org/c/coreboot/+/48344/comment/31fd5fef_8f4597ee PS2, Line 417: USE_CAR_NEM_ENHANCED_V3
There is no _V1/_V2 anymore. I think what is different for ADL is just the 0xc85 register. […]
We should probably just add another Kconfig similar to CAR_HAS_SF_MASKS, which will program the new MSRs
Attention is currently required from: Furquan Shaikh, Subrata Banik. Hello build bot (Jenkins), Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/48344
to look at the new patch set (#3).
Change subject: soc/intel/common/block/cpu: Introduce CAR_HAS_YMM Kconfig ......................................................................
soc/intel/common/block/cpu: Introduce CAR_HAS_YMM Kconfig
List of changes: 1. Default select INTEL_CAR_NEM_ENHANCED to use the existing algorithm 2. Select CAR_HAS_SF_MASKS 3. Select COS_MAPPED_TO_MSB 4. Add new MSR 0xc85 IA32_YMM 4. a. Update eNEM init flow:
- Set MSR 0x1891 IA32_CR_SF_QOS_MASK_1 = no. of ways of LLC - (2^(no. of data ways)-1) - Set MSR 0x1892 IA32_CR_SF_QOS_MASK_2 = (2^(no. of data ways)-1) - Set MSR 0xC85 L3_Protected_ways = (2^(no. of data ways)-1)
b. Update eNEM teardown flow: - Set MSR 0xC85 L3_Protected_ways = 0x00000
This new eNEM flow can be used for ADL SoC and onwards.
Change-Id: Idb5a9ec74c50bda371c30e13aeadbb4326887fd6 Signed-off-by: Subrata Banik subrata.banik@intel.com --- M src/include/cpu/x86/msr.h M src/soc/intel/common/block/cpu/Kconfig M src/soc/intel/common/block/cpu/car/cache_as_ram.S M src/soc/intel/common/block/cpu/car/exit_car.S 4 files changed, 35 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/44/48344/3
Attention is currently required from: Furquan Shaikh. Hello build bot (Jenkins), Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/48344
to look at the new patch set (#4).
Change subject: soc/intel/common/block/cpu: Introduce CAR_HAS_YMM Kconfig ......................................................................
soc/intel/common/block/cpu: Introduce CAR_HAS_YMM Kconfig
List of changes: 1. Default select INTEL_CAR_NEM_ENHANCED to use the existing algorithm 2. Select CAR_HAS_SF_MASKS 3. Select COS_MAPPED_TO_MSB 4. Add new MSR 0xc85 IA32_YMM 4. a. Update eNEM init flow:
- Set MSR 0x1891 IA32_CR_SF_QOS_MASK_1 = no. of ways of LLC - (2^(no. of data ways)-1) - Set MSR 0x1892 IA32_CR_SF_QOS_MASK_2 = (2^(no. of data ways)-1) - Set MSR 0xC85 L3_Protected_ways = (2^(no. of data ways)-1)
b. Update eNEM teardown flow: - Set MSR 0xC85 L3_Protected_ways = 0x00000
This new eNEM flow can be used for ADL SoC and onwards.
BUG=b:168820083
Change-Id: Idb5a9ec74c50bda371c30e13aeadbb4326887fd6 Signed-off-by: Subrata Banik subrata.banik@intel.com --- M src/include/cpu/x86/msr.h M src/soc/intel/common/block/cpu/Kconfig M src/soc/intel/common/block/cpu/car/cache_as_ram.S M src/soc/intel/common/block/cpu/car/exit_car.S 4 files changed, 35 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/44/48344/4
Attention is currently required from: Furquan Shaikh, Tim Wawrzynczak. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48344 )
Change subject: soc/intel/common/block/cpu: Introduce CAR_HAS_YMM Kconfig ......................................................................
Patch Set 4:
(1 comment)
File src/soc/intel/common/block/cpu/car/cache_as_ram.S:
https://review.coreboot.org/c/coreboot/+/48344/comment/f70c5a4d_b5e9626c PS2, Line 417: USE_CAR_NEM_ENHANCED_V3
We should probably just add another Kconfig similar to CAR_HAS_SF_MASKS, which will program the new […]
Ack
Attention is currently required from: Subrata Banik. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48344 )
Change subject: soc/intel/common/block/cpu: Introduce CAR_HAS_YMM Kconfig ......................................................................
Patch Set 4:
(1 comment)
File src/soc/intel/common/block/cpu/Kconfig:
https://review.coreboot.org/c/coreboot/+/48344/comment/f432b549_ae1e74e5 PS4, Line 77: YMM What does `YMM` mean?
Attention is currently required from: Angel Pons. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48344 )
Change subject: soc/intel/common/block/cpu: Introduce CAR_HAS_YMM Kconfig ......................................................................
Patch Set 4:
(1 comment)
File src/soc/intel/common/block/cpu/Kconfig:
https://review.coreboot.org/c/coreboot/+/48344/comment/5b2cb433_0f6bb7dc PS4, Line 77: YMM
What does `YMM` mean?
Good question, i need to get the full form. i read this as "magic" MSR 😊
Attention is currently required from: Angel Pons. Hello build bot (Jenkins), Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/48344
to look at the new patch set (#5).
Change subject: soc/intel/common/block/cpu: Introduce CAR_HAS_YMM Kconfig ......................................................................
soc/intel/common/block/cpu: Introduce CAR_HAS_YMM Kconfig
List of changes: 1. Default select INTEL_CAR_NEM_ENHANCED to use the existing algorithm 2. Select CAR_HAS_SF_MASKS 3. Select COS_MAPPED_TO_MSB 4. Add new MSR 0xc85 IA32_YMM 4. a. Update eNEM init flow:
- Set MSR 0x1891 IA32_CR_SF_QOS_MASK_1 = no. of ways of LLC - (2^(no. of data ways)-1) - Set MSR 0x1892 IA32_CR_SF_QOS_MASK_2 = (2^(no. of data ways)-1) - Set MSR 0xC85 L3_Protected_ways = (2^(no. of data ways)-1)
b. Update eNEM teardown flow: - Set MSR 0xC85 L3_Protected_ways = 0x00000
This new eNEM flow can be used for ADL SoC and onwards.
BUG=b:168820083
Change-Id: Idb5a9ec74c50bda371c30e13aeadbb4326887fd6 Signed-off-by: Subrata Banik subrata.banik@intel.com --- M src/include/cpu/x86/msr.h M src/soc/intel/common/block/cpu/Kconfig M src/soc/intel/common/block/cpu/car/cache_as_ram.S M src/soc/intel/common/block/cpu/car/exit_car.S 4 files changed, 36 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/44/48344/5
Attention is currently required from: Subrata Banik, Angel Pons. Rizwan Qureshi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48344 )
Change subject: soc/intel/common/block/cpu: Introduce CAR_HAS_YMM Kconfig ......................................................................
Patch Set 5:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/48344/comment/2b272f19_4ad38b37 PS5, Line 26: BUG=b:168820083 TEST? I think we have quite big LLC size for ADL-P and BIOS code is not that large enough to fill that. We need to check that code region caching and eviction is working with some dummy reads to fill up the cache.
Attention is currently required from: Subrata Banik, Angel Pons. Hello build bot (Jenkins), Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/48344
to look at the new patch set (#6).
Change subject: soc/intel/common/block/cpu: Introduce CAR_HAS_YMM Kconfig ......................................................................
soc/intel/common/block/cpu: Introduce CAR_HAS_YMM Kconfig
List of changes: 1. Default select INTEL_CAR_NEM_ENHANCED to use the existing algorithm 2. Select CAR_HAS_SF_MASKS 3. Select COS_MAPPED_TO_MSB 4. Add new MSR 0xc85 IA32_YMM 4. a. Update eNEM init flow:
- Set MSR 0x1891 IA32_CR_SF_QOS_MASK_1 = no. of ways of LLC - (2^(no. of data ways)-1) - Set MSR 0x1892 IA32_CR_SF_QOS_MASK_2 = (2^(no. of data ways)-1) - Set MSR 0xC85 L3_Protected_ways = (2^(no. of data ways)-1)
b. Update eNEM teardown flow: - Set MSR 0xC85 L3_Protected_ways = 0x00000
This new eNEM flow can be used for ADL SoC and onwards.
BUG=b:168820083 TEST=Verified filling up the entire cache with memcpy at the beginning itself and then running the entire bootblock, verstage, debug FSP-M without running into any issue. This proofs that code caching and eviction is working as expected in eNEM mode.
Change-Id: Idb5a9ec74c50bda371c30e13aeadbb4326887fd6 Signed-off-by: Subrata Banik subrata.banik@intel.com --- M src/include/cpu/x86/msr.h M src/soc/intel/common/block/cpu/Kconfig M src/soc/intel/common/block/cpu/car/cache_as_ram.S M src/soc/intel/common/block/cpu/car/exit_car.S 4 files changed, 36 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/44/48344/6
Attention is currently required from: Rizwan Qureshi, Angel Pons. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48344 )
Change subject: soc/intel/common/block/cpu: Introduce CAR_HAS_YMM Kconfig ......................................................................
Patch Set 6:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/48344/comment/d42c8551_4cbcd9f8 PS5, Line 26: BUG=b:168820083
TEST? […]
Ack
Attention is currently required from: Rizwan Qureshi, Angel Pons. Hello build bot (Jenkins), Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/48344
to look at the new patch set (#7).
Change subject: soc/intel/common/block/cpu: Introduce CAR_HAS_YMM Kconfig ......................................................................
soc/intel/common/block/cpu: Introduce CAR_HAS_YMM Kconfig
List of changes: 1. Default select INTEL_CAR_NEM_ENHANCED to use the existing algorithm 2. Select CAR_HAS_SF_MASKS 3. Select COS_MAPPED_TO_MSB 4. Add new MSR 0xc85 IA32_YMM 4. a. Update eNEM init flow:
- Set MSR 0x1891 IA32_CR_SF_QOS_MASK_1 = (1 << 2*no. of ways of LLC) - (2^(no. of data ways)-1) - Set MSR 0x1892 IA32_CR_SF_QOS_MASK_2 = (2^(no. of data ways)-1) - Set MSR 0xC85 L3_Protected_ways = (2^(no. of data ways)-1)
b. Update eNEM teardown flow: - Set MSR 0xC85 L3_Protected_ways = 0x00000
This new eNEM flow can be used for ADL SoC and onwards.
BUG=b:168820083 TEST=Verified filling up the entire cache with memcpy at the beginning itself and then running the entire bootblock, verstage, debug FSP-M without running into any issue. This proofs that code caching and eviction is working as expected in eNEM mode.
Change-Id: Idb5a9ec74c50bda371c30e13aeadbb4326887fd6 Signed-off-by: Subrata Banik subrata.banik@intel.com --- M src/include/cpu/x86/msr.h M src/soc/intel/common/block/cpu/Kconfig M src/soc/intel/common/block/cpu/car/cache_as_ram.S M src/soc/intel/common/block/cpu/car/exit_car.S 4 files changed, 31 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/44/48344/7
Attention is currently required from: Rizwan Qureshi, Angel Pons. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48344 )
Change subject: soc/intel/common/block/cpu: Introduce CAR_HAS_YMM Kconfig ......................................................................
Patch Set 7:
(1 comment)
File src/soc/intel/common/block/cpu/Kconfig:
https://review.coreboot.org/c/coreboot/+/48344/comment/fc6ed86f_c004833d PS4, Line 77: YMM
Good question, i need to get the full form. […]
YMM = = yens’ magic MSR but we will refer this as protected way from eviction
Attention is currently required from: Rizwan Qureshi, Angel Pons. Hello build bot (Jenkins), Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/48344
to look at the new patch set (#8).
Change subject: soc/intel/common/block/cpu: Introduce CAR_HAS_YMM Kconfig ......................................................................
soc/intel/common/block/cpu: Introduce CAR_HAS_YMM Kconfig
List of changes: 1. Default select INTEL_CAR_NEM_ENHANCED to use the existing algorithm 2. Select CAR_HAS_SF_MASKS 3. Select COS_MAPPED_TO_MSB 4. Add new MSR 0xc85 IA32_L3_PROTECTED_WAYS 4. a. Update eNEM init flow:
- Calcuate SFWayCnt = (MSR 0xC87) & Bit [5:0] - Set MSR 0x1891 IA32_CR_SF_QOS_MASK_1 = (1 << SFWayCnt) - (1 << data_ways) - 1 - Set MSR 0x1892 IA32_CR_SF_QOS_MASK_2 = (2^(no. of data ways)-1) - Set MSR 0xC85 L3_Protected_ways = (2^(no. of data ways)-1)
b. Update eNEM teardown flow: - Set MSR 0xC85 L3_Protected_ways = 0x00000
This new eNEM flow can be used for ADL SoC and onwards.
BUG=b:168820083 TEST=Verified filling up the entire cache with memcpy at the beginning itself and then running the entire bootblock, verstage, debug FSP-M without running into any issue. This proofs that code caching and eviction is working as expected in eNEM mode.
Change-Id: Idb5a9ec74c50bda371c30e13aeadbb4326887fd6 Signed-off-by: Subrata Banik subrata.banik@intel.com --- M src/include/cpu/x86/msr.h M src/soc/intel/common/block/cpu/Kconfig M src/soc/intel/common/block/cpu/car/cache_as_ram.S M src/soc/intel/common/block/cpu/car/exit_car.S 4 files changed, 31 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/44/48344/8
Attention is currently required from: Rizwan Qureshi, Angel Pons. Hello build bot (Jenkins), Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/48344
to look at the new patch set (#9).
Change subject: soc/intel/common/block/cpu: Introduce CAR_HAS_YMM Kconfig ......................................................................
soc/intel/common/block/cpu: Introduce CAR_HAS_YMM Kconfig
List of changes: 1. Default select INTEL_CAR_NEM_ENHANCED to use the existing algorithm 2. Select CAR_HAS_SF_MASKS 3. Select COS_MAPPED_TO_MSB 4. Add new MSR 0xc85 IA32_L3_PROTECTED_WAYS a. Update eNEM init flow: - Calcuate SFWayCnt = (MSR 0xC87) & Bit [5:0] - Set MSR 0x1891 IA32_CR_SF_QOS_MASK_1 = (1 << SFWayCnt) - (1 << data_ways) - 1 - Set MSR 0x1892 IA32_CR_SF_QOS_MASK_2 = (2^(no. of data ways)-1) - Set MSR 0xC85 L3_Protected_ways = (2^(no. of data ways)-1) b. Update eNEM teardown flow: - Set MSR 0xC85 L3_Protected_ways = 0x00000
This new eNEM flow can be used for ADL SoC and onwards.
BUG=b:168820083 TEST=Verified filling up the entire cache with memcpy at the beginning itself and then running the entire bootblock, verstage, debug FSP-M without running into any issue. This proofs that code caching and eviction is working as expected in eNEM mode.
Change-Id: Idb5a9ec74c50bda371c30e13aeadbb4326887fd6 Signed-off-by: Subrata Banik subrata.banik@intel.com --- M src/include/cpu/x86/msr.h M src/soc/intel/common/block/cpu/Kconfig M src/soc/intel/common/block/cpu/car/cache_as_ram.S M src/soc/intel/common/block/cpu/car/exit_car.S 4 files changed, 31 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/44/48344/9
Attention is currently required from: Rizwan Qureshi, Subrata Banik, Angel Pons. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48344 )
Change subject: soc/intel/common/block/cpu: Introduce CAR_HAS_YMM Kconfig ......................................................................
Patch Set 9:
(6 comments)
File src/soc/intel/common/block/cpu/Kconfig:
https://review.coreboot.org/c/coreboot/+/48344/comment/e35e3f46_5b7ba20c PS9, Line 73: CAR_HAS_YMM suggestion: `CAR_HAS_L3_PROTECTED_WAYS`
https://review.coreboot.org/c/coreboot/+/48344/comment/a939a51f_af6d88df PS9, Line 80: SF snoop filter
File src/soc/intel/common/block/cpu/car/cache_as_ram.S:
https://review.coreboot.org/c/coreboot/+/48344/comment/2abc40dc_20d8d127 PS9, Line 542: #if CONFIG(CAR_HAS_YMM) This code also uses rdmsr/wrmsr and so has to use `ecx`, therefore its value must be saved first. IOW, the current structure allows you to select CAR_HAS_YMM but not CAR_HAS_SF_MASKS, and in that case, `edi` would not contain the expected backed up number of ways when you try to restore from it on line 554. Therefore, you need to save it again here too, i.e.: ``` mov %ecx, %edi ```
https://review.coreboot.org/c/coreboot/+/48344/comment/1625272d_10def34d PS9, Line 543: /* Set MSR 0x1892 IA32_CR_SF_QOS_MASK_2 = (2^(no, of data ways) - 1) */ can you also add a clarification that this value is also the non-eviction mask?
https://review.coreboot.org/c/coreboot/+/48344/comment/e4683c33_248e9125 PS9, Line 550: mov %ebx, %eax : xorl %edx, %edx IIUC, these registers should still contain these values (I don't think wrmsr should have changed these registers, just read them)
File src/soc/intel/common/block/cpu/car/exit_car.S:
https://review.coreboot.org/c/coreboot/+/48344/comment/6b144226_70f5bcd7 PS9, Line 102: mov $0x00000, %eax `xorl %eax, %eax`
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Change subject: soc/intel/common/block/cpu: Introduce CAR_HAS_YMM Kconfig ......................................................................
Patch Set 9:
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/48344/comment/0318d072_e9af3ac4 PS9, Line 11: 2. Select CAR_HAS_SF_MASKS : 3. Select COS_MAPPED_TO_MSB where is this?
https://review.coreboot.org/c/coreboot/+/48344/comment/57a80c91_bd1ded5a PS9, Line 28: proofs proves
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Change subject: soc/intel/common/block/cpu: Introduce CAR_HAS_YMM Kconfig ......................................................................
Patch Set 9:
(8 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/48344/comment/ad669aca_6e4008e2 PS9, Line 11: 2. Select CAR_HAS_SF_MASKS : 3. Select COS_MAPPED_TO_MSB
where is this?
Ack
https://review.coreboot.org/c/coreboot/+/48344/comment/04fad95d_1a7273c7 PS9, Line 28: proofs
proves
OMG 😭
File src/soc/intel/common/block/cpu/Kconfig:
https://review.coreboot.org/c/coreboot/+/48344/comment/261a0457_78eae7e9 PS9, Line 73: CAR_HAS_YMM
suggestion: […]
Ack
https://review.coreboot.org/c/coreboot/+/48344/comment/46d35b9b_abe33bf6 PS9, Line 80: SF
snoop filter
Ack
File src/soc/intel/common/block/cpu/car/cache_as_ram.S:
https://review.coreboot.org/c/coreboot/+/48344/comment/3009f166_5af53c41 PS9, Line 542: #if CONFIG(CAR_HAS_YMM)
This code also uses rdmsr/wrmsr and so has to use `ecx`, therefore its value must be saved first. […]
Ack
https://review.coreboot.org/c/coreboot/+/48344/comment/e09217b9_c60d1e5c PS9, Line 543: /* Set MSR 0x1892 IA32_CR_SF_QOS_MASK_2 = (2^(no, of data ways) - 1) */
can you also add a clarification that this value is also the non-eviction mask?
Ack
https://review.coreboot.org/c/coreboot/+/48344/comment/898dc14e_5bf98705 PS9, Line 550: mov %ebx, %eax : xorl %edx, %edx
IIUC, these registers should still contain these values (I don't think wrmsr should have changed the […]
Ack
File src/soc/intel/common/block/cpu/car/exit_car.S:
https://review.coreboot.org/c/coreboot/+/48344/comment/27740a17_022c3ad2 PS9, Line 102: mov $0x00000, %eax
`xorl %eax, %eax`
Ack
Attention is currently required from: Tim Wawrzynczak, Rizwan Qureshi, Angel Pons. Hello build bot (Jenkins), Patrick Rudolph,
I'd like you to reexamine a change. Please visit
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to look at the new patch set (#10).
Change subject: soc/intel/common/block/cpu: Introduce CAR_HAS_L3_PROTECTED_WAYS Kconfig ......................................................................
soc/intel/common/block/cpu: Introduce CAR_HAS_L3_PROTECTED_WAYS Kconfig
Alder Lake onwards IA SoC to select CAR_HAS_L3_PROTECTED_WAYS from SoC Kconfig and here is modified flow as below: 1. Default select INTEL_CAR_NEM_ENHANCED to use the existing algorithm 2. Add new MSR 0xc85 IA32_L3_PROTECTED_WAYS a. Update eNEM init flow: - Set Non-Eviction Mask #2 MSR 0x1892 IA32_CR_SF_QOS_MASK_2 = (2^(no. of data ways)-1) - Set MSR 0xC85 L3_Protected_ways = (2^(no. of data ways)-1) b. Update eNEM teardown flow: - Set MSR 0xC85 L3_Protected_ways = 0x00000
BUG=b:168820083 TEST=Verified filling up the entire cache with memcpy at the beginning itself and then running the entire bootblock, verstage, debug FSP-M without running into any issue. This proves that code caching and eviction is working as expected in eNEM mode.
Change-Id: Idb5a9ec74c50bda371c30e13aeadbb4326887fd6 Signed-off-by: Subrata Banik subrata.banik@intel.com --- M src/include/cpu/x86/msr.h M src/soc/intel/common/block/cpu/Kconfig M src/soc/intel/common/block/cpu/car/cache_as_ram.S M src/soc/intel/common/block/cpu/car/exit_car.S 4 files changed, 33 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/44/48344/10
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Change subject: soc/intel/common/block/cpu: Introduce CAR_HAS_L3_PROTECTED_WAYS Kconfig ......................................................................
Patch Set 10:
(1 comment)
File src/soc/intel/common/block/cpu/car/cache_as_ram.S:
https://review.coreboot.org/c/coreboot/+/48344/comment/c817e3ff_dc4c7817 PS2, Line 417: USE_CAR_NEM_ENHANCED_V3
Ack
@Tim/Furquan, Do you see any ACK here ? not sure why it points be that there is an unresolved comment ?
Attention is currently required from: Tim Wawrzynczak, Rizwan Qureshi, Angel Pons. Hello build bot (Jenkins), Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/48344
to look at the new patch set (#11).
Change subject: soc/intel/common/block/cpu: Introduce CAR_HAS_L3_PROTECTED_WAYS Kconfig ......................................................................
soc/intel/common/block/cpu: Introduce CAR_HAS_L3_PROTECTED_WAYS Kconfig
Alder Lake onwards IA SoC to select CAR_HAS_L3_PROTECTED_WAYS from SoC Kconfig and here is modified flow as below: 1. Default select INTEL_CAR_NEM_ENHANCED to use the existing algorithm 2. Add new MSR 0xc85 IA32_L3_PROTECTED_WAYS a. Update eNEM init flow: - Set Non-Eviction Mask #2 MSR 0x1892 IA32_CR_SF_QOS_MASK_2 = ((1 << data ways) - 1) - Set MSR 0xC85 L3_Protected_ways = ((1 << data ways) - 1) b. Update eNEM teardown flow: - Set MSR 0xC85 L3_Protected_ways = 0x00000
BUG=b:168820083 TEST=Verified filling up the entire cache with memcpy at the beginning itself and then running the entire bootblock, verstage, debug FSP-M without running into any issue. This proves that code caching and eviction is working as expected in eNEM mode.
Change-Id: Idb5a9ec74c50bda371c30e13aeadbb4326887fd6 Signed-off-by: Subrata Banik subrata.banik@intel.com --- M src/include/cpu/x86/msr.h M src/soc/intel/common/block/cpu/Kconfig M src/soc/intel/common/block/cpu/car/cache_as_ram.S M src/soc/intel/common/block/cpu/car/exit_car.S 4 files changed, 36 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/44/48344/11
Attention is currently required from: Furquan Shaikh, Tim Wawrzynczak, Rizwan Qureshi, Angel Pons. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48344 )
Change subject: soc/intel/common/block/cpu: Introduce CAR_HAS_L3_PROTECTED_WAYS Kconfig ......................................................................
Patch Set 11:
(1 comment)
File src/soc/intel/common/block/cpu/car/cache_as_ram.S:
https://review.coreboot.org/c/coreboot/+/48344/comment/cc6f5554_d0593d16 PS2, Line 417: USE_CAR_NEM_ENHANCED_V3
@Tim/Furquan, Do you see any ACK here ? not sure why it points be that there is an unresolved commen […]
comment
Attention is currently required from: Furquan Shaikh, Tim Wawrzynczak, Rizwan Qureshi, Angel Pons. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48344 )
Change subject: soc/intel/common/block/cpu: Introduce CAR_HAS_L3_PROTECTED_WAYS Kconfig ......................................................................
Patch Set 11:
(1 comment)
File src/soc/intel/common/block/cpu/car/cache_as_ram.S:
https://review.coreboot.org/c/coreboot/+/48344/comment/926a9f00_ea75f8ef PS2, Line 417: USE_CAR_NEM_ENHANCED_V3
comment
Ack
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Change subject: soc/intel/common/block/cpu: Introduce CAR_HAS_L3_PROTECTED_WAYS Kconfig ......................................................................
Patch Set 12:
(3 comments)
File src/soc/intel/common/block/cpu/car/cache_as_ram.S:
https://review.coreboot.org/c/coreboot/+/48344/comment/a7752376_ae9707b0 PS12, Line 517: mov %ebx, %ecx /* back up number of ways */ : mov %eax, %ebx /* back up the non-eviction mask*/ Thinking out loud (for a later change): Now that there are `wrmsr` and `rdmsr` calls below, maybe we should not use `ecx` for a backup location, since it is required to be used for the msr instructions (obv. not eax or edx either) and thus has to be backed-up several times. edi and esi seem like good backup locations (the only `rep` prefix is in the clear_car macro)
https://review.coreboot.org/c/coreboot/+/48344/comment/f6d26406_d33b074a PS12, Line 558: %bl, shouldn't this be %edi (data_ways) ? ebx contains the non-eviction mask at this point
https://review.coreboot.org/c/coreboot/+/48344/comment/f95d25ae_de641bf4 PS12, Line 557: mov $0x01, %eax : mov %bl, %cl : shl %cl, %eax : subl $0x01, %eax doesn't `ebx` already hold the correct value (the data ways non-eviction mask) to program into the MSR at this point? `(1 << data_ways) - 1` ?
Attention is currently required from: Furquan Shaikh, Tim Wawrzynczak, Rizwan Qureshi, Angel Pons. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48344 )
Change subject: soc/intel/common/block/cpu: Introduce CAR_HAS_L3_PROTECTED_WAYS Kconfig ......................................................................
Patch Set 12:
(1 comment)
File src/soc/intel/common/block/cpu/car/cache_as_ram.S:
https://review.coreboot.org/c/coreboot/+/48344/comment/549d4cec_0e9f2b42 PS12, Line 517: mov %ebx, %ecx /* back up number of ways */ : mov %eax, %ebx /* back up the non-eviction mask*/
Thinking out loud (for a later change): Now that there are `wrmsr` and `rdmsr` calls below, maybe we […]
i agree, i will modify the code to make sure we use edi/esi at first place then rebase all CLs on top of that. SG?
Attention is currently required from: Furquan Shaikh, Rizwan Qureshi, Subrata Banik, Angel Pons. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48344 )
Change subject: soc/intel/common/block/cpu: Introduce CAR_HAS_L3_PROTECTED_WAYS Kconfig ......................................................................
Patch Set 12:
(1 comment)
File src/soc/intel/common/block/cpu/car/cache_as_ram.S:
https://review.coreboot.org/c/coreboot/+/48344/comment/fda0524a_e18ce0be PS12, Line 517: mov %ebx, %ecx /* back up number of ways */ : mov %eax, %ebx /* back up the non-eviction mask*/
i agree, i will modify the code to make sure we use edi/esi at first place then rebase all CLs on to […]
If you want to do that now, feel free, but it's not urgent
Attention is currently required from: Furquan Shaikh, Tim Wawrzynczak, Rizwan Qureshi, Angel Pons. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48344 )
Change subject: soc/intel/common/block/cpu: Introduce CAR_HAS_L3_PROTECTED_WAYS Kconfig ......................................................................
Patch Set 12:
(1 comment)
File src/soc/intel/common/block/cpu/car/cache_as_ram.S:
https://review.coreboot.org/c/coreboot/+/48344/comment/939f2bc3_4ed15a4d PS12, Line 517: mov %ebx, %ecx /* back up number of ways */ : mov %eax, %ebx /* back up the non-eviction mask*/
If you want to do that now, feel free, but it's not urgent
I will give a try tomorrow, i hope this shouldn't take much time. might need your support to review additional CLs 😊
Attention is currently required from: Furquan Shaikh, Tim Wawrzynczak, Rizwan Qureshi, Angel Pons. Hello build bot (Jenkins), Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/48344
to look at the new patch set (#13).
Change subject: soc/intel/common/block/cpu: Introduce CAR_HAS_L3_PROTECTED_WAYS Kconfig ......................................................................
soc/intel/common/block/cpu: Introduce CAR_HAS_L3_PROTECTED_WAYS Kconfig
Alder Lake onwards IA SoC to select CAR_HAS_L3_PROTECTED_WAYS from SoC Kconfig and here is modified flow as below: 1. Default select INTEL_CAR_NEM_ENHANCED to use the existing algorithm 2. Add new MSR 0xc85 IA32_L3_PROTECTED_WAYS a. Update eNEM init flow: - Set Non-Eviction Mask #2 MSR 0x1892 IA32_CR_SF_QOS_MASK_2 = ((1 << data ways) - 1) - Set MSR 0xC85 L3_Protected_ways = ((1 << data ways) - 1) b. Update eNEM teardown flow: - Set MSR 0xC85 L3_Protected_ways = 0x00000
BUG=b:168820083 TEST=Verified filling up the entire cache with memcpy at the beginning itself and then running the entire bootblock, verstage, debug FSP-M without running into any issue. This proves that code caching and eviction is working as expected in eNEM mode.
Change-Id: Idb5a9ec74c50bda371c30e13aeadbb4326887fd6 Signed-off-by: Subrata Banik subrata.banik@intel.com --- M src/include/cpu/x86/msr.h M src/soc/intel/common/block/cpu/Kconfig M src/soc/intel/common/block/cpu/car/cache_as_ram.S M src/soc/intel/common/block/cpu/car/exit_car.S 4 files changed, 31 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/44/48344/13
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Change subject: soc/intel/common/block/cpu: Introduce CAR_HAS_L3_PROTECTED_WAYS Kconfig ......................................................................
Patch Set 13:
(3 comments)
File src/soc/intel/common/block/cpu/car/cache_as_ram.S:
https://review.coreboot.org/c/coreboot/+/48344/comment/09453f4f_7274541b PS12, Line 517: mov %ebx, %ecx /* back up number of ways */ : mov %eax, %ebx /* back up the non-eviction mask*/
I will give a try tomorrow, i hope this shouldn't take much time. […]
Ack
https://review.coreboot.org/c/coreboot/+/48344/comment/ed8fd0d2_ec6b5d98 PS12, Line 558: %bl,
shouldn't this be %edi (data_ways) ? ebx contains the non-eviction mask at this point
Ack
https://review.coreboot.org/c/coreboot/+/48344/comment/85794138_fc6333d1 PS12, Line 557: mov $0x01, %eax : mov %bl, %cl : shl %cl, %eax : subl $0x01, %eax
doesn't `ebx` already hold the correct value (the data ways non-eviction mask) to program into the M […]
Ack
Attention is currently required from: Furquan Shaikh, Tim Wawrzynczak, Rizwan Qureshi, Angel Pons. Hello build bot (Jenkins), Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/48344
to look at the new patch set (#15).
Change subject: soc/intel/common/block/cpu: Introduce CAR_HAS_L3_PROTECTED_WAYS Kconfig ......................................................................
soc/intel/common/block/cpu: Introduce CAR_HAS_L3_PROTECTED_WAYS Kconfig
Alder Lake onwards IA SoC to select CAR_HAS_L3_PROTECTED_WAYS from SoC Kconfig and here is modified flow as below: 1. Default select INTEL_CAR_NEM_ENHANCED to use the existing algorithm 2. Add new MSR 0xc85 IA32_L3_PROTECTED_WAYS a. Update eNEM init flow: - Set Non-Eviction Mask #2 MSR 0x1892 IA32_CR_SF_QOS_MASK_2 = (1 << data ways) - 1 - Set MSR 0xC85 L3_Protected_ways = (1 << data ways) - 1 b. Update eNEM teardown flow: - Set MSR 0xC85 L3_Protected_ways = 0x00000
BUG=b:168820083 TEST=Verified filling up the entire cache with memcpy at the beginning itself and then running the entire bootblock, verstage, debug FSP-M without running into any issue. This proves that code caching and eviction is working as expected in eNEM mode.
Change-Id: Idb5a9ec74c50bda371c30e13aeadbb4326887fd6 Signed-off-by: Subrata Banik subrata.banik@intel.com --- M src/include/cpu/x86/msr.h M src/soc/intel/common/block/cpu/Kconfig M src/soc/intel/common/block/cpu/car/cache_as_ram.S M src/soc/intel/common/block/cpu/car/exit_car.S 4 files changed, 31 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/44/48344/15
Attention is currently required from: Furquan Shaikh, Rizwan Qureshi, Subrata Banik, Angel Pons. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48344 )
Change subject: soc/intel/common/block/cpu: Introduce CAR_HAS_L3_PROTECTED_WAYS Kconfig ......................................................................
Patch Set 15: Code-Review+1
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Change subject: soc/intel/common/block/cpu: Introduce CAR_HAS_L3_PROTECTED_WAYS Kconfig ......................................................................
Patch Set 15:
(1 comment)
File src/soc/intel/common/block/cpu/car/cache_as_ram.S:
https://review.coreboot.org/c/coreboot/+/48344/comment/a2a4ea30_0535fe4f PS15, Line 549: /* : * Program MSR 0x1892 Non-Eviction Mask #2 : * IA32_CR_SF_QOS_MASK_2 = ((1 << data ways) - 1) : */ : mov %esi, %eax : xorl %edx, %edx : mov $IA32_CR_SF_QOS_MASK_2, %ecx : wrmsr Why is this programmed only for L3 protected ways? SF QOS mask 2 must be programmed always i.e. it should be set to non-evict mask above when setting SF QOS mask 1.
Attention is currently required from: Rizwan Qureshi, Subrata Banik, Angel Pons. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48344 )
Change subject: soc/intel/common/block/cpu: Introduce CAR_HAS_L3_PROTECTED_WAYS Kconfig ......................................................................
Patch Set 15: -Code-Review
Attention is currently required from: Rizwan Qureshi, Subrata Banik, Angel Pons. Hello build bot (Jenkins), Tim Wawrzynczak, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/48344
to look at the new patch set (#16).
Change subject: soc/intel/common/block/cpu: Introduce CAR_HAS_L3_PROTECTED_WAYS Kconfig ......................................................................
soc/intel/common/block/cpu: Introduce CAR_HAS_L3_PROTECTED_WAYS Kconfig
Alder Lake onwards IA SoC to select CAR_HAS_L3_PROTECTED_WAYS from SoC Kconfig and here is modified flow as below: Add new MSR 0xc85 IA32_L3_PROTECTED_WAYS Update eNEM init flow: - Set MSR 0xC85 L3_Protected_ways = (1 << data ways) - 1 Update eNEM teardown flow: - Set MSR 0xC85 L3_Protected_ways = 0x00000
BUG=b:168820083 TEST=Verified filling up the entire cache with memcpy at the beginning itself and then running the entire bootblock, verstage, debug FSP-M without running into any issue. This proves that code caching and eviction is working as expected in eNEM mode.
Change-Id: Idb5a9ec74c50bda371c30e13aeadbb4326887fd6 Signed-off-by: Subrata Banik subrata.banik@intel.com --- M src/include/cpu/x86/msr.h M src/soc/intel/common/block/cpu/Kconfig M src/soc/intel/common/block/cpu/car/cache_as_ram.S M src/soc/intel/common/block/cpu/car/exit_car.S 4 files changed, 21 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/44/48344/16
Attention is currently required from: Rizwan Qureshi, Angel Pons. Hello build bot (Jenkins), Tim Wawrzynczak, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/48344
to look at the new patch set (#18).
Change subject: soc/intel/common/block/cpu: Introduce CAR_HAS_L3_PROTECTED_WAYS Kconfig ......................................................................
soc/intel/common/block/cpu: Introduce CAR_HAS_L3_PROTECTED_WAYS Kconfig
Alder Lake onwards IA SoC to select CAR_HAS_L3_PROTECTED_WAYS from SoC Kconfig and here is modified flow as below: Add new MSR 0xc85 IA32_L3_PROTECTED_WAYS Update eNEM init flow: - Set MSR 0xC85 L3_Protected_ways = (1 << data ways) - 1 Update eNEM teardown flow: - Set MSR 0xC85 L3_Protected_ways = 0x00000
BUG=b:168820083 TEST=Verified filling up the entire cache with memcpy at the beginning itself and then running the entire bootblock, verstage, debug FSP-M without running into any issue. This proves that code caching and eviction is working as expected in eNEM mode.
Change-Id: Idb5a9ec74c50bda371c30e13aeadbb4326887fd6 Signed-off-by: Subrata Banik subrata.banik@intel.com --- M src/include/cpu/x86/msr.h M src/soc/intel/common/block/cpu/Kconfig M src/soc/intel/common/block/cpu/car/cache_as_ram.S M src/soc/intel/common/block/cpu/car/exit_car.S 4 files changed, 23 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/44/48344/18
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Change subject: soc/intel/common/block/cpu: Introduce CAR_HAS_L3_PROTECTED_WAYS Kconfig ......................................................................
Patch Set 22: Code-Review+2
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Change subject: soc/intel/common/block/cpu: Introduce CAR_HAS_L3_PROTECTED_WAYS Kconfig ......................................................................
Patch Set 22:
(1 comment)
File src/soc/intel/common/block/cpu/car/cache_as_ram.S:
https://review.coreboot.org/c/coreboot/+/48344/comment/5605c5b6_dfb9ffc5 PS15, Line 549: /* : * Program MSR 0x1892 Non-Eviction Mask #2 : * IA32_CR_SF_QOS_MASK_2 = ((1 << data ways) - 1) : */ : mov %esi, %eax : xorl %edx, %edx : mov $IA32_CR_SF_QOS_MASK_2, %ecx : wrmsr
Why is this programmed only for L3 protected ways? SF QOS mask 2 must be programmed always i.e. […]
Ack
Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48344 )
Change subject: soc/intel/common/block/cpu: Introduce CAR_HAS_L3_PROTECTED_WAYS Kconfig ......................................................................
Patch Set 23:
(1 comment)
Patchset:
PS23: @Furquan/Tim: Do you see any "ACK", looks like there is still one "unresolved" comment as per patchset 2 which I'm unable to resolve and same time unable to merge this CL. please help.
Attention is currently required from: Furquan Shaikh, Subrata Banik. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48344 )
Change subject: soc/intel/common/block/cpu: Introduce CAR_HAS_L3_PROTECTED_WAYS Kconfig ......................................................................
Patch Set 23:
(1 comment)
Patchset:
PS2:
Please see my comments on the bug.
@Subrata
Attention is currently required from: Furquan Shaikh, Angel Pons. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48344 )
Change subject: soc/intel/common/block/cpu: Introduce CAR_HAS_L3_PROTECTED_WAYS Kconfig ......................................................................
Patch Set 23:
(1 comment)
Patchset:
PS2:
@Subrata
thanks Angel.
Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/48344 )
Change subject: soc/intel/common/block/cpu: Introduce CAR_HAS_L3_PROTECTED_WAYS Kconfig ......................................................................
soc/intel/common/block/cpu: Introduce CAR_HAS_L3_PROTECTED_WAYS Kconfig
Alder Lake onwards IA SoC to select CAR_HAS_L3_PROTECTED_WAYS from SoC Kconfig and here is modified flow as below: Add new MSR 0xc85 IA32_L3_PROTECTED_WAYS Update eNEM init flow: - Set MSR 0xC85 L3_Protected_ways = (1 << data ways) - 1 Update eNEM teardown flow: - Set MSR 0xC85 L3_Protected_ways = 0x00000
BUG=b:168820083 TEST=Verified filling up the entire cache with memcpy at the beginning itself and then running the entire bootblock, verstage, debug FSP-M without running into any issue. This proves that code caching and eviction is working as expected in eNEM mode.
Change-Id: Idb5a9ec74c50bda371c30e13aeadbb4326887fd6 Signed-off-by: Subrata Banik subrata.banik@intel.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/48344 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Tim Wawrzynczak twawrzynczak@chromium.org --- M src/include/cpu/x86/msr.h M src/soc/intel/common/block/cpu/Kconfig M src/soc/intel/common/block/cpu/car/cache_as_ram.S M src/soc/intel/common/block/cpu/car/exit_car.S 4 files changed, 23 insertions(+), 0 deletions(-)
Approvals: build bot (Jenkins): Verified Tim Wawrzynczak: Looks good to me, approved
diff --git a/src/include/cpu/x86/msr.h b/src/include/cpu/x86/msr.h index 9e7e6fd..a8d5e22 100644 --- a/src/include/cpu/x86/msr.h +++ b/src/include/cpu/x86/msr.h @@ -88,6 +88,7 @@ #define IA32_HWP_CAPABILITIES 0x771 #define IA32_HWP_REQUEST 0x774 #define IA32_HWP_STATUS 0x777 +#define IA32_L3_PROTECTED_WAYS 0xc85 #define IA32_SF_QOS_INFO 0xc87 #define IA32_SF_WAY_COUNT_MASK 0x3f #define IA32_PQR_ASSOC 0xc8f diff --git a/src/soc/intel/common/block/cpu/Kconfig b/src/soc/intel/common/block/cpu/Kconfig index f02af1f..342edb5 100644 --- a/src/soc/intel/common/block/cpu/Kconfig +++ b/src/soc/intel/common/block/cpu/Kconfig @@ -78,6 +78,14 @@ On TGL and JSL platform the class of service configuration is mapped to MSB of MSR IA32_PQR_ASSOC.
+config CAR_HAS_L3_PROTECTED_WAYS + bool + depends on INTEL_CAR_NEM_ENHANCED + help + On ADL and onwards platform has a newer requirement to protect + L3 ways in Non-Inclusive eNEM mode. Hence, MSR 0xc85 is to program + the data ways. + config USE_INTEL_FSP_MP_INIT bool "Perform MP Initialization by FSP" default n diff --git a/src/soc/intel/common/block/cpu/car/cache_as_ram.S b/src/soc/intel/common/block/cpu/car/cache_as_ram.S index 74c1860..f0c3149 100644 --- a/src/soc/intel/common/block/cpu/car/cache_as_ram.S +++ b/src/soc/intel/common/block/cpu/car/cache_as_ram.S @@ -567,6 +567,13 @@ movl $IA32_CR_SF_QOS_MASK_1, %ecx wrmsr #endif +#if CONFIG(CAR_HAS_L3_PROTECTED_WAYS) + /* Set MSR 0xC85 L3_Protected_ways = ((1 << data ways) - 1) */ + mov %esi, %eax + xorl %edx, %edx + mov $IA32_L3_PROTECTED_WAYS, %ecx + wrmsr +#endif /* * Program MSR 0xC91 IA32_L3_MASK_1 * This MSR contain one bit per each way of LLC diff --git a/src/soc/intel/common/block/cpu/car/exit_car.S b/src/soc/intel/common/block/cpu/car/exit_car.S index 191232a..cfb1ab5 100644 --- a/src/soc/intel/common/block/cpu/car/exit_car.S +++ b/src/soc/intel/common/block/cpu/car/exit_car.S @@ -96,6 +96,13 @@ rdmsr and $~IA32_PQR_ASSOC_MASK, %edx wrmsr +#if CONFIG(CAR_HAS_L3_PROTECTED_WAYS) + /* Set MSR 0xC85 L3_Protected_ways = 0x00000 */ + mov $IA32_L3_PROTECTED_WAYS, %ecx + xorl %eax, %eax + xorl %edx, %edx + wrmsr +#endif #endif
/* Return to caller. */
9elements QA has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48344 )
Change subject: soc/intel/common/block/cpu: Introduce CAR_HAS_L3_PROTECTED_WAYS Kconfig ......................................................................
Patch Set 25:
Automatic boot test returned (PASS/FAIL/TOTAL): 11 / 1 / 12
PASS: x86_32 "ThinkPad T500" , build config LENOVO_T500 and payload SeaBIOS : https://lava.9esec.io/r/73018 PASS: x86_32 "HP Z220 SFF Workstation" , build config HP_Z220_SFF_WORKSTATION and payload LinuxBoot_BB_kexec : https://lava.9esec.io/r/73017 PASS: x86_64 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC.X86_64 and payload TianoCore : https://lava.9esec.io/r/73016 PASS: x86_32 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC and payload TianoCore : https://lava.9esec.io/r/73015 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35_SMM_TSEG and payload TianoCore : https://lava.9esec.io/r/73014 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35_SMM_TSEG and payload SeaBIOS : https://lava.9esec.io/r/73013 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35 and payload TianoCore : https://lava.9esec.io/r/73012 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35 and payload SeaBIOS : https://lava.9esec.io/r/73011 PASS: x86_64 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_X86_64 and payload SeaBIOS : https://lava.9esec.io/r/73010 FAIL: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_ASAN and payload SeaBIOS : https://lava.9esec.io/r/73009 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_ and payload SeaBIOS : https://lava.9esec.io/r/73008 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX and payload SeaBIOS : https://lava.9esec.io/r/73007
Please note: This test is under development and might not be accurate at all!
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9elements QA (Code Review) -
Angel Pons (Code Review)
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Furquan Shaikh (Code Review)
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Rizwan Qureshi (Code Review)
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Subrata Banik (Code Review)
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Tim Wawrzynczak (Code Review)