Attention is currently required from: Rizwan Qureshi, Subrata Banik, Angel Pons.
1 comment:
File src/soc/intel/common/block/cpu/car/cache_as_ram.S:
/*
* Program MSR 0x1892 Non-Eviction Mask #2
* IA32_CR_SF_QOS_MASK_2 = ((1 << data ways) - 1)
*/
mov %esi, %eax
xorl %edx, %edx
mov $IA32_CR_SF_QOS_MASK_2, %ecx
wrmsr
Why is this programmed only for L3 protected ways? SF QOS mask 2 must be programmed always i.e. it should be set to non-evict mask above when setting SF QOS mask 1.
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