Name of user not set #1002476 has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34686 )
Change subject: src: Kconfig: Update config for default path ......................................................................
src: Kconfig: Update config for default path
Change-Id: I35b0b08a13ad2deeb3e2efa146ab1916d5d23a14 Signed-off-by: Himanshu Sahdev himanshusah@hcl.com --- M src/cpu/intel/fsp_model_406dx/Kconfig M src/mainboard/adi/rcc-dff/Kconfig M src/mainboard/esd/atom15/Kconfig M src/mainboard/intel/bayleybay_fsp/Kconfig M src/mainboard/intel/minnowmax/Kconfig M src/mainboard/intel/mohonpeak/Kconfig M src/northbridge/intel/fsp_rangeley/fsp/Kconfig M src/soc/intel/fsp_baytrail/Kconfig M src/soc/intel/fsp_baytrail/fsp/Kconfig M src/southbridge/intel/fsp_rangeley/Kconfig 10 files changed, 9 insertions(+), 26 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/86/34686/1
diff --git a/src/cpu/intel/fsp_model_406dx/Kconfig b/src/cpu/intel/fsp_model_406dx/Kconfig index 6bf8dc7..5c981f7 100644 --- a/src/cpu/intel/fsp_model_406dx/Kconfig +++ b/src/cpu/intel/fsp_model_406dx/Kconfig @@ -56,9 +56,4 @@ string default "cpu/intel/fsp_model_406dx/bootblock.c"
-#set up microcode for rangeley POSTGOLD4 release -config CPU_MICROCODE_HEADER_FILES - string - default "../intel/cpu/rangeley/microcode/microcode-m01406d000e.h ../intel/cpu/rangeley/microcode/microcode-m01406d8128.h" - endif #CPU_INTEL_FSP_MODEL_406DX diff --git a/src/mainboard/adi/rcc-dff/Kconfig b/src/mainboard/adi/rcc-dff/Kconfig index e7be77c..ef9d091 100644 --- a/src/mainboard/adi/rcc-dff/Kconfig +++ b/src/mainboard/adi/rcc-dff/Kconfig @@ -38,7 +38,7 @@
config FSP_FILE string - default "../intel/fsp/rangeley/FvFsp.bin" + default "3rdparty/fsp/RangeleyFspBinPkg/FspBin/RangeleyFSP.fd"
config CBFS_SIZE hex diff --git a/src/mainboard/esd/atom15/Kconfig b/src/mainboard/esd/atom15/Kconfig index 5726461..9e9769f 100644 --- a/src/mainboard/esd/atom15/Kconfig +++ b/src/mainboard/esd/atom15/Kconfig @@ -37,7 +37,7 @@
config FSP_FILE string - default "../intel/fsp/baytrail/BAYTRAIL_FSP.fd" + default "3rdparty/fsp/BayTrailFspBinPkg/FspBin/BAYTRAIL_FSP.fd"
config CBFS_SIZE hex diff --git a/src/mainboard/intel/bayleybay_fsp/Kconfig b/src/mainboard/intel/bayleybay_fsp/Kconfig index 4a08fb1..833c7b2 100644 --- a/src/mainboard/intel/bayleybay_fsp/Kconfig +++ b/src/mainboard/intel/bayleybay_fsp/Kconfig @@ -39,8 +39,7 @@
config FSP_FILE string - default "../intel/fsp/baytrail/BAYTRAIL_FSP_ECC.fd" if BOARD_INTEL_BAKERSPORT_FSP - default "../intel/fsp/baytrail/BAYTRAIL_FSP.fd" + default "3rdparty/fsp/BayTrailFspBinPkg/FspBin/BAYTRAIL_FSP.fd"
config CBFS_SIZE hex diff --git a/src/mainboard/intel/minnowmax/Kconfig b/src/mainboard/intel/minnowmax/Kconfig index ca24c92..f65a180 100644 --- a/src/mainboard/intel/minnowmax/Kconfig +++ b/src/mainboard/intel/minnowmax/Kconfig @@ -37,7 +37,7 @@
config FSP_FILE string - default "../intel/fsp/baytrail/BAYTRAIL_FSP.fd" + default "3rdparty/fsp/BayTrailFspBinPkg/FspBin/BAYTRAIL_FSP.fd"
config CBFS_SIZE hex diff --git a/src/mainboard/intel/mohonpeak/Kconfig b/src/mainboard/intel/mohonpeak/Kconfig index de91ca4..1b30f3d 100644 --- a/src/mainboard/intel/mohonpeak/Kconfig +++ b/src/mainboard/intel/mohonpeak/Kconfig @@ -38,7 +38,7 @@
config FSP_FILE string - default "../intel/fsp/rangeley/FvFsp.bin" + default "3rdparty/fsp/RangeleyFspBinPkg/FspBin/RangeleyFSP.fd"
config CBFS_SIZE hex diff --git a/src/northbridge/intel/fsp_rangeley/fsp/Kconfig b/src/northbridge/intel/fsp_rangeley/fsp/Kconfig index 67ed66b..1c7fb7c 100644 --- a/src/northbridge/intel/fsp_rangeley/fsp/Kconfig +++ b/src/northbridge/intel/fsp_rangeley/fsp/Kconfig @@ -22,7 +22,7 @@
config FSP_FILE string - default "../intel/fsp/rangeley/FvFsp.bin" + default "3rdparty/fsp/RangeleyFspBinPkg/FspBin/RangeleyFSP.fd" help The path and filename of the Intel FSP binary for this platform.
diff --git a/src/soc/intel/fsp_baytrail/Kconfig b/src/soc/intel/fsp_baytrail/Kconfig index 072df29..64b4bab 100644 --- a/src/soc/intel/fsp_baytrail/Kconfig +++ b/src/soc/intel/fsp_baytrail/Kconfig @@ -97,11 +97,7 @@
config VGA_BIOS_FILE string - default "../intel/cpu/baytrail/vbios/Vga.dat" if VGA_BIOS - -config CPU_MICROCODE_HEADER_FILES - string - default "../intel/cpu/baytrail/microcode/M0130673322.h ../intel/cpu/baytrail/microcode/M0130679901.h ../intel/cpu/baytrail/microcode/M0230672228.h" + default "3rdparty/fsp/BayTrailFspBinPkg/Vbios/Vga.dat" if VGA_BIOS
## Baytrail Specific FSP Kconfig source src/soc/intel/fsp_baytrail/fsp/Kconfig diff --git a/src/soc/intel/fsp_baytrail/fsp/Kconfig b/src/soc/intel/fsp_baytrail/fsp/Kconfig index 3fe358e..b733268 100644 --- a/src/soc/intel/fsp_baytrail/fsp/Kconfig +++ b/src/soc/intel/fsp_baytrail/fsp/Kconfig @@ -21,7 +21,7 @@
config FSP_FILE string - default "../intel/fsp/baytrail/BAYTRAIL_FSP.fd" + default "3rdparty/fsp/BayTrailFspBinPkg/FspBin/BAYTRAIL_FSP.fd" help The path and filename of the Intel FSP binary for this platform.
diff --git a/src/southbridge/intel/fsp_rangeley/Kconfig b/src/southbridge/intel/fsp_rangeley/Kconfig index 4526cb3..90013de 100644 --- a/src/southbridge/intel/fsp_rangeley/Kconfig +++ b/src/southbridge/intel/fsp_rangeley/Kconfig @@ -47,12 +47,5 @@ config HPET_MIN_TICKS hex default 0x80 - -config IFD_BIN_PATH - string - depends on HAVE_IFD_BIN - default "../intel/mainboard/intel/rangeley" - help - The path and filename to the descriptor.bin file. - + endif
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34686 )
Change subject: src: Kconfig: Update config for default path ......................................................................
Patch Set 1:
(1 comment)
https://review.coreboot.org/c/coreboot/+/34686/1/src/southbridge/intel/fsp_r... File src/southbridge/intel/fsp_rangeley/Kconfig:
https://review.coreboot.org/c/coreboot/+/34686/1/src/southbridge/intel/fsp_r... PS1, Line 50: trailing whitespace
Hello Patrick Rudolph, Huang Jin, Philipp Deppenwiese, build bot (Jenkins), David Guckian,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/34686
to look at the new patch set (#2).
Change subject: src: Kconfig: Update config for default path ......................................................................
src: Kconfig: Update config for default path
Change-Id: I35b0b08a13ad2deeb3e2efa146ab1916d5d23a14 Signed-off-by: Himanshu Sahdev himanshusah@hcl.com --- M src/cpu/intel/fsp_model_406dx/Kconfig M src/mainboard/adi/rcc-dff/Kconfig M src/mainboard/esd/atom15/Kconfig M src/mainboard/intel/bayleybay_fsp/Kconfig M src/mainboard/intel/minnowmax/Kconfig M src/mainboard/intel/mohonpeak/Kconfig M src/northbridge/intel/fsp_rangeley/fsp/Kconfig M src/soc/intel/fsp_baytrail/Kconfig M src/soc/intel/fsp_baytrail/fsp/Kconfig M src/southbridge/intel/fsp_rangeley/Kconfig 10 files changed, 8 insertions(+), 25 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/86/34686/2
David Hendricks has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34686 )
Change subject: src: Kconfig: Update config for default path ......................................................................
Patch Set 2: Code-Review-1
(4 comments)
Thanks for updating the default FSP and VGA BIOS paths. However, I think you should leave the IFD and microcode paths alone until we have paths within 3rdparty/blobs to use instead. Removing the options entirely will almost certainly break things.
https://review.coreboot.org/c/coreboot/+/34686/2//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/34686/2//COMMIT_MSG@7 PS2, Line 7: src: Kconfig: Update config for default path This is too vague. How about: baytrail/rangeley: Update paths for FSP_FILE and VGA_BIOS_BIN
https://review.coreboot.org/c/coreboot/+/34686/2/src/cpu/intel/fsp_model_406... File src/cpu/intel/fsp_model_406dx/Kconfig:
https://review.coreboot.org/c/coreboot/+/34686/2/src/cpu/intel/fsp_model_406... PS2, Line 62: This will likely break things for users of this CPU. Please add the microcode header files to 3rdparty/blobs/cpu/intel/model_406dx/ and point there instead of removing this option.
https://review.coreboot.org/c/coreboot/+/34686/2/src/soc/intel/fsp_baytrail/... File src/soc/intel/fsp_baytrail/Kconfig:
https://review.coreboot.org/c/coreboot/+/34686/2/src/soc/intel/fsp_baytrail/... PS2, Line 104: Please add the microcode headers to 3rdparty/blobs/soc/intel/baytrail/ instead of removing this option all together.
https://review.coreboot.org/c/coreboot/+/34686/2/src/southbridge/intel/fsp_r... File src/southbridge/intel/fsp_rangeley/Kconfig:
https://review.coreboot.org/c/coreboot/+/34686/2/src/southbridge/intel/fsp_r... PS2, Line 51: This should probably be left alone until the mainboards which use Rangeley each have a default descriptor in 3rdparty/blobs/mainboard/
Hello Patrick Rudolph, Huang Jin, David Hendricks, Philipp Deppenwiese, build bot (Jenkins), David Guckian,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/34686
to look at the new patch set (#3).
Change subject: src: Kconfig: Update config for default path ......................................................................
src: Kconfig: Update config for default path
Change-Id: I35b0b08a13ad2deeb3e2efa146ab1916d5d23a14 Signed-off-by: Himanshu Sahdev himanshusah@hcl.com --- M src/mainboard/adi/rcc-dff/Kconfig M src/mainboard/esd/atom15/Kconfig M src/mainboard/intel/bayleybay_fsp/Kconfig M src/mainboard/intel/minnowmax/Kconfig M src/mainboard/intel/mohonpeak/Kconfig M src/northbridge/intel/fsp_rangeley/fsp/Kconfig M src/soc/intel/fsp_baytrail/Kconfig M src/soc/intel/fsp_baytrail/fsp/Kconfig 8 files changed, 8 insertions(+), 9 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/86/34686/3
Hello Patrick Rudolph, Huang Jin, David Hendricks, Philipp Deppenwiese, build bot (Jenkins), David Guckian,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/34686
to look at the new patch set (#4).
Change subject: baytrail/rangeley: Update paths for FSP_FILE and VGA_BIOS_BIN ......................................................................
baytrail/rangeley: Update paths for FSP_FILE and VGA_BIOS_BIN
Change-Id: I35b0b08a13ad2deeb3e2efa146ab1916d5d23a14 Signed-off-by: Himanshu Sahdev himanshusah@hcl.com --- M src/mainboard/adi/rcc-dff/Kconfig M src/mainboard/esd/atom15/Kconfig M src/mainboard/intel/bayleybay_fsp/Kconfig M src/mainboard/intel/minnowmax/Kconfig M src/mainboard/intel/mohonpeak/Kconfig M src/northbridge/intel/fsp_rangeley/fsp/Kconfig M src/soc/intel/fsp_baytrail/Kconfig M src/soc/intel/fsp_baytrail/fsp/Kconfig 8 files changed, 8 insertions(+), 9 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/86/34686/4
Name of user not set #1002476 has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34686 )
Change subject: baytrail/rangeley: Update paths for FSP_FILE and VGA_BIOS_BIN ......................................................................
Patch Set 4:
(4 comments)
It's done.
https://review.coreboot.org/c/coreboot/+/34686/2//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/34686/2//COMMIT_MSG@7 PS2, Line 7: src: Kconfig: Update config for default path
This is too vague. How about: […]
Ack
https://review.coreboot.org/c/coreboot/+/34686/2/src/cpu/intel/fsp_model_406... File src/cpu/intel/fsp_model_406dx/Kconfig:
https://review.coreboot.org/c/coreboot/+/34686/2/src/cpu/intel/fsp_model_406... PS2, Line 62:
This will likely break things for users of this CPU. […]
I take it back this time.
https://review.coreboot.org/c/coreboot/+/34686/2/src/soc/intel/fsp_baytrail/... File src/soc/intel/fsp_baytrail/Kconfig:
https://review.coreboot.org/c/coreboot/+/34686/2/src/soc/intel/fsp_baytrail/... PS2, Line 104:
Please add the microcode headers to 3rdparty/blobs/soc/intel/baytrail/ instead of removing this opti […]
Though I have known to this path doesn't point it out before as these headers doesn't work for me (may be I'm not lucky) on minnow board max and as binary is also present and already included as an alternative. As the files present in 3rdparty/blobs/soc/intel/baytrail/ are not exact same headers, I am leaving it as is.
https://review.coreboot.org/c/coreboot/+/34686/2/src/southbridge/intel/fsp_r... File src/southbridge/intel/fsp_rangeley/Kconfig:
https://review.coreboot.org/c/coreboot/+/34686/2/src/southbridge/intel/fsp_r... PS2, Line 51:
This should probably be left alone until the mainboards which use Rangeley each have a default descr […]
Done
David Hendricks has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34686 )
Change subject: baytrail/rangeley: Update paths for FSP_FILE and VGA_BIOS_BIN ......................................................................
Patch Set 5:
(1 comment)
https://review.coreboot.org/c/coreboot/+/34686/2/src/soc/intel/fsp_baytrail/... File src/soc/intel/fsp_baytrail/Kconfig:
https://review.coreboot.org/c/coreboot/+/34686/2/src/soc/intel/fsp_baytrail/... PS2, Line 104:
Though I have known to this path doesn't point it out before as these headers doesn't work for me (m […]
Yeah, the headers are a bit weird. I had issues a couple years ago too: https://mail.coreboot.org/pipermail/coreboot/2017-August/084837.html
You are correct that there is a microcode binary in 3rdparty/blobs/soc/intel/baytrail/ but line 48 of this Kconfig file shows that headers are selected by default (select USES_MICROCODE_HEADER_FILES if HAVE_FSP_BIN).
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34686 )
Change subject: baytrail/rangeley: Update paths for FSP_FILE and VGA_BIOS_BIN ......................................................................
Patch Set 5: Code-Review+1
(2 comments)
https://review.coreboot.org/c/coreboot/+/34686/5//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/34686/5//COMMIT_MSG@7 PS5, Line 7: Update paths for FSP_FILE and VGA_BIOS_BIN I don't see VGA_BIOS_BIN being changed, but rather VGA_BIOS_FILE. Typo?
https://review.coreboot.org/c/coreboot/+/34686/5/src/mainboard/adi/rcc-dff/K... File src/mainboard/adi/rcc-dff/Kconfig:
https://review.coreboot.org/c/coreboot/+/34686/5/src/mainboard/adi/rcc-dff/K... PS5, Line 39: config FSP_FILE I would say the mainboard-specific Kconfig is now redundant, since it defines the same filepath as the SoC Kconfig
Hello Patrick Rudolph, Angel Pons, Huang Jin, David Hendricks, Philipp Deppenwiese, build bot (Jenkins), David Guckian,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/34686
to look at the new patch set (#6).
Change subject: baytrail/rangeley: Update paths for FSP_FILE and VGA_BIOS_FILE ......................................................................
baytrail/rangeley: Update paths for FSP_FILE and VGA_BIOS_FILE
Change-Id: I35b0b08a13ad2deeb3e2efa146ab1916d5d23a14 Signed-off-by: Himanshu Sahdev himanshusah@hcl.com --- M src/mainboard/adi/rcc-dff/Kconfig M src/mainboard/esd/atom15/Kconfig M src/mainboard/intel/bayleybay_fsp/Kconfig M src/mainboard/intel/minnowmax/Kconfig M src/mainboard/intel/mohonpeak/Kconfig M src/northbridge/intel/fsp_rangeley/fsp/Kconfig M src/soc/intel/fsp_baytrail/Kconfig M src/soc/intel/fsp_baytrail/fsp/Kconfig 8 files changed, 8 insertions(+), 9 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/86/34686/6
Name of user not set #1002476 has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34686 )
Change subject: baytrail/rangeley: Update paths for FSP_FILE and VGA_BIOS_FILE ......................................................................
Patch Set 6:
(2 comments)
It's done
https://review.coreboot.org/c/coreboot/+/34686/5//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/34686/5//COMMIT_MSG@7 PS5, Line 7: Update paths for FSP_FILE and VGA_BIOS_BIN
I don't see VGA_BIOS_BIN being changed, but rather VGA_BIOS_FILE. […]
Ack
https://review.coreboot.org/c/coreboot/+/34686/5/src/mainboard/adi/rcc-dff/K... File src/mainboard/adi/rcc-dff/Kconfig:
https://review.coreboot.org/c/coreboot/+/34686/5/src/mainboard/adi/rcc-dff/K... PS5, Line 39: config FSP_FILE
I would say the mainboard-specific Kconfig is now redundant, since it defines the same filepath as t […]
Acknowledged SoC-specific Kconfig: Removing default FSP_FILE might affect other mainboards. Mainboard-specific Kconfig: preferred the default parameter(FSP_FILE) from mainboard over the soc. Also, anyone can take up initiative to clean up things with the different commit, I am just keeping the change as it is for now.
Name of user not set #1002476 has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34686 )
Change subject: baytrail/rangeley: Update paths for FSP_FILE and VGA_BIOS_FILE ......................................................................
Patch Set 6:
(1 comment)
https://review.coreboot.org/c/coreboot/+/34686/2/src/soc/intel/fsp_baytrail/... File src/soc/intel/fsp_baytrail/Kconfig:
https://review.coreboot.org/c/coreboot/+/34686/2/src/soc/intel/fsp_baytrail/... PS2, Line 104:
Yeah, the headers are a bit weird. I had issues a couple years ago too: https://mail.coreboot. […]
Yes, the line 48 select headers by default but rather I personally won't mind it there in place of the microcode binary present in 3rdparty/blobs/soc/intel/baytrail/ as it also didn't work for me (might need to be updated). I would have to get microcode externally for my board. Anyone can update Kconfig for select USES_MICROCODE_HEADER_FILES if HAVE_FSP_BIN once verified the present binary is working fine.
David Guckian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34686 )
Change subject: baytrail/rangeley: Update paths for FSP_FILE and VGA_BIOS_FILE ......................................................................
Patch Set 6: Code-Review+1
Martin L Roth has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/34686?usp=email )
Change subject: baytrail/rangeley: Update paths for FSP_FILE and VGA_BIOS_FILE ......................................................................
Abandoned
This patch has not been touched in over 12 months. Anyone who wants to take over work on this patch, please feel free to restore it and do any work needed to get it merged. If you create a new patch based on this work, please credit the original author.
-
Angel Pons (Code Review) -
build bot (Jenkins) (Code Review)
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David Guckian (Code Review)
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David Hendricks (Code Review)
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Martin L Roth (Code Review)
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Name of user not set (Code Review)