Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34840 )
Change subject: intel/smm: Provide common smm_relocation_params ......................................................................
intel/smm: Provide common smm_relocation_params
Pull in all copies of smm_relocation_params structs defined for intel platforms.
Pull in all the inlined MSR accessors to the header file.
Change-Id: I39c6cffee95433aea1a3c783b869eedfff094413 Signed-off-by: Kyösti Mälkki kyosti.malkki@gmail.com --- M src/cpu/intel/haswell/smmrelocate.c M src/cpu/intel/smm/gen1/smmrelocate.c A src/include/cpu/intel/smm_reloc.h M src/soc/intel/apollolake/cpu.c M src/soc/intel/baytrail/cpu.c M src/soc/intel/broadwell/include/soc/smm.h M src/soc/intel/broadwell/smmrelocate.c M src/soc/intel/cannonlake/include/soc/smm.h M src/soc/intel/cannonlake/smmrelocate.c M src/soc/intel/common/Makefile.inc M src/soc/intel/fsp_broadwell_de/include/soc/smm.h M src/soc/intel/fsp_broadwell_de/smmrelocate.c M src/soc/intel/icelake/include/soc/smm.h M src/soc/intel/icelake/smmrelocate.c M src/soc/intel/skylake/include/soc/smm.h M src/soc/intel/skylake/smmrelocate.c 16 files changed, 91 insertions(+), 185 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/34840/1
diff --git a/src/cpu/intel/haswell/smmrelocate.c b/src/cpu/intel/haswell/smmrelocate.c index 5cda618..5a26aff 100644 --- a/src/cpu/intel/haswell/smmrelocate.c +++ b/src/cpu/intel/haswell/smmrelocate.c @@ -25,6 +25,7 @@ #include <cpu/x86/mtrr.h> #include <cpu/x86/smm.h> #include <cpu/intel/em64t101_save_state.h> +#include <cpu/intel/smm_reloc.h> #include <console/console.h> #include <northbridge/intel/haswell/haswell.h> #include <southbridge/intel/lynxpoint/pch.h> @@ -46,49 +47,10 @@ #define SMRR_SUPPORTED (1 << 11) #define PRMRR_SUPPORTED (1 << 12)
-struct smm_relocation_params { - uintptr_t ied_base; - size_t ied_size; - msr_t smrr_base; - msr_t smrr_mask; - msr_t prmrr_base; - msr_t prmrr_mask; - msr_t uncore_prmrr_base; - msr_t uncore_prmrr_mask; - /* The smm_save_state_in_msrs field indicates if SMM save state - * locations live in MSRs. This indicates to the CPUs how to adjust - * the SMMBASE and IEDBASE */ - int smm_save_state_in_msrs; -};
/* This gets filled in and used during relocation. */ -static struct smm_relocation_params smm_reloc_params; +struct smm_relocation_params smm_reloc_params;
-static inline void write_smrr(struct smm_relocation_params *relo_params) -{ - printk(BIOS_DEBUG, "Writing SMRR. base = 0x%08x, mask=0x%08x\n", - relo_params->smrr_base.lo, relo_params->smrr_mask.lo); - wrmsr(IA32_SMRR_PHYS_BASE, relo_params->smrr_base); - wrmsr(IA32_SMRR_PHYS_MASK, relo_params->smrr_mask); -} - -static inline void write_prmrr(struct smm_relocation_params *relo_params) -{ - printk(BIOS_DEBUG, "Writing PRMRR. base = 0x%08x, mask=0x%08x\n", - relo_params->prmrr_base.lo, relo_params->prmrr_mask.lo); - wrmsr(MSR_PRMRR_PHYS_BASE, relo_params->prmrr_base); - wrmsr(MSR_PRMRR_PHYS_MASK, relo_params->prmrr_mask); -} - -static inline void write_uncore_prmrr(struct smm_relocation_params *relo_params) -{ - printk(BIOS_DEBUG, - "Writing UNCORE_PRMRR. base = 0x%08x, mask=0x%08x\n", - relo_params->uncore_prmrr_base.lo, - relo_params->uncore_prmrr_mask.lo); - wrmsr(MSR_UNCORE_PRMRR_PHYS_BASE, relo_params->uncore_prmrr_base); - wrmsr(MSR_UNCORE_PRMRR_PHYS_MASK, relo_params->uncore_prmrr_mask); -}
static void update_save_state(int cpu, uintptr_t curr_smbase, uintptr_t staggered_smbase, diff --git a/src/cpu/intel/smm/gen1/smmrelocate.c b/src/cpu/intel/smm/gen1/smmrelocate.c index d200805..bb19c8c 100644 --- a/src/cpu/intel/smm/gen1/smmrelocate.c +++ b/src/cpu/intel/smm/gen1/smmrelocate.c @@ -28,6 +28,7 @@ #include <cpu/x86/mtrr.h> #include <cpu/x86/smm.h> #include <cpu/intel/em64t101_save_state.h> +#include <cpu/intel/smm_reloc.h> #include <console/console.h> #include <smp/node.h> #include "smi.h" @@ -47,15 +48,9 @@ } __packed;
-struct smm_relocation_params { - uintptr_t ied_base; - size_t ied_size; - msr_t smrr_base; - msr_t smrr_mask; -};
/* This gets filled in and used during relocation. */ -static struct smm_relocation_params smm_reloc_params; +struct smm_relocation_params smm_reloc_params;
/* On model_6fx, model_1067x and model_106cx SMRR functions slightly differently. The MSR are at different location from the rest @@ -95,15 +90,6 @@ wrmsr(MSR_SMRR_PHYS_MASK, relo_params->smrr_mask); }
-static void write_smrr(struct smm_relocation_params *relo_params) -{ - printk(BIOS_DEBUG, "Writing SMRR. base = 0x%08x, mask=0x%08x\n", - relo_params->smrr_base.lo, relo_params->smrr_mask.lo); - - wrmsr(IA32_SMRR_PHYS_BASE, relo_params->smrr_base); - wrmsr(IA32_SMRR_PHYS_MASK, relo_params->smrr_mask); -} - static void fill_in_relocation_params(struct smm_relocation_params *params) { uintptr_t tseg_base; diff --git a/src/include/cpu/intel/smm_reloc.h b/src/include/cpu/intel/smm_reloc.h new file mode 100644 index 0000000..cbcdb56 --- /dev/null +++ b/src/include/cpu/intel/smm_reloc.h @@ -0,0 +1,73 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __INTEL_SMM_RELOC_H__ +#define __INTEL_SMM_RELOC_H__ + +#include <console/console.h> +#include <cpu/x86/msr.h> +#include <cpu/x86/mtrr.h> + +struct smm_relocation_params { + uintptr_t ied_base; + size_t ied_size; + msr_t smrr_base; + msr_t smrr_mask; + msr_t prmrr_base; + msr_t prmrr_mask; + msr_t uncore_prmrr_base; + msr_t uncore_prmrr_mask; + /* + * The smm_save_state_in_msrs field indicates if SMM save state + * locations live in MSRs. This indicates to the CPUs how to adjust + * the SMMBASE and IEDBASE + */ + int smm_save_state_in_msrs; +}; + +extern struct smm_relocation_params smm_reloc_params; + +void fill_in_smrr(struct smm_relocation_params *params); + +#define MSR_PRMRR_PHYS_BASE 0x1f4 +#define MSR_PRMRR_PHYS_MASK 0x1f5 +#define MSR_UNCORE_PRMRR_PHYS_BASE 0x2f4 +#define MSR_UNCORE_PRMRR_PHYS_MASK 0x2f5 + +static inline void write_smrr(struct smm_relocation_params *relo_params) +{ + printk(BIOS_DEBUG, "Writing SMRR. base = 0x%08x, mask=0x%08x\n", + relo_params->smrr_base.lo, relo_params->smrr_mask.lo); + wrmsr(IA32_SMRR_PHYS_BASE, relo_params->smrr_base); + wrmsr(IA32_SMRR_PHYS_MASK, relo_params->smrr_mask); +} + +static inline void write_prmrr(struct smm_relocation_params *relo_params) +{ + printk(BIOS_DEBUG, "Writing PRMRR. base = 0x%08x, mask=0x%08x\n", + relo_params->prmrr_base.lo, relo_params->prmrr_mask.lo); + wrmsr(MSR_PRMRR_PHYS_BASE, relo_params->prmrr_base); + wrmsr(MSR_PRMRR_PHYS_MASK, relo_params->prmrr_mask); +} + +static inline void write_uncore_prmrr(struct smm_relocation_params *relo_params) +{ + printk(BIOS_DEBUG, + "Writing UNCORE_PRMRR. base = 0x%08x, mask=0x%08x\n", + relo_params->uncore_prmrr_base.lo, + relo_params->uncore_prmrr_mask.lo); + wrmsr(MSR_UNCORE_PRMRR_PHYS_BASE, relo_params->uncore_prmrr_base); + wrmsr(MSR_UNCORE_PRMRR_PHYS_MASK, relo_params->uncore_prmrr_mask); +} + +#endif diff --git a/src/soc/intel/apollolake/cpu.c b/src/soc/intel/apollolake/cpu.c index 9fbcc07..e834142 100644 --- a/src/soc/intel/apollolake/cpu.c +++ b/src/soc/intel/apollolake/cpu.c @@ -31,6 +31,7 @@ #include <cpu/x86/mtrr.h> #include <cpu/x86/smm.h> #include <cpu/intel/em64t100_save_state.h> +#include <cpu/intel/smm_reloc.h> #include <device/device.h> #include <device/pci.h> #include <fsp/api.h> diff --git a/src/soc/intel/baytrail/cpu.c b/src/soc/intel/baytrail/cpu.c index d25a740..05d7a82 100644 --- a/src/soc/intel/baytrail/cpu.c +++ b/src/soc/intel/baytrail/cpu.c @@ -26,6 +26,7 @@ #include <cpu/x86/mtrr.h> #include <cpu/x86/smm.h> #include <cpu/intel/em64t100_save_state.h> +#include <cpu/intel/smm_reloc.h> #include <reg_script.h>
#include <soc/iosf.h> diff --git a/src/soc/intel/broadwell/include/soc/smm.h b/src/soc/intel/broadwell/include/soc/smm.h index 9ad3128..08c1ad8 100644 --- a/src/soc/intel/broadwell/include/soc/smm.h +++ b/src/soc/intel/broadwell/include/soc/smm.h @@ -25,20 +25,6 @@ u8 reserved[34]; } __packed;
-struct smm_relocation_params { - uintptr_t ied_base; - size_t ied_size; - msr_t smrr_base; - msr_t smrr_mask; - msr_t prmrr_base; - msr_t prmrr_mask; - msr_t uncore_prmrr_base; - msr_t uncore_prmrr_mask; - /* The smm_save_state_in_msrs field indicates if SMM save state - * locations live in MSRs. This indicates to the CPUs how to adjust - * the SMMBASE and IEDBASE */ - int smm_save_state_in_msrs; -};
void smm_relocation_handler(int cpu, uintptr_t curr_smbase, uintptr_t staggered_smbase); diff --git a/src/soc/intel/broadwell/smmrelocate.c b/src/soc/intel/broadwell/smmrelocate.c index 2cf97e3..5cac560 100644 --- a/src/soc/intel/broadwell/smmrelocate.c +++ b/src/soc/intel/broadwell/smmrelocate.c @@ -25,6 +25,7 @@ #include <cpu/x86/mtrr.h> #include <cpu/x86/smm.h> #include <cpu/intel/em64t101_save_state.h> +#include <cpu/intel/smm_reloc.h> #include <console/console.h> #include <soc/cpu.h> #include <soc/msr.h> @@ -33,33 +34,8 @@ #include <soc/systemagent.h>
/* This gets filled in and used during relocation. */ -static struct smm_relocation_params smm_reloc_params; +struct smm_relocation_params smm_reloc_params;
-static inline void write_smrr(struct smm_relocation_params *relo_params) -{ - printk(BIOS_DEBUG, "Writing SMRR. base = 0x%08x, mask=0x%08x\n", - relo_params->smrr_base.lo, relo_params->smrr_mask.lo); - wrmsr(IA32_SMRR_PHYS_BASE, relo_params->smrr_base); - wrmsr(IA32_SMRR_PHYS_MASK, relo_params->smrr_mask); -} - -static inline void write_prmrr(struct smm_relocation_params *relo_params) -{ - printk(BIOS_DEBUG, "Writing PRMRR. base = 0x%08x, mask=0x%08x\n", - relo_params->prmrr_base.lo, relo_params->prmrr_mask.lo); - wrmsr(MSR_PRMRR_PHYS_BASE, relo_params->prmrr_base); - wrmsr(MSR_PRMRR_PHYS_MASK, relo_params->prmrr_mask); -} - -static inline void write_uncore_prmrr(struct smm_relocation_params *relo_params) -{ - printk(BIOS_DEBUG, - "Writing UNCORE_PRMRR. base = 0x%08x, mask=0x%08x\n", - relo_params->uncore_prmrr_base.lo, - relo_params->uncore_prmrr_mask.lo); - wrmsr(MSR_UNCORE_PRMRR_PHYS_BASE, relo_params->uncore_prmrr_base); - wrmsr(MSR_UNCORE_PRMRR_PHYS_MASK, relo_params->uncore_prmrr_mask); -}
static void update_save_state(int cpu, uintptr_t curr_smbase, uintptr_t staggered_smbase, diff --git a/src/soc/intel/cannonlake/include/soc/smm.h b/src/soc/intel/cannonlake/include/soc/smm.h index ed8cbef..3c1f35c 100644 --- a/src/soc/intel/cannonlake/include/soc/smm.h +++ b/src/soc/intel/cannonlake/include/soc/smm.h @@ -28,19 +28,6 @@ u8 reserved[34]; } __packed;
-struct smm_relocation_params { - uintptr_t ied_base; - size_t ied_size; - msr_t smrr_base; - msr_t smrr_mask; - /* - * The smm_save_state_in_msrs field indicates if SMM save state - * locations live in MSRs. This indicates to the CPUs how to adjust - * the SMMBASE and IEDBASE - */ - int smm_save_state_in_msrs; -}; - /* Mainboard handler for eSPI SMIs */ void mainboard_smi_espi_handler(void);
diff --git a/src/soc/intel/cannonlake/smmrelocate.c b/src/soc/intel/cannonlake/smmrelocate.c index 3da1a56..a552b58 100644 --- a/src/soc/intel/cannonlake/smmrelocate.c +++ b/src/soc/intel/cannonlake/smmrelocate.c @@ -27,6 +27,7 @@ #include <cpu/x86/mtrr.h> #include <cpu/x86/smm.h> #include <cpu/intel/em64t101_save_state.h> +#include <cpu/intel/smm_reloc.h> #include <console/console.h> #include <intelblocks/smm.h> #include <soc/cpu.h> @@ -37,15 +38,8 @@ #include "chip.h"
/* This gets filled in and used during relocation. */ -static struct smm_relocation_params smm_reloc_params; +struct smm_relocation_params smm_reloc_params;
-static inline void write_smrr(struct smm_relocation_params *relo_params) -{ - printk(BIOS_DEBUG, "Writing SMRR. base = 0x%08x, mask=0x%08x\n", - relo_params->smrr_base.lo, relo_params->smrr_mask.lo); - wrmsr(IA32_SMRR_PHYS_BASE, relo_params->smrr_base); - wrmsr(IA32_SMRR_PHYS_MASK, relo_params->smrr_mask); -}
static void update_save_state(int cpu, uintptr_t curr_smbase, uintptr_t staggered_smbase, diff --git a/src/soc/intel/common/Makefile.inc b/src/soc/intel/common/Makefile.inc index 22d350c..b5d45bb 100644 --- a/src/soc/intel/common/Makefile.inc +++ b/src/soc/intel/common/Makefile.inc @@ -4,6 +4,8 @@ subdirs-y += block/ subdirs-y += pch/
+subdirs-y += ../../../cpu/intel/smm + verstage-$(CONFIG_SOC_INTEL_COMMON_RESET) += reset.c
bootblock-$(CONFIG_SOC_INTEL_COMMON_RESET) += reset.c diff --git a/src/soc/intel/fsp_broadwell_de/include/soc/smm.h b/src/soc/intel/fsp_broadwell_de/include/soc/smm.h index 3307cb0..3040688 100644 --- a/src/soc/intel/fsp_broadwell_de/include/soc/smm.h +++ b/src/soc/intel/fsp_broadwell_de/include/soc/smm.h @@ -26,18 +26,6 @@ u8 reserved[34]; } __packed;
-struct smm_relocation_params { - uintptr_t ied_base; - size_t ied_size; - msr_t smrr_base; - msr_t smrr_mask; - msr_t prmrr_base; - msr_t prmrr_mask; - /* The smm_save_state_in_msrs field indicates if SMM save state - locations live in MSRs. This indicates to the CPUs how to adjust - the SMMBASE and IEDBASE. */ - int smm_save_state_in_msrs; -};
void smm_relocation_handler(int cpu, uintptr_t curr_smbase, uintptr_t staggered_smbase); diff --git a/src/soc/intel/fsp_broadwell_de/smmrelocate.c b/src/soc/intel/fsp_broadwell_de/smmrelocate.c index 283f5c1..d797438 100644 --- a/src/soc/intel/fsp_broadwell_de/smmrelocate.c +++ b/src/soc/intel/fsp_broadwell_de/smmrelocate.c @@ -24,6 +24,7 @@ #include <cpu/x86/mtrr.h> #include <cpu/x86/smm.h> #include <cpu/intel/em64t101_save_state.h> +#include <cpu/intel/smm_reloc.h> #include <console/console.h> #include <device/pci_ops.h> #include <soc/lpc.h> @@ -33,23 +34,8 @@ #include <soc/broadwell_de.h>
/* This gets filled in and used during relocation. */ -static struct smm_relocation_params smm_reloc_params; +struct smm_relocation_params smm_reloc_params;
-static inline void write_smrr(struct smm_relocation_params *relo_params) -{ - printk(BIOS_DEBUG, "Writing SMRR. base = 0x%08x, mask=0x%08x\n", - relo_params->smrr_base.lo, relo_params->smrr_mask.lo); - wrmsr(IA32_SMRR_PHYS_BASE, relo_params->smrr_base); - wrmsr(IA32_SMRR_PHYS_MASK, relo_params->smrr_mask); -} - -static inline void write_prmrr(struct smm_relocation_params *relo_params) -{ - printk(BIOS_DEBUG, "Writing PRMRR. base = 0x%08x, mask=0x%08x\n", - relo_params->prmrr_base.lo, relo_params->prmrr_mask.lo); - wrmsr(MSR_PRMRR_PHYS_BASE, relo_params->prmrr_base); - wrmsr(MSR_PRMRR_PHYS_MASK, relo_params->prmrr_mask); -}
static void update_save_state(int cpu, uintptr_t curr_smbase, uintptr_t staggered_smbase, diff --git a/src/soc/intel/icelake/include/soc/smm.h b/src/soc/intel/icelake/include/soc/smm.h index 5d64d3b..b427085 100644 --- a/src/soc/intel/icelake/include/soc/smm.h +++ b/src/soc/intel/icelake/include/soc/smm.h @@ -27,18 +27,6 @@ u8 reserved[34]; } __packed;
-struct smm_relocation_params { - uintptr_t ied_base; - size_t ied_size; - msr_t smrr_base; - msr_t smrr_mask; - /* - * The smm_save_state_in_msrs field indicates if SMM save state - * locations live in MSRs. This indicates to the CPUs how to adjust - * the SMMBASE and IEDBASE - */ - int smm_save_state_in_msrs; -};
/* Mainboard handler for eSPI SMIs */ void mainboard_smi_espi_handler(void); diff --git a/src/soc/intel/icelake/smmrelocate.c b/src/soc/intel/icelake/smmrelocate.c index 3e949b2..21b9a13 100644 --- a/src/soc/intel/icelake/smmrelocate.c +++ b/src/soc/intel/icelake/smmrelocate.c @@ -26,6 +26,7 @@ #include <cpu/x86/mtrr.h> #include <cpu/x86/smm.h> #include <cpu/intel/em64t101_save_state.h> +#include <cpu/intel/smm_reloc.h> #include <console/console.h> #include <intelblocks/smm.h> #include <soc/cpu.h> @@ -36,15 +37,8 @@ #include <soc/systemagent.h>
/* This gets filled in and used during relocation. */ -static struct smm_relocation_params smm_reloc_params; +struct smm_relocation_params smm_reloc_params;
-static inline void write_smrr(struct smm_relocation_params *relo_params) -{ - printk(BIOS_DEBUG, "Writing SMRR. base = 0x%08x, mask=0x%08x\n", - relo_params->smrr_base.lo, relo_params->smrr_mask.lo); - wrmsr(IA32_SMRR_PHYS_BASE, relo_params->smrr_base); - wrmsr(IA32_SMRR_PHYS_MASK, relo_params->smrr_mask); -}
static void update_save_state(int cpu, uintptr_t curr_smbase, uintptr_t staggered_smbase, diff --git a/src/soc/intel/skylake/include/soc/smm.h b/src/soc/intel/skylake/include/soc/smm.h index 6eb6b1e..8fa415c 100644 --- a/src/soc/intel/skylake/include/soc/smm.h +++ b/src/soc/intel/skylake/include/soc/smm.h @@ -29,18 +29,6 @@ u8 reserved[34]; } __packed;
-struct smm_relocation_params { - uintptr_t ied_base; - size_t ied_size; - msr_t smrr_base; - msr_t smrr_mask; - /* - * The smm_save_state_in_msrs field indicates if SMM save state - * locations live in MSRs. This indicates to the CPUs how to adjust - * the SMMBASE and IEDBASE - */ - int smm_save_state_in_msrs; -};
void smm_relocation_handler(int cpu, uintptr_t curr_smbase, uintptr_t staggered_smbase); diff --git a/src/soc/intel/skylake/smmrelocate.c b/src/soc/intel/skylake/smmrelocate.c index ebb853a..b80aa14 100644 --- a/src/soc/intel/skylake/smmrelocate.c +++ b/src/soc/intel/skylake/smmrelocate.c @@ -26,6 +26,7 @@ #include <cpu/x86/mtrr.h> #include <cpu/x86/smm.h> #include <cpu/intel/em64t101_save_state.h> +#include <cpu/intel/smm_reloc.h> #include <console/console.h> #include <intelblocks/smm.h> #include <soc/cpu.h> @@ -36,15 +37,8 @@ #include "chip.h"
/* This gets filled in and used during relocation. */ -static struct smm_relocation_params smm_reloc_params; +struct smm_relocation_params smm_reloc_params;
-static inline void write_smrr(struct smm_relocation_params *relo_params) -{ - printk(BIOS_DEBUG, "Writing SMRR. base = 0x%08x, mask=0x%08x\n", - relo_params->smrr_base.lo, relo_params->smrr_mask.lo); - wrmsr(IA32_SMRR_PHYS_BASE, relo_params->smrr_base); - wrmsr(IA32_SMRR_PHYS_MASK, relo_params->smrr_mask); -}
static void update_save_state(int cpu, uintptr_t curr_smbase, uintptr_t staggered_smbase,
Hello Patrick Rudolph, Philipp Deppenwiese, build bot (Jenkins), Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/34840
to look at the new patch set (#2).
Change subject: intel/smm: Provide common smm_relocation_params ......................................................................
intel/smm: Provide common smm_relocation_params
Pull in all copies of smm_relocation_params structs defined for intel platforms.
Pull in all the inlined MSR accessors to the header file.
Change-Id: I39c6cffee95433aea1a3c783b869eedfff094413 Signed-off-by: Kyösti Mälkki kyosti.malkki@gmail.com --- M src/cpu/intel/haswell/smmrelocate.c A src/cpu/intel/smm/Makefile.inc M src/cpu/intel/smm/gen1/smmrelocate.c A src/cpu/intel/smm/smm_reloc.c A src/include/cpu/intel/smm_reloc.h M src/soc/intel/apollolake/cpu.c M src/soc/intel/baytrail/cpu.c M src/soc/intel/braswell/cpu.c M src/soc/intel/broadwell/include/soc/smm.h M src/soc/intel/broadwell/smmrelocate.c M src/soc/intel/cannonlake/include/soc/smm.h M src/soc/intel/cannonlake/smmrelocate.c M src/soc/intel/common/Makefile.inc M src/soc/intel/fsp_baytrail/cpu.c M src/soc/intel/fsp_broadwell_de/include/soc/smm.h M src/soc/intel/fsp_broadwell_de/smmrelocate.c M src/soc/intel/icelake/include/soc/smm.h M src/soc/intel/icelake/smmrelocate.c M src/soc/intel/skylake/include/soc/smm.h M src/soc/intel/skylake/smmrelocate.c 20 files changed, 99 insertions(+), 220 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/34840/2
Hello Patrick Rudolph, Huang Jin, Philipp Deppenwiese, build bot (Jenkins), Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/34840
to look at the new patch set (#3).
Change subject: intel/smm: Provide common smm_relocation_params ......................................................................
intel/smm: Provide common smm_relocation_params
Pull in all copies of smm_relocation_params structs defined for intel platforms.
Pull in all the inlined MSR accessors to the header file.
Change-Id: I39c6cffee95433aea1a3c783b869eedfff094413 Signed-off-by: Kyösti Mälkki kyosti.malkki@gmail.com --- M src/cpu/intel/haswell/smmrelocate.c A src/cpu/intel/smm/Makefile.inc M src/cpu/intel/smm/gen1/smmrelocate.c A src/cpu/intel/smm/smm_reloc.c M src/cpu/x86/Makefile.inc A src/include/cpu/intel/smm_reloc.h M src/soc/intel/apollolake/cpu.c M src/soc/intel/baytrail/cpu.c M src/soc/intel/braswell/cpu.c M src/soc/intel/broadwell/include/soc/smm.h M src/soc/intel/broadwell/smmrelocate.c M src/soc/intel/cannonlake/include/soc/smm.h M src/soc/intel/cannonlake/smmrelocate.c M src/soc/intel/fsp_baytrail/cpu.c M src/soc/intel/fsp_broadwell_de/include/soc/smm.h M src/soc/intel/fsp_broadwell_de/smmrelocate.c M src/soc/intel/icelake/include/soc/smm.h M src/soc/intel/icelake/smmrelocate.c M src/soc/intel/skylake/include/soc/smm.h M src/soc/intel/skylake/smmrelocate.c 20 files changed, 100 insertions(+), 220 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/34840/3
Hello Patrick Rudolph, Huang Jin, Philipp Deppenwiese, build bot (Jenkins), Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/34840
to look at the new patch set (#4).
Change subject: intel/smm: Provide common smm_relocation_params ......................................................................
intel/smm: Provide common smm_relocation_params
Pull in all copies of smm_relocation_params structs defined for intel platforms.
Pull in all the inlined MSR accessors to the header file.
Change-Id: I39c6cffee95433aea1a3c783b869eedfff094413 Signed-off-by: Kyösti Mälkki kyosti.malkki@gmail.com --- M src/cpu/intel/haswell/smmrelocate.c A src/cpu/intel/smm/Makefile.inc M src/cpu/intel/smm/gen1/smmrelocate.c A src/cpu/intel/smm/smm_reloc.c M src/cpu/x86/Makefile.inc A src/include/cpu/intel/smm_reloc.h M src/soc/intel/apollolake/cpu.c M src/soc/intel/baytrail/cpu.c M src/soc/intel/braswell/cpu.c M src/soc/intel/broadwell/include/soc/smm.h M src/soc/intel/broadwell/smmrelocate.c M src/soc/intel/cannonlake/include/soc/smm.h M src/soc/intel/cannonlake/smmrelocate.c M src/soc/intel/fsp_baytrail/cpu.c M src/soc/intel/fsp_broadwell_de/include/soc/smm.h M src/soc/intel/fsp_broadwell_de/smmrelocate.c M src/soc/intel/icelake/include/soc/smm.h M src/soc/intel/icelake/smmrelocate.c M src/soc/intel/skylake/include/soc/smm.h M src/soc/intel/skylake/smmrelocate.c 20 files changed, 104 insertions(+), 222 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/34840/4
Hello Aaron Durbin, Patrick Rudolph, Huang Jin, Arthur Heymans, Philipp Deppenwiese, build bot (Jenkins), Furquan Shaikh, Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/34840
to look at the new patch set (#6).
Change subject: intel/smm: Provide common smm_relocation_params ......................................................................
intel/smm: Provide common smm_relocation_params
Pull in all copies of smm_relocation_params structs defined for intel platforms.
Pull in all the inlined MSR accessors to the header file.
Change-Id: I39c6cffee95433aea1a3c783b869eedfff094413 Signed-off-by: Kyösti Mälkki kyosti.malkki@gmail.com --- M src/cpu/intel/haswell/smmrelocate.c A src/cpu/intel/smm/Makefile.inc M src/cpu/intel/smm/gen1/smmrelocate.c A src/cpu/intel/smm/smm_reloc.c M src/cpu/x86/Makefile.inc M src/include/cpu/intel/smm_reloc.h M src/soc/intel/baytrail/cpu.c M src/soc/intel/braswell/cpu.c M src/soc/intel/broadwell/cpu.c M src/soc/intel/broadwell/include/soc/smm.h M src/soc/intel/broadwell/memmap.c M src/soc/intel/broadwell/pei_data.c M src/soc/intel/broadwell/romstage/raminit.c M src/soc/intel/broadwell/smi.c M src/soc/intel/broadwell/smihandler.c M src/soc/intel/broadwell/smmrelocate.c M src/soc/intel/cannonlake/cpu.c M src/soc/intel/cannonlake/include/soc/smm.h M src/soc/intel/cannonlake/smmrelocate.c M src/soc/intel/fsp_baytrail/cpu.c M src/soc/intel/fsp_baytrail/include/soc/smm.h M src/soc/intel/fsp_broadwell_de/cpu.c M src/soc/intel/fsp_broadwell_de/include/soc/smm.h M src/soc/intel/fsp_broadwell_de/smi.c M src/soc/intel/fsp_broadwell_de/smihandler.c M src/soc/intel/fsp_broadwell_de/smmrelocate.c M src/soc/intel/icelake/cpu.c M src/soc/intel/icelake/include/soc/smm.h M src/soc/intel/icelake/smmrelocate.c M src/soc/intel/skylake/cpu.c M src/soc/intel/skylake/include/soc/smm.h M src/soc/intel/skylake/smmrelocate.c 32 files changed, 74 insertions(+), 387 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/34840/6
Hello Aaron Durbin, Patrick Rudolph, Huang Jin, Arthur Heymans, Philipp Deppenwiese, build bot (Jenkins), Furquan Shaikh, Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/34840
to look at the new patch set (#7).
Change subject: intel/smm: Provide common smm_relocation_params ......................................................................
intel/smm: Provide common smm_relocation_params
Pull in all copies of smm_relocation_params structs defined for intel platforms.
Pull in all the inlined MSR accessors to the header file.
Change-Id: I39c6cffee95433aea1a3c783b869eedfff094413 Signed-off-by: Kyösti Mälkki kyosti.malkki@gmail.com --- M src/cpu/intel/haswell/smmrelocate.c A src/cpu/intel/smm/Makefile.inc M src/cpu/intel/smm/gen1/smmrelocate.c A src/cpu/intel/smm/smm_reloc.c M src/cpu/x86/Makefile.inc M src/include/cpu/intel/smm_reloc.h M src/soc/intel/baytrail/cpu.c M src/soc/intel/braswell/cpu.c M src/soc/intel/broadwell/cpu.c M src/soc/intel/broadwell/include/soc/smm.h M src/soc/intel/broadwell/memmap.c M src/soc/intel/broadwell/pei_data.c M src/soc/intel/broadwell/romstage/raminit.c M src/soc/intel/broadwell/smi.c M src/soc/intel/broadwell/smihandler.c M src/soc/intel/broadwell/smmrelocate.c M src/soc/intel/cannonlake/cpu.c M src/soc/intel/cannonlake/include/soc/smm.h M src/soc/intel/cannonlake/smmrelocate.c M src/soc/intel/fsp_baytrail/cpu.c M src/soc/intel/fsp_baytrail/include/soc/smm.h M src/soc/intel/fsp_broadwell_de/cpu.c M src/soc/intel/fsp_broadwell_de/include/soc/smm.h M src/soc/intel/fsp_broadwell_de/smi.c M src/soc/intel/fsp_broadwell_de/smihandler.c M src/soc/intel/fsp_broadwell_de/smmrelocate.c M src/soc/intel/icelake/cpu.c M src/soc/intel/icelake/include/soc/smm.h M src/soc/intel/icelake/smmrelocate.c M src/soc/intel/skylake/cpu.c M src/soc/intel/skylake/include/soc/smm.h M src/soc/intel/skylake/smmrelocate.c 32 files changed, 73 insertions(+), 387 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/34840/7
Aaron Durbin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34840 )
Change subject: intel/smm: Provide common smm_relocation_params ......................................................................
Patch Set 7:
(2 comments)
https://review.coreboot.org/c/coreboot/+/34840/7/src/cpu/x86/Makefile.inc File src/cpu/x86/Makefile.inc:
https://review.coreboot.org/c/coreboot/+/34840/7/src/cpu/x86/Makefile.inc@9 PS7, Line 9: # This is hacky. Indeed. Can we not conditionalize it?
https://review.coreboot.org/c/coreboot/+/34840/7/src/include/cpu/intel/smm_r... File src/include/cpu/intel/smm_reloc.h:
https://review.coreboot.org/c/coreboot/+/34840/7/src/include/cpu/intel/smm_r... PS7, Line 88: static inline void write_smrr(struct smm_relocation_params *relo_params) const on the types for these files?
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34840 )
Change subject: intel/smm: Provide common smm_relocation_params ......................................................................
Patch Set 8:
(1 comment)
https://review.coreboot.org/c/coreboot/+/34840/8/src/soc/intel/fsp_broadwell... File src/soc/intel/fsp_broadwell_de/include/soc/smm.h:
PS8: Looks like it could be removed later.
Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34840 )
Change subject: intel/smm: Provide common smm_relocation_params ......................................................................
Patch Set 8:
(1 comment)
https://review.coreboot.org/c/coreboot/+/34840/8/src/soc/intel/fsp_broadwell... File src/soc/intel/fsp_broadwell_de/include/soc/smm.h:
PS8:
Looks like it could be removed later.
That will happen, it was just easier first to keep the empty #include in place.
Aaron Durbin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34840 )
Change subject: intel/smm: Provide common smm_relocation_params ......................................................................
Patch Set 10: Code-Review+2
Hello Aaron Durbin, Patrick Rudolph, Huang Jin, Arthur Heymans, Philipp Deppenwiese, build bot (Jenkins), Furquan Shaikh, Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/34840
to look at the new patch set (#11).
Change subject: intel/smm: Provide common smm_relocation_params ......................................................................
intel/smm: Provide common smm_relocation_params
Pull in all copies of smm_relocation_params structs defined for intel platforms.
Pull in all the inlined MSR accessors to the header file.
Change-Id: I39c6cffee95433aea1a3c783b869eedfff094413 Signed-off-by: Kyösti Mälkki kyosti.malkki@gmail.com --- M src/cpu/intel/haswell/smmrelocate.c A src/cpu/intel/smm/Makefile.inc M src/cpu/intel/smm/gen1/smmrelocate.c R src/cpu/intel/smm/smm_reloc.c M src/cpu/x86/Makefile.inc M src/include/cpu/intel/smm_reloc.h M src/mainboard/google/auron/smihandler.c M src/mainboard/google/jecht/smihandler.c M src/soc/intel/baytrail/cpu.c M src/soc/intel/braswell/cpu.c M src/soc/intel/broadwell/cpu.c D src/soc/intel/broadwell/include/soc/smm.h M src/soc/intel/broadwell/memmap.c M src/soc/intel/broadwell/pei_data.c M src/soc/intel/broadwell/romstage/raminit.c M src/soc/intel/broadwell/smi.c M src/soc/intel/broadwell/smihandler.c M src/soc/intel/broadwell/smmrelocate.c M src/soc/intel/cannonlake/cpu.c D src/soc/intel/cannonlake/include/soc/smm.h M src/soc/intel/cannonlake/smmrelocate.c M src/soc/intel/fsp_baytrail/cpu.c M src/soc/intel/fsp_broadwell_de/cpu.c D src/soc/intel/fsp_broadwell_de/include/soc/smm.h M src/soc/intel/fsp_broadwell_de/smi.c M src/soc/intel/fsp_broadwell_de/smihandler.c M src/soc/intel/fsp_broadwell_de/smmrelocate.c M src/soc/intel/icelake/cpu.c D src/soc/intel/icelake/include/soc/smm.h M src/soc/intel/icelake/smmrelocate.c M src/soc/intel/skylake/cpu.c D src/soc/intel/skylake/include/soc/smm.h M src/soc/intel/skylake/smmrelocate.c M src/soc/intel/tigerlake/cpu.c D src/soc/intel/tigerlake/include/soc/smm.h M src/soc/intel/tigerlake/smmrelocate.c 36 files changed, 59 insertions(+), 421 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/34840/11
Hello Aaron Durbin, Patrick Rudolph, Huang Jin, Arthur Heymans, Philipp Deppenwiese, build bot (Jenkins), Furquan Shaikh, Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/34840
to look at the new patch set (#13).
Change subject: intel/smm: Provide common smm_relocation_params ......................................................................
intel/smm: Provide common smm_relocation_params
Pull in all copies of smm_relocation_params structs defined for intel platforms.
Pull in all the inlined MSR accessors to the header file.
Change-Id: I39c6cffee95433aea1a3c783b869eedfff094413 Signed-off-by: Kyösti Mälkki kyosti.malkki@gmail.com --- M src/cpu/intel/haswell/smmrelocate.c A src/cpu/intel/smm/Makefile.inc M src/cpu/intel/smm/gen1/smmrelocate.c R src/cpu/intel/smm/smm_reloc.c M src/cpu/x86/Makefile.inc M src/include/cpu/intel/smm_reloc.h M src/mainboard/google/auron/smihandler.c M src/mainboard/google/jecht/smihandler.c M src/soc/intel/baytrail/cpu.c M src/soc/intel/braswell/cpu.c M src/soc/intel/broadwell/cpu.c D src/soc/intel/broadwell/include/soc/smm.h M src/soc/intel/broadwell/memmap.c M src/soc/intel/broadwell/pei_data.c M src/soc/intel/broadwell/romstage/raminit.c M src/soc/intel/broadwell/smi.c M src/soc/intel/broadwell/smihandler.c M src/soc/intel/broadwell/smmrelocate.c M src/soc/intel/cannonlake/cpu.c D src/soc/intel/cannonlake/include/soc/smm.h M src/soc/intel/cannonlake/smmrelocate.c M src/soc/intel/fsp_baytrail/cpu.c M src/soc/intel/fsp_broadwell_de/cpu.c D src/soc/intel/fsp_broadwell_de/include/soc/smm.h M src/soc/intel/fsp_broadwell_de/smi.c M src/soc/intel/fsp_broadwell_de/smihandler.c M src/soc/intel/fsp_broadwell_de/smmrelocate.c M src/soc/intel/icelake/cpu.c D src/soc/intel/icelake/include/soc/smm.h M src/soc/intel/icelake/smmrelocate.c M src/soc/intel/skylake/cpu.c D src/soc/intel/skylake/include/soc/smm.h M src/soc/intel/skylake/smmrelocate.c M src/soc/intel/tigerlake/cpu.c D src/soc/intel/tigerlake/include/soc/smm.h M src/soc/intel/tigerlake/smmrelocate.c 36 files changed, 59 insertions(+), 423 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/34840/13
Hello Aaron Durbin, Patrick Rudolph, Huang Jin, Arthur Heymans, Philipp Deppenwiese, build bot (Jenkins), Furquan Shaikh, Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/34840
to look at the new patch set (#14).
Change subject: intel/smm: Provide common smm_relocation_params ......................................................................
intel/smm: Provide common smm_relocation_params
Pull in all copies of smm_relocation_params structs defined for intel platforms.
Pull in all the inlined MSR accessors to the header file.
Change-Id: I39c6cffee95433aea1a3c783b869eedfff094413 Signed-off-by: Kyösti Mälkki kyosti.malkki@gmail.com --- M src/cpu/intel/haswell/smmrelocate.c A src/cpu/intel/smm/Makefile.inc M src/cpu/intel/smm/gen1/smmrelocate.c R src/cpu/intel/smm/smm_reloc.c M src/cpu/x86/Makefile.inc M src/include/cpu/intel/smm_reloc.h M src/mainboard/google/auron/smihandler.c M src/mainboard/google/jecht/smihandler.c M src/soc/intel/baytrail/cpu.c M src/soc/intel/braswell/cpu.c M src/soc/intel/broadwell/cpu.c D src/soc/intel/broadwell/include/soc/smm.h M src/soc/intel/broadwell/memmap.c M src/soc/intel/broadwell/pei_data.c M src/soc/intel/broadwell/romstage/raminit.c M src/soc/intel/broadwell/smi.c M src/soc/intel/broadwell/smihandler.c M src/soc/intel/broadwell/smmrelocate.c M src/soc/intel/cannonlake/cpu.c D src/soc/intel/cannonlake/include/soc/smm.h M src/soc/intel/cannonlake/smmrelocate.c M src/soc/intel/fsp_baytrail/cpu.c M src/soc/intel/fsp_broadwell_de/cpu.c D src/soc/intel/fsp_broadwell_de/include/soc/smm.h M src/soc/intel/fsp_broadwell_de/smi.c M src/soc/intel/fsp_broadwell_de/smihandler.c M src/soc/intel/fsp_broadwell_de/smmrelocate.c M src/soc/intel/icelake/cpu.c D src/soc/intel/icelake/include/soc/smm.h M src/soc/intel/icelake/smmrelocate.c M src/soc/intel/skylake/cpu.c D src/soc/intel/skylake/include/soc/smm.h M src/soc/intel/skylake/smmrelocate.c M src/soc/intel/tigerlake/cpu.c D src/soc/intel/tigerlake/include/soc/smm.h M src/soc/intel/tigerlake/smmrelocate.c 36 files changed, 60 insertions(+), 423 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/34840/14
Aaron Durbin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34840 )
Change subject: intel/smm: Provide common smm_relocation_params ......................................................................
Patch Set 14: Code-Review+2
(1 comment)
https://review.coreboot.org/c/coreboot/+/34840/14/src/cpu/x86/Makefile.inc File src/cpu/x86/Makefile.inc:
https://review.coreboot.org/c/coreboot/+/34840/14/src/cpu/x86/Makefile.inc@9 PS14, Line 9: # This is hacky. And will break if there are multiple objects named smm_reloc_params and HAVE_SMI_HANDLER is enabled. Could you expand this comment to relfect that? Or add a Kconfig that pulls in this directory when the Kconfig is selected?
Hello Aaron Durbin, Patrick Rudolph, Huang Jin, Arthur Heymans, Philipp Deppenwiese, build bot (Jenkins), Furquan Shaikh, Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/34840
to look at the new patch set (#15).
Change subject: intel/smm: Provide common smm_relocation_params ......................................................................
intel/smm: Provide common smm_relocation_params
Pull in all copies of smm_relocation_params structs defined for intel platforms.
Pull in all the inlined MSR accessors to the header file.
Change-Id: I39c6cffee95433aea1a3c783b869eedfff094413 Signed-off-by: Kyösti Mälkki kyosti.malkki@gmail.com --- M src/cpu/intel/common/Kconfig M src/cpu/intel/haswell/smmrelocate.c A src/cpu/intel/smm/Makefile.inc M src/cpu/intel/smm/gen1/smmrelocate.c R src/cpu/intel/smm/smm_reloc.c M src/cpu/x86/Makefile.inc M src/include/cpu/intel/smm_reloc.h M src/mainboard/google/auron/smihandler.c M src/mainboard/google/jecht/smihandler.c M src/soc/intel/baytrail/cpu.c M src/soc/intel/braswell/cpu.c M src/soc/intel/broadwell/cpu.c D src/soc/intel/broadwell/include/soc/smm.h M src/soc/intel/broadwell/memmap.c M src/soc/intel/broadwell/pei_data.c M src/soc/intel/broadwell/romstage/raminit.c M src/soc/intel/broadwell/smi.c M src/soc/intel/broadwell/smihandler.c M src/soc/intel/broadwell/smmrelocate.c M src/soc/intel/cannonlake/cpu.c D src/soc/intel/cannonlake/include/soc/smm.h M src/soc/intel/cannonlake/smmrelocate.c M src/soc/intel/fsp_baytrail/cpu.c M src/soc/intel/fsp_broadwell_de/cpu.c D src/soc/intel/fsp_broadwell_de/include/soc/smm.h M src/soc/intel/fsp_broadwell_de/smi.c M src/soc/intel/fsp_broadwell_de/smihandler.c M src/soc/intel/fsp_broadwell_de/smmrelocate.c M src/soc/intel/icelake/cpu.c D src/soc/intel/icelake/include/soc/smm.h M src/soc/intel/icelake/smmrelocate.c M src/soc/intel/skylake/cpu.c D src/soc/intel/skylake/include/soc/smm.h M src/soc/intel/skylake/smmrelocate.c M src/soc/intel/tigerlake/cpu.c D src/soc/intel/tigerlake/include/soc/smm.h M src/soc/intel/tigerlake/smmrelocate.c 37 files changed, 63 insertions(+), 423 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/34840/15
Aaron Durbin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34840 )
Change subject: intel/smm: Provide common smm_relocation_params ......................................................................
Patch Set 15: Code-Review+2
Hello Aaron Durbin, Patrick Rudolph, Huang Jin, Arthur Heymans, Philipp Deppenwiese, build bot (Jenkins), Furquan Shaikh, Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/34840
to look at the new patch set (#16).
Change subject: intel/smm: Provide common smm_relocation_params ......................................................................
intel/smm: Provide common smm_relocation_params
Pull in all copies of smm_relocation_params structs defined for intel platforms.
Pull in all the inlined MSR accessors to the header file.
Change-Id: I39c6cffee95433aea1a3c783b869eedfff094413 Signed-off-by: Kyösti Mälkki kyosti.malkki@gmail.com --- M src/cpu/intel/common/Kconfig M src/cpu/intel/haswell/smmrelocate.c A src/cpu/intel/smm/Makefile.inc M src/cpu/intel/smm/gen1/smmrelocate.c A src/cpu/intel/smm/smm_reloc.c M src/cpu/x86/Makefile.inc M src/include/cpu/intel/smm_reloc.h M src/mainboard/google/auron/smihandler.c M src/mainboard/google/jecht/smihandler.c M src/soc/intel/baytrail/cpu.c M src/soc/intel/braswell/cpu.c M src/soc/intel/broadwell/cpu.c D src/soc/intel/broadwell/include/soc/smm.h M src/soc/intel/broadwell/memmap.c M src/soc/intel/broadwell/pei_data.c M src/soc/intel/broadwell/romstage/raminit.c M src/soc/intel/broadwell/smi.c M src/soc/intel/broadwell/smihandler.c M src/soc/intel/broadwell/smmrelocate.c M src/soc/intel/cannonlake/cpu.c D src/soc/intel/cannonlake/include/soc/smm.h M src/soc/intel/cannonlake/smmrelocate.c M src/soc/intel/icelake/cpu.c D src/soc/intel/icelake/include/soc/smm.h M src/soc/intel/icelake/smmrelocate.c M src/soc/intel/skylake/cpu.c D src/soc/intel/skylake/include/soc/smm.h M src/soc/intel/skylake/smmrelocate.c M src/soc/intel/tigerlake/cpu.c D src/soc/intel/tigerlake/include/soc/smm.h M src/soc/intel/tigerlake/smmrelocate.c 31 files changed, 77 insertions(+), 347 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/34840/16
Hello Aaron Durbin, Patrick Rudolph, Huang Jin, Arthur Heymans, Philipp Deppenwiese, build bot (Jenkins), Furquan Shaikh, Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/34840
to look at the new patch set (#17).
Change subject: intel/smm: Provide common smm_relocation_params ......................................................................
intel/smm: Provide common smm_relocation_params
Pull in all copies of smm_relocation_params structs defined for intel platforms.
Pull in all the inlined MSR accessors to the header file.
Change-Id: I39c6cffee95433aea1a3c783b869eedfff094413 Signed-off-by: Kyösti Mälkki kyosti.malkki@gmail.com --- M src/cpu/intel/common/Kconfig M src/cpu/intel/haswell/smmrelocate.c A src/cpu/intel/smm/Makefile.inc M src/cpu/intel/smm/gen1/smmrelocate.c A src/cpu/intel/smm/smm_reloc.c M src/cpu/x86/Makefile.inc M src/include/cpu/intel/smm_reloc.h M src/mainboard/google/auron/smihandler.c M src/mainboard/google/jecht/smihandler.c M src/soc/intel/baytrail/cpu.c M src/soc/intel/braswell/cpu.c M src/soc/intel/broadwell/cpu.c D src/soc/intel/broadwell/include/soc/smm.h M src/soc/intel/broadwell/memmap.c M src/soc/intel/broadwell/pei_data.c M src/soc/intel/broadwell/romstage/raminit.c M src/soc/intel/broadwell/smi.c M src/soc/intel/broadwell/smihandler.c M src/soc/intel/broadwell/smmrelocate.c M src/soc/intel/cannonlake/cpu.c D src/soc/intel/cannonlake/include/soc/smm.h M src/soc/intel/cannonlake/smmrelocate.c M src/soc/intel/icelake/Kconfig M src/soc/intel/icelake/cpu.c D src/soc/intel/icelake/include/soc/smm.h M src/soc/intel/icelake/smmrelocate.c M src/soc/intel/skylake/cpu.c D src/soc/intel/skylake/include/soc/smm.h M src/soc/intel/skylake/smmrelocate.c M src/soc/intel/tigerlake/cpu.c D src/soc/intel/tigerlake/include/soc/smm.h M src/soc/intel/tigerlake/smmrelocate.c 32 files changed, 78 insertions(+), 347 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/34840/17
Aaron Durbin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34840 )
Change subject: intel/smm: Provide common smm_relocation_params ......................................................................
Patch Set 17: Code-Review+2
Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34840 )
Change subject: intel/smm: Provide common smm_relocation_params ......................................................................
Patch Set 17:
(3 comments)
https://review.coreboot.org/c/coreboot/+/34840/7/src/cpu/x86/Makefile.inc File src/cpu/x86/Makefile.inc:
https://review.coreboot.org/c/coreboot/+/34840/7/src/cpu/x86/Makefile.inc@9 PS7, Line 9: # This is hacky.
Indeed. […]
Done
https://review.coreboot.org/c/coreboot/+/34840/14/src/cpu/x86/Makefile.inc File src/cpu/x86/Makefile.inc:
https://review.coreboot.org/c/coreboot/+/34840/14/src/cpu/x86/Makefile.inc@9 PS14, Line 9: # This is hacky.
And will break if there are multiple objects named smm_reloc_params and HAVE_SMI_HANDLER is enabled. […]
Done
https://review.coreboot.org/c/coreboot/+/34840/7/src/include/cpu/intel/smm_r... File src/include/cpu/intel/smm_reloc.h:
https://review.coreboot.org/c/coreboot/+/34840/7/src/include/cpu/intel/smm_r... PS7, Line 88: static inline void write_smrr(struct smm_relocation_params *relo_params)
const on the types for these files?
Followup work removes these inlined versions, I'll deal with it then.
Kyösti Mälkki has submitted this change. ( https://review.coreboot.org/c/coreboot/+/34840 )
Change subject: intel/smm: Provide common smm_relocation_params ......................................................................
intel/smm: Provide common smm_relocation_params
Pull in all copies of smm_relocation_params structs defined for intel platforms.
Pull in all the inlined MSR accessors to the header file.
Change-Id: I39c6cffee95433aea1a3c783b869eedfff094413 Signed-off-by: Kyösti Mälkki kyosti.malkki@gmail.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/34840 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Aaron Durbin adurbin@chromium.org --- M src/cpu/intel/common/Kconfig M src/cpu/intel/haswell/smmrelocate.c A src/cpu/intel/smm/Makefile.inc M src/cpu/intel/smm/gen1/smmrelocate.c A src/cpu/intel/smm/smm_reloc.c M src/cpu/x86/Makefile.inc M src/include/cpu/intel/smm_reloc.h M src/mainboard/google/auron/smihandler.c M src/mainboard/google/jecht/smihandler.c M src/soc/intel/baytrail/cpu.c M src/soc/intel/braswell/cpu.c M src/soc/intel/broadwell/cpu.c D src/soc/intel/broadwell/include/soc/smm.h M src/soc/intel/broadwell/memmap.c M src/soc/intel/broadwell/pei_data.c M src/soc/intel/broadwell/romstage/raminit.c M src/soc/intel/broadwell/smi.c M src/soc/intel/broadwell/smihandler.c M src/soc/intel/broadwell/smmrelocate.c M src/soc/intel/cannonlake/cpu.c D src/soc/intel/cannonlake/include/soc/smm.h M src/soc/intel/cannonlake/smmrelocate.c M src/soc/intel/icelake/Kconfig M src/soc/intel/icelake/cpu.c D src/soc/intel/icelake/include/soc/smm.h M src/soc/intel/icelake/smmrelocate.c M src/soc/intel/skylake/cpu.c D src/soc/intel/skylake/include/soc/smm.h M src/soc/intel/skylake/smmrelocate.c M src/soc/intel/tigerlake/cpu.c D src/soc/intel/tigerlake/include/soc/smm.h M src/soc/intel/tigerlake/smmrelocate.c 32 files changed, 78 insertions(+), 347 deletions(-)
Approvals: build bot (Jenkins): Verified Aaron Durbin: Looks good to me, approved
diff --git a/src/cpu/intel/common/Kconfig b/src/cpu/intel/common/Kconfig index 4fa3aff..0f2a652 100644 --- a/src/cpu/intel/common/Kconfig +++ b/src/cpu/intel/common/Kconfig @@ -26,3 +26,7 @@ bool
endif + +config CPU_INTEL_COMMON_SMM + bool + default y if CPU_INTEL_COMMON diff --git a/src/cpu/intel/haswell/smmrelocate.c b/src/cpu/intel/haswell/smmrelocate.c index c33a00a..8419746 100644 --- a/src/cpu/intel/haswell/smmrelocate.c +++ b/src/cpu/intel/haswell/smmrelocate.c @@ -45,49 +45,7 @@ #define SMRR_SUPPORTED (1 << 11) #define PRMRR_SUPPORTED (1 << 12)
-struct smm_relocation_params { - uintptr_t ied_base; - size_t ied_size; - msr_t smrr_base; - msr_t smrr_mask; - msr_t prmrr_base; - msr_t prmrr_mask; - msr_t uncore_prmrr_base; - msr_t uncore_prmrr_mask; - /* The smm_save_state_in_msrs field indicates if SMM save state - * locations live in MSRs. This indicates to the CPUs how to adjust - * the SMMBASE and IEDBASE */ - int smm_save_state_in_msrs; -};
-/* This gets filled in and used during relocation. */ -static struct smm_relocation_params smm_reloc_params; - -static inline void write_smrr(struct smm_relocation_params *relo_params) -{ - printk(BIOS_DEBUG, "Writing SMRR. base = 0x%08x, mask=0x%08x\n", - relo_params->smrr_base.lo, relo_params->smrr_mask.lo); - wrmsr(IA32_SMRR_PHYS_BASE, relo_params->smrr_base); - wrmsr(IA32_SMRR_PHYS_MASK, relo_params->smrr_mask); -} - -static inline void write_prmrr(struct smm_relocation_params *relo_params) -{ - printk(BIOS_DEBUG, "Writing PRMRR. base = 0x%08x, mask=0x%08x\n", - relo_params->prmrr_base.lo, relo_params->prmrr_mask.lo); - wrmsr(MSR_PRMRR_PHYS_BASE, relo_params->prmrr_base); - wrmsr(MSR_PRMRR_PHYS_MASK, relo_params->prmrr_mask); -} - -static inline void write_uncore_prmrr(struct smm_relocation_params *relo_params) -{ - printk(BIOS_DEBUG, - "Writing UNCORE_PRMRR. base = 0x%08x, mask=0x%08x\n", - relo_params->uncore_prmrr_base.lo, - relo_params->uncore_prmrr_mask.lo); - wrmsr(MSR_UNCORE_PRMRR_PHYS_BASE, relo_params->uncore_prmrr_base); - wrmsr(MSR_UNCORE_PRMRR_PHYS_MASK, relo_params->uncore_prmrr_mask); -}
static void update_save_state(int cpu, uintptr_t curr_smbase, uintptr_t staggered_smbase, diff --git a/src/cpu/intel/smm/Makefile.inc b/src/cpu/intel/smm/Makefile.inc new file mode 100644 index 0000000..a49b796 --- /dev/null +++ b/src/cpu/intel/smm/Makefile.inc @@ -0,0 +1 @@ +ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smm_reloc.c diff --git a/src/cpu/intel/smm/gen1/smmrelocate.c b/src/cpu/intel/smm/gen1/smmrelocate.c index 5350d1c..c177e9b 100644 --- a/src/cpu/intel/smm/gen1/smmrelocate.c +++ b/src/cpu/intel/smm/gen1/smmrelocate.c @@ -39,17 +39,6 @@ #define C_BASE_SEG ((0 << 2) | (1 << 1) | (0 << 0))
- -struct smm_relocation_params { - uintptr_t ied_base; - size_t ied_size; - msr_t smrr_base; - msr_t smrr_mask; -}; - -/* This gets filled in and used during relocation. */ -static struct smm_relocation_params smm_reloc_params; - /* On model_6fx, model_1067x and model_106cx SMRR functions slightly differently. The MSR are at different location from the rest and need to be explicitly enabled in IA32_FEATURE_CONTROL MSR. */ @@ -88,15 +77,6 @@ wrmsr(MSR_SMRR_PHYS_MASK, relo_params->smrr_mask); }
-static void write_smrr(struct smm_relocation_params *relo_params) -{ - printk(BIOS_DEBUG, "Writing SMRR. base = 0x%08x, mask=0x%08x\n", - relo_params->smrr_base.lo, relo_params->smrr_mask.lo); - - wrmsr(IA32_SMRR_PHYS_BASE, relo_params->smrr_base); - wrmsr(IA32_SMRR_PHYS_MASK, relo_params->smrr_mask); -} - static void fill_in_relocation_params(struct smm_relocation_params *params) { uintptr_t tseg_base; diff --git a/src/cpu/intel/smm/smm_reloc.c b/src/cpu/intel/smm/smm_reloc.c new file mode 100644 index 0000000..860c095 --- /dev/null +++ b/src/cpu/intel/smm/smm_reloc.c @@ -0,0 +1,16 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <cpu/intel/smm_reloc.h> + +struct smm_relocation_params smm_reloc_params; diff --git a/src/cpu/x86/Makefile.inc b/src/cpu/x86/Makefile.inc index 9c18d44..55d1fad 100644 --- a/src/cpu/x86/Makefile.inc +++ b/src/cpu/x86/Makefile.inc @@ -6,6 +6,8 @@ ramstage-$(CONFIG_MIRROR_PAYLOAD_TO_RAM_BEFORE_LOADING) += mirror_payload.c ramstage-y += backup_default_smm.c
+subdirs-$(CONFIG_CPU_INTEL_COMMON_SMM) += ../intel/smm + additional-dirs += $(obj)/cpu/x86
SIPI_ELF=$(obj)/cpu/x86/sipi_vector.elf diff --git a/src/include/cpu/intel/smm_reloc.h b/src/include/cpu/intel/smm_reloc.h index cb196fc..bef8d4e 100644 --- a/src/include/cpu/intel/smm_reloc.h +++ b/src/include/cpu/intel/smm_reloc.h @@ -14,7 +14,29 @@ #ifndef __INTEL_SMM_RELOC_H__ #define __INTEL_SMM_RELOC_H__
+#include <console/console.h> #include <types.h> +#include <cpu/x86/msr.h> +#include <cpu/x86/mtrr.h> + +struct smm_relocation_params { + uintptr_t ied_base; + size_t ied_size; + msr_t smrr_base; + msr_t smrr_mask; + msr_t prmrr_base; + msr_t prmrr_mask; + msr_t uncore_prmrr_base; + msr_t uncore_prmrr_mask; + /* + * The smm_save_state_in_msrs field indicates if SMM save state + * locations live in MSRs. This indicates to the CPUs how to adjust + * the SMMBASE and IEDBASE + */ + int smm_save_state_in_msrs; +}; + +extern struct smm_relocation_params smm_reloc_params;
struct ied_header { char signature[10]; @@ -42,4 +64,36 @@
bool cpu_has_alternative_smrr(void);
+ +#define MSR_PRMRR_PHYS_BASE 0x1f4 +#define MSR_PRMRR_PHYS_MASK 0x1f5 +#define MSR_UNCORE_PRMRR_PHYS_BASE 0x2f4 +#define MSR_UNCORE_PRMRR_PHYS_MASK 0x2f5 + +static inline void write_smrr(struct smm_relocation_params *relo_params) +{ + printk(BIOS_DEBUG, "Writing SMRR. base = 0x%08x, mask=0x%08x\n", + relo_params->smrr_base.lo, relo_params->smrr_mask.lo); + wrmsr(IA32_SMRR_PHYS_BASE, relo_params->smrr_base); + wrmsr(IA32_SMRR_PHYS_MASK, relo_params->smrr_mask); +} + +static inline void write_prmrr(struct smm_relocation_params *relo_params) +{ + printk(BIOS_DEBUG, "Writing PRMRR. base = 0x%08x, mask=0x%08x\n", + relo_params->prmrr_base.lo, relo_params->prmrr_mask.lo); + wrmsr(MSR_PRMRR_PHYS_BASE, relo_params->prmrr_base); + wrmsr(MSR_PRMRR_PHYS_MASK, relo_params->prmrr_mask); +} + +static inline void write_uncore_prmrr(struct smm_relocation_params *relo_params) +{ + printk(BIOS_DEBUG, + "Writing UNCORE_PRMRR. base = 0x%08x, mask=0x%08x\n", + relo_params->uncore_prmrr_base.lo, + relo_params->uncore_prmrr_mask.lo); + wrmsr(MSR_UNCORE_PRMRR_PHYS_BASE, relo_params->uncore_prmrr_base); + wrmsr(MSR_UNCORE_PRMRR_PHYS_MASK, relo_params->uncore_prmrr_mask); +} + #endif diff --git a/src/mainboard/google/auron/smihandler.c b/src/mainboard/google/auron/smihandler.c index 4cc0aa8..862e2c3 100644 --- a/src/mainboard/google/auron/smihandler.c +++ b/src/mainboard/google/auron/smihandler.c @@ -19,7 +19,6 @@ #include <console/console.h> #include <cpu/x86/smm.h> #include <soc/pm.h> -#include <soc/smm.h> #include <elog.h> #include <ec/google/chromeec/ec.h> #include <soc/gpio.h> diff --git a/src/mainboard/google/jecht/smihandler.c b/src/mainboard/google/jecht/smihandler.c index 8e8c9d4..f324813 100644 --- a/src/mainboard/google/jecht/smihandler.c +++ b/src/mainboard/google/jecht/smihandler.c @@ -18,7 +18,6 @@ #include <console/console.h> #include <cpu/x86/smm.h> #include <soc/pm.h> -#include <soc/smm.h> #include <ec/google/chromeec/ec.h> #include <soc/gpio.h> #include <soc/iomap.h> diff --git a/src/soc/intel/baytrail/cpu.c b/src/soc/intel/baytrail/cpu.c index edc4e83..d12ece0 100644 --- a/src/soc/intel/baytrail/cpu.c +++ b/src/soc/intel/baytrail/cpu.c @@ -33,7 +33,6 @@ #include <soc/msr.h> #include <soc/pattrs.h> #include <soc/ramstage.h> -#include <soc/smm.h>
/* Core level MSRs */ const struct reg_script core_msr_script[] = { @@ -88,13 +87,6 @@ * MP and SMM loading initialization. */
-struct smm_relocation_params { - msr_t smrr_base; - msr_t smrr_mask; -}; - -static struct smm_relocation_params smm_reloc_params; - /* Package level MSRs */ static const struct reg_script package_msr_script[] = { /* Set Package TDP to ~7W */ diff --git a/src/soc/intel/braswell/cpu.c b/src/soc/intel/braswell/cpu.c index 665b030..a44b9cb 100644 --- a/src/soc/intel/braswell/cpu.c +++ b/src/soc/intel/braswell/cpu.c @@ -22,7 +22,6 @@ #include <cpu/intel/microcode.h> #include <cpu/intel/smm_reloc.h> #include <cpu/intel/turbo.h> -#include <cpu/intel/smm_reloc.h> #include <cpu/x86/cache.h> #include <cpu/x86/lapic.h> #include <cpu/x86/mp.h> @@ -34,7 +33,6 @@ #include <soc/msr.h> #include <soc/pattrs.h> #include <soc/ramstage.h> -#include <soc/smm.h> #include <stdlib.h>
/* Core level MSRs */ @@ -98,13 +96,6 @@ * MP and SMM loading initialization. */
-struct smm_relocation_params { - msr_t smrr_base; - msr_t smrr_mask; -}; - -static struct smm_relocation_params smm_reloc_params; - /* Package level MSRs */ static const struct reg_script package_msr_script[] = { /* Set Package TDP to ~7W */ diff --git a/src/soc/intel/broadwell/cpu.c b/src/soc/intel/broadwell/cpu.c index 8fe66dc..287b5b5 100644 --- a/src/soc/intel/broadwell/cpu.c +++ b/src/soc/intel/broadwell/cpu.c @@ -36,7 +36,6 @@ #include <soc/pci_devs.h> #include <soc/ramstage.h> #include <soc/rcba.h> -#include <soc/smm.h> #include <soc/systemagent.h> #include <soc/intel/broadwell/chip.h> #include <cpu/intel/common/common.h> diff --git a/src/soc/intel/broadwell/include/soc/smm.h b/src/soc/intel/broadwell/include/soc/smm.h deleted file mode 100644 index 909294c..0000000 --- a/src/soc/intel/broadwell/include/soc/smm.h +++ /dev/null @@ -1,38 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2014 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef _BROADWELL_SMM_H_ -#define _BROADWELL_SMM_H_ - -#include <stdint.h> -#include <cpu/x86/msr.h> - - -struct smm_relocation_params { - uintptr_t ied_base; - size_t ied_size; - msr_t smrr_base; - msr_t smrr_mask; - msr_t prmrr_base; - msr_t prmrr_mask; - msr_t uncore_prmrr_base; - msr_t uncore_prmrr_mask; - /* The smm_save_state_in_msrs field indicates if SMM save state - * locations live in MSRs. This indicates to the CPUs how to adjust - * the SMMBASE and IEDBASE */ - int smm_save_state_in_msrs; -}; - -#endif diff --git a/src/soc/intel/broadwell/memmap.c b/src/soc/intel/broadwell/memmap.c index ad50dd3..48492d3 100644 --- a/src/soc/intel/broadwell/memmap.c +++ b/src/soc/intel/broadwell/memmap.c @@ -21,7 +21,6 @@ #include <device/pci_ops.h> #include <soc/pci_devs.h> #include <soc/systemagent.h> -#include <soc/smm.h> #include <stdint.h>
static uintptr_t dpr_region_start(void) diff --git a/src/soc/intel/broadwell/pei_data.c b/src/soc/intel/broadwell/pei_data.c index f745348..09753ad 100644 --- a/src/soc/intel/broadwell/pei_data.c +++ b/src/soc/intel/broadwell/pei_data.c @@ -19,7 +19,6 @@ #include <soc/iomap.h> #include <soc/pei_data.h> #include <soc/pei_wrapper.h> -#include <soc/smm.h>
static void ABI_X86 send_to_console(unsigned char b) { diff --git a/src/soc/intel/broadwell/romstage/raminit.c b/src/soc/intel/broadwell/romstage/raminit.c index c13761d..03b564f 100644 --- a/src/soc/intel/broadwell/romstage/raminit.c +++ b/src/soc/intel/broadwell/romstage/raminit.c @@ -33,7 +33,6 @@ #include <soc/pei_wrapper.h> #include <soc/pm.h> #include <soc/romstage.h> -#include <soc/smm.h> #include <soc/systemagent.h>
/* diff --git a/src/soc/intel/broadwell/smi.c b/src/soc/intel/broadwell/smi.c index 17196da..2bdeecc 100644 --- a/src/soc/intel/broadwell/smi.c +++ b/src/soc/intel/broadwell/smi.c @@ -24,7 +24,6 @@ #include <soc/iomap.h> #include <soc/pch.h> #include <soc/pm.h> -#include <soc/smm.h>
void smm_southbridge_clear_state(void) { diff --git a/src/soc/intel/broadwell/smihandler.c b/src/soc/intel/broadwell/smihandler.c index ca99487..c2843a7 100644 --- a/src/soc/intel/broadwell/smihandler.c +++ b/src/soc/intel/broadwell/smihandler.c @@ -33,7 +33,6 @@ #include <soc/pci_devs.h> #include <soc/pm.h> #include <soc/rcba.h> -#include <soc/smm.h> #include <soc/xhci.h> #include <drivers/intel/gma/i915_reg.h>
diff --git a/src/soc/intel/broadwell/smmrelocate.c b/src/soc/intel/broadwell/smmrelocate.c index 21c534a..b5af989 100644 --- a/src/soc/intel/broadwell/smmrelocate.c +++ b/src/soc/intel/broadwell/smmrelocate.c @@ -30,37 +30,8 @@ #include <soc/cpu.h> #include <soc/msr.h> #include <soc/pci_devs.h> -#include <soc/smm.h> #include <soc/systemagent.h>
-/* This gets filled in and used during relocation. */ -static struct smm_relocation_params smm_reloc_params; - -static inline void write_smrr(struct smm_relocation_params *relo_params) -{ - printk(BIOS_DEBUG, "Writing SMRR. base = 0x%08x, mask=0x%08x\n", - relo_params->smrr_base.lo, relo_params->smrr_mask.lo); - wrmsr(IA32_SMRR_PHYS_BASE, relo_params->smrr_base); - wrmsr(IA32_SMRR_PHYS_MASK, relo_params->smrr_mask); -} - -static inline void write_prmrr(struct smm_relocation_params *relo_params) -{ - printk(BIOS_DEBUG, "Writing PRMRR. base = 0x%08x, mask=0x%08x\n", - relo_params->prmrr_base.lo, relo_params->prmrr_mask.lo); - wrmsr(MSR_PRMRR_PHYS_BASE, relo_params->prmrr_base); - wrmsr(MSR_PRMRR_PHYS_MASK, relo_params->prmrr_mask); -} - -static inline void write_uncore_prmrr(struct smm_relocation_params *relo_params) -{ - printk(BIOS_DEBUG, - "Writing UNCORE_PRMRR. base = 0x%08x, mask=0x%08x\n", - relo_params->uncore_prmrr_base.lo, - relo_params->uncore_prmrr_mask.lo); - wrmsr(MSR_UNCORE_PRMRR_PHYS_BASE, relo_params->uncore_prmrr_base); - wrmsr(MSR_UNCORE_PRMRR_PHYS_MASK, relo_params->uncore_prmrr_mask); -}
static void update_save_state(int cpu, uintptr_t curr_smbase, uintptr_t staggered_smbase, diff --git a/src/soc/intel/cannonlake/cpu.c b/src/soc/intel/cannonlake/cpu.c index c3a27ae..f01b499 100644 --- a/src/soc/intel/cannonlake/cpu.c +++ b/src/soc/intel/cannonlake/cpu.c @@ -28,7 +28,6 @@ #include <soc/msr.h> #include <soc/pci_devs.h> #include <soc/pm.h> -#include <soc/smm.h> #include <soc/systemagent.h> #include <cpu/x86/mtrr.h> #include <cpu/intel/microcode.h> diff --git a/src/soc/intel/cannonlake/include/soc/smm.h b/src/soc/intel/cannonlake/include/soc/smm.h deleted file mode 100644 index 95c1abd..0000000 --- a/src/soc/intel/cannonlake/include/soc/smm.h +++ /dev/null @@ -1,39 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2014 Google Inc. - * Copyright (C) 2017 Intel Corporation. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef _SOC_SMM_H_ -#define _SOC_SMM_H_ - -#include <stdint.h> -#include <cpu/x86/msr.h> -#include <cpu/x86/smm.h> -#include <soc/gpio.h> - - -struct smm_relocation_params { - uintptr_t ied_base; - size_t ied_size; - msr_t smrr_base; - msr_t smrr_mask; - /* - * The smm_save_state_in_msrs field indicates if SMM save state - * locations live in MSRs. This indicates to the CPUs how to adjust - * the SMMBASE and IEDBASE - */ - int smm_save_state_in_msrs; -}; - -#endif diff --git a/src/soc/intel/cannonlake/smmrelocate.c b/src/soc/intel/cannonlake/smmrelocate.c index 6680bf3..54e2f92 100644 --- a/src/soc/intel/cannonlake/smmrelocate.c +++ b/src/soc/intel/cannonlake/smmrelocate.c @@ -31,20 +31,9 @@ #include <soc/cpu.h> #include <soc/msr.h> #include <soc/pci_devs.h> -#include <soc/smm.h> #include <soc/systemagent.h> #include "chip.h"
-/* This gets filled in and used during relocation. */ -static struct smm_relocation_params smm_reloc_params; - -static inline void write_smrr(struct smm_relocation_params *relo_params) -{ - printk(BIOS_DEBUG, "Writing SMRR. base = 0x%08x, mask=0x%08x\n", - relo_params->smrr_base.lo, relo_params->smrr_mask.lo); - wrmsr(IA32_SMRR_PHYS_BASE, relo_params->smrr_base); - wrmsr(IA32_SMRR_PHYS_MASK, relo_params->smrr_mask); -}
static void update_save_state(int cpu, uintptr_t curr_smbase, uintptr_t staggered_smbase, diff --git a/src/soc/intel/icelake/Kconfig b/src/soc/intel/icelake/Kconfig index 418c317..cb9de14 100644 --- a/src/soc/intel/icelake/Kconfig +++ b/src/soc/intel/icelake/Kconfig @@ -36,6 +36,7 @@ select SMP select SOC_AHCI_PORT_IMPLEMENTED_INVERT select PMC_GLOBAL_RESET_ENABLE_LOCK + select CPU_INTEL_COMMON_SMM select SOC_INTEL_COMMON select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE select SOC_INTEL_COMMON_BLOCK diff --git a/src/soc/intel/icelake/cpu.c b/src/soc/intel/icelake/cpu.c index a2d9f7a..e058442 100644 --- a/src/soc/intel/icelake/cpu.c +++ b/src/soc/intel/icelake/cpu.c @@ -30,7 +30,6 @@ #include <soc/msr.h> #include <soc/pci_devs.h> #include <soc/pm.h> -#include <soc/smm.h> #include <soc/soc_chip.h>
static void soc_fsp_load(void) diff --git a/src/soc/intel/icelake/include/soc/smm.h b/src/soc/intel/icelake/include/soc/smm.h deleted file mode 100644 index 4393167..0000000 --- a/src/soc/intel/icelake/include/soc/smm.h +++ /dev/null @@ -1,38 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2018 Intel Corp. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef _SOC_SMM_H_ -#define _SOC_SMM_H_ - -#include <stdint.h> -#include <cpu/x86/msr.h> -#include <cpu/x86/smm.h> -#include <soc/gpio.h> - - -struct smm_relocation_params { - uintptr_t ied_base; - size_t ied_size; - msr_t smrr_base; - msr_t smrr_mask; - /* - * The smm_save_state_in_msrs field indicates if SMM save state - * locations live in MSRs. This indicates to the CPUs how to adjust - * the SMMBASE and IEDBASE - */ - int smm_save_state_in_msrs; -}; - -#endif diff --git a/src/soc/intel/icelake/smmrelocate.c b/src/soc/intel/icelake/smmrelocate.c index 8f56ad6..cc8a5ff 100644 --- a/src/soc/intel/icelake/smmrelocate.c +++ b/src/soc/intel/icelake/smmrelocate.c @@ -30,20 +30,9 @@ #include <soc/cpu.h> #include <soc/msr.h> #include <soc/pci_devs.h> -#include <soc/smm.h> #include <soc/soc_chip.h> #include <soc/systemagent.h>
-/* This gets filled in and used during relocation. */ -static struct smm_relocation_params smm_reloc_params; - -static inline void write_smrr(struct smm_relocation_params *relo_params) -{ - printk(BIOS_DEBUG, "Writing SMRR. base = 0x%08x, mask=0x%08x\n", - relo_params->smrr_base.lo, relo_params->smrr_mask.lo); - wrmsr(IA32_SMRR_PHYS_BASE, relo_params->smrr_base); - wrmsr(IA32_SMRR_PHYS_MASK, relo_params->smrr_mask); -}
static void update_save_state(int cpu, uintptr_t curr_smbase, uintptr_t staggered_smbase, diff --git a/src/soc/intel/skylake/cpu.c b/src/soc/intel/skylake/cpu.c index 7a45693..f5273f6 100644 --- a/src/soc/intel/skylake/cpu.c +++ b/src/soc/intel/skylake/cpu.c @@ -41,7 +41,6 @@ #include <soc/pci_devs.h> #include <soc/pm.h> #include <soc/ramstage.h> -#include <soc/smm.h> #include <soc/systemagent.h> #include <timer.h>
diff --git a/src/soc/intel/skylake/include/soc/smm.h b/src/soc/intel/skylake/include/soc/smm.h deleted file mode 100644 index 88ce9e3..0000000 --- a/src/soc/intel/skylake/include/soc/smm.h +++ /dev/null @@ -1,40 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2014 Google Inc. - * Copyright (C) 2015 Intel Corporation. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef _SOC_SMM_H_ -#define _SOC_SMM_H_ - -#include <stdint.h> -#include <cpu/x86/msr.h> -#include <cpu/x86/smm.h> -#include <intelblocks/smihandler.h> -#include <soc/gpio.h> - - -struct smm_relocation_params { - uintptr_t ied_base; - size_t ied_size; - msr_t smrr_base; - msr_t smrr_mask; - /* - * The smm_save_state_in_msrs field indicates if SMM save state - * locations live in MSRs. This indicates to the CPUs how to adjust - * the SMMBASE and IEDBASE - */ - int smm_save_state_in_msrs; -}; - -#endif diff --git a/src/soc/intel/skylake/smmrelocate.c b/src/soc/intel/skylake/smmrelocate.c index e1779d1..65d96ae 100644 --- a/src/soc/intel/skylake/smmrelocate.c +++ b/src/soc/intel/skylake/smmrelocate.c @@ -31,20 +31,9 @@ #include <soc/cpu.h> #include <soc/msr.h> #include <soc/pci_devs.h> -#include <soc/smm.h> #include <soc/systemagent.h> #include "chip.h"
-/* This gets filled in and used during relocation. */ -static struct smm_relocation_params smm_reloc_params; - -static inline void write_smrr(struct smm_relocation_params *relo_params) -{ - printk(BIOS_DEBUG, "Writing SMRR. base = 0x%08x, mask=0x%08x\n", - relo_params->smrr_base.lo, relo_params->smrr_mask.lo); - wrmsr(IA32_SMRR_PHYS_BASE, relo_params->smrr_base); - wrmsr(IA32_SMRR_PHYS_MASK, relo_params->smrr_mask); -}
static void update_save_state(int cpu, uintptr_t curr_smbase, uintptr_t staggered_smbase, diff --git a/src/soc/intel/tigerlake/cpu.c b/src/soc/intel/tigerlake/cpu.c index 4174cd2..5f4f081 100644 --- a/src/soc/intel/tigerlake/cpu.c +++ b/src/soc/intel/tigerlake/cpu.c @@ -36,7 +36,6 @@ #include <soc/msr.h> #include <soc/pci_devs.h> #include <soc/pm.h> -#include <soc/smm.h> #include <soc/soc_chip.h>
static void soc_fsp_load(void) diff --git a/src/soc/intel/tigerlake/include/soc/smm.h b/src/soc/intel/tigerlake/include/soc/smm.h deleted file mode 100644 index 4393167..0000000 --- a/src/soc/intel/tigerlake/include/soc/smm.h +++ /dev/null @@ -1,38 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2018 Intel Corp. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef _SOC_SMM_H_ -#define _SOC_SMM_H_ - -#include <stdint.h> -#include <cpu/x86/msr.h> -#include <cpu/x86/smm.h> -#include <soc/gpio.h> - - -struct smm_relocation_params { - uintptr_t ied_base; - size_t ied_size; - msr_t smrr_base; - msr_t smrr_mask; - /* - * The smm_save_state_in_msrs field indicates if SMM save state - * locations live in MSRs. This indicates to the CPUs how to adjust - * the SMMBASE and IEDBASE - */ - int smm_save_state_in_msrs; -}; - -#endif diff --git a/src/soc/intel/tigerlake/smmrelocate.c b/src/soc/intel/tigerlake/smmrelocate.c index b3f9836..53f206d 100644 --- a/src/soc/intel/tigerlake/smmrelocate.c +++ b/src/soc/intel/tigerlake/smmrelocate.c @@ -30,7 +30,6 @@ #include <soc/cpu.h> #include <soc/msr.h> #include <soc/pci_devs.h> -#include <soc/smm.h> #include <soc/soc_chip.h> #include <soc/systemagent.h>
-
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