Kyösti Mälkki submitted this change.
intel/smm: Provide common smm_relocation_params
Pull in all copies of smm_relocation_params structs defined
for intel platforms.
Pull in all the inlined MSR accessors to the header file.
Change-Id: I39c6cffee95433aea1a3c783b869eedfff094413
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34840
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
---
M src/cpu/intel/common/Kconfig
M src/cpu/intel/haswell/smmrelocate.c
A src/cpu/intel/smm/Makefile.inc
M src/cpu/intel/smm/gen1/smmrelocate.c
A src/cpu/intel/smm/smm_reloc.c
M src/cpu/x86/Makefile.inc
M src/include/cpu/intel/smm_reloc.h
M src/mainboard/google/auron/smihandler.c
M src/mainboard/google/jecht/smihandler.c
M src/soc/intel/baytrail/cpu.c
M src/soc/intel/braswell/cpu.c
M src/soc/intel/broadwell/cpu.c
D src/soc/intel/broadwell/include/soc/smm.h
M src/soc/intel/broadwell/memmap.c
M src/soc/intel/broadwell/pei_data.c
M src/soc/intel/broadwell/romstage/raminit.c
M src/soc/intel/broadwell/smi.c
M src/soc/intel/broadwell/smihandler.c
M src/soc/intel/broadwell/smmrelocate.c
M src/soc/intel/cannonlake/cpu.c
D src/soc/intel/cannonlake/include/soc/smm.h
M src/soc/intel/cannonlake/smmrelocate.c
M src/soc/intel/icelake/Kconfig
M src/soc/intel/icelake/cpu.c
D src/soc/intel/icelake/include/soc/smm.h
M src/soc/intel/icelake/smmrelocate.c
M src/soc/intel/skylake/cpu.c
D src/soc/intel/skylake/include/soc/smm.h
M src/soc/intel/skylake/smmrelocate.c
M src/soc/intel/tigerlake/cpu.c
D src/soc/intel/tigerlake/include/soc/smm.h
M src/soc/intel/tigerlake/smmrelocate.c
32 files changed, 78 insertions(+), 347 deletions(-)
diff --git a/src/cpu/intel/common/Kconfig b/src/cpu/intel/common/Kconfig
index 4fa3aff..0f2a652 100644
--- a/src/cpu/intel/common/Kconfig
+++ b/src/cpu/intel/common/Kconfig
@@ -26,3 +26,7 @@
bool
endif
+
+config CPU_INTEL_COMMON_SMM
+ bool
+ default y if CPU_INTEL_COMMON
diff --git a/src/cpu/intel/haswell/smmrelocate.c b/src/cpu/intel/haswell/smmrelocate.c
index c33a00a..8419746 100644
--- a/src/cpu/intel/haswell/smmrelocate.c
+++ b/src/cpu/intel/haswell/smmrelocate.c
@@ -45,49 +45,7 @@
#define SMRR_SUPPORTED (1 << 11)
#define PRMRR_SUPPORTED (1 << 12)
-struct smm_relocation_params {
- uintptr_t ied_base;
- size_t ied_size;
- msr_t smrr_base;
- msr_t smrr_mask;
- msr_t prmrr_base;
- msr_t prmrr_mask;
- msr_t uncore_prmrr_base;
- msr_t uncore_prmrr_mask;
- /* The smm_save_state_in_msrs field indicates if SMM save state
- * locations live in MSRs. This indicates to the CPUs how to adjust
- * the SMMBASE and IEDBASE */
- int smm_save_state_in_msrs;
-};
-/* This gets filled in and used during relocation. */
-static struct smm_relocation_params smm_reloc_params;
-
-static inline void write_smrr(struct smm_relocation_params *relo_params)
-{
- printk(BIOS_DEBUG, "Writing SMRR. base = 0x%08x, mask=0x%08x\n",
- relo_params->smrr_base.lo, relo_params->smrr_mask.lo);
- wrmsr(IA32_SMRR_PHYS_BASE, relo_params->smrr_base);
- wrmsr(IA32_SMRR_PHYS_MASK, relo_params->smrr_mask);
-}
-
-static inline void write_prmrr(struct smm_relocation_params *relo_params)
-{
- printk(BIOS_DEBUG, "Writing PRMRR. base = 0x%08x, mask=0x%08x\n",
- relo_params->prmrr_base.lo, relo_params->prmrr_mask.lo);
- wrmsr(MSR_PRMRR_PHYS_BASE, relo_params->prmrr_base);
- wrmsr(MSR_PRMRR_PHYS_MASK, relo_params->prmrr_mask);
-}
-
-static inline void write_uncore_prmrr(struct smm_relocation_params *relo_params)
-{
- printk(BIOS_DEBUG,
- "Writing UNCORE_PRMRR. base = 0x%08x, mask=0x%08x\n",
- relo_params->uncore_prmrr_base.lo,
- relo_params->uncore_prmrr_mask.lo);
- wrmsr(MSR_UNCORE_PRMRR_PHYS_BASE, relo_params->uncore_prmrr_base);
- wrmsr(MSR_UNCORE_PRMRR_PHYS_MASK, relo_params->uncore_prmrr_mask);
-}
static void update_save_state(int cpu, uintptr_t curr_smbase,
uintptr_t staggered_smbase,
diff --git a/src/cpu/intel/smm/Makefile.inc b/src/cpu/intel/smm/Makefile.inc
new file mode 100644
index 0000000..a49b796
--- /dev/null
+++ b/src/cpu/intel/smm/Makefile.inc
@@ -0,0 +1 @@
+ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smm_reloc.c
diff --git a/src/cpu/intel/smm/gen1/smmrelocate.c b/src/cpu/intel/smm/gen1/smmrelocate.c
index 5350d1c..c177e9b 100644
--- a/src/cpu/intel/smm/gen1/smmrelocate.c
+++ b/src/cpu/intel/smm/gen1/smmrelocate.c
@@ -39,17 +39,6 @@
#define C_BASE_SEG ((0 << 2) | (1 << 1) | (0 << 0))
-
-struct smm_relocation_params {
- uintptr_t ied_base;
- size_t ied_size;
- msr_t smrr_base;
- msr_t smrr_mask;
-};
-
-/* This gets filled in and used during relocation. */
-static struct smm_relocation_params smm_reloc_params;
-
/* On model_6fx, model_1067x and model_106cx SMRR functions slightly
differently. The MSR are at different location from the rest
and need to be explicitly enabled in IA32_FEATURE_CONTROL MSR. */
@@ -88,15 +77,6 @@
wrmsr(MSR_SMRR_PHYS_MASK, relo_params->smrr_mask);
}
-static void write_smrr(struct smm_relocation_params *relo_params)
-{
- printk(BIOS_DEBUG, "Writing SMRR. base = 0x%08x, mask=0x%08x\n",
- relo_params->smrr_base.lo, relo_params->smrr_mask.lo);
-
- wrmsr(IA32_SMRR_PHYS_BASE, relo_params->smrr_base);
- wrmsr(IA32_SMRR_PHYS_MASK, relo_params->smrr_mask);
-}
-
static void fill_in_relocation_params(struct smm_relocation_params *params)
{
uintptr_t tseg_base;
diff --git a/src/cpu/intel/smm/smm_reloc.c b/src/cpu/intel/smm/smm_reloc.c
new file mode 100644
index 0000000..860c095
--- /dev/null
+++ b/src/cpu/intel/smm/smm_reloc.c
@@ -0,0 +1,16 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <cpu/intel/smm_reloc.h>
+
+struct smm_relocation_params smm_reloc_params;
diff --git a/src/cpu/x86/Makefile.inc b/src/cpu/x86/Makefile.inc
index 9c18d44..55d1fad 100644
--- a/src/cpu/x86/Makefile.inc
+++ b/src/cpu/x86/Makefile.inc
@@ -6,6 +6,8 @@
ramstage-$(CONFIG_MIRROR_PAYLOAD_TO_RAM_BEFORE_LOADING) += mirror_payload.c
ramstage-y += backup_default_smm.c
+subdirs-$(CONFIG_CPU_INTEL_COMMON_SMM) += ../intel/smm
+
additional-dirs += $(obj)/cpu/x86
SIPI_ELF=$(obj)/cpu/x86/sipi_vector.elf
diff --git a/src/include/cpu/intel/smm_reloc.h b/src/include/cpu/intel/smm_reloc.h
index cb196fc..bef8d4e 100644
--- a/src/include/cpu/intel/smm_reloc.h
+++ b/src/include/cpu/intel/smm_reloc.h
@@ -14,7 +14,29 @@
#ifndef __INTEL_SMM_RELOC_H__
#define __INTEL_SMM_RELOC_H__
+#include <console/console.h>
#include <types.h>
+#include <cpu/x86/msr.h>
+#include <cpu/x86/mtrr.h>
+
+struct smm_relocation_params {
+ uintptr_t ied_base;
+ size_t ied_size;
+ msr_t smrr_base;
+ msr_t smrr_mask;
+ msr_t prmrr_base;
+ msr_t prmrr_mask;
+ msr_t uncore_prmrr_base;
+ msr_t uncore_prmrr_mask;
+ /*
+ * The smm_save_state_in_msrs field indicates if SMM save state
+ * locations live in MSRs. This indicates to the CPUs how to adjust
+ * the SMMBASE and IEDBASE
+ */
+ int smm_save_state_in_msrs;
+};
+
+extern struct smm_relocation_params smm_reloc_params;
struct ied_header {
char signature[10];
@@ -42,4 +64,36 @@
bool cpu_has_alternative_smrr(void);
+
+#define MSR_PRMRR_PHYS_BASE 0x1f4
+#define MSR_PRMRR_PHYS_MASK 0x1f5
+#define MSR_UNCORE_PRMRR_PHYS_BASE 0x2f4
+#define MSR_UNCORE_PRMRR_PHYS_MASK 0x2f5
+
+static inline void write_smrr(struct smm_relocation_params *relo_params)
+{
+ printk(BIOS_DEBUG, "Writing SMRR. base = 0x%08x, mask=0x%08x\n",
+ relo_params->smrr_base.lo, relo_params->smrr_mask.lo);
+ wrmsr(IA32_SMRR_PHYS_BASE, relo_params->smrr_base);
+ wrmsr(IA32_SMRR_PHYS_MASK, relo_params->smrr_mask);
+}
+
+static inline void write_prmrr(struct smm_relocation_params *relo_params)
+{
+ printk(BIOS_DEBUG, "Writing PRMRR. base = 0x%08x, mask=0x%08x\n",
+ relo_params->prmrr_base.lo, relo_params->prmrr_mask.lo);
+ wrmsr(MSR_PRMRR_PHYS_BASE, relo_params->prmrr_base);
+ wrmsr(MSR_PRMRR_PHYS_MASK, relo_params->prmrr_mask);
+}
+
+static inline void write_uncore_prmrr(struct smm_relocation_params *relo_params)
+{
+ printk(BIOS_DEBUG,
+ "Writing UNCORE_PRMRR. base = 0x%08x, mask=0x%08x\n",
+ relo_params->uncore_prmrr_base.lo,
+ relo_params->uncore_prmrr_mask.lo);
+ wrmsr(MSR_UNCORE_PRMRR_PHYS_BASE, relo_params->uncore_prmrr_base);
+ wrmsr(MSR_UNCORE_PRMRR_PHYS_MASK, relo_params->uncore_prmrr_mask);
+}
+
#endif
diff --git a/src/mainboard/google/auron/smihandler.c b/src/mainboard/google/auron/smihandler.c
index 4cc0aa8..862e2c3 100644
--- a/src/mainboard/google/auron/smihandler.c
+++ b/src/mainboard/google/auron/smihandler.c
@@ -19,7 +19,6 @@
#include <console/console.h>
#include <cpu/x86/smm.h>
#include <soc/pm.h>
-#include <soc/smm.h>
#include <elog.h>
#include <ec/google/chromeec/ec.h>
#include <soc/gpio.h>
diff --git a/src/mainboard/google/jecht/smihandler.c b/src/mainboard/google/jecht/smihandler.c
index 8e8c9d4..f324813 100644
--- a/src/mainboard/google/jecht/smihandler.c
+++ b/src/mainboard/google/jecht/smihandler.c
@@ -18,7 +18,6 @@
#include <console/console.h>
#include <cpu/x86/smm.h>
#include <soc/pm.h>
-#include <soc/smm.h>
#include <ec/google/chromeec/ec.h>
#include <soc/gpio.h>
#include <soc/iomap.h>
diff --git a/src/soc/intel/baytrail/cpu.c b/src/soc/intel/baytrail/cpu.c
index edc4e83..d12ece0 100644
--- a/src/soc/intel/baytrail/cpu.c
+++ b/src/soc/intel/baytrail/cpu.c
@@ -33,7 +33,6 @@
#include <soc/msr.h>
#include <soc/pattrs.h>
#include <soc/ramstage.h>
-#include <soc/smm.h>
/* Core level MSRs */
const struct reg_script core_msr_script[] = {
@@ -88,13 +87,6 @@
* MP and SMM loading initialization.
*/
-struct smm_relocation_params {
- msr_t smrr_base;
- msr_t smrr_mask;
-};
-
-static struct smm_relocation_params smm_reloc_params;
-
/* Package level MSRs */
static const struct reg_script package_msr_script[] = {
/* Set Package TDP to ~7W */
diff --git a/src/soc/intel/braswell/cpu.c b/src/soc/intel/braswell/cpu.c
index 665b030..a44b9cb 100644
--- a/src/soc/intel/braswell/cpu.c
+++ b/src/soc/intel/braswell/cpu.c
@@ -22,7 +22,6 @@
#include <cpu/intel/microcode.h>
#include <cpu/intel/smm_reloc.h>
#include <cpu/intel/turbo.h>
-#include <cpu/intel/smm_reloc.h>
#include <cpu/x86/cache.h>
#include <cpu/x86/lapic.h>
#include <cpu/x86/mp.h>
@@ -34,7 +33,6 @@
#include <soc/msr.h>
#include <soc/pattrs.h>
#include <soc/ramstage.h>
-#include <soc/smm.h>
#include <stdlib.h>
/* Core level MSRs */
@@ -98,13 +96,6 @@
* MP and SMM loading initialization.
*/
-struct smm_relocation_params {
- msr_t smrr_base;
- msr_t smrr_mask;
-};
-
-static struct smm_relocation_params smm_reloc_params;
-
/* Package level MSRs */
static const struct reg_script package_msr_script[] = {
/* Set Package TDP to ~7W */
diff --git a/src/soc/intel/broadwell/cpu.c b/src/soc/intel/broadwell/cpu.c
index 8fe66dc..287b5b5 100644
--- a/src/soc/intel/broadwell/cpu.c
+++ b/src/soc/intel/broadwell/cpu.c
@@ -36,7 +36,6 @@
#include <soc/pci_devs.h>
#include <soc/ramstage.h>
#include <soc/rcba.h>
-#include <soc/smm.h>
#include <soc/systemagent.h>
#include <soc/intel/broadwell/chip.h>
#include <cpu/intel/common/common.h>
diff --git a/src/soc/intel/broadwell/include/soc/smm.h b/src/soc/intel/broadwell/include/soc/smm.h
deleted file mode 100644
index 909294c..0000000
--- a/src/soc/intel/broadwell/include/soc/smm.h
+++ /dev/null
@@ -1,38 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2014 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#ifndef _BROADWELL_SMM_H_
-#define _BROADWELL_SMM_H_
-
-#include <stdint.h>
-#include <cpu/x86/msr.h>
-
-
-struct smm_relocation_params {
- uintptr_t ied_base;
- size_t ied_size;
- msr_t smrr_base;
- msr_t smrr_mask;
- msr_t prmrr_base;
- msr_t prmrr_mask;
- msr_t uncore_prmrr_base;
- msr_t uncore_prmrr_mask;
- /* The smm_save_state_in_msrs field indicates if SMM save state
- * locations live in MSRs. This indicates to the CPUs how to adjust
- * the SMMBASE and IEDBASE */
- int smm_save_state_in_msrs;
-};
-
-#endif
diff --git a/src/soc/intel/broadwell/memmap.c b/src/soc/intel/broadwell/memmap.c
index ad50dd3..48492d3 100644
--- a/src/soc/intel/broadwell/memmap.c
+++ b/src/soc/intel/broadwell/memmap.c
@@ -21,7 +21,6 @@
#include <device/pci_ops.h>
#include <soc/pci_devs.h>
#include <soc/systemagent.h>
-#include <soc/smm.h>
#include <stdint.h>
static uintptr_t dpr_region_start(void)
diff --git a/src/soc/intel/broadwell/pei_data.c b/src/soc/intel/broadwell/pei_data.c
index f745348..09753ad 100644
--- a/src/soc/intel/broadwell/pei_data.c
+++ b/src/soc/intel/broadwell/pei_data.c
@@ -19,7 +19,6 @@
#include <soc/iomap.h>
#include <soc/pei_data.h>
#include <soc/pei_wrapper.h>
-#include <soc/smm.h>
static void ABI_X86 send_to_console(unsigned char b)
{
diff --git a/src/soc/intel/broadwell/romstage/raminit.c b/src/soc/intel/broadwell/romstage/raminit.c
index c13761d..03b564f 100644
--- a/src/soc/intel/broadwell/romstage/raminit.c
+++ b/src/soc/intel/broadwell/romstage/raminit.c
@@ -33,7 +33,6 @@
#include <soc/pei_wrapper.h>
#include <soc/pm.h>
#include <soc/romstage.h>
-#include <soc/smm.h>
#include <soc/systemagent.h>
/*
diff --git a/src/soc/intel/broadwell/smi.c b/src/soc/intel/broadwell/smi.c
index 17196da..2bdeecc 100644
--- a/src/soc/intel/broadwell/smi.c
+++ b/src/soc/intel/broadwell/smi.c
@@ -24,7 +24,6 @@
#include <soc/iomap.h>
#include <soc/pch.h>
#include <soc/pm.h>
-#include <soc/smm.h>
void smm_southbridge_clear_state(void)
{
diff --git a/src/soc/intel/broadwell/smihandler.c b/src/soc/intel/broadwell/smihandler.c
index ca99487..c2843a7 100644
--- a/src/soc/intel/broadwell/smihandler.c
+++ b/src/soc/intel/broadwell/smihandler.c
@@ -33,7 +33,6 @@
#include <soc/pci_devs.h>
#include <soc/pm.h>
#include <soc/rcba.h>
-#include <soc/smm.h>
#include <soc/xhci.h>
#include <drivers/intel/gma/i915_reg.h>
diff --git a/src/soc/intel/broadwell/smmrelocate.c b/src/soc/intel/broadwell/smmrelocate.c
index 21c534a..b5af989 100644
--- a/src/soc/intel/broadwell/smmrelocate.c
+++ b/src/soc/intel/broadwell/smmrelocate.c
@@ -30,37 +30,8 @@
#include <soc/cpu.h>
#include <soc/msr.h>
#include <soc/pci_devs.h>
-#include <soc/smm.h>
#include <soc/systemagent.h>
-/* This gets filled in and used during relocation. */
-static struct smm_relocation_params smm_reloc_params;
-
-static inline void write_smrr(struct smm_relocation_params *relo_params)
-{
- printk(BIOS_DEBUG, "Writing SMRR. base = 0x%08x, mask=0x%08x\n",
- relo_params->smrr_base.lo, relo_params->smrr_mask.lo);
- wrmsr(IA32_SMRR_PHYS_BASE, relo_params->smrr_base);
- wrmsr(IA32_SMRR_PHYS_MASK, relo_params->smrr_mask);
-}
-
-static inline void write_prmrr(struct smm_relocation_params *relo_params)
-{
- printk(BIOS_DEBUG, "Writing PRMRR. base = 0x%08x, mask=0x%08x\n",
- relo_params->prmrr_base.lo, relo_params->prmrr_mask.lo);
- wrmsr(MSR_PRMRR_PHYS_BASE, relo_params->prmrr_base);
- wrmsr(MSR_PRMRR_PHYS_MASK, relo_params->prmrr_mask);
-}
-
-static inline void write_uncore_prmrr(struct smm_relocation_params *relo_params)
-{
- printk(BIOS_DEBUG,
- "Writing UNCORE_PRMRR. base = 0x%08x, mask=0x%08x\n",
- relo_params->uncore_prmrr_base.lo,
- relo_params->uncore_prmrr_mask.lo);
- wrmsr(MSR_UNCORE_PRMRR_PHYS_BASE, relo_params->uncore_prmrr_base);
- wrmsr(MSR_UNCORE_PRMRR_PHYS_MASK, relo_params->uncore_prmrr_mask);
-}
static void update_save_state(int cpu, uintptr_t curr_smbase,
uintptr_t staggered_smbase,
diff --git a/src/soc/intel/cannonlake/cpu.c b/src/soc/intel/cannonlake/cpu.c
index c3a27ae..f01b499 100644
--- a/src/soc/intel/cannonlake/cpu.c
+++ b/src/soc/intel/cannonlake/cpu.c
@@ -28,7 +28,6 @@
#include <soc/msr.h>
#include <soc/pci_devs.h>
#include <soc/pm.h>
-#include <soc/smm.h>
#include <soc/systemagent.h>
#include <cpu/x86/mtrr.h>
#include <cpu/intel/microcode.h>
diff --git a/src/soc/intel/cannonlake/include/soc/smm.h b/src/soc/intel/cannonlake/include/soc/smm.h
deleted file mode 100644
index 95c1abd..0000000
--- a/src/soc/intel/cannonlake/include/soc/smm.h
+++ /dev/null
@@ -1,39 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2014 Google Inc.
- * Copyright (C) 2017 Intel Corporation.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#ifndef _SOC_SMM_H_
-#define _SOC_SMM_H_
-
-#include <stdint.h>
-#include <cpu/x86/msr.h>
-#include <cpu/x86/smm.h>
-#include <soc/gpio.h>
-
-
-struct smm_relocation_params {
- uintptr_t ied_base;
- size_t ied_size;
- msr_t smrr_base;
- msr_t smrr_mask;
- /*
- * The smm_save_state_in_msrs field indicates if SMM save state
- * locations live in MSRs. This indicates to the CPUs how to adjust
- * the SMMBASE and IEDBASE
- */
- int smm_save_state_in_msrs;
-};
-
-#endif
diff --git a/src/soc/intel/cannonlake/smmrelocate.c b/src/soc/intel/cannonlake/smmrelocate.c
index 6680bf3..54e2f92 100644
--- a/src/soc/intel/cannonlake/smmrelocate.c
+++ b/src/soc/intel/cannonlake/smmrelocate.c
@@ -31,20 +31,9 @@
#include <soc/cpu.h>
#include <soc/msr.h>
#include <soc/pci_devs.h>
-#include <soc/smm.h>
#include <soc/systemagent.h>
#include "chip.h"
-/* This gets filled in and used during relocation. */
-static struct smm_relocation_params smm_reloc_params;
-
-static inline void write_smrr(struct smm_relocation_params *relo_params)
-{
- printk(BIOS_DEBUG, "Writing SMRR. base = 0x%08x, mask=0x%08x\n",
- relo_params->smrr_base.lo, relo_params->smrr_mask.lo);
- wrmsr(IA32_SMRR_PHYS_BASE, relo_params->smrr_base);
- wrmsr(IA32_SMRR_PHYS_MASK, relo_params->smrr_mask);
-}
static void update_save_state(int cpu, uintptr_t curr_smbase,
uintptr_t staggered_smbase,
diff --git a/src/soc/intel/icelake/Kconfig b/src/soc/intel/icelake/Kconfig
index 418c317..cb9de14 100644
--- a/src/soc/intel/icelake/Kconfig
+++ b/src/soc/intel/icelake/Kconfig
@@ -36,6 +36,7 @@
select SMP
select SOC_AHCI_PORT_IMPLEMENTED_INVERT
select PMC_GLOBAL_RESET_ENABLE_LOCK
+ select CPU_INTEL_COMMON_SMM
select SOC_INTEL_COMMON
select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE
select SOC_INTEL_COMMON_BLOCK
diff --git a/src/soc/intel/icelake/cpu.c b/src/soc/intel/icelake/cpu.c
index a2d9f7a..e058442 100644
--- a/src/soc/intel/icelake/cpu.c
+++ b/src/soc/intel/icelake/cpu.c
@@ -30,7 +30,6 @@
#include <soc/msr.h>
#include <soc/pci_devs.h>
#include <soc/pm.h>
-#include <soc/smm.h>
#include <soc/soc_chip.h>
static void soc_fsp_load(void)
diff --git a/src/soc/intel/icelake/include/soc/smm.h b/src/soc/intel/icelake/include/soc/smm.h
deleted file mode 100644
index 4393167..0000000
--- a/src/soc/intel/icelake/include/soc/smm.h
+++ /dev/null
@@ -1,38 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2018 Intel Corp.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#ifndef _SOC_SMM_H_
-#define _SOC_SMM_H_
-
-#include <stdint.h>
-#include <cpu/x86/msr.h>
-#include <cpu/x86/smm.h>
-#include <soc/gpio.h>
-
-
-struct smm_relocation_params {
- uintptr_t ied_base;
- size_t ied_size;
- msr_t smrr_base;
- msr_t smrr_mask;
- /*
- * The smm_save_state_in_msrs field indicates if SMM save state
- * locations live in MSRs. This indicates to the CPUs how to adjust
- * the SMMBASE and IEDBASE
- */
- int smm_save_state_in_msrs;
-};
-
-#endif
diff --git a/src/soc/intel/icelake/smmrelocate.c b/src/soc/intel/icelake/smmrelocate.c
index 8f56ad6..cc8a5ff 100644
--- a/src/soc/intel/icelake/smmrelocate.c
+++ b/src/soc/intel/icelake/smmrelocate.c
@@ -30,20 +30,9 @@
#include <soc/cpu.h>
#include <soc/msr.h>
#include <soc/pci_devs.h>
-#include <soc/smm.h>
#include <soc/soc_chip.h>
#include <soc/systemagent.h>
-/* This gets filled in and used during relocation. */
-static struct smm_relocation_params smm_reloc_params;
-
-static inline void write_smrr(struct smm_relocation_params *relo_params)
-{
- printk(BIOS_DEBUG, "Writing SMRR. base = 0x%08x, mask=0x%08x\n",
- relo_params->smrr_base.lo, relo_params->smrr_mask.lo);
- wrmsr(IA32_SMRR_PHYS_BASE, relo_params->smrr_base);
- wrmsr(IA32_SMRR_PHYS_MASK, relo_params->smrr_mask);
-}
static void update_save_state(int cpu, uintptr_t curr_smbase,
uintptr_t staggered_smbase,
diff --git a/src/soc/intel/skylake/cpu.c b/src/soc/intel/skylake/cpu.c
index 7a45693..f5273f6 100644
--- a/src/soc/intel/skylake/cpu.c
+++ b/src/soc/intel/skylake/cpu.c
@@ -41,7 +41,6 @@
#include <soc/pci_devs.h>
#include <soc/pm.h>
#include <soc/ramstage.h>
-#include <soc/smm.h>
#include <soc/systemagent.h>
#include <timer.h>
diff --git a/src/soc/intel/skylake/include/soc/smm.h b/src/soc/intel/skylake/include/soc/smm.h
deleted file mode 100644
index 88ce9e3..0000000
--- a/src/soc/intel/skylake/include/soc/smm.h
+++ /dev/null
@@ -1,40 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2014 Google Inc.
- * Copyright (C) 2015 Intel Corporation.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#ifndef _SOC_SMM_H_
-#define _SOC_SMM_H_
-
-#include <stdint.h>
-#include <cpu/x86/msr.h>
-#include <cpu/x86/smm.h>
-#include <intelblocks/smihandler.h>
-#include <soc/gpio.h>
-
-
-struct smm_relocation_params {
- uintptr_t ied_base;
- size_t ied_size;
- msr_t smrr_base;
- msr_t smrr_mask;
- /*
- * The smm_save_state_in_msrs field indicates if SMM save state
- * locations live in MSRs. This indicates to the CPUs how to adjust
- * the SMMBASE and IEDBASE
- */
- int smm_save_state_in_msrs;
-};
-
-#endif
diff --git a/src/soc/intel/skylake/smmrelocate.c b/src/soc/intel/skylake/smmrelocate.c
index e1779d1..65d96ae 100644
--- a/src/soc/intel/skylake/smmrelocate.c
+++ b/src/soc/intel/skylake/smmrelocate.c
@@ -31,20 +31,9 @@
#include <soc/cpu.h>
#include <soc/msr.h>
#include <soc/pci_devs.h>
-#include <soc/smm.h>
#include <soc/systemagent.h>
#include "chip.h"
-/* This gets filled in and used during relocation. */
-static struct smm_relocation_params smm_reloc_params;
-
-static inline void write_smrr(struct smm_relocation_params *relo_params)
-{
- printk(BIOS_DEBUG, "Writing SMRR. base = 0x%08x, mask=0x%08x\n",
- relo_params->smrr_base.lo, relo_params->smrr_mask.lo);
- wrmsr(IA32_SMRR_PHYS_BASE, relo_params->smrr_base);
- wrmsr(IA32_SMRR_PHYS_MASK, relo_params->smrr_mask);
-}
static void update_save_state(int cpu, uintptr_t curr_smbase,
uintptr_t staggered_smbase,
diff --git a/src/soc/intel/tigerlake/cpu.c b/src/soc/intel/tigerlake/cpu.c
index 4174cd2..5f4f081 100644
--- a/src/soc/intel/tigerlake/cpu.c
+++ b/src/soc/intel/tigerlake/cpu.c
@@ -36,7 +36,6 @@
#include <soc/msr.h>
#include <soc/pci_devs.h>
#include <soc/pm.h>
-#include <soc/smm.h>
#include <soc/soc_chip.h>
static void soc_fsp_load(void)
diff --git a/src/soc/intel/tigerlake/include/soc/smm.h b/src/soc/intel/tigerlake/include/soc/smm.h
deleted file mode 100644
index 4393167..0000000
--- a/src/soc/intel/tigerlake/include/soc/smm.h
+++ /dev/null
@@ -1,38 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2018 Intel Corp.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#ifndef _SOC_SMM_H_
-#define _SOC_SMM_H_
-
-#include <stdint.h>
-#include <cpu/x86/msr.h>
-#include <cpu/x86/smm.h>
-#include <soc/gpio.h>
-
-
-struct smm_relocation_params {
- uintptr_t ied_base;
- size_t ied_size;
- msr_t smrr_base;
- msr_t smrr_mask;
- /*
- * The smm_save_state_in_msrs field indicates if SMM save state
- * locations live in MSRs. This indicates to the CPUs how to adjust
- * the SMMBASE and IEDBASE
- */
- int smm_save_state_in_msrs;
-};
-
-#endif
diff --git a/src/soc/intel/tigerlake/smmrelocate.c b/src/soc/intel/tigerlake/smmrelocate.c
index b3f9836..53f206d 100644
--- a/src/soc/intel/tigerlake/smmrelocate.c
+++ b/src/soc/intel/tigerlake/smmrelocate.c
@@ -30,7 +30,6 @@
#include <soc/cpu.h>
#include <soc/msr.h>
#include <soc/pci_devs.h>
-#include <soc/smm.h>
#include <soc/soc_chip.h>
#include <soc/systemagent.h>
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