Kyösti Mälkki has uploaded this change for review.
intel/smm: Provide common smm_relocation_params
Pull in all copies of smm_relocation_params structs defined
for intel platforms.
Pull in all the inlined MSR accessors to the header file.
Change-Id: I39c6cffee95433aea1a3c783b869eedfff094413
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
---
M src/cpu/intel/haswell/smmrelocate.c
M src/cpu/intel/smm/gen1/smmrelocate.c
A src/include/cpu/intel/smm_reloc.h
M src/soc/intel/apollolake/cpu.c
M src/soc/intel/baytrail/cpu.c
M src/soc/intel/broadwell/include/soc/smm.h
M src/soc/intel/broadwell/smmrelocate.c
M src/soc/intel/cannonlake/include/soc/smm.h
M src/soc/intel/cannonlake/smmrelocate.c
M src/soc/intel/common/Makefile.inc
M src/soc/intel/fsp_broadwell_de/include/soc/smm.h
M src/soc/intel/fsp_broadwell_de/smmrelocate.c
M src/soc/intel/icelake/include/soc/smm.h
M src/soc/intel/icelake/smmrelocate.c
M src/soc/intel/skylake/include/soc/smm.h
M src/soc/intel/skylake/smmrelocate.c
16 files changed, 91 insertions(+), 185 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/34840/1
diff --git a/src/cpu/intel/haswell/smmrelocate.c b/src/cpu/intel/haswell/smmrelocate.c
index 5cda618..5a26aff 100644
--- a/src/cpu/intel/haswell/smmrelocate.c
+++ b/src/cpu/intel/haswell/smmrelocate.c
@@ -25,6 +25,7 @@
#include <cpu/x86/mtrr.h>
#include <cpu/x86/smm.h>
#include <cpu/intel/em64t101_save_state.h>
+#include <cpu/intel/smm_reloc.h>
#include <console/console.h>
#include <northbridge/intel/haswell/haswell.h>
#include <southbridge/intel/lynxpoint/pch.h>
@@ -46,49 +47,10 @@
#define SMRR_SUPPORTED (1 << 11)
#define PRMRR_SUPPORTED (1 << 12)
-struct smm_relocation_params {
- uintptr_t ied_base;
- size_t ied_size;
- msr_t smrr_base;
- msr_t smrr_mask;
- msr_t prmrr_base;
- msr_t prmrr_mask;
- msr_t uncore_prmrr_base;
- msr_t uncore_prmrr_mask;
- /* The smm_save_state_in_msrs field indicates if SMM save state
- * locations live in MSRs. This indicates to the CPUs how to adjust
- * the SMMBASE and IEDBASE */
- int smm_save_state_in_msrs;
-};
/* This gets filled in and used during relocation. */
-static struct smm_relocation_params smm_reloc_params;
+struct smm_relocation_params smm_reloc_params;
-static inline void write_smrr(struct smm_relocation_params *relo_params)
-{
- printk(BIOS_DEBUG, "Writing SMRR. base = 0x%08x, mask=0x%08x\n",
- relo_params->smrr_base.lo, relo_params->smrr_mask.lo);
- wrmsr(IA32_SMRR_PHYS_BASE, relo_params->smrr_base);
- wrmsr(IA32_SMRR_PHYS_MASK, relo_params->smrr_mask);
-}
-
-static inline void write_prmrr(struct smm_relocation_params *relo_params)
-{
- printk(BIOS_DEBUG, "Writing PRMRR. base = 0x%08x, mask=0x%08x\n",
- relo_params->prmrr_base.lo, relo_params->prmrr_mask.lo);
- wrmsr(MSR_PRMRR_PHYS_BASE, relo_params->prmrr_base);
- wrmsr(MSR_PRMRR_PHYS_MASK, relo_params->prmrr_mask);
-}
-
-static inline void write_uncore_prmrr(struct smm_relocation_params *relo_params)
-{
- printk(BIOS_DEBUG,
- "Writing UNCORE_PRMRR. base = 0x%08x, mask=0x%08x\n",
- relo_params->uncore_prmrr_base.lo,
- relo_params->uncore_prmrr_mask.lo);
- wrmsr(MSR_UNCORE_PRMRR_PHYS_BASE, relo_params->uncore_prmrr_base);
- wrmsr(MSR_UNCORE_PRMRR_PHYS_MASK, relo_params->uncore_prmrr_mask);
-}
static void update_save_state(int cpu, uintptr_t curr_smbase,
uintptr_t staggered_smbase,
diff --git a/src/cpu/intel/smm/gen1/smmrelocate.c b/src/cpu/intel/smm/gen1/smmrelocate.c
index d200805..bb19c8c 100644
--- a/src/cpu/intel/smm/gen1/smmrelocate.c
+++ b/src/cpu/intel/smm/gen1/smmrelocate.c
@@ -28,6 +28,7 @@
#include <cpu/x86/mtrr.h>
#include <cpu/x86/smm.h>
#include <cpu/intel/em64t101_save_state.h>
+#include <cpu/intel/smm_reloc.h>
#include <console/console.h>
#include <smp/node.h>
#include "smi.h"
@@ -47,15 +48,9 @@
} __packed;
-struct smm_relocation_params {
- uintptr_t ied_base;
- size_t ied_size;
- msr_t smrr_base;
- msr_t smrr_mask;
-};
/* This gets filled in and used during relocation. */
-static struct smm_relocation_params smm_reloc_params;
+struct smm_relocation_params smm_reloc_params;
/* On model_6fx, model_1067x and model_106cx SMRR functions slightly
differently. The MSR are at different location from the rest
@@ -95,15 +90,6 @@
wrmsr(MSR_SMRR_PHYS_MASK, relo_params->smrr_mask);
}
-static void write_smrr(struct smm_relocation_params *relo_params)
-{
- printk(BIOS_DEBUG, "Writing SMRR. base = 0x%08x, mask=0x%08x\n",
- relo_params->smrr_base.lo, relo_params->smrr_mask.lo);
-
- wrmsr(IA32_SMRR_PHYS_BASE, relo_params->smrr_base);
- wrmsr(IA32_SMRR_PHYS_MASK, relo_params->smrr_mask);
-}
-
static void fill_in_relocation_params(struct smm_relocation_params *params)
{
uintptr_t tseg_base;
diff --git a/src/include/cpu/intel/smm_reloc.h b/src/include/cpu/intel/smm_reloc.h
new file mode 100644
index 0000000..cbcdb56
--- /dev/null
+++ b/src/include/cpu/intel/smm_reloc.h
@@ -0,0 +1,73 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __INTEL_SMM_RELOC_H__
+#define __INTEL_SMM_RELOC_H__
+
+#include <console/console.h>
+#include <cpu/x86/msr.h>
+#include <cpu/x86/mtrr.h>
+
+struct smm_relocation_params {
+ uintptr_t ied_base;
+ size_t ied_size;
+ msr_t smrr_base;
+ msr_t smrr_mask;
+ msr_t prmrr_base;
+ msr_t prmrr_mask;
+ msr_t uncore_prmrr_base;
+ msr_t uncore_prmrr_mask;
+ /*
+ * The smm_save_state_in_msrs field indicates if SMM save state
+ * locations live in MSRs. This indicates to the CPUs how to adjust
+ * the SMMBASE and IEDBASE
+ */
+ int smm_save_state_in_msrs;
+};
+
+extern struct smm_relocation_params smm_reloc_params;
+
+void fill_in_smrr(struct smm_relocation_params *params);
+
+#define MSR_PRMRR_PHYS_BASE 0x1f4
+#define MSR_PRMRR_PHYS_MASK 0x1f5
+#define MSR_UNCORE_PRMRR_PHYS_BASE 0x2f4
+#define MSR_UNCORE_PRMRR_PHYS_MASK 0x2f5
+
+static inline void write_smrr(struct smm_relocation_params *relo_params)
+{
+ printk(BIOS_DEBUG, "Writing SMRR. base = 0x%08x, mask=0x%08x\n",
+ relo_params->smrr_base.lo, relo_params->smrr_mask.lo);
+ wrmsr(IA32_SMRR_PHYS_BASE, relo_params->smrr_base);
+ wrmsr(IA32_SMRR_PHYS_MASK, relo_params->smrr_mask);
+}
+
+static inline void write_prmrr(struct smm_relocation_params *relo_params)
+{
+ printk(BIOS_DEBUG, "Writing PRMRR. base = 0x%08x, mask=0x%08x\n",
+ relo_params->prmrr_base.lo, relo_params->prmrr_mask.lo);
+ wrmsr(MSR_PRMRR_PHYS_BASE, relo_params->prmrr_base);
+ wrmsr(MSR_PRMRR_PHYS_MASK, relo_params->prmrr_mask);
+}
+
+static inline void write_uncore_prmrr(struct smm_relocation_params *relo_params)
+{
+ printk(BIOS_DEBUG,
+ "Writing UNCORE_PRMRR. base = 0x%08x, mask=0x%08x\n",
+ relo_params->uncore_prmrr_base.lo,
+ relo_params->uncore_prmrr_mask.lo);
+ wrmsr(MSR_UNCORE_PRMRR_PHYS_BASE, relo_params->uncore_prmrr_base);
+ wrmsr(MSR_UNCORE_PRMRR_PHYS_MASK, relo_params->uncore_prmrr_mask);
+}
+
+#endif
diff --git a/src/soc/intel/apollolake/cpu.c b/src/soc/intel/apollolake/cpu.c
index 9fbcc07..e834142 100644
--- a/src/soc/intel/apollolake/cpu.c
+++ b/src/soc/intel/apollolake/cpu.c
@@ -31,6 +31,7 @@
#include <cpu/x86/mtrr.h>
#include <cpu/x86/smm.h>
#include <cpu/intel/em64t100_save_state.h>
+#include <cpu/intel/smm_reloc.h>
#include <device/device.h>
#include <device/pci.h>
#include <fsp/api.h>
diff --git a/src/soc/intel/baytrail/cpu.c b/src/soc/intel/baytrail/cpu.c
index d25a740..05d7a82 100644
--- a/src/soc/intel/baytrail/cpu.c
+++ b/src/soc/intel/baytrail/cpu.c
@@ -26,6 +26,7 @@
#include <cpu/x86/mtrr.h>
#include <cpu/x86/smm.h>
#include <cpu/intel/em64t100_save_state.h>
+#include <cpu/intel/smm_reloc.h>
#include <reg_script.h>
#include <soc/iosf.h>
diff --git a/src/soc/intel/broadwell/include/soc/smm.h b/src/soc/intel/broadwell/include/soc/smm.h
index 9ad3128..08c1ad8 100644
--- a/src/soc/intel/broadwell/include/soc/smm.h
+++ b/src/soc/intel/broadwell/include/soc/smm.h
@@ -25,20 +25,6 @@
u8 reserved[34];
} __packed;
-struct smm_relocation_params {
- uintptr_t ied_base;
- size_t ied_size;
- msr_t smrr_base;
- msr_t smrr_mask;
- msr_t prmrr_base;
- msr_t prmrr_mask;
- msr_t uncore_prmrr_base;
- msr_t uncore_prmrr_mask;
- /* The smm_save_state_in_msrs field indicates if SMM save state
- * locations live in MSRs. This indicates to the CPUs how to adjust
- * the SMMBASE and IEDBASE */
- int smm_save_state_in_msrs;
-};
void smm_relocation_handler(int cpu, uintptr_t curr_smbase,
uintptr_t staggered_smbase);
diff --git a/src/soc/intel/broadwell/smmrelocate.c b/src/soc/intel/broadwell/smmrelocate.c
index 2cf97e3..5cac560 100644
--- a/src/soc/intel/broadwell/smmrelocate.c
+++ b/src/soc/intel/broadwell/smmrelocate.c
@@ -25,6 +25,7 @@
#include <cpu/x86/mtrr.h>
#include <cpu/x86/smm.h>
#include <cpu/intel/em64t101_save_state.h>
+#include <cpu/intel/smm_reloc.h>
#include <console/console.h>
#include <soc/cpu.h>
#include <soc/msr.h>
@@ -33,33 +34,8 @@
#include <soc/systemagent.h>
/* This gets filled in and used during relocation. */
-static struct smm_relocation_params smm_reloc_params;
+struct smm_relocation_params smm_reloc_params;
-static inline void write_smrr(struct smm_relocation_params *relo_params)
-{
- printk(BIOS_DEBUG, "Writing SMRR. base = 0x%08x, mask=0x%08x\n",
- relo_params->smrr_base.lo, relo_params->smrr_mask.lo);
- wrmsr(IA32_SMRR_PHYS_BASE, relo_params->smrr_base);
- wrmsr(IA32_SMRR_PHYS_MASK, relo_params->smrr_mask);
-}
-
-static inline void write_prmrr(struct smm_relocation_params *relo_params)
-{
- printk(BIOS_DEBUG, "Writing PRMRR. base = 0x%08x, mask=0x%08x\n",
- relo_params->prmrr_base.lo, relo_params->prmrr_mask.lo);
- wrmsr(MSR_PRMRR_PHYS_BASE, relo_params->prmrr_base);
- wrmsr(MSR_PRMRR_PHYS_MASK, relo_params->prmrr_mask);
-}
-
-static inline void write_uncore_prmrr(struct smm_relocation_params *relo_params)
-{
- printk(BIOS_DEBUG,
- "Writing UNCORE_PRMRR. base = 0x%08x, mask=0x%08x\n",
- relo_params->uncore_prmrr_base.lo,
- relo_params->uncore_prmrr_mask.lo);
- wrmsr(MSR_UNCORE_PRMRR_PHYS_BASE, relo_params->uncore_prmrr_base);
- wrmsr(MSR_UNCORE_PRMRR_PHYS_MASK, relo_params->uncore_prmrr_mask);
-}
static void update_save_state(int cpu, uintptr_t curr_smbase,
uintptr_t staggered_smbase,
diff --git a/src/soc/intel/cannonlake/include/soc/smm.h b/src/soc/intel/cannonlake/include/soc/smm.h
index ed8cbef..3c1f35c 100644
--- a/src/soc/intel/cannonlake/include/soc/smm.h
+++ b/src/soc/intel/cannonlake/include/soc/smm.h
@@ -28,19 +28,6 @@
u8 reserved[34];
} __packed;
-struct smm_relocation_params {
- uintptr_t ied_base;
- size_t ied_size;
- msr_t smrr_base;
- msr_t smrr_mask;
- /*
- * The smm_save_state_in_msrs field indicates if SMM save state
- * locations live in MSRs. This indicates to the CPUs how to adjust
- * the SMMBASE and IEDBASE
- */
- int smm_save_state_in_msrs;
-};
-
/* Mainboard handler for eSPI SMIs */
void mainboard_smi_espi_handler(void);
diff --git a/src/soc/intel/cannonlake/smmrelocate.c b/src/soc/intel/cannonlake/smmrelocate.c
index 3da1a56..a552b58 100644
--- a/src/soc/intel/cannonlake/smmrelocate.c
+++ b/src/soc/intel/cannonlake/smmrelocate.c
@@ -27,6 +27,7 @@
#include <cpu/x86/mtrr.h>
#include <cpu/x86/smm.h>
#include <cpu/intel/em64t101_save_state.h>
+#include <cpu/intel/smm_reloc.h>
#include <console/console.h>
#include <intelblocks/smm.h>
#include <soc/cpu.h>
@@ -37,15 +38,8 @@
#include "chip.h"
/* This gets filled in and used during relocation. */
-static struct smm_relocation_params smm_reloc_params;
+struct smm_relocation_params smm_reloc_params;
-static inline void write_smrr(struct smm_relocation_params *relo_params)
-{
- printk(BIOS_DEBUG, "Writing SMRR. base = 0x%08x, mask=0x%08x\n",
- relo_params->smrr_base.lo, relo_params->smrr_mask.lo);
- wrmsr(IA32_SMRR_PHYS_BASE, relo_params->smrr_base);
- wrmsr(IA32_SMRR_PHYS_MASK, relo_params->smrr_mask);
-}
static void update_save_state(int cpu, uintptr_t curr_smbase,
uintptr_t staggered_smbase,
diff --git a/src/soc/intel/common/Makefile.inc b/src/soc/intel/common/Makefile.inc
index 22d350c..b5d45bb 100644
--- a/src/soc/intel/common/Makefile.inc
+++ b/src/soc/intel/common/Makefile.inc
@@ -4,6 +4,8 @@
subdirs-y += block/
subdirs-y += pch/
+subdirs-y += ../../../cpu/intel/smm
+
verstage-$(CONFIG_SOC_INTEL_COMMON_RESET) += reset.c
bootblock-$(CONFIG_SOC_INTEL_COMMON_RESET) += reset.c
diff --git a/src/soc/intel/fsp_broadwell_de/include/soc/smm.h b/src/soc/intel/fsp_broadwell_de/include/soc/smm.h
index 3307cb0..3040688 100644
--- a/src/soc/intel/fsp_broadwell_de/include/soc/smm.h
+++ b/src/soc/intel/fsp_broadwell_de/include/soc/smm.h
@@ -26,18 +26,6 @@
u8 reserved[34];
} __packed;
-struct smm_relocation_params {
- uintptr_t ied_base;
- size_t ied_size;
- msr_t smrr_base;
- msr_t smrr_mask;
- msr_t prmrr_base;
- msr_t prmrr_mask;
- /* The smm_save_state_in_msrs field indicates if SMM save state
- locations live in MSRs. This indicates to the CPUs how to adjust
- the SMMBASE and IEDBASE. */
- int smm_save_state_in_msrs;
-};
void smm_relocation_handler(int cpu, uintptr_t curr_smbase,
uintptr_t staggered_smbase);
diff --git a/src/soc/intel/fsp_broadwell_de/smmrelocate.c b/src/soc/intel/fsp_broadwell_de/smmrelocate.c
index 283f5c1..d797438 100644
--- a/src/soc/intel/fsp_broadwell_de/smmrelocate.c
+++ b/src/soc/intel/fsp_broadwell_de/smmrelocate.c
@@ -24,6 +24,7 @@
#include <cpu/x86/mtrr.h>
#include <cpu/x86/smm.h>
#include <cpu/intel/em64t101_save_state.h>
+#include <cpu/intel/smm_reloc.h>
#include <console/console.h>
#include <device/pci_ops.h>
#include <soc/lpc.h>
@@ -33,23 +34,8 @@
#include <soc/broadwell_de.h>
/* This gets filled in and used during relocation. */
-static struct smm_relocation_params smm_reloc_params;
+struct smm_relocation_params smm_reloc_params;
-static inline void write_smrr(struct smm_relocation_params *relo_params)
-{
- printk(BIOS_DEBUG, "Writing SMRR. base = 0x%08x, mask=0x%08x\n",
- relo_params->smrr_base.lo, relo_params->smrr_mask.lo);
- wrmsr(IA32_SMRR_PHYS_BASE, relo_params->smrr_base);
- wrmsr(IA32_SMRR_PHYS_MASK, relo_params->smrr_mask);
-}
-
-static inline void write_prmrr(struct smm_relocation_params *relo_params)
-{
- printk(BIOS_DEBUG, "Writing PRMRR. base = 0x%08x, mask=0x%08x\n",
- relo_params->prmrr_base.lo, relo_params->prmrr_mask.lo);
- wrmsr(MSR_PRMRR_PHYS_BASE, relo_params->prmrr_base);
- wrmsr(MSR_PRMRR_PHYS_MASK, relo_params->prmrr_mask);
-}
static void update_save_state(int cpu, uintptr_t curr_smbase,
uintptr_t staggered_smbase,
diff --git a/src/soc/intel/icelake/include/soc/smm.h b/src/soc/intel/icelake/include/soc/smm.h
index 5d64d3b..b427085 100644
--- a/src/soc/intel/icelake/include/soc/smm.h
+++ b/src/soc/intel/icelake/include/soc/smm.h
@@ -27,18 +27,6 @@
u8 reserved[34];
} __packed;
-struct smm_relocation_params {
- uintptr_t ied_base;
- size_t ied_size;
- msr_t smrr_base;
- msr_t smrr_mask;
- /*
- * The smm_save_state_in_msrs field indicates if SMM save state
- * locations live in MSRs. This indicates to the CPUs how to adjust
- * the SMMBASE and IEDBASE
- */
- int smm_save_state_in_msrs;
-};
/* Mainboard handler for eSPI SMIs */
void mainboard_smi_espi_handler(void);
diff --git a/src/soc/intel/icelake/smmrelocate.c b/src/soc/intel/icelake/smmrelocate.c
index 3e949b2..21b9a13 100644
--- a/src/soc/intel/icelake/smmrelocate.c
+++ b/src/soc/intel/icelake/smmrelocate.c
@@ -26,6 +26,7 @@
#include <cpu/x86/mtrr.h>
#include <cpu/x86/smm.h>
#include <cpu/intel/em64t101_save_state.h>
+#include <cpu/intel/smm_reloc.h>
#include <console/console.h>
#include <intelblocks/smm.h>
#include <soc/cpu.h>
@@ -36,15 +37,8 @@
#include <soc/systemagent.h>
/* This gets filled in and used during relocation. */
-static struct smm_relocation_params smm_reloc_params;
+struct smm_relocation_params smm_reloc_params;
-static inline void write_smrr(struct smm_relocation_params *relo_params)
-{
- printk(BIOS_DEBUG, "Writing SMRR. base = 0x%08x, mask=0x%08x\n",
- relo_params->smrr_base.lo, relo_params->smrr_mask.lo);
- wrmsr(IA32_SMRR_PHYS_BASE, relo_params->smrr_base);
- wrmsr(IA32_SMRR_PHYS_MASK, relo_params->smrr_mask);
-}
static void update_save_state(int cpu, uintptr_t curr_smbase,
uintptr_t staggered_smbase,
diff --git a/src/soc/intel/skylake/include/soc/smm.h b/src/soc/intel/skylake/include/soc/smm.h
index 6eb6b1e..8fa415c 100644
--- a/src/soc/intel/skylake/include/soc/smm.h
+++ b/src/soc/intel/skylake/include/soc/smm.h
@@ -29,18 +29,6 @@
u8 reserved[34];
} __packed;
-struct smm_relocation_params {
- uintptr_t ied_base;
- size_t ied_size;
- msr_t smrr_base;
- msr_t smrr_mask;
- /*
- * The smm_save_state_in_msrs field indicates if SMM save state
- * locations live in MSRs. This indicates to the CPUs how to adjust
- * the SMMBASE and IEDBASE
- */
- int smm_save_state_in_msrs;
-};
void smm_relocation_handler(int cpu, uintptr_t curr_smbase,
uintptr_t staggered_smbase);
diff --git a/src/soc/intel/skylake/smmrelocate.c b/src/soc/intel/skylake/smmrelocate.c
index ebb853a..b80aa14 100644
--- a/src/soc/intel/skylake/smmrelocate.c
+++ b/src/soc/intel/skylake/smmrelocate.c
@@ -26,6 +26,7 @@
#include <cpu/x86/mtrr.h>
#include <cpu/x86/smm.h>
#include <cpu/intel/em64t101_save_state.h>
+#include <cpu/intel/smm_reloc.h>
#include <console/console.h>
#include <intelblocks/smm.h>
#include <soc/cpu.h>
@@ -36,15 +37,8 @@
#include "chip.h"
/* This gets filled in and used during relocation. */
-static struct smm_relocation_params smm_reloc_params;
+struct smm_relocation_params smm_reloc_params;
-static inline void write_smrr(struct smm_relocation_params *relo_params)
-{
- printk(BIOS_DEBUG, "Writing SMRR. base = 0x%08x, mask=0x%08x\n",
- relo_params->smrr_base.lo, relo_params->smrr_mask.lo);
- wrmsr(IA32_SMRR_PHYS_BASE, relo_params->smrr_base);
- wrmsr(IA32_SMRR_PHYS_MASK, relo_params->smrr_mask);
-}
static void update_save_state(int cpu, uintptr_t curr_smbase,
uintptr_t staggered_smbase,
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