Hello Aaron Durbin,
I'd like you to do a code review. Please visit
https://review.coreboot.org/c/coreboot/+/38424
to review the following change.
Change subject: cbfs: Enable CBFS mcache on (almost) all boards ......................................................................
cbfs: Enable CBFS mcache on (almost) all boards
This patch flips the default of CONFIG_NO_CBFS_MCACHE so the feature is enabled by default. Only a few boards with notoriously little space still have it explicitly disabled. All others get the new section added to their memlayout... 8K seems like a sane default to start with.
Change-Id: I0abd1c813aece6e78fb883f292ce6c9319545c44 Signed-off-by: Julius Werner jwerner@chromium.org --- M src/arch/x86/Kconfig M src/arch/x86/car.ld M src/cpu/ti/am335x/memlayout.ld M src/lib/Kconfig M src/mainboard/emulation/qemu-aarch64/memlayout.ld M src/mainboard/emulation/qemu-armv7/memlayout.ld M src/mainboard/emulation/qemu-power8/memlayout.ld M src/mainboard/emulation/qemu-riscv/memlayout.ld M src/mainboard/emulation/spike-riscv/memlayout.ld M src/mainboard/google/octopus/Kconfig M src/soc/cavium/cn81xx/include/soc/memlayout.ld M src/soc/mediatek/mt8173/include/soc/memlayout.ld M src/soc/mediatek/mt8183/include/soc/memlayout.ld M src/soc/nvidia/tegra124/include/soc/memlayout.ld M src/soc/nvidia/tegra210/include/soc/memlayout.ld M src/soc/qualcomm/ipq40xx/include/soc/memlayout.ld M src/soc/qualcomm/ipq806x/include/soc/memlayout.ld M src/soc/qualcomm/qcs405/include/soc/memlayout.ld M src/soc/qualcomm/sc7180/include/soc/memlayout.ld M src/soc/qualcomm/sdm845/include/soc/memlayout.ld M src/soc/rockchip/rk3288/Kconfig M src/soc/rockchip/rk3399/include/soc/memlayout.ld M src/soc/samsung/exynos5250/include/soc/memlayout.ld M src/soc/samsung/exynos5420/include/soc/memlayout.ld M src/soc/sifive/fu540/include/soc/memlayout.ld 25 files changed, 51 insertions(+), 20 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/24/38424/1
diff --git a/src/arch/x86/Kconfig b/src/arch/x86/Kconfig index 1c55bdb..7cf049d 100644 --- a/src/arch/x86/Kconfig +++ b/src/arch/x86/Kconfig @@ -155,6 +155,13 @@ help Increase this value if preram cbmem console is getting truncated
+config CBFS_MCACHE_SIZE + hex + depends on !NO_CBFS_MCACHE + default 0x2000 + help + Increase this value if you see CBFS mcache overflow warnings + config PC80_SYSTEM bool default y if ARCH_X86 diff --git a/src/arch/x86/car.ld b/src/arch/x86/car.ld index 2e29112..52e081a 100644 --- a/src/arch/x86/car.ld +++ b/src/arch/x86/car.ld @@ -60,6 +60,9 @@ #if !CONFIG(NO_FMAP_CACHE) FMAP_CACHE(., FMAP_SIZE) #endif +#if !CONFIG(NO_CBFS_MCACHE) + CBFS_MCACHE(., CONFIG_CBFS_MCACHE_SIZE) +#endif
_car_ehci_dbg_info = .; /* Reserve sizeof(struct ehci_dbg_info). */ diff --git a/src/cpu/ti/am335x/memlayout.ld b/src/cpu/ti/am335x/memlayout.ld index f69a315..9bc7b75 100644 --- a/src/cpu/ti/am335x/memlayout.ld +++ b/src/cpu/ti/am335x/memlayout.ld @@ -19,7 +19,8 @@ { DRAM_START(0x40000000) BOOTBLOCK(0x402f0400, 20K) - ROMSTAGE(0x402f5400, 88K) + ROMSTAGE(0x402f5400, 80K) + CBFS_MCACHE(0x40309400, 8K) FMAP_CACHE(0x4030b400, 2K) STACK(0x4030be00, 4K) RAMSTAGE(0x80200000, 192K) diff --git a/src/lib/Kconfig b/src/lib/Kconfig index 26bf0be..4d2bf80 100644 --- a/src/lib/Kconfig +++ b/src/lib/Kconfig @@ -78,7 +78,6 @@
config NO_CBFS_MCACHE bool - default y help Disables the CBFS metadata cache. This means that your platform does not need to provide a CBFS_MCACHE section in memlayout and can save diff --git a/src/mainboard/emulation/qemu-aarch64/memlayout.ld b/src/mainboard/emulation/qemu-aarch64/memlayout.ld index aba4205..544f89f 100644 --- a/src/mainboard/emulation/qemu-aarch64/memlayout.ld +++ b/src/mainboard/emulation/qemu-aarch64/memlayout.ld @@ -24,7 +24,8 @@
DRAM_START(0x40000000) BOOTBLOCK(0x60010000, 64K) - STACK(0x60020000, 62K) + STACK(0x60020000, 54K) + CBFS_MCACHE(0x6002D800, 8K) FMAP_CACHE(0x6002F800, 2K) ROMSTAGE(0x60030000, 128K) RAMSTAGE(0x60070000, 16M) diff --git a/src/mainboard/emulation/qemu-armv7/memlayout.ld b/src/mainboard/emulation/qemu-armv7/memlayout.ld index 2b33cb3..de09cbb 100644 --- a/src/mainboard/emulation/qemu-armv7/memlayout.ld +++ b/src/mainboard/emulation/qemu-armv7/memlayout.ld @@ -43,6 +43,7 @@
BOOTBLOCK(0x00000, 64K) FMAP_CACHE(0x10000, 2K) + CBFS_MCACHE(0x10800, 8K)
DRAM_START(0x60000000) STACK(0x60000000, 64K) diff --git a/src/mainboard/emulation/qemu-power8/memlayout.ld b/src/mainboard/emulation/qemu-power8/memlayout.ld index c22d3e4..81fe7f4 100644 --- a/src/mainboard/emulation/qemu-power8/memlayout.ld +++ b/src/mainboard/emulation/qemu-power8/memlayout.ld @@ -27,5 +27,6 @@ STACK(0x40000, 0x3ff00) PRERAM_CBMEM_CONSOLE(0x80000, 8K) FMAP_CACHE(0x82000, 2K) + CBFS_MCACHE(0x82800, 8K) RAMSTAGE(0x100000, 16M) } diff --git a/src/mainboard/emulation/qemu-riscv/memlayout.ld b/src/mainboard/emulation/qemu-riscv/memlayout.ld index e53df38..7eb0f00 100644 --- a/src/mainboard/emulation/qemu-riscv/memlayout.ld +++ b/src/mainboard/emulation/qemu-riscv/memlayout.ld @@ -38,6 +38,7 @@ #endif PRERAM_CBMEM_CONSOLE(STAGES_START + 128K, 8K) FMAP_CACHE(STAGES_START + 136K, 2K) + CBFS_MCACHE(STAGES_START + 138K, 8K) RAMSTAGE(STAGES_START + 200K, 16M) STACK(STAGES_START + 200K + 16M, 4K) } diff --git a/src/mainboard/emulation/spike-riscv/memlayout.ld b/src/mainboard/emulation/spike-riscv/memlayout.ld index b6e4d9d..376b9b1 100644 --- a/src/mainboard/emulation/spike-riscv/memlayout.ld +++ b/src/mainboard/emulation/spike-riscv/memlayout.ld @@ -24,7 +24,8 @@ DRAM_START(START) BOOTBLOCK(START, 64K) STACK(START + 8M, 4K) - FMAP_CACHE(START + 8M + 4K, 2K) + FMAP_CACHE(START + 12M, 2K) + CBFS_CACHE(START + 14M, 8K) /* hole at (START + 8M + 6K, 58K) */ ROMSTAGE(START + 8M + 64K, 128K) PRERAM_CBMEM_CONSOLE(START + 8M + 192k, 8K) diff --git a/src/mainboard/google/octopus/Kconfig b/src/mainboard/google/octopus/Kconfig index 3139716..8a33b5f 100644 --- a/src/mainboard/google/octopus/Kconfig +++ b/src/mainboard/google/octopus/Kconfig @@ -23,6 +23,7 @@ select MAINBOARD_HAS_TPM2 select GOOGLE_SMBIOS_MAINBOARD_VERSION select NO_FMAP_CACHE + select NO_CBFS_MCACHE
if BOARD_GOOGLE_BASEBOARD_OCTOPUS
diff --git a/src/soc/cavium/cn81xx/include/soc/memlayout.ld b/src/soc/cavium/cn81xx/include/soc/memlayout.ld index 1a0eb15..e78aa20 100644 --- a/src/soc/cavium/cn81xx/include/soc/memlayout.ld +++ b/src/soc/cavium/cn81xx/include/soc/memlayout.ld @@ -34,7 +34,8 @@ PRERAM_CBFS_CACHE(BOOTROM_OFFSET + 0x6000, 6K) FMAP_CACHE(BOOTROM_OFFSET + 0x7800, 2K) PRERAM_CBMEM_CONSOLE(BOOTROM_OFFSET + 0x8000, 8K) - BOOTBLOCK(BOOTROM_OFFSET + 0x20000, 64K) + BOOTBLOCK(BOOTROM_OFFSET + 0x20000, 56K) + CBFS_MCACHE(BOOTROM_OFFSET + 0x2e000, 8K) VBOOT2_WORK(BOOTROM_OFFSET + 0x30000, 12K) VBOOT2_TPM_LOG(BOOTROM_OFFSET + 0x33000, 2K) VERSTAGE(BOOTROM_OFFSET + 0x33800, 50K) diff --git a/src/soc/mediatek/mt8173/include/soc/memlayout.ld b/src/soc/mediatek/mt8173/include/soc/memlayout.ld index 2358c39..2d364b5 100644 --- a/src/soc/mediatek/mt8173/include/soc/memlayout.ld +++ b/src/soc/mediatek/mt8173/include/soc/memlayout.ld @@ -43,7 +43,8 @@ FMAP_CACHE(0x00103800, 2K) PRERAM_CBMEM_CONSOLE(0x00104000, 12K) WATCHDOG_TOMBSTONE(0x00107000, 4) - PRERAM_CBFS_CACHE(0x00107004, 16K - 4) + PRERAM_CBFS_CACHE(0x00107004, 8K - 4) + CBFS_MCACHE(0x00109000, 8K) TIMESTAMP(0x0010B000, 4K) ROMSTAGE(0x0010C000, 92K) STACK(0x00124000, 16K) diff --git a/src/soc/mediatek/mt8183/include/soc/memlayout.ld b/src/soc/mediatek/mt8183/include/soc/memlayout.ld index 996d2ec..0d20e31 100644 --- a/src/soc/mediatek/mt8183/include/soc/memlayout.ld +++ b/src/soc/mediatek/mt8183/include/soc/memlayout.ld @@ -43,7 +43,8 @@
SRAM_L2C_START(0x00200000) OVERLAP_DECOMPRESSOR_VERSTAGE_ROMSTAGE(0x00201000, 188K) - BOOTBLOCK(0x00230000, 64K) + BOOTBLOCK(0x00230000, 56K) + CBFS_MCACHE(0x0023e000, 8K) DRAM_INIT_CODE(0x00240000, 208K) PRERAM_CBFS_CACHE(0x00274000, 48K) SRAM_L2C_END(0x00280000) diff --git a/src/soc/nvidia/tegra124/include/soc/memlayout.ld b/src/soc/nvidia/tegra124/include/soc/memlayout.ld index 7e2cc7a..a342f6a 100644 --- a/src/soc/nvidia/tegra124/include/soc/memlayout.ld +++ b/src/soc/nvidia/tegra124/include/soc/memlayout.ld @@ -29,7 +29,8 @@ TTB(0x40000000, 16K + 32) PRERAM_CBMEM_CONSOLE(0x40004020, 6K - 32) FMAP_CACHE(0x40005800, 2K) - PRERAM_CBFS_CACHE(0x40006000, 14K) + CBFS_MCACHE(0x40006000, 8K) + PRERAM_CBFS_CACHE(0x40008000, 6K) VBOOT2_WORK(0x40009800, 12K) VBOOT2_TPM_LOG(0x4000D800, 2K) STACK(0x4000E000, 8K) diff --git a/src/soc/nvidia/tegra210/include/soc/memlayout.ld b/src/soc/nvidia/tegra210/include/soc/memlayout.ld index b7268d1..44f0153 100644 --- a/src/soc/nvidia/tegra210/include/soc/memlayout.ld +++ b/src/soc/nvidia/tegra210/include/soc/memlayout.ld @@ -30,7 +30,8 @@ SRAM_START(0x40000000) PRERAM_CBMEM_CONSOLE(0x40000000, 2K) FMAP_CACHE(0x40000800, 2K) - PRERAM_CBFS_CACHE(0x40001000, 28K) + PRERAM_CBFS_CACHE(0x40001000, 20K) + CBFS_MCACHE(0x40006000, 8K) VBOOT2_WORK(0x40008000, 12K) VBOOT2_TPM_LOG(0x4000B000, 2K) #if ENV_ARM64 diff --git a/src/soc/qualcomm/ipq40xx/include/soc/memlayout.ld b/src/soc/qualcomm/ipq40xx/include/soc/memlayout.ld index 6ff1018..76685cf 100644 --- a/src/soc/qualcomm/ipq40xx/include/soc/memlayout.ld +++ b/src/soc/qualcomm/ipq40xx/include/soc/memlayout.ld @@ -34,7 +34,8 @@ /* This includes bootblock image, can be reused after bootblock starts */ /* UBER_SBL(0x0A0C0000, 48K) */
- PRERAM_CBFS_CACHE(0x0A0C0000, 92K) + PRERAM_CBFS_CACHE(0x0A0C0000, 84K) + CBFS_MCACHE(0x0A0ED800, 8K) FMAP_CACHE(0x0A0EF800, 2K)
TTB(0x0A0F0000, 16K) diff --git a/src/soc/qualcomm/ipq806x/include/soc/memlayout.ld b/src/soc/qualcomm/ipq806x/include/soc/memlayout.ld index 595d939..6e309c0 100644 --- a/src/soc/qualcomm/ipq806x/include/soc/memlayout.ld +++ b/src/soc/qualcomm/ipq806x/include/soc/memlayout.ld @@ -38,7 +38,8 @@ QCA_SHARED_RAM(2A03F000, 4K) */ STACK(0x2A040000, 16K) - PRERAM_CBFS_CACHE(0x2A044000, 91K) + PRERAM_CBFS_CACHE(0x2A044000, 83K) + CBFS_MCACHE(0x2A059000, 8K) FMAP_CACHE(0x2A05B000, 2K) TTB_SUBTABLES(0x2A05B800, 2K) TTB(0x2A05C000, 16K) diff --git a/src/soc/qualcomm/qcs405/include/soc/memlayout.ld b/src/soc/qualcomm/qcs405/include/soc/memlayout.ld index dd013b5..9d92949 100644 --- a/src/soc/qualcomm/qcs405/include/soc/memlayout.ld +++ b/src/soc/qualcomm/qcs405/include/soc/memlayout.ld @@ -38,7 +38,8 @@ STACK(0x8C4B000, 16K) TIMESTAMP(0x8C4F000, 1K) PRERAM_CBMEM_CONSOLE(0x8C4F400, 32K) - PRERAM_CBFS_CACHE(0x8C57400, 70K) + PRERAM_CBFS_CACHE(0x8C57400, 62K) + CBFS_MCACHE(0x8C66C00, 8K) FMAP_CACHE(0x8C68C00, 2K) REGION(bsram_unused, 0x8C69400, 0xA1C00, 0x100) BSRAM_END(0x8D80000) diff --git a/src/soc/qualcomm/sc7180/include/soc/memlayout.ld b/src/soc/qualcomm/sc7180/include/soc/memlayout.ld index 7323119..838fda3 100644 --- a/src/soc/qualcomm/sc7180/include/soc/memlayout.ld +++ b/src/soc/qualcomm/sc7180/include/soc/memlayout.ld @@ -52,6 +52,7 @@ REGION(qclib_serial_log, 0x14852000, 4K, 4K) REGION(ddr_information, 0x14853000, 1K, 1K) FMAP_CACHE(0x14853400, 2K) + CBFS_MCACHE(0x14853C00, 8K) REGION(dcb, 0x14870000, 16K, 4K) REGION(pmic, 0x14874000, 44K, 4K) REGION(limits_cfg, 0x1487F000, 4K, 4K) diff --git a/src/soc/qualcomm/sdm845/include/soc/memlayout.ld b/src/soc/qualcomm/sdm845/include/soc/memlayout.ld index c3a3b4c..5ea3e96 100644 --- a/src/soc/qualcomm/sdm845/include/soc/memlayout.ld +++ b/src/soc/qualcomm/sdm845/include/soc/memlayout.ld @@ -58,7 +58,8 @@ PRERAM_CBMEM_CONSOLE(0x14836400, 32K) PRERAM_CBFS_CACHE(0x1483E400, 70K) FMAP_CACHE(0x1484FC00, 2K) - REGION(bsram_unused, 0x14850400, 0x9DB00, 0x100) + CBFS_MCACHE(0x1485400, 8K) + REGION(bsram_unused, 0x14852400, 0x9BB00, 0x100) REGION(ddr_information, 0x148EDF00, 256, 256) REGION(limits_cfg, 0x148EE000, 4K, 4K) REGION(qclib_serial_log, 0x148EF000, 4K, 4K) diff --git a/src/soc/rockchip/rk3288/Kconfig b/src/soc/rockchip/rk3288/Kconfig index 6a44ccd..e36a8e8 100644 --- a/src/soc/rockchip/rk3288/Kconfig +++ b/src/soc/rockchip/rk3288/Kconfig @@ -30,6 +30,7 @@ select HAVE_LINEAR_FRAMEBUFFER select NO_BOOTBLOCK_CONSOLE select NO_FMAP_CACHE + select NO_CBFS_MCACHE
if SOC_ROCKCHIP_RK3288
diff --git a/src/soc/rockchip/rk3399/include/soc/memlayout.ld b/src/soc/rockchip/rk3399/include/soc/memlayout.ld index 4e46e2d..2c7be29 100644 --- a/src/soc/rockchip/rk3399/include/soc/memlayout.ld +++ b/src/soc/rockchip/rk3399/include/soc/memlayout.ld @@ -37,11 +37,12 @@ FMAP_CACHE(0xFF8C1400, 2K) TIMESTAMP(0xFF8C1C00, 1K) /* 0xFF8C2004 is the entry point address the masked ROM will jump to. */ - OVERLAP_DECOMPRESSOR_VERSTAGE_ROMSTAGE(0xFF8C2004, 88K - 4) - BOOTBLOCK(0xFF8D8000, 40K) + OVERLAP_DECOMPRESSOR_VERSTAGE_ROMSTAGE(0xFF8C2004, 84K - 4) + BOOTBLOCK(0xFF8D7000, 40K) #endif - VBOOT2_WORK(0XFF8E2000, 12K) - TTB(0xFF8E5000, 24K) + CBFS_MCACHE(0xFF8E1000, 8K) + VBOOT2_WORK(0XFF8E3000, 12K) + TTB(0xFF8E6000, 20K) PRERAM_CBMEM_CONSOLE(0xFF8EB000, 8K) STACK(0xFF8ED000, 12K) SRAM_END(0xFF8F0000) diff --git a/src/soc/samsung/exynos5250/include/soc/memlayout.ld b/src/soc/samsung/exynos5250/include/soc/memlayout.ld index 7e052f0..e97fcb0 100644 --- a/src/soc/samsung/exynos5250/include/soc/memlayout.ld +++ b/src/soc/samsung/exynos5250/include/soc/memlayout.ld @@ -31,7 +31,8 @@ ROMSTAGE(0x2030000, 128K) /* 32K hole */ TTB(0x2058000, 16K) - PRERAM_CBFS_CACHE(0x205C000, 76K) + PRERAM_CBFS_CACHE(0x205C000, 68K) + CBFS_MCACHE(0x206D000, 8K) FMAP_CACHE(0x206F000, 2K) VBOOT2_TPM_LOG(0x206F800, 2K) VBOOT2_WORK(0x2070000, 12K) diff --git a/src/soc/samsung/exynos5420/include/soc/memlayout.ld b/src/soc/samsung/exynos5420/include/soc/memlayout.ld index ff781d2..e2e51c0 100644 --- a/src/soc/samsung/exynos5420/include/soc/memlayout.ld +++ b/src/soc/samsung/exynos5420/include/soc/memlayout.ld @@ -32,7 +32,8 @@ ROMSTAGE(0x2030000, 128K) /* 32K hole */ TTB(0x2058000, 16K) - PRERAM_CBFS_CACHE(0x205C000, 74K) + PRERAM_CBFS_CACHE(0x205C000, 66K) + CBFS_MCACHE(0x206C800, 8K) FMAP_CACHE(0x206E800, 2K) STACK(0x206F000, 16K) /* 1K hole for weird kernel-shared CPU/SMP state structure that doesn't diff --git a/src/soc/sifive/fu540/include/soc/memlayout.ld b/src/soc/sifive/fu540/include/soc/memlayout.ld index 46c559c..cc4f900 100644 --- a/src/soc/sifive/fu540/include/soc/memlayout.ld +++ b/src/soc/sifive/fu540/include/soc/memlayout.ld @@ -26,7 +26,8 @@ L2LIM_START(FU540_L2LIM) BOOTBLOCK(FU540_L2LIM, 64K) CAR_STACK(FU540_L2LIM + 64K, 20K) - PRERAM_CBMEM_CONSOLE(FU540_L2LIM + 84K, 8K) + PRERAM_CBMEM_CONSOLE(FU540_L2LIM + 76K, 8K) + CBFS_MCACHE(FU540_L2LIM + 84K, 8K) FMAP_CACHE(FU540_L2LIM + 92K, 2K) ROMSTAGE(FU540_L2LIM + 128K, 128K) PRERAM_CBFS_CACHE(FU540_L2LIM + 256K, 128K)
Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38424 )
Change subject: cbfs: Enable CBFS mcache on (almost) all boards ......................................................................
Patch Set 1:
(1 comment)
https://review.coreboot.org/c/coreboot/+/38424/1/src/arch/x86/Kconfig File src/arch/x86/Kconfig:
https://review.coreboot.org/c/coreboot/+/38424/1/src/arch/x86/Kconfig@163 PS1, Line 163: Increase this value if you see CBFS mcache overflow warnings Dot at the end?
Hello Aaron Durbin, ron minnich, build bot (Jenkins), Philipp Hug,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/38424
to look at the new patch set (#2).
Change subject: cbfs: Enable CBFS mcache on (almost) all boards ......................................................................
cbfs: Enable CBFS mcache on (almost) all boards
This patch flips the default of CONFIG_NO_CBFS_MCACHE so the feature is enabled by default. Only a few boards with notoriously little space still have it explicitly disabled. All others get the new section added to their memlayout... 8K seems like a sane default to start with.
Change-Id: I0abd1c813aece6e78fb883f292ce6c9319545c44 Signed-off-by: Julius Werner jwerner@chromium.org --- M src/arch/x86/Kconfig M src/arch/x86/car.ld M src/cpu/ti/am335x/memlayout.ld M src/lib/Kconfig M src/mainboard/emulation/qemu-aarch64/memlayout.ld M src/mainboard/emulation/qemu-armv7/memlayout.ld M src/mainboard/emulation/qemu-power8/memlayout.ld M src/mainboard/emulation/qemu-riscv/memlayout.ld M src/mainboard/emulation/spike-riscv/memlayout.ld M src/mainboard/google/octopus/Kconfig M src/soc/cavium/cn81xx/include/soc/memlayout.ld M src/soc/mediatek/mt8173/include/soc/memlayout.ld M src/soc/mediatek/mt8183/include/soc/memlayout.ld M src/soc/nvidia/tegra124/include/soc/memlayout.ld M src/soc/nvidia/tegra210/include/soc/memlayout.ld M src/soc/qualcomm/ipq40xx/include/soc/memlayout.ld M src/soc/qualcomm/ipq806x/include/soc/memlayout.ld M src/soc/qualcomm/qcs405/include/soc/memlayout.ld M src/soc/qualcomm/sc7180/include/soc/memlayout.ld M src/soc/qualcomm/sdm845/include/soc/memlayout.ld M src/soc/rockchip/rk3288/Kconfig M src/soc/rockchip/rk3399/include/soc/memlayout.ld M src/soc/samsung/exynos5250/include/soc/memlayout.ld M src/soc/samsung/exynos5420/include/soc/memlayout.ld M src/soc/sifive/fu540/include/soc/memlayout.ld 25 files changed, 51 insertions(+), 20 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/24/38424/2
Julius Werner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38424 )
Change subject: cbfs: Enable CBFS mcache on (almost) all boards ......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/c/coreboot/+/38424/1/src/arch/x86/Kconfig File src/arch/x86/Kconfig:
https://review.coreboot.org/c/coreboot/+/38424/1/src/arch/x86/Kconfig@163 PS1, Line 163: Increase this value if you see CBFS mcache overflow warnings
Dot at the end?
Done
Hello Aaron Durbin, ron minnich, build bot (Jenkins), Philipp Hug,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/38424
to look at the new patch set (#3).
Change subject: cbfs: Enable CBFS mcache on (almost) all boards ......................................................................
cbfs: Enable CBFS mcache on (almost) all boards
This patch flips the default of CONFIG_NO_CBFS_MCACHE so the feature is enabled by default. Only a few boards with notoriously little space still have it explicitly disabled. All others get the new section added to their memlayout... 8K seems like a sane default to start with.
Change-Id: I0abd1c813aece6e78fb883f292ce6c9319545c44 Signed-off-by: Julius Werner jwerner@chromium.org --- M src/arch/x86/Kconfig M src/arch/x86/car.ld M src/cpu/ti/am335x/memlayout.ld M src/lib/Kconfig M src/mainboard/emulation/qemu-aarch64/memlayout.ld M src/mainboard/emulation/qemu-armv7/memlayout.ld M src/mainboard/emulation/qemu-power8/memlayout.ld M src/mainboard/emulation/qemu-riscv/memlayout.ld M src/mainboard/emulation/spike-riscv/memlayout.ld M src/mainboard/google/octopus/Kconfig M src/soc/cavium/cn81xx/include/soc/memlayout.ld M src/soc/mediatek/mt8173/include/soc/memlayout.ld M src/soc/mediatek/mt8183/include/soc/memlayout.ld M src/soc/nvidia/tegra124/include/soc/memlayout.ld M src/soc/nvidia/tegra210/include/soc/memlayout.ld M src/soc/qualcomm/ipq40xx/include/soc/memlayout.ld M src/soc/qualcomm/ipq806x/include/soc/memlayout.ld M src/soc/qualcomm/qcs405/include/soc/memlayout.ld M src/soc/qualcomm/sc7180/include/soc/memlayout.ld M src/soc/qualcomm/sdm845/include/soc/memlayout.ld M src/soc/rockchip/rk3288/Kconfig M src/soc/rockchip/rk3399/include/soc/memlayout.ld M src/soc/samsung/exynos5250/include/soc/memlayout.ld M src/soc/samsung/exynos5420/include/soc/memlayout.ld M src/soc/sifive/fu540/include/soc/memlayout.ld 25 files changed, 51 insertions(+), 20 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/24/38424/3
Hello Aaron Durbin, ron minnich, build bot (Jenkins), Philipp Hug,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/38424
to look at the new patch set (#4).
Change subject: cbfs: Enable CBFS mcache on most boards ......................................................................
cbfs: Enable CBFS mcache on most boards
This patch flips the default of CONFIG_NO_CBFS_MCACHE so the feature is enabled by default. Some older boards with insufficient SRAM/CAR space still have it explicitly disabled. All others get the new section added to their memlayout... 8K seems like a sane default to start with.
Change-Id: I0abd1c813aece6e78fb883f292ce6c9319545c44 Signed-off-by: Julius Werner jwerner@chromium.org --- M src/arch/x86/Kconfig M src/arch/x86/car.ld M src/cpu/ti/am335x/memlayout.ld M src/lib/Kconfig M src/mainboard/asus/p5gc-mx/Kconfig M src/mainboard/emulation/qemu-aarch64/memlayout.ld M src/mainboard/emulation/qemu-armv7/memlayout.ld M src/mainboard/emulation/qemu-power8/memlayout.ld M src/mainboard/emulation/qemu-riscv/memlayout.ld M src/mainboard/emulation/spike-riscv/memlayout.ld M src/mainboard/gigabyte/ga-945gcm-s2l/Kconfig M src/mainboard/google/octopus/Kconfig M src/mainboard/intel/d945gclf/Kconfig M src/mainboard/lenovo/t400/Kconfig M src/northbridge/intel/e7505/Kconfig M src/northbridge/intel/i440bx/Kconfig M src/northbridge/intel/pineview/Kconfig M src/northbridge/intel/x4x/Kconfig M src/soc/cavium/cn81xx/include/soc/memlayout.ld M src/soc/intel/braswell/Kconfig M src/soc/mediatek/mt8173/include/soc/memlayout.ld M src/soc/mediatek/mt8183/include/soc/memlayout.ld M src/soc/nvidia/tegra124/include/soc/memlayout.ld M src/soc/nvidia/tegra210/include/soc/memlayout.ld M src/soc/qualcomm/ipq40xx/include/soc/memlayout.ld M src/soc/qualcomm/ipq806x/include/soc/memlayout.ld M src/soc/qualcomm/qcs405/include/soc/memlayout.ld M src/soc/qualcomm/sc7180/include/soc/memlayout.ld M src/soc/qualcomm/sdm845/include/soc/memlayout.ld M src/soc/rockchip/rk3288/Kconfig M src/soc/rockchip/rk3399/include/soc/memlayout.ld M src/soc/samsung/exynos5250/include/soc/memlayout.ld M src/soc/samsung/exynos5420/include/soc/memlayout.ld M src/soc/sifive/fu540/include/soc/memlayout.ld 34 files changed, 61 insertions(+), 21 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/24/38424/4
Hello Alexander Couzens, Patrick Rudolph, Aaron Durbin, ron minnich, build bot (Jenkins), Damien Zammit, Philipp Hug,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/38424
to look at the new patch set (#5).
Change subject: cbfs: Enable CBFS mcache on most boards ......................................................................
cbfs: Enable CBFS mcache on most boards
This patch flips the default of CONFIG_NO_CBFS_MCACHE so the feature is enabled by default. Some older boards with insufficient SRAM/CAR space still have it explicitly disabled. All others get the new section added to their memlayout... 8K seems like a sane default to start with.
Change-Id: I0abd1c813aece6e78fb883f292ce6c9319545c44 Signed-off-by: Julius Werner jwerner@chromium.org --- M src/arch/x86/Kconfig M src/arch/x86/car.ld M src/cpu/ti/am335x/memlayout.ld M src/lib/Kconfig M src/mainboard/asus/p5gc-mx/Kconfig M src/mainboard/emulation/qemu-aarch64/memlayout.ld M src/mainboard/emulation/qemu-armv7/memlayout.ld M src/mainboard/emulation/qemu-power8/memlayout.ld M src/mainboard/emulation/qemu-riscv/memlayout.ld M src/mainboard/emulation/spike-riscv/memlayout.ld M src/mainboard/gigabyte/ga-945gcm-s2l/Kconfig M src/mainboard/google/octopus/Kconfig M src/mainboard/intel/d945gclf/Kconfig M src/mainboard/lenovo/t400/Kconfig M src/northbridge/intel/e7505/Kconfig M src/northbridge/intel/i440bx/Kconfig M src/northbridge/intel/pineview/Kconfig M src/northbridge/intel/x4x/Kconfig M src/soc/cavium/cn81xx/include/soc/memlayout.ld M src/soc/intel/braswell/Kconfig M src/soc/mediatek/mt8173/include/soc/memlayout.ld M src/soc/mediatek/mt8183/include/soc/memlayout.ld M src/soc/nvidia/tegra124/include/soc/memlayout.ld M src/soc/nvidia/tegra210/include/soc/memlayout.ld M src/soc/qualcomm/ipq40xx/include/soc/memlayout.ld M src/soc/qualcomm/ipq806x/include/soc/memlayout.ld M src/soc/qualcomm/qcs405/include/soc/memlayout.ld M src/soc/qualcomm/sc7180/include/soc/memlayout.ld M src/soc/qualcomm/sdm845/include/soc/memlayout.ld M src/soc/rockchip/rk3288/Kconfig M src/soc/rockchip/rk3399/include/soc/memlayout.ld M src/soc/samsung/exynos5250/include/soc/memlayout.ld M src/soc/samsung/exynos5420/include/soc/memlayout.ld M src/soc/sifive/fu540/include/soc/memlayout.ld 34 files changed, 61 insertions(+), 21 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/24/38424/5
Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38424 )
Change subject: cbfs: Enable CBFS mcache on most boards ......................................................................
Patch Set 5:
It should be no problem to increase CAR space on the x86 boards in here.
Julius Werner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38424 )
Change subject: cbfs: Enable CBFS mcache on most boards ......................................................................
Patch Set 5:
It should be no problem to increase CAR space on the x86 boards in here.
You mean instead of disabling it on those northbridges? You may be right but I don't have any experience with those platforms and what to look out for when changing the CAR size (and no boards to test), so I think I'd rather check this patch in as is for now and if there's desire to use this feature on some of those boards later, it should be easy to enable for someone who is familiar with them.
Hello build bot (Jenkins), Damien Zammit, Philipp Hug, Alexander Couzens, Patrick Rudolph, Aaron Durbin, ron minnich,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/38424
to look at the new patch set (#9).
Change subject: cbfs: Enable CBFS mcache on most boards ......................................................................
cbfs: Enable CBFS mcache on most boards
This patch flips the default of CONFIG_NO_CBFS_MCACHE so the feature is enabled by default. Some older boards with insufficient SRAM/CAR space still have it explicitly disabled. All others get the new section added to their memlayout... 8K seems like a sane default to start with.
Change-Id: I0abd1c813aece6e78fb883f292ce6c9319545c44 Signed-off-by: Julius Werner jwerner@chromium.org --- M src/arch/x86/Kconfig M src/arch/x86/car.ld M src/cpu/ti/am335x/memlayout.ld M src/lib/Kconfig M src/mainboard/asus/p5gc-mx/Kconfig M src/mainboard/emulation/qemu-aarch64/memlayout.ld M src/mainboard/emulation/qemu-armv7/memlayout.ld M src/mainboard/emulation/qemu-power8/memlayout.ld M src/mainboard/emulation/qemu-riscv/memlayout.ld M src/mainboard/emulation/spike-riscv/memlayout.ld M src/mainboard/gigabyte/ga-945gcm-s2l/Kconfig M src/mainboard/google/octopus/Kconfig M src/mainboard/intel/d945gclf/Kconfig M src/mainboard/lenovo/t400/Kconfig M src/northbridge/intel/e7505/Kconfig M src/northbridge/intel/i440bx/Kconfig M src/northbridge/intel/pineview/Kconfig M src/northbridge/intel/x4x/Kconfig M src/soc/cavium/cn81xx/include/soc/memlayout.ld M src/soc/intel/braswell/Kconfig M src/soc/mediatek/mt8173/include/soc/memlayout.ld M src/soc/mediatek/mt8183/include/soc/memlayout.ld M src/soc/nvidia/tegra124/include/soc/memlayout.ld M src/soc/nvidia/tegra210/include/soc/memlayout.ld M src/soc/qualcomm/ipq40xx/include/soc/memlayout.ld M src/soc/qualcomm/ipq806x/include/soc/memlayout.ld M src/soc/qualcomm/qcs405/include/soc/memlayout.ld M src/soc/qualcomm/sc7180/include/soc/memlayout.ld M src/soc/qualcomm/sdm845/include/soc/memlayout.ld M src/soc/rockchip/rk3288/Kconfig M src/soc/rockchip/rk3399/include/soc/memlayout.ld M src/soc/samsung/exynos5250/include/soc/memlayout.ld M src/soc/samsung/exynos5420/include/soc/memlayout.ld M src/soc/sifive/fu540/include/soc/memlayout.ld 34 files changed, 61 insertions(+), 21 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/24/38424/9
Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38424 )
Change subject: cbfs: Enable CBFS mcache on most boards ......................................................................
Patch Set 10:
(1 comment)
https://review.coreboot.org/c/coreboot/+/38424/10/src/arch/x86/car.ld File src/arch/x86/car.ld:
https://review.coreboot.org/c/coreboot/+/38424/10/src/arch/x86/car.ld@50 PS10, Line 50: #if !CONFIG(NO_CBFS_MCACHE) : CBFS_MCACHE(., CONFIG_CBFS_MCACHE_SIZE) : #endif On x86 the RO-flash is typically cached. Would just selecting NO_CBFS_MCACHE on x86 not be a better idea?
Julius Werner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38424 )
Change subject: cbfs: Enable CBFS mcache on most boards ......................................................................
Patch Set 10:
(1 comment)
https://review.coreboot.org/c/coreboot/+/38424/10/src/arch/x86/car.ld File src/arch/x86/car.ld:
https://review.coreboot.org/c/coreboot/+/38424/10/src/arch/x86/car.ld@50 PS10, Line 50: #if !CONFIG(NO_CBFS_MCACHE) : CBFS_MCACHE(., CONFIG_CBFS_MCACHE_SIZE) : #endif
On x86 the RO-flash is typically cached. […]
I definitely want it to work, because it will be required for the verification stuff I want to implement later. When you need full TOCTOU protection you don't want to depend on if and how long the hardware might cache things behind your back, you need to be 100% sure the bytes you're looking at now are still the bytes you verified earlier.
If you want I can change the default on x86 for now. But as long as there's enough CAR space (and it seems there is plenty on recent platforms), leaving it on shouldn't hurt?
Hello build bot (Jenkins), Patrick Georgi, Damien Zammit, Philipp Hug, Alexander Couzens, Patrick Rudolph, Aaron Durbin, ron minnich,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/38424
to look at the new patch set (#12).
Change subject: cbfs: Enable CBFS mcache on most boards ......................................................................
cbfs: Enable CBFS mcache on most boards
This patch flips the default of CONFIG_NO_CBFS_MCACHE so the feature is enabled by default. Some older boards with insufficient SRAM/CAR space still have it explicitly disabled. All others get the new section added to their memlayout... 8K seems like a sane default to start with.
Change-Id: I0abd1c813aece6e78fb883f292ce6c9319545c44 Signed-off-by: Julius Werner jwerner@chromium.org --- M src/arch/x86/Kconfig M src/arch/x86/car.ld M src/lib/Kconfig M src/mainboard/asus/p5gc-mx/Kconfig M src/mainboard/emulation/qemu-aarch64/memlayout.ld M src/mainboard/emulation/qemu-armv7/memlayout.ld M src/mainboard/emulation/qemu-power8/memlayout.ld M src/mainboard/emulation/qemu-riscv/memlayout.ld M src/mainboard/emulation/spike-riscv/memlayout.ld M src/mainboard/gigabyte/ga-945gcm-s2l/Kconfig M src/mainboard/google/octopus/Kconfig M src/mainboard/intel/d945gclf/Kconfig M src/mainboard/lenovo/t400/Kconfig M src/northbridge/intel/e7505/Kconfig M src/northbridge/intel/i440bx/Kconfig M src/northbridge/intel/pineview/Kconfig M src/northbridge/intel/x4x/Kconfig M src/soc/cavium/cn81xx/memlayout.ld M src/soc/intel/braswell/Kconfig M src/soc/mediatek/mt8173/memlayout.ld M src/soc/mediatek/mt8183/memlayout.ld M src/soc/nvidia/tegra124/memlayout.ld M src/soc/nvidia/tegra210/memlayout.ld M src/soc/qualcomm/ipq40xx/memlayout.ld M src/soc/qualcomm/ipq806x/memlayout.ld M src/soc/qualcomm/qcs405/memlayout.ld M src/soc/qualcomm/sc7180/memlayout.ld M src/soc/qualcomm/sdm845/memlayout.ld M src/soc/rockchip/rk3288/Kconfig M src/soc/rockchip/rk3399/memlayout.ld M src/soc/samsung/exynos5250/memlayout.ld M src/soc/samsung/exynos5420/memlayout.ld M src/soc/sifive/fu540/memlayout.ld M src/soc/ti/am335x/memlayout.ld 34 files changed, 61 insertions(+), 21 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/24/38424/12
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38424 )
Change subject: cbfs: Enable CBFS mcache on most boards ......................................................................
Patch Set 12:
(1 comment)
https://review.coreboot.org/c/coreboot/+/38424/12//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/38424/12//COMMIT_MSG@10 PS12, Line 10: boards why not chipsets?
Aaron Durbin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38424 )
Change subject: cbfs: Enable CBFS mcache on most boards ......................................................................
Patch Set 13:
i386-elf-ld.bfd: /cb-build/coreboot-gerrit.0/chromeos/GOOGLE_BERKNIP/bootblock/lib/cbfs.o: in function `cbfs_get_boot_device': /home/coreboot/node-root/workspace/coreboot-gerrit/src/lib/cbfs.c:373: undefined reference to `_ecbfs_mcache'
src/soc/amd/picasso/memlayout_x86.ld will need to be edited as well. I think it can live just before the ASSERTs just below BOOTBLOCK entry.
Aaron Durbin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38424 )
Change subject: cbfs: Enable CBFS mcache on most boards ......................................................................
Patch Set 13:
Patch Set 13:
i386-elf-ld.bfd: /cb-build/coreboot-gerrit.0/chromeos/GOOGLE_BERKNIP/bootblock/lib/cbfs.o: in function `cbfs_get_boot_device': /home/coreboot/node-root/workspace/coreboot-gerrit/src/lib/cbfs.c:373: undefined reference to `_ecbfs_mcache'
src/soc/amd/picasso/memlayout_x86.ld will need to be edited as well. I think it can live just before the ASSERTs just below BOOTBLOCK entry.
Hrmm. I just remembered we're statically laying things out so we'll need to double check addresses.
Julius Werner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38424 )
Change subject: cbfs: Enable CBFS mcache on most boards ......................................................................
Patch Set 13:
src/soc/amd/picasso/memlayout_x86.ld will need to be edited as well. I think it can live just before the ASSERTs just below BOOTBLOCK entry.
Hrmm. I just remembered we're statically laying things out so we'll need to double check addresses.
Ehh... Picasso is a whole different can of worms with the whole verstage-before-bootblock thing violating basic assumptions. It doesn't have FMAP_CACHE support yet either, I think? (I saw Martin upload something once but don't remember if it really went through...) I think I wanna focus on getting this to work on the normal boards first, and let the AMD situation fully settle, and then I'll eventually probably have to ask some platform experts for help to see how we can get all this to work on there.
I can fix Asurada for now though.
Hello build bot (Jenkins), Patrick Georgi, Damien Zammit, Philipp Hug, Angel Pons, Alexander Couzens, Aaron Durbin, Patrick Rudolph, ron minnich,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/38424
to look at the new patch set (#14).
Change subject: cbfs: Enable CBFS mcache on most chipsets ......................................................................
cbfs: Enable CBFS mcache on most chipsets
This patch flips the default of CONFIG_NO_CBFS_MCACHE so the feature is enabled by default. Some older chipsets with insufficient SRAM/CAR space still have it explicitly disabled. All others get the new section added to their memlayout... 8K seems like a sane default to start with.
Change-Id: I0abd1c813aece6e78fb883f292ce6c9319545c44 Signed-off-by: Julius Werner jwerner@chromium.org --- M src/arch/x86/Kconfig M src/arch/x86/car.ld M src/lib/Kconfig M src/mainboard/asus/p5gc-mx/Kconfig M src/mainboard/emulation/qemu-aarch64/memlayout.ld M src/mainboard/emulation/qemu-armv7/memlayout.ld M src/mainboard/emulation/qemu-power8/memlayout.ld M src/mainboard/emulation/qemu-riscv/memlayout.ld M src/mainboard/emulation/spike-riscv/memlayout.ld M src/mainboard/gigabyte/ga-945gcm-s2l/Kconfig M src/mainboard/google/octopus/Kconfig M src/mainboard/intel/d945gclf/Kconfig M src/mainboard/lenovo/t400/Kconfig M src/northbridge/intel/e7505/Kconfig M src/northbridge/intel/i440bx/Kconfig M src/northbridge/intel/pineview/Kconfig M src/northbridge/intel/x4x/Kconfig M src/soc/amd/picasso/Kconfig M src/soc/cavium/cn81xx/memlayout.ld M src/soc/intel/braswell/Kconfig M src/soc/mediatek/mt8173/memlayout.ld M src/soc/mediatek/mt8183/memlayout.ld M src/soc/mediatek/mt8192/include/soc/memlayout.ld M src/soc/nvidia/tegra124/memlayout.ld M src/soc/nvidia/tegra210/memlayout.ld M src/soc/qualcomm/ipq40xx/memlayout.ld M src/soc/qualcomm/ipq806x/memlayout.ld M src/soc/qualcomm/qcs405/memlayout.ld M src/soc/qualcomm/sc7180/memlayout.ld M src/soc/qualcomm/sdm845/memlayout.ld M src/soc/rockchip/rk3288/Kconfig M src/soc/rockchip/rk3399/memlayout.ld M src/soc/samsung/exynos5250/memlayout.ld M src/soc/samsung/exynos5420/memlayout.ld M src/soc/sifive/fu540/memlayout.ld M src/soc/ti/am335x/memlayout.ld 36 files changed, 64 insertions(+), 22 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/24/38424/14
Julius Werner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38424 )
Change subject: cbfs: Enable CBFS mcache on most chipsets ......................................................................
Patch Set 14:
(1 comment)
https://review.coreboot.org/c/coreboot/+/38424/12//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/38424/12//COMMIT_MSG@10 PS12, Line 10: boards
why not chipsets?
Done
Aaron Durbin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38424 )
Change subject: cbfs: Enable CBFS mcache on most chipsets ......................................................................
Patch Set 14:
Patch Set 13:
src/soc/amd/picasso/memlayout_x86.ld will need to be edited as well. I think it can live just before the ASSERTs just below BOOTBLOCK entry.
Hrmm. I just remembered we're statically laying things out so we'll need to double check addresses.
Ehh... Picasso is a whole different can of worms with the whole verstage-before-bootblock thing violating basic assumptions. It doesn't have FMAP_CACHE support yet either, I think? (I saw Martin upload something once but don't remember if it really went through...) I think I wanna focus on getting this to work on the normal boards first, and let the AMD situation fully settle, and then I'll eventually probably have to ask some platform experts for help to see how we can get all this to work on there.
I can fix Asurada for now though.
I can help w/ the right entry in the linker script. Please remind me when you are ready for it.
Hello build bot (Jenkins), Patrick Georgi, Damien Zammit, Philipp Hug, Angel Pons, Alexander Couzens, Aaron Durbin, Patrick Rudolph, ron minnich,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/38424
to look at the new patch set (#15).
Change subject: cbfs: Enable CBFS mcache on most chipsets ......................................................................
cbfs: Enable CBFS mcache on most chipsets
This patch flips the default of CONFIG_NO_CBFS_MCACHE so the feature is enabled by default. Some older chipsets with insufficient SRAM/CAR space still have it explicitly disabled. All others get the new section added to their memlayout... 8K seems like a sane default to start with.
Change-Id: I0abd1c813aece6e78fb883f292ce6c9319545c44 Signed-off-by: Julius Werner jwerner@chromium.org --- M src/arch/x86/Kconfig M src/arch/x86/car.ld M src/lib/Kconfig M src/mainboard/asus/p5gc-mx/Kconfig M src/mainboard/emulation/qemu-aarch64/memlayout.ld M src/mainboard/emulation/qemu-armv7/memlayout.ld M src/mainboard/emulation/qemu-power8/memlayout.ld M src/mainboard/emulation/qemu-riscv/memlayout.ld M src/mainboard/emulation/spike-riscv/memlayout.ld M src/mainboard/gigabyte/ga-945gcm-s2l/Kconfig M src/mainboard/google/octopus/Kconfig M src/mainboard/intel/d945gclf/Kconfig M src/mainboard/lenovo/t400/Kconfig M src/northbridge/intel/e7505/Kconfig M src/northbridge/intel/i440bx/Kconfig M src/northbridge/intel/pineview/Kconfig M src/northbridge/intel/x4x/Kconfig M src/soc/amd/picasso/memlayout_psp_verstage.ld M src/soc/amd/picasso/memlayout_x86.ld M src/soc/cavium/cn81xx/memlayout.ld M src/soc/intel/braswell/Kconfig M src/soc/mediatek/mt8173/memlayout.ld M src/soc/mediatek/mt8183/memlayout.ld M src/soc/mediatek/mt8192/include/soc/memlayout.ld M src/soc/nvidia/tegra124/memlayout.ld M src/soc/nvidia/tegra210/memlayout.ld M src/soc/qualcomm/ipq40xx/memlayout.ld M src/soc/qualcomm/ipq806x/memlayout.ld M src/soc/qualcomm/qcs405/memlayout.ld M src/soc/qualcomm/sc7180/memlayout.ld M src/soc/qualcomm/sdm845/memlayout.ld M src/soc/rockchip/rk3288/Kconfig M src/soc/rockchip/rk3399/memlayout.ld M src/soc/samsung/exynos5250/memlayout.ld M src/soc/samsung/exynos5420/memlayout.ld M src/soc/sifive/fu540/memlayout.ld M src/soc/ti/am335x/memlayout.ld 37 files changed, 67 insertions(+), 22 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/24/38424/15
Julius Werner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38424 )
Change subject: cbfs: Enable CBFS mcache on most chipsets ......................................................................
Patch Set 14:
I can help w/ the right entry in the linker script. Please remind me when you are ready for it.
That's not really what I mean though... I mean things like my cbfs_get_boot_device() using ENV_BOOTBLOCK to determine when to initialize the cache. Although I guess I can use the ENV_INITIAL_STAGE Martin added recently and then maybe it's just gonna work out of the box? (That requires that the PSP verstage actually makes at least one CBFS access, but it looks like it does?)
Turned it on for Picasso now, could one of you help test it out?
Martin Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38424 )
Change subject: cbfs: Enable CBFS mcache on most chipsets ......................................................................
Patch Set 15:
(1 comment)
Patch Set 13:
Ehh... Picasso is a whole different can of worms with the whole verstage-before-bootblock thing violating basic assumptions. It doesn't have FMAP_CACHE support yet either, I think? (I saw Martin upload something once but don't remember if it really went through...)
The FMAP_CACHE change went through. We should be able to support loading the cbfs_mcache in verstage and transferring it through as well.
https://review.coreboot.org/c/coreboot/+/38424/15/src/mainboard/emulation/qe... File src/mainboard/emulation/qemu-aarch64/memlayout.ld:
https://review.coreboot.org/c/coreboot/+/38424/15/src/mainboard/emulation/qe... PS15, Line 23: CBFS_MCACHE(0x6002D800, 8K) Should this obey the Kconfig option? If not, should it throw an error if Kconfig is set for no cbfs_mcache?
Julius Werner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38424 )
Change subject: cbfs: Enable CBFS mcache on most chipsets ......................................................................
Patch Set 15:
(2 comments)
https://review.coreboot.org/c/coreboot/+/38424/15/src/mainboard/emulation/qe... File src/mainboard/emulation/qemu-aarch64/memlayout.ld:
https://review.coreboot.org/c/coreboot/+/38424/15/src/mainboard/emulation/qe... PS15, Line 23: CBFS_MCACHE(0x6002D800, 8K)
Should this obey the Kconfig option? If not, should it throw an error if Kconfig is set for no cbfs […]
We generally make the non-x86 memlayouts static (and not dynamic with using '.' for the address everywhere, like car.ld and what you did for Picasso). The reasoning is that you usually need to find some way to fit all the optional features in together anyway, and once you have that there's no need to "save" that space when the option is disabled either, it's not like it would really be useful for anything else at that point. So this will still create a _cbfs_mcache region and there'll just be no code doing anything with it if the Kconfig is disabled (which follows established practice, e.g. with FMAP_CACHE() below or VBOOT2_WORK() on other boards).
Also, it's not really optional for this board. I intentionally made NO_CBFS_MCACHE a Kconfig that isn't user-selectable in menuconfig. Either the board really can't fit it and then it has to 'select' that option, or it can fit it and then there should be no reason why a normal user would want to disable it.
https://review.coreboot.org/c/coreboot/+/38424/15/src/soc/amd/picasso/memlay... File src/soc/amd/picasso/memlayout_x86.ld:
https://review.coreboot.org/c/coreboot/+/38424/15/src/soc/amd/picasso/memlay... PS15, Line 82: VBOOT2_WORK(., VB2_FIRMWARE_WORKBUF_RECOMMENDED_SIZE) Not related to my patch, but shouldn't all the ALIGN_COUNTER(64) in memlayout_psp_verstage.ld also be reflected here? Otherwise, if one of these sizes was actually not divisible by 64, the internal offsets in your transfer buffer would all get out of sync...
(BTW, have you considered just making a separate memlayout_transfer_buffer.inc to list all these regions that you #include both here and in memlayout_psp_verstage.ld? That would save you the pain of manually making sure that you always keep everything in sync in this block between the two files.)
Martin Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38424 )
Change subject: cbfs: Enable CBFS mcache on most chipsets ......................................................................
Patch Set 16:
(2 comments)
https://review.coreboot.org/c/coreboot/+/38424/15/src/mainboard/emulation/qe... File src/mainboard/emulation/qemu-aarch64/memlayout.ld:
https://review.coreboot.org/c/coreboot/+/38424/15/src/mainboard/emulation/qe... PS15, Line 23: CBFS_MCACHE(0x6002D800, 8K)
We generally make the non-x86 memlayouts static (and not dynamic with using '. […]
Makes sense.
https://review.coreboot.org/c/coreboot/+/38424/15/src/soc/amd/picasso/memlay... File src/soc/amd/picasso/memlayout_x86.ld:
https://review.coreboot.org/c/coreboot/+/38424/15/src/soc/amd/picasso/memlay... PS15, Line 82: VBOOT2_WORK(., VB2_FIRMWARE_WORKBUF_RECOMMENDED_SIZE)
Not related to my patch, but shouldn't all the ALIGN_COUNTER(64) in memlayout_psp_verstage. […]
You're right. Thanks. I'll make those changes.
Aaron Durbin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38424 )
Change subject: cbfs: Enable CBFS mcache on most chipsets ......................................................................
Patch Set 17:
(1 comment)
https://review.coreboot.org/c/coreboot/+/38424/17/src/soc/amd/picasso/memlay... File src/soc/amd/picasso/memlayout_x86.ld:
https://review.coreboot.org/c/coreboot/+/38424/17/src/soc/amd/picasso/memlay... PS17, Line 88: CBFS_MCACHE(., CONFIG_CBFS_MCACHE_SIZE) i386-elf-ld.bfd: cbfs_mcache must be aligned to 4!
Clearly something is off. Needs more investigation.
Hello build bot (Jenkins), Martin Roth, Patrick Georgi, Damien Zammit, Philipp Hug, Angel Pons, Alexander Couzens, Aaron Durbin, Patrick Rudolph, ron minnich,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/38424
to look at the new patch set (#18).
Change subject: cbfs: Enable CBFS mcache on most chipsets ......................................................................
cbfs: Enable CBFS mcache on most chipsets
This patch flips the default of CONFIG_NO_CBFS_MCACHE so the feature is enabled by default. Some older chipsets with insufficient SRAM/CAR space still have it explicitly disabled. All others get the new section added to their memlayout... 8K seems like a sane default to start with.
Change-Id: I0abd1c813aece6e78fb883f292ce6c9319545c44 Signed-off-by: Julius Werner jwerner@chromium.org --- M src/arch/x86/Kconfig M src/arch/x86/car.ld M src/lib/Kconfig M src/mainboard/asus/p5gc-mx/Kconfig M src/mainboard/emulation/qemu-aarch64/memlayout.ld M src/mainboard/emulation/qemu-armv7/memlayout.ld M src/mainboard/emulation/qemu-power8/memlayout.ld M src/mainboard/emulation/qemu-riscv/memlayout.ld M src/mainboard/emulation/spike-riscv/memlayout.ld M src/mainboard/gigabyte/ga-945gcm-s2l/Kconfig M src/mainboard/google/octopus/Kconfig M src/mainboard/intel/d945gclf/Kconfig M src/mainboard/lenovo/t400/Kconfig M src/northbridge/intel/e7505/Kconfig M src/northbridge/intel/i440bx/Kconfig M src/northbridge/intel/pineview/Kconfig M src/northbridge/intel/x4x/Kconfig M src/soc/amd/picasso/memlayout_psp_verstage.ld M src/soc/amd/picasso/memlayout_x86.ld M src/soc/cavium/cn81xx/memlayout.ld M src/soc/intel/braswell/Kconfig M src/soc/mediatek/mt8173/memlayout.ld M src/soc/mediatek/mt8183/memlayout.ld M src/soc/mediatek/mt8192/include/soc/memlayout.ld M src/soc/nvidia/tegra124/memlayout.ld M src/soc/nvidia/tegra210/memlayout.ld M src/soc/qualcomm/ipq40xx/memlayout.ld M src/soc/qualcomm/ipq806x/memlayout.ld M src/soc/qualcomm/qcs405/memlayout.ld M src/soc/qualcomm/sc7180/memlayout.ld M src/soc/qualcomm/sdm845/memlayout.ld M src/soc/rockchip/rk3288/Kconfig M src/soc/rockchip/rk3399/memlayout.ld M src/soc/samsung/exynos5250/memlayout.ld M src/soc/samsung/exynos5420/memlayout.ld M src/soc/sifive/fu540/memlayout.ld M src/soc/ti/am335x/memlayout.ld 37 files changed, 68 insertions(+), 22 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/24/38424/18
Julius Werner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38424 )
Change subject: cbfs: Enable CBFS mcache on most chipsets ......................................................................
Patch Set 18:
(2 comments)
https://review.coreboot.org/c/coreboot/+/38424/10/src/arch/x86/car.ld File src/arch/x86/car.ld:
https://review.coreboot.org/c/coreboot/+/38424/10/src/arch/x86/car.ld@50 PS10, Line 50: #if !CONFIG(NO_CBFS_MCACHE) : CBFS_MCACHE(., CONFIG_CBFS_MCACHE_SIZE) : #endif
I definitely want it to work, because it will be required for the verification stuff I want to imple […]
Ack
https://review.coreboot.org/c/coreboot/+/38424/17/src/soc/amd/picasso/memlay... File src/soc/amd/picasso/memlayout_x86.ld:
https://review.coreboot.org/c/coreboot/+/38424/17/src/soc/amd/picasso/memlay... PS17, Line 88: CBFS_MCACHE(., CONFIG_CBFS_MCACHE_SIZE)
i386-elf-ld.bfd: cbfs_mcache must be aligned to 4! […]
I've copied in the one ALIGN_COUNTER(64) from the PSP memlayout that prevents this issue now, I'll leave it to Martin to clean up the whole thing later as he sees fit.
Aaron Durbin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38424 )
Change subject: cbfs: Enable CBFS mcache on most chipsets ......................................................................
Patch Set 18:
(1 comment)
https://review.coreboot.org/c/coreboot/+/38424/17/src/soc/amd/picasso/memlay... File src/soc/amd/picasso/memlayout_x86.ld:
https://review.coreboot.org/c/coreboot/+/38424/17/src/soc/amd/picasso/memlay... PS17, Line 88: CBFS_MCACHE(., CONFIG_CBFS_MCACHE_SIZE)
I've copied in the one ALIGN_COUNTER(64) from the PSP memlayout that prevents this issue now, I'll l […]
Build still failed. I'm not sure why. Seems to be the same message. I'll have to beat on this to sort it out, I think.
Julius Werner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38424 )
Change subject: cbfs: Enable CBFS mcache on most chipsets ......................................................................
Patch Set 18:
(1 comment)
https://review.coreboot.org/c/coreboot/+/38424/17/src/soc/amd/picasso/memlay... File src/soc/amd/picasso/memlayout_x86.ld:
https://review.coreboot.org/c/coreboot/+/38424/17/src/soc/amd/picasso/memlay... PS17, Line 88: CBFS_MCACHE(., CONFIG_CBFS_MCACHE_SIZE)
Build still failed. I'm not sure why. Seems to be the same message. […]
Sorry, I stared at the FMAP structure layout for minutes convincing myself that it will always be a multiple of 4, but I still somehow missed that the area flags are a uint16_t. Those struct were designed somewhat... unfortunate in multiple ways.
I'll probably just flip these to fix, then the FMAP edge at the end can be as ragged as it wants.
Hello build bot (Jenkins), Martin Roth, Patrick Georgi, Damien Zammit, Philipp Hug, Angel Pons, Alexander Couzens, Aaron Durbin, Patrick Rudolph, ron minnich,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/38424
to look at the new patch set (#19).
Change subject: cbfs: Enable CBFS mcache on most chipsets ......................................................................
cbfs: Enable CBFS mcache on most chipsets
This patch flips the default of CONFIG_NO_CBFS_MCACHE so the feature is enabled by default. Some older chipsets with insufficient SRAM/CAR space still have it explicitly disabled. All others get the new section added to their memlayout... 8K seems like a sane default to start with.
Change-Id: I0abd1c813aece6e78fb883f292ce6c9319545c44 Signed-off-by: Julius Werner jwerner@chromium.org --- M src/arch/x86/Kconfig M src/arch/x86/car.ld M src/lib/Kconfig M src/mainboard/asus/p5gc-mx/Kconfig M src/mainboard/emulation/qemu-aarch64/memlayout.ld M src/mainboard/emulation/qemu-armv7/memlayout.ld M src/mainboard/emulation/qemu-power8/memlayout.ld M src/mainboard/emulation/qemu-riscv/memlayout.ld M src/mainboard/emulation/spike-riscv/memlayout.ld M src/mainboard/gigabyte/ga-945gcm-s2l/Kconfig M src/mainboard/google/octopus/Kconfig M src/mainboard/intel/d945gclf/Kconfig M src/mainboard/lenovo/t400/Kconfig M src/northbridge/intel/e7505/Kconfig M src/northbridge/intel/i440bx/Kconfig M src/northbridge/intel/pineview/Kconfig M src/northbridge/intel/x4x/Kconfig M src/soc/amd/picasso/memlayout_psp_verstage.ld M src/soc/amd/picasso/memlayout_x86.ld M src/soc/cavium/cn81xx/memlayout.ld M src/soc/intel/braswell/Kconfig M src/soc/mediatek/mt8173/memlayout.ld M src/soc/mediatek/mt8183/memlayout.ld M src/soc/mediatek/mt8192/include/soc/memlayout.ld M src/soc/nvidia/tegra124/memlayout.ld M src/soc/nvidia/tegra210/memlayout.ld M src/soc/qualcomm/ipq40xx/memlayout.ld M src/soc/qualcomm/ipq806x/memlayout.ld M src/soc/qualcomm/qcs405/memlayout.ld M src/soc/qualcomm/sc7180/memlayout.ld M src/soc/qualcomm/sdm845/memlayout.ld M src/soc/rockchip/rk3288/Kconfig M src/soc/rockchip/rk3399/memlayout.ld M src/soc/samsung/exynos5250/memlayout.ld M src/soc/samsung/exynos5420/memlayout.ld M src/soc/sifive/fu540/memlayout.ld M src/soc/ti/am335x/memlayout.ld 37 files changed, 67 insertions(+), 22 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/24/38424/19
Hello build bot (Jenkins), Martin Roth, Patrick Georgi, Damien Zammit, Philipp Hug, Angel Pons, Alexander Couzens, Aaron Durbin, Patrick Rudolph, ron minnich,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/38424
to look at the new patch set (#20).
Change subject: cbfs: Enable CBFS mcache on most chipsets ......................................................................
cbfs: Enable CBFS mcache on most chipsets
This patch flips the default of CONFIG_NO_CBFS_MCACHE so the feature is enabled by default. Some older chipsets with insufficient SRAM/CAR space still have it explicitly disabled. All others get the new section added to their memlayout... 8K seems like a sane default to start with.
Change-Id: I0abd1c813aece6e78fb883f292ce6c9319545c44 Signed-off-by: Julius Werner jwerner@chromium.org --- M src/arch/x86/Kconfig M src/arch/x86/car.ld M src/lib/Kconfig M src/mainboard/asus/p5gc-mx/Kconfig M src/mainboard/emulation/qemu-aarch64/memlayout.ld M src/mainboard/emulation/qemu-armv7/memlayout.ld M src/mainboard/emulation/qemu-power8/memlayout.ld M src/mainboard/emulation/qemu-riscv/memlayout.ld M src/mainboard/emulation/spike-riscv/memlayout.ld M src/mainboard/gigabyte/ga-945gcm-s2l/Kconfig M src/mainboard/google/octopus/Kconfig M src/mainboard/intel/d945gclf/Kconfig M src/mainboard/lenovo/t400/Kconfig M src/northbridge/intel/e7505/Kconfig M src/northbridge/intel/i440bx/Kconfig M src/northbridge/intel/pineview/Kconfig M src/northbridge/intel/x4x/Kconfig M src/soc/amd/picasso/memlayout_transfer_buffer.inc M src/soc/amd/picasso/memlayout_x86.ld M src/soc/cavium/cn81xx/memlayout.ld M src/soc/intel/braswell/Kconfig M src/soc/mediatek/mt8173/memlayout.ld M src/soc/mediatek/mt8183/memlayout.ld M src/soc/mediatek/mt8192/include/soc/memlayout.ld M src/soc/nvidia/tegra124/memlayout.ld M src/soc/nvidia/tegra210/memlayout.ld M src/soc/qualcomm/ipq40xx/memlayout.ld M src/soc/qualcomm/ipq806x/memlayout.ld M src/soc/qualcomm/qcs405/memlayout.ld M src/soc/qualcomm/sc7180/memlayout.ld M src/soc/rockchip/rk3288/Kconfig M src/soc/rockchip/rk3399/memlayout.ld M src/soc/samsung/exynos5250/memlayout.ld M src/soc/samsung/exynos5420/memlayout.ld M src/soc/sifive/fu540/memlayout.ld M src/soc/ti/am335x/memlayout.ld 36 files changed, 64 insertions(+), 21 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/24/38424/20
Hello build bot (Jenkins), Martin Roth, Patrick Georgi, Damien Zammit, Philipp Hug, Angel Pons, Alexander Couzens, Aaron Durbin, Patrick Rudolph, ron minnich,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/38424
to look at the new patch set (#21).
Change subject: cbfs: Enable CBFS mcache on most chipsets ......................................................................
cbfs: Enable CBFS mcache on most chipsets
This patch flips the default of CONFIG_NO_CBFS_MCACHE so the feature is enabled by default. Some older chipsets with insufficient SRAM/CAR space still have it explicitly disabled. All others get the new section added to their memlayout... 8K seems like a sane default to start with.
Change-Id: I0abd1c813aece6e78fb883f292ce6c9319545c44 Signed-off-by: Julius Werner jwerner@chromium.org --- M src/arch/x86/Kconfig M src/arch/x86/car.ld M src/lib/Kconfig M src/mainboard/asus/p5gc-mx/Kconfig M src/mainboard/emulation/qemu-aarch64/memlayout.ld M src/mainboard/emulation/qemu-armv7/memlayout.ld M src/mainboard/emulation/qemu-power8/memlayout.ld M src/mainboard/emulation/qemu-riscv/memlayout.ld M src/mainboard/emulation/spike-riscv/memlayout.ld M src/mainboard/gigabyte/ga-945gcm-s2l/Kconfig M src/mainboard/google/octopus/Kconfig M src/mainboard/intel/d945gclf/Kconfig M src/mainboard/lenovo/t400/Kconfig M src/northbridge/intel/e7505/Kconfig M src/northbridge/intel/i440bx/Kconfig M src/northbridge/intel/pineview/Kconfig M src/northbridge/intel/x4x/Kconfig M src/soc/amd/picasso/memlayout_transfer_buffer.inc M src/soc/amd/picasso/memlayout_x86.ld M src/soc/cavium/cn81xx/memlayout.ld M src/soc/intel/braswell/Kconfig M src/soc/mediatek/mt8173/memlayout.ld M src/soc/mediatek/mt8183/memlayout.ld M src/soc/mediatek/mt8192/include/soc/memlayout.ld M src/soc/nvidia/tegra124/memlayout.ld M src/soc/nvidia/tegra210/memlayout.ld M src/soc/qualcomm/ipq40xx/memlayout.ld M src/soc/qualcomm/ipq806x/memlayout.ld M src/soc/qualcomm/qcs405/memlayout.ld M src/soc/qualcomm/sc7180/memlayout.ld M src/soc/rockchip/rk3288/Kconfig M src/soc/rockchip/rk3399/memlayout.ld M src/soc/samsung/exynos5250/memlayout.ld M src/soc/samsung/exynos5420/memlayout.ld M src/soc/sifive/fu540/memlayout.ld M src/soc/ti/am335x/memlayout.ld 36 files changed, 64 insertions(+), 21 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/24/38424/21
Hello build bot (Jenkins), Martin Roth, Patrick Georgi, Damien Zammit, Philipp Hug, Angel Pons, Alexander Couzens, Aaron Durbin, Patrick Rudolph, ron minnich,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/38424
to look at the new patch set (#22).
Change subject: cbfs: Enable CBFS mcache on most chipsets ......................................................................
cbfs: Enable CBFS mcache on most chipsets
This patch flips the default of CONFIG_NO_CBFS_MCACHE so the feature is enabled by default. Some older chipsets with insufficient SRAM/CAR space still have it explicitly disabled. All others get the new section added to their memlayout... 8K seems like a sane default to start with.
Change-Id: I0abd1c813aece6e78fb883f292ce6c9319545c44 Signed-off-by: Julius Werner jwerner@chromium.org --- M src/arch/x86/Kconfig M src/arch/x86/car.ld M src/lib/Kconfig M src/mainboard/asus/p5gc-mx/Kconfig M src/mainboard/emulation/qemu-aarch64/memlayout.ld M src/mainboard/emulation/qemu-armv7/memlayout.ld M src/mainboard/emulation/qemu-power8/memlayout.ld M src/mainboard/emulation/qemu-riscv/memlayout.ld M src/mainboard/emulation/spike-riscv/memlayout.ld M src/mainboard/gigabyte/ga-945gcm-s2l/Kconfig M src/mainboard/google/octopus/Kconfig M src/mainboard/lenovo/t400/Kconfig M src/northbridge/intel/e7505/Kconfig M src/northbridge/intel/i440bx/Kconfig M src/northbridge/intel/pineview/Kconfig M src/northbridge/intel/x4x/Kconfig M src/soc/amd/picasso/memlayout_transfer_buffer.inc M src/soc/amd/picasso/memlayout_x86.ld M src/soc/cavium/cn81xx/memlayout.ld M src/soc/intel/braswell/Kconfig M src/soc/mediatek/mt8173/memlayout.ld M src/soc/mediatek/mt8183/memlayout.ld M src/soc/mediatek/mt8192/include/soc/memlayout.ld M src/soc/nvidia/tegra124/memlayout.ld M src/soc/nvidia/tegra210/memlayout.ld M src/soc/qualcomm/ipq40xx/memlayout.ld M src/soc/qualcomm/ipq806x/memlayout.ld M src/soc/qualcomm/qcs405/memlayout.ld M src/soc/qualcomm/sc7180/memlayout.ld M src/soc/rockchip/rk3288/Kconfig M src/soc/rockchip/rk3399/memlayout.ld M src/soc/samsung/exynos5250/memlayout.ld M src/soc/samsung/exynos5420/memlayout.ld M src/soc/sifive/fu540/memlayout.ld M src/soc/ti/am335x/memlayout.ld 35 files changed, 65 insertions(+), 23 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/24/38424/22
Patrick Georgi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38424 )
Change subject: cbfs: Enable CBFS mcache on most chipsets ......................................................................
Patch Set 22: Code-Review+2
It looks reasonable and I think now, shortly after a release is the best time to get it in, given how many different SoCs it impacts directly.
That said, could you send a mail to the list outlining that this change is in with a call for testing (I suppose a simple boot test should be good enough)? That way, if there are issues we can sort them out soon rather than in several months when everybody has already moved on to the next complicated thing?
Patrick Georgi has uploaded a new patch set (#23) to the change originally created by Julius Werner. ( https://review.coreboot.org/c/coreboot/+/38424 )
Change subject: cbfs: Enable CBFS mcache on most chipsets ......................................................................
cbfs: Enable CBFS mcache on most chipsets
This patch flips the default of CONFIG_NO_CBFS_MCACHE so the feature is enabled by default. Some older chipsets with insufficient SRAM/CAR space still have it explicitly disabled. All others get the new section added to their memlayout... 8K seems like a sane default to start with.
Change-Id: I0abd1c813aece6e78fb883f292ce6c9319545c44 Signed-off-by: Julius Werner jwerner@chromium.org --- M src/arch/x86/Kconfig M src/arch/x86/car.ld M src/lib/Kconfig M src/mainboard/asus/p5gc-mx/Kconfig M src/mainboard/emulation/qemu-aarch64/memlayout.ld M src/mainboard/emulation/qemu-armv7/memlayout.ld M src/mainboard/emulation/qemu-power8/memlayout.ld M src/mainboard/emulation/qemu-riscv/memlayout.ld M src/mainboard/emulation/spike-riscv/memlayout.ld M src/mainboard/gigabyte/ga-945gcm-s2l/Kconfig M src/mainboard/google/octopus/Kconfig M src/mainboard/lenovo/t400/Kconfig M src/northbridge/intel/e7505/Kconfig M src/northbridge/intel/i440bx/Kconfig M src/northbridge/intel/pineview/Kconfig M src/northbridge/intel/x4x/Kconfig M src/soc/amd/common/block/cpu/noncar/memlayout_transfer_buffer.inc M src/soc/amd/common/block/cpu/noncar/memlayout_x86.ld M src/soc/cavium/cn81xx/memlayout.ld M src/soc/intel/braswell/Kconfig M src/soc/mediatek/mt8173/memlayout.ld M src/soc/mediatek/mt8183/memlayout.ld M src/soc/mediatek/mt8192/include/soc/memlayout.ld M src/soc/nvidia/tegra124/memlayout.ld M src/soc/nvidia/tegra210/memlayout.ld M src/soc/qualcomm/ipq40xx/memlayout.ld M src/soc/qualcomm/ipq806x/memlayout.ld M src/soc/qualcomm/qcs405/memlayout.ld M src/soc/qualcomm/sc7180/memlayout.ld M src/soc/rockchip/rk3288/Kconfig M src/soc/rockchip/rk3399/memlayout.ld M src/soc/samsung/exynos5250/memlayout.ld M src/soc/samsung/exynos5420/memlayout.ld M src/soc/sifive/fu540/memlayout.ld M src/soc/ti/am335x/memlayout.ld 35 files changed, 64 insertions(+), 22 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/24/38424/23
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38424 )
Change subject: cbfs: Enable CBFS mcache on most chipsets ......................................................................
Patch Set 23: Code-Review+2
Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/38424 )
Change subject: cbfs: Enable CBFS mcache on most chipsets ......................................................................
cbfs: Enable CBFS mcache on most chipsets
This patch flips the default of CONFIG_NO_CBFS_MCACHE so the feature is enabled by default. Some older chipsets with insufficient SRAM/CAR space still have it explicitly disabled. All others get the new section added to their memlayout... 8K seems like a sane default to start with.
Change-Id: I0abd1c813aece6e78fb883f292ce6c9319545c44 Signed-off-by: Julius Werner jwerner@chromium.org Reviewed-on: https://review.coreboot.org/c/coreboot/+/38424 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Furquan Shaikh furquan@google.com --- M src/arch/x86/Kconfig M src/arch/x86/car.ld M src/lib/Kconfig M src/mainboard/asus/p5gc-mx/Kconfig M src/mainboard/emulation/qemu-aarch64/memlayout.ld M src/mainboard/emulation/qemu-armv7/memlayout.ld M src/mainboard/emulation/qemu-power8/memlayout.ld M src/mainboard/emulation/qemu-riscv/memlayout.ld M src/mainboard/emulation/spike-riscv/memlayout.ld M src/mainboard/gigabyte/ga-945gcm-s2l/Kconfig M src/mainboard/google/octopus/Kconfig M src/mainboard/lenovo/t400/Kconfig M src/northbridge/intel/e7505/Kconfig M src/northbridge/intel/i440bx/Kconfig M src/northbridge/intel/pineview/Kconfig M src/northbridge/intel/x4x/Kconfig M src/soc/amd/common/block/cpu/noncar/memlayout_transfer_buffer.inc M src/soc/amd/common/block/cpu/noncar/memlayout_x86.ld M src/soc/cavium/cn81xx/memlayout.ld M src/soc/intel/braswell/Kconfig M src/soc/mediatek/mt8173/memlayout.ld M src/soc/mediatek/mt8183/memlayout.ld M src/soc/mediatek/mt8192/include/soc/memlayout.ld M src/soc/nvidia/tegra124/memlayout.ld M src/soc/nvidia/tegra210/memlayout.ld M src/soc/qualcomm/ipq40xx/memlayout.ld M src/soc/qualcomm/ipq806x/memlayout.ld M src/soc/qualcomm/qcs405/memlayout.ld M src/soc/qualcomm/sc7180/memlayout.ld M src/soc/rockchip/rk3288/Kconfig M src/soc/rockchip/rk3399/memlayout.ld M src/soc/samsung/exynos5250/memlayout.ld M src/soc/samsung/exynos5420/memlayout.ld M src/soc/sifive/fu540/memlayout.ld M src/soc/ti/am335x/memlayout.ld 35 files changed, 64 insertions(+), 22 deletions(-)
Approvals: build bot (Jenkins): Verified Furquan Shaikh: Looks good to me, approved
diff --git a/src/arch/x86/Kconfig b/src/arch/x86/Kconfig index b5e52e6..95c87da 100644 --- a/src/arch/x86/Kconfig +++ b/src/arch/x86/Kconfig @@ -144,6 +144,13 @@ help Increase this value if preram cbmem console is getting truncated
+config CBFS_MCACHE_SIZE + hex + depends on !NO_CBFS_MCACHE + default 0x2000 + help + Increase this value if you see CBFS mcache overflow warnings. + config PC80_SYSTEM bool default y if ARCH_X86 diff --git a/src/arch/x86/car.ld b/src/arch/x86/car.ld index c291efb..9f8c2ad 100644 --- a/src/arch/x86/car.ld +++ b/src/arch/x86/car.ld @@ -48,6 +48,9 @@
TIMESTAMP(., 0x200)
+#if !CONFIG(NO_CBFS_MCACHE) + CBFS_MCACHE(., CONFIG_CBFS_MCACHE_SIZE) +#endif #if !CONFIG(NO_FMAP_CACHE) FMAP_CACHE(., FMAP_SIZE) #endif diff --git a/src/lib/Kconfig b/src/lib/Kconfig index ab2b9c5..ab0182c 100644 --- a/src/lib/Kconfig +++ b/src/lib/Kconfig @@ -83,7 +83,6 @@
config NO_CBFS_MCACHE bool - default y help Disables the CBFS metadata cache. This means that your platform does not need to provide a CBFS_MCACHE section in memlayout and can save diff --git a/src/mainboard/asus/p5gc-mx/Kconfig b/src/mainboard/asus/p5gc-mx/Kconfig index ff3bbca..a0dc96e7 100644 --- a/src/mainboard/asus/p5gc-mx/Kconfig +++ b/src/mainboard/asus/p5gc-mx/Kconfig @@ -17,6 +17,7 @@ select BOARD_ROMSIZE_KB_512 select MAINBOARD_HAS_NATIVE_VGA_INIT select INTEL_GMA_HAVE_VBT + select NO_CBFS_MCACHE
config MAINBOARD_DIR string diff --git a/src/mainboard/emulation/qemu-aarch64/memlayout.ld b/src/mainboard/emulation/qemu-aarch64/memlayout.ld index cee77cd..ae00e96 100644 --- a/src/mainboard/emulation/qemu-aarch64/memlayout.ld +++ b/src/mainboard/emulation/qemu-aarch64/memlayout.ld @@ -19,7 +19,8 @@ REGION(secram, 0xe000000, 0x1000000, 4096) DRAM_START(0x40000000) BOOTBLOCK(0x60010000, 64K) - STACK(0x60020000, 62K) + STACK(0x60020000, 54K) + CBFS_MCACHE(0x6002D800, 8K) FMAP_CACHE(0x6002F800, 2K) TIMESTAMP(0x60030000, 1K) ROMSTAGE(0x60031000, 128K) diff --git a/src/mainboard/emulation/qemu-armv7/memlayout.ld b/src/mainboard/emulation/qemu-armv7/memlayout.ld index 4ddc6d2..5f32d8b 100644 --- a/src/mainboard/emulation/qemu-armv7/memlayout.ld +++ b/src/mainboard/emulation/qemu-armv7/memlayout.ld @@ -35,6 +35,7 @@ BOOTBLOCK(0x60010000, 128K) FMAP_CACHE(0x60030000, 4K) TIMESTAMP(0x60031000, 1K) + CBFS_MCACHE(0x60031400, 7K) /* TODO: Implement MMU support and move TTB to a better location. */ TTB(0x60034000, 16K) ROMSTAGE(0x60038000, 128K) diff --git a/src/mainboard/emulation/qemu-power8/memlayout.ld b/src/mainboard/emulation/qemu-power8/memlayout.ld index 90aaec6..66f2c75 100644 --- a/src/mainboard/emulation/qemu-power8/memlayout.ld +++ b/src/mainboard/emulation/qemu-power8/memlayout.ld @@ -13,5 +13,6 @@ STACK(0x40000, 0x3ff00) PRERAM_CBMEM_CONSOLE(0x80000, 8K) FMAP_CACHE(0x82000, 2K) + CBFS_MCACHE(0x82800, 8K) RAMSTAGE(0x100000, 16M) } diff --git a/src/mainboard/emulation/qemu-riscv/memlayout.ld b/src/mainboard/emulation/qemu-riscv/memlayout.ld index cfa0513..96ab74c 100644 --- a/src/mainboard/emulation/qemu-riscv/memlayout.ld +++ b/src/mainboard/emulation/qemu-riscv/memlayout.ld @@ -25,6 +25,7 @@ #endif PRERAM_CBMEM_CONSOLE(STAGES_START + 128K, 8K) FMAP_CACHE(STAGES_START + 136K, 2K) + CBFS_MCACHE(STAGES_START + 138K, 8K) RAMSTAGE(STAGES_START + 200K, 16M) STACK(STAGES_START + 200K + 16M, 4K) } diff --git a/src/mainboard/emulation/spike-riscv/memlayout.ld b/src/mainboard/emulation/spike-riscv/memlayout.ld index e08fd72..7ec4892 100644 --- a/src/mainboard/emulation/spike-riscv/memlayout.ld +++ b/src/mainboard/emulation/spike-riscv/memlayout.ld @@ -12,7 +12,8 @@ BOOTBLOCK(START, 64K) STACK(START + 8M, 4K) FMAP_CACHE(START + 8M + 4K, 2K) - /* hole at (START + 8M + 6K, 58K) */ + CBFS_MCACHE(START + 8M + 6K, 8K) + /* hole at (START + 8M + 14K, 50K) */ ROMSTAGE(START + 8M + 64K, 128K) PRERAM_CBMEM_CONSOLE(START + 8M + 192k, 8K) RAMSTAGE(START + 8M + 200K, 256K) diff --git a/src/mainboard/gigabyte/ga-945gcm-s2l/Kconfig b/src/mainboard/gigabyte/ga-945gcm-s2l/Kconfig index 9a8bf5b..f6a99e7 100644 --- a/src/mainboard/gigabyte/ga-945gcm-s2l/Kconfig +++ b/src/mainboard/gigabyte/ga-945gcm-s2l/Kconfig @@ -18,6 +18,7 @@ select MAINBOARD_HAS_NATIVE_VGA_INIT select REALTEK_8168_RESET if BOARD_GIGABYTE_GA_945GCM_S2L select INTEL_GMA_HAVE_VBT + select NO_CBFS_MCACHE
config MAINBOARD_DIR string diff --git a/src/mainboard/google/octopus/Kconfig b/src/mainboard/google/octopus/Kconfig index 588c8ed..7e8e277 100644 --- a/src/mainboard/google/octopus/Kconfig +++ b/src/mainboard/google/octopus/Kconfig @@ -26,6 +26,7 @@ select GOOGLE_SMBIOS_MAINBOARD_VERSION select NO_BOOTBLOCK_CONSOLE select NO_FMAP_CACHE + select NO_CBFS_MCACHE
if BOARD_GOOGLE_BASEBOARD_OCTOPUS
diff --git a/src/mainboard/lenovo/t400/Kconfig b/src/mainboard/lenovo/t400/Kconfig index 5b3ecf1..809ea45 100644 --- a/src/mainboard/lenovo/t400/Kconfig +++ b/src/mainboard/lenovo/t400/Kconfig @@ -26,6 +26,7 @@ select MAINBOARD_HAS_LIBGFXINIT select MAINBOARD_USES_IFD_GBE_REGION if !BOARD_LENOVO_R500 select INTEL_GMA_HAVE_VBT + select NO_CBFS_MCACHE
config VBOOT select VBOOT_VBNV_CMOS diff --git a/src/northbridge/intel/e7505/Kconfig b/src/northbridge/intel/e7505/Kconfig index 32fe1cf..e07691a 100644 --- a/src/northbridge/intel/e7505/Kconfig +++ b/src/northbridge/intel/e7505/Kconfig @@ -9,5 +9,6 @@ def_bool y select NO_MMCONF_SUPPORT select HAVE_DEBUG_RAM_SETUP + select NO_CBFS_MCACHE
endif diff --git a/src/northbridge/intel/i440bx/Kconfig b/src/northbridge/intel/i440bx/Kconfig index 8a6783e..0e61285 100644 --- a/src/northbridge/intel/i440bx/Kconfig +++ b/src/northbridge/intel/i440bx/Kconfig @@ -5,6 +5,7 @@ select NO_MMCONF_SUPPORT select HAVE_DEBUG_RAM_SETUP select NO_BOOTBLOCK_CONSOLE + select NO_CBFS_MCACHE
config SDRAMPWR_4DIMM bool diff --git a/src/northbridge/intel/pineview/Kconfig b/src/northbridge/intel/pineview/Kconfig index a1b0894..185beebe 100644 --- a/src/northbridge/intel/pineview/Kconfig +++ b/src/northbridge/intel/pineview/Kconfig @@ -14,6 +14,7 @@ select INTEL_EDID if MAINBOARD_DO_NATIVE_VGA_INIT select INTEL_GMA_ACPI select PARALLEL_MP + select NO_CBFS_MCACHE
config VGA_BIOS_ID string diff --git a/src/northbridge/intel/x4x/Kconfig b/src/northbridge/intel/x4x/Kconfig index 00e9a3a..8226fe9 100644 --- a/src/northbridge/intel/x4x/Kconfig +++ b/src/northbridge/intel/x4x/Kconfig @@ -13,6 +13,7 @@ select CACHE_MRC_SETTINGS select PARALLEL_MP select BOOT_DEVICE_SPI_FLASH_NO_EARLY_WRITES + select NO_CBFS_MCACHE
config CBFS_SIZE hex diff --git a/src/soc/amd/common/block/cpu/noncar/memlayout_transfer_buffer.inc b/src/soc/amd/common/block/cpu/noncar/memlayout_transfer_buffer.inc index a88e81a..d9bd096 100644 --- a/src/soc/amd/common/block/cpu/noncar/memlayout_transfer_buffer.inc +++ b/src/soc/amd/common/block/cpu/noncar/memlayout_transfer_buffer.inc @@ -12,6 +12,7 @@ ALIGN_COUNTER(64) PRERAM_CBMEM_CONSOLE(., CONFIG_PRERAM_CBMEM_CONSOLE_SIZE) TIMESTAMP(., TIMESTAMP_BUFFER_SIZE) + CBFS_MCACHE(., CONFIG_CBFS_MCACHE_SIZE) FMAP_CACHE(., FMAP_SIZE)
#if CONFIG(VBOOT) diff --git a/src/soc/amd/common/block/cpu/noncar/memlayout_x86.ld b/src/soc/amd/common/block/cpu/noncar/memlayout_x86.ld index 369d431..bf101e3 100644 --- a/src/soc/amd/common/block/cpu/noncar/memlayout_x86.ld +++ b/src/soc/amd/common/block/cpu/noncar/memlayout_x86.ld @@ -39,6 +39,8 @@ * | Unused hole | * +--------------------------------+ * | FMAP cache (FMAP_SIZE) | + * +--------------------------------+ + * | CBFS mcache (CBFS_MCACHE_SIZE) | * +--------------------------------+ PSP_SHAREDMEM_BASE + 0x40 + VB2_FIRMWARE_WORKBUF_RECOMMENDED_SIZE + PRERAM_CBMEM_CONSOLE_SIZE + 0x200 * | Early Timestamp region (512B) | * +--------------------------------+ PSP_SHAREDMEM_BASE + 0x40 + VB2_FIRMWARE_WORKBUF_RECOMMENDED_SIZE + PRERAM_CBMEM_CONSOLE_SIZE diff --git a/src/soc/cavium/cn81xx/memlayout.ld b/src/soc/cavium/cn81xx/memlayout.ld index 79673c9..0257b23 100644 --- a/src/soc/cavium/cn81xx/memlayout.ld +++ b/src/soc/cavium/cn81xx/memlayout.ld @@ -20,7 +20,8 @@ PRERAM_CBFS_CACHE(BOOTROM_OFFSET + 0x6000, 6K) FMAP_CACHE(BOOTROM_OFFSET + 0x7800, 2K) PRERAM_CBMEM_CONSOLE(BOOTROM_OFFSET + 0x8000, 8K) - BOOTBLOCK(BOOTROM_OFFSET + 0x20000, 64K) + BOOTBLOCK(BOOTROM_OFFSET + 0x20000, 56K) + CBFS_MCACHE(BOOTROM_OFFSET + 0x2e000, 8K) VBOOT2_WORK(BOOTROM_OFFSET + 0x30000, 12K) TPM_TCPA_LOG(BOOTROM_OFFSET + 0x33000, 2K) VERSTAGE(BOOTROM_OFFSET + 0x33800, 50K) diff --git a/src/soc/intel/braswell/Kconfig b/src/soc/intel/braswell/Kconfig index edbc6fd..dcc30ee 100644 --- a/src/soc/intel/braswell/Kconfig +++ b/src/soc/intel/braswell/Kconfig @@ -42,6 +42,7 @@ select CPU_INTEL_COMMON select SOUTHBRIDGE_INTEL_COMMON_SMBUS select SOUTHBRIDGE_INTEL_COMMON_SPI_SILVERMONT + select NO_CBFS_MCACHE
config DCACHE_BSP_STACK_SIZE hex diff --git a/src/soc/mediatek/mt8173/memlayout.ld b/src/soc/mediatek/mt8173/memlayout.ld index 4aece51..d9a6d83 100644 --- a/src/soc/mediatek/mt8173/memlayout.ld +++ b/src/soc/mediatek/mt8173/memlayout.ld @@ -30,7 +30,8 @@ FMAP_CACHE(0x00103800, 2K) PRERAM_CBMEM_CONSOLE(0x00104000, 12K) WATCHDOG_TOMBSTONE(0x00107000, 4) - PRERAM_CBFS_CACHE(0x00107004, 16K - 4) + PRERAM_CBFS_CACHE(0x00107004, 8K - 4) + CBFS_MCACHE(0x00109000, 8K) TIMESTAMP(0x0010B000, 4K) ROMSTAGE(0x0010C000, 92K) STACK(0x00124000, 16K) diff --git a/src/soc/mediatek/mt8183/memlayout.ld b/src/soc/mediatek/mt8183/memlayout.ld index a266377..db56666 100644 --- a/src/soc/mediatek/mt8183/memlayout.ld +++ b/src/soc/mediatek/mt8183/memlayout.ld @@ -30,7 +30,8 @@
SRAM_L2C_START(0x00200000) OVERLAP_DECOMPRESSOR_VERSTAGE_ROMSTAGE(0x00201000, 188K) - BOOTBLOCK(0x00230000, 64K) + BOOTBLOCK(0x00230000, 56K) + CBFS_MCACHE(0x0023e000, 8K) DRAM_INIT_CODE(0x00240000, 208K) PRERAM_CBFS_CACHE(0x00274000, 48K) SRAM_L2C_END(0x00280000) diff --git a/src/soc/mediatek/mt8192/include/soc/memlayout.ld b/src/soc/mediatek/mt8192/include/soc/memlayout.ld index c016d5f..2a21dd6 100644 --- a/src/soc/mediatek/mt8192/include/soc/memlayout.ld +++ b/src/soc/mediatek/mt8192/include/soc/memlayout.ld @@ -26,9 +26,10 @@ TPM_TCPA_LOG(0x00103000, 2K) FMAP_CACHE(0x00103800, 2K) WATCHDOG_TOMBSTONE(0x00104000, 4) - PRERAM_CBMEM_CONSOLE(0x00104004, 19K - 4) - TIMESTAMP(0x00108c00, 1K) - STACK(0x00109000, 16K) + PRERAM_CBMEM_CONSOLE(0x00104004, 15K - 4) + CBFS_MCACHE(0x00107c00, 8K) + TIMESTAMP(0x00109c00, 1K) + STACK(0x0010a000, 12K) TTB(0x0010d000, 28K) DMA_COHERENT(0x00114000, 4K) /* diff --git a/src/soc/nvidia/tegra124/memlayout.ld b/src/soc/nvidia/tegra124/memlayout.ld index 94b6fd8..f661d2a 100644 --- a/src/soc/nvidia/tegra124/memlayout.ld +++ b/src/soc/nvidia/tegra124/memlayout.ld @@ -16,7 +16,8 @@ TTB(0x40000000, 16K + 32) PRERAM_CBMEM_CONSOLE(0x40004020, 6K - 32) FMAP_CACHE(0x40005800, 2K) - PRERAM_CBFS_CACHE(0x40006000, 14K) + CBFS_MCACHE(0x40006000, 8K) + PRERAM_CBFS_CACHE(0x40008000, 6K) VBOOT2_WORK(0x40009800, 12K) TPM_TCPA_LOG(0x4000D800, 2K) STACK(0x4000E000, 8K) diff --git a/src/soc/nvidia/tegra210/memlayout.ld b/src/soc/nvidia/tegra210/memlayout.ld index e5620bc..42f2164 100644 --- a/src/soc/nvidia/tegra210/memlayout.ld +++ b/src/soc/nvidia/tegra210/memlayout.ld @@ -17,7 +17,8 @@ SRAM_START(0x40000000) PRERAM_CBMEM_CONSOLE(0x40000000, 2K) FMAP_CACHE(0x40000800, 2K) - PRERAM_CBFS_CACHE(0x40001000, 28K) + PRERAM_CBFS_CACHE(0x40001000, 20K) + CBFS_MCACHE(0x40006000, 8K) VBOOT2_WORK(0x40008000, 12K) TPM_TCPA_LOG(0x4000B000, 2K) #if ENV_ARM64 diff --git a/src/soc/qualcomm/ipq40xx/memlayout.ld b/src/soc/qualcomm/ipq40xx/memlayout.ld index 1a2dd31..4c54294 100644 --- a/src/soc/qualcomm/ipq40xx/memlayout.ld +++ b/src/soc/qualcomm/ipq40xx/memlayout.ld @@ -20,7 +20,8 @@ /* This includes bootblock image, can be reused after bootblock starts */ /* UBER_SBL(0x0A0C0000, 48K) */
- PRERAM_CBFS_CACHE(0x0A0C0000, 92K) + PRERAM_CBFS_CACHE(0x0A0C0000, 84K) + CBFS_MCACHE(0x0A0ED800, 8K) FMAP_CACHE(0x0A0EF800, 2K)
TTB(0x0A0F0000, 16K) diff --git a/src/soc/qualcomm/ipq806x/memlayout.ld b/src/soc/qualcomm/ipq806x/memlayout.ld index 6e7e56c..793e74e 100644 --- a/src/soc/qualcomm/ipq806x/memlayout.ld +++ b/src/soc/qualcomm/ipq806x/memlayout.ld @@ -24,7 +24,8 @@ QCA_SHARED_RAM(2A03F000, 4K) */ STACK(0x2A040000, 16K) - PRERAM_CBFS_CACHE(0x2A044000, 91K) + PRERAM_CBFS_CACHE(0x2A044000, 83K) + CBFS_MCACHE(0x2A059000, 8K) FMAP_CACHE(0x2A05B000, 2K) TTB_SUBTABLES(0x2A05B800, 2K) TTB(0x2A05C000, 16K) diff --git a/src/soc/qualcomm/qcs405/memlayout.ld b/src/soc/qualcomm/qcs405/memlayout.ld index ff2ad2f..a282512 100644 --- a/src/soc/qualcomm/qcs405/memlayout.ld +++ b/src/soc/qualcomm/qcs405/memlayout.ld @@ -25,7 +25,8 @@ STACK(0x8C4B000, 16K) TIMESTAMP(0x8C4F000, 1K) PRERAM_CBMEM_CONSOLE(0x8C4F400, 32K) - PRERAM_CBFS_CACHE(0x8C57400, 70K) + PRERAM_CBFS_CACHE(0x8C57400, 62K) + CBFS_MCACHE(0x8C66C00, 8K) FMAP_CACHE(0x8C68C00, 2K) REGION(bsram_unused, 0x8C69400, 0xA1C00, 0x100) BSRAM_END(0x8D80000) diff --git a/src/soc/qualcomm/sc7180/memlayout.ld b/src/soc/qualcomm/sc7180/memlayout.ld index 482620a..ca9c993 100644 --- a/src/soc/qualcomm/sc7180/memlayout.ld +++ b/src/soc/qualcomm/sc7180/memlayout.ld @@ -43,6 +43,7 @@ REGION(qclib_serial_log, 0x14852000, 4K, 4K) REGION(ddr_information, 0x14853000, 1K, 1K) FMAP_CACHE(0x14853400, 2K) + CBFS_MCACHE(0x14853C00, 8K) REGION(dcb, 0x1485b000, 16K, 4K) REGION(pmic, 0x1485f000, 48K, 4K) REGION(qclib, 0x1486b000, 596K, 4K) diff --git a/src/soc/rockchip/rk3288/Kconfig b/src/soc/rockchip/rk3288/Kconfig index 3dc9a9b..a51df2a 100644 --- a/src/soc/rockchip/rk3288/Kconfig +++ b/src/soc/rockchip/rk3288/Kconfig @@ -17,6 +17,7 @@ select HAVE_LINEAR_FRAMEBUFFER select NO_BOOTBLOCK_CONSOLE select NO_FMAP_CACHE + select NO_CBFS_MCACHE
if SOC_ROCKCHIP_RK3288
diff --git a/src/soc/rockchip/rk3399/memlayout.ld b/src/soc/rockchip/rk3399/memlayout.ld index 72836b5..aa925a2 100644 --- a/src/soc/rockchip/rk3399/memlayout.ld +++ b/src/soc/rockchip/rk3399/memlayout.ld @@ -24,11 +24,12 @@ FMAP_CACHE(0xFF8C1400, 2K) TIMESTAMP(0xFF8C1C00, 1K) /* 0xFF8C2004 is the entry point address the masked ROM will jump to. */ - OVERLAP_DECOMPRESSOR_VERSTAGE_ROMSTAGE(0xFF8C2004, 88K - 4) - BOOTBLOCK(0xFF8D8000, 40K) + OVERLAP_DECOMPRESSOR_VERSTAGE_ROMSTAGE(0xFF8C2004, 84K - 4) + BOOTBLOCK(0xFF8D7000, 40K) #endif - VBOOT2_WORK(0XFF8E2000, 12K) - TTB(0xFF8E5000, 24K) + CBFS_MCACHE(0xFF8E1000, 8K) + VBOOT2_WORK(0XFF8E3000, 12K) + TTB(0xFF8E6000, 20K) PRERAM_CBMEM_CONSOLE(0xFF8EB000, 8K) STACK(0xFF8ED000, 12K) SRAM_END(0xFF8F0000) diff --git a/src/soc/samsung/exynos5250/memlayout.ld b/src/soc/samsung/exynos5250/memlayout.ld index be4bb6e..eec9f60 100644 --- a/src/soc/samsung/exynos5250/memlayout.ld +++ b/src/soc/samsung/exynos5250/memlayout.ld @@ -18,7 +18,8 @@ ROMSTAGE(0x2030000, 128K) /* 32K hole */ TTB(0x2058000, 16K) - PRERAM_CBFS_CACHE(0x205C000, 76K) + PRERAM_CBFS_CACHE(0x205C000, 68K) + CBFS_MCACHE(0x206D000, 8K) FMAP_CACHE(0x206F000, 2K) TPM_TCPA_LOG(0x206F800, 2K) VBOOT2_WORK(0x2070000, 12K) diff --git a/src/soc/samsung/exynos5420/memlayout.ld b/src/soc/samsung/exynos5420/memlayout.ld index e299001..7c89413 100644 --- a/src/soc/samsung/exynos5420/memlayout.ld +++ b/src/soc/samsung/exynos5420/memlayout.ld @@ -19,7 +19,8 @@ ROMSTAGE(0x2030000, 128K) /* 32K hole */ TTB(0x2058000, 16K) - PRERAM_CBFS_CACHE(0x205C000, 74K) + PRERAM_CBFS_CACHE(0x205C000, 66K) + CBFS_MCACHE(0x206C800, 8K) FMAP_CACHE(0x206E800, 2K) STACK(0x206F000, 16K) /* 1K hole for weird kernel-shared CPU/SMP state structure that doesn't diff --git a/src/soc/sifive/fu540/memlayout.ld b/src/soc/sifive/fu540/memlayout.ld index fd63dc0..b365b96 100644 --- a/src/soc/sifive/fu540/memlayout.ld +++ b/src/soc/sifive/fu540/memlayout.ld @@ -12,8 +12,9 @@ { L2LIM_START(FU540_L2LIM) BOOTBLOCK(FU540_L2LIM, 64K) - CAR_STACK(FU540_L2LIM + 64K, 20K) - PRERAM_CBMEM_CONSOLE(FU540_L2LIM + 84K, 8K) + CAR_STACK(FU540_L2LIM + 64K, 12K) + PRERAM_CBMEM_CONSOLE(FU540_L2LIM + 76K, 8K) + CBFS_MCACHE(FU540_L2LIM + 84K, 8K) FMAP_CACHE(FU540_L2LIM + 92K, 2K) ROMSTAGE(FU540_L2LIM + 128K, 128K) PRERAM_CBFS_CACHE(FU540_L2LIM + 256K, 128K) diff --git a/src/soc/ti/am335x/memlayout.ld b/src/soc/ti/am335x/memlayout.ld index 720da26..042febe 100644 --- a/src/soc/ti/am335x/memlayout.ld +++ b/src/soc/ti/am335x/memlayout.ld @@ -9,6 +9,7 @@ SRAM_START(0x402f0400) BOOTBLOCK(0x402f0400, 20K) FMAP_CACHE(0x402f0400+20K, 2K) + CBFS_MCACHE(0x402f0400+20K+2K, 8K) TTB(0x402F8000, 16K) ROMSTAGE(0x402F8000+16K, 40K)
Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38424 )
Change subject: cbfs: Enable CBFS mcache on most chipsets ......................................................................
Patch Set 24:
on mandolin i got a "CBFS ERROR: CBFS mcache overflow!", but it still boots successfully. is that something that i should be concerned about?
Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38424 )
Change subject: cbfs: Enable CBFS mcache on most chipsets ......................................................................
Patch Set 24:
Patch Set 24:
on mandolin i got a "CBFS ERROR: CBFS mcache overflow!", but it still boots successfully. is that something that i should be concerned about?
https://review.coreboot.org/c/coreboot/+/48277 Might be a fix if it's not a real overflow.
Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38424 )
Change subject: cbfs: Enable CBFS mcache on most chipsets ......................................................................
Patch Set 24:
Patch Set 24:
Patch Set 24:
on mandolin i got a "CBFS ERROR: CBFS mcache overflow!", but it still boots successfully. is that something that i should be concerned about?
https://review.coreboot.org/c/coreboot/+/48277 Might be a fix if it's not a real overflow.
yep, that made the message go away, so it doesn't seem to be a real overflow
Julius Werner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38424 )
Change subject: cbfs: Enable CBFS mcache on most chipsets ......................................................................
Patch Set 24:
yep, that made the message go away, so it doesn't seem to be a real overflow
It was probably looking for a file that doesn't exist, that would trigger this and then you don't get a NOT_FOUND error but you still get some kind of error and the calling code behaves the same. Anyway, was just an incorrect check in the mcache code, is fixed now.
Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38424 )
Change subject: cbfs: Enable CBFS mcache on most chipsets ......................................................................
Patch Set 24:
Patch Set 24:
yep, that made the message go away, so it doesn't seem to be a real overflow
It was probably looking for a file that doesn't exist, that would trigger this and then you don't get a NOT_FOUND error but you still get some kind of error and the calling code behaves the same. Anyway, was just an incorrect check in the mcache code, is fixed now.
Yep, there was also a not found error somewhere near that and i've verified that the patch Arthur linked fixed the symptoms i commented about earlier
HAOUAS Elyes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38424 )
Change subject: cbfs: Enable CBFS mcache on most chipsets ......................................................................
Patch Set 24:
Hi Julius,
Would you please revert this patch ? I'm getting "Cache as RAM area is too full" error when I rebase https://review.coreboot.org/c/coreboot/+/25509 on master:
CC bootblock/southbridge/intel/common/rtc.o CC bootblock/southbridge/intel/common/usb_debug.o CC bootblock/southbridge/intel/i82801gx/bootblock.o CC bootblock/southbridge/intel/i82801gx/early_init.o CC bootblock/superio/winbond/common/early_init.o LINK cbfs/fallback/bootblock.debug /home/elyes/coreboot/util/crossgcc/xgcc/bin/i386-elf-ld.bfd: Cache as RAM area is too full make: *** [src/arch/x86/Makefile.inc:110 : build/cbfs/fallback/bootblock.debug] Erreur 1
Thank you
HAOUAS Elyes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38424 )
Change subject: cbfs: Enable CBFS mcache on most chipsets ......................................................................
Patch Set 24:
Patch Set 24:
Hi Julius,
Would you please revert this patch ? I'm getting "Cache as RAM area is too full" error when I rebase https://review.coreboot.org/c/coreboot/+/25509 on master:
CC bootblock/southbridge/intel/common/rtc.o CC bootblock/southbridge/intel/common/usb_debug.o CC bootblock/southbridge/intel/i82801gx/bootblock.o CC bootblock/southbridge/intel/i82801gx/early_init.o CC bootblock/superio/winbond/common/early_init.o LINK cbfs/fallback/bootblock.debug/home/elyes/coreboot/util/crossgcc/xgcc/bin/i386-elf-ld.bfd: Cache as RAM area is too full make: *** [src/arch/x86/Makefile.inc:110 : build/cbfs/fallback/bootblock.debug] Erreur 1
Thank you
Sorry, I forget to add "select NO_CBFS_MCACHE" now the error is gone. Thank you.
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Aaron Durbin (Code Review) -
Angel Pons (Code Review)
-
Arthur Heymans (Code Review)
-
Felix Held (Code Review)
-
Furquan Shaikh (Code Review)
-
HAOUAS Elyes (Code Review)
-
Julius Werner (Code Review)
-
Martin Roth (Code Review)
-
Patrick Georgi (Code Review)
-
Paul Menzel (Code Review)