Julius Werner would like Aaron Durbin to review this change.
cbfs: Enable CBFS mcache on (almost) all boards
This patch flips the default of CONFIG_NO_CBFS_MCACHE so the feature is
enabled by default. Only a few boards with notoriously little space
still have it explicitly disabled. All others get the new section added
to their memlayout... 8K seems like a sane default to start with.
Change-Id: I0abd1c813aece6e78fb883f292ce6c9319545c44
Signed-off-by: Julius Werner <jwerner@chromium.org>
---
M src/arch/x86/Kconfig
M src/arch/x86/car.ld
M src/cpu/ti/am335x/memlayout.ld
M src/lib/Kconfig
M src/mainboard/emulation/qemu-aarch64/memlayout.ld
M src/mainboard/emulation/qemu-armv7/memlayout.ld
M src/mainboard/emulation/qemu-power8/memlayout.ld
M src/mainboard/emulation/qemu-riscv/memlayout.ld
M src/mainboard/emulation/spike-riscv/memlayout.ld
M src/mainboard/google/octopus/Kconfig
M src/soc/cavium/cn81xx/include/soc/memlayout.ld
M src/soc/mediatek/mt8173/include/soc/memlayout.ld
M src/soc/mediatek/mt8183/include/soc/memlayout.ld
M src/soc/nvidia/tegra124/include/soc/memlayout.ld
M src/soc/nvidia/tegra210/include/soc/memlayout.ld
M src/soc/qualcomm/ipq40xx/include/soc/memlayout.ld
M src/soc/qualcomm/ipq806x/include/soc/memlayout.ld
M src/soc/qualcomm/qcs405/include/soc/memlayout.ld
M src/soc/qualcomm/sc7180/include/soc/memlayout.ld
M src/soc/qualcomm/sdm845/include/soc/memlayout.ld
M src/soc/rockchip/rk3288/Kconfig
M src/soc/rockchip/rk3399/include/soc/memlayout.ld
M src/soc/samsung/exynos5250/include/soc/memlayout.ld
M src/soc/samsung/exynos5420/include/soc/memlayout.ld
M src/soc/sifive/fu540/include/soc/memlayout.ld
25 files changed, 51 insertions(+), 20 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/24/38424/1
diff --git a/src/arch/x86/Kconfig b/src/arch/x86/Kconfig
index 1c55bdb..7cf049d 100644
--- a/src/arch/x86/Kconfig
+++ b/src/arch/x86/Kconfig
@@ -155,6 +155,13 @@
help
Increase this value if preram cbmem console is getting truncated
+config CBFS_MCACHE_SIZE
+ hex
+ depends on !NO_CBFS_MCACHE
+ default 0x2000
+ help
+ Increase this value if you see CBFS mcache overflow warnings
+
config PC80_SYSTEM
bool
default y if ARCH_X86
diff --git a/src/arch/x86/car.ld b/src/arch/x86/car.ld
index 2e29112..52e081a 100644
--- a/src/arch/x86/car.ld
+++ b/src/arch/x86/car.ld
@@ -60,6 +60,9 @@
#if !CONFIG(NO_FMAP_CACHE)
FMAP_CACHE(., FMAP_SIZE)
#endif
+#if !CONFIG(NO_CBFS_MCACHE)
+ CBFS_MCACHE(., CONFIG_CBFS_MCACHE_SIZE)
+#endif
_car_ehci_dbg_info = .;
/* Reserve sizeof(struct ehci_dbg_info). */
diff --git a/src/cpu/ti/am335x/memlayout.ld b/src/cpu/ti/am335x/memlayout.ld
index f69a315..9bc7b75 100644
--- a/src/cpu/ti/am335x/memlayout.ld
+++ b/src/cpu/ti/am335x/memlayout.ld
@@ -19,7 +19,8 @@
{
DRAM_START(0x40000000)
BOOTBLOCK(0x402f0400, 20K)
- ROMSTAGE(0x402f5400, 88K)
+ ROMSTAGE(0x402f5400, 80K)
+ CBFS_MCACHE(0x40309400, 8K)
FMAP_CACHE(0x4030b400, 2K)
STACK(0x4030be00, 4K)
RAMSTAGE(0x80200000, 192K)
diff --git a/src/lib/Kconfig b/src/lib/Kconfig
index 26bf0be..4d2bf80 100644
--- a/src/lib/Kconfig
+++ b/src/lib/Kconfig
@@ -78,7 +78,6 @@
config NO_CBFS_MCACHE
bool
- default y
help
Disables the CBFS metadata cache. This means that your platform does
not need to provide a CBFS_MCACHE section in memlayout and can save
diff --git a/src/mainboard/emulation/qemu-aarch64/memlayout.ld b/src/mainboard/emulation/qemu-aarch64/memlayout.ld
index aba4205..544f89f 100644
--- a/src/mainboard/emulation/qemu-aarch64/memlayout.ld
+++ b/src/mainboard/emulation/qemu-aarch64/memlayout.ld
@@ -24,7 +24,8 @@
DRAM_START(0x40000000)
BOOTBLOCK(0x60010000, 64K)
- STACK(0x60020000, 62K)
+ STACK(0x60020000, 54K)
+ CBFS_MCACHE(0x6002D800, 8K)
FMAP_CACHE(0x6002F800, 2K)
ROMSTAGE(0x60030000, 128K)
RAMSTAGE(0x60070000, 16M)
diff --git a/src/mainboard/emulation/qemu-armv7/memlayout.ld b/src/mainboard/emulation/qemu-armv7/memlayout.ld
index 2b33cb3..de09cbb 100644
--- a/src/mainboard/emulation/qemu-armv7/memlayout.ld
+++ b/src/mainboard/emulation/qemu-armv7/memlayout.ld
@@ -43,6 +43,7 @@
BOOTBLOCK(0x00000, 64K)
FMAP_CACHE(0x10000, 2K)
+ CBFS_MCACHE(0x10800, 8K)
DRAM_START(0x60000000)
STACK(0x60000000, 64K)
diff --git a/src/mainboard/emulation/qemu-power8/memlayout.ld b/src/mainboard/emulation/qemu-power8/memlayout.ld
index c22d3e4..81fe7f4 100644
--- a/src/mainboard/emulation/qemu-power8/memlayout.ld
+++ b/src/mainboard/emulation/qemu-power8/memlayout.ld
@@ -27,5 +27,6 @@
STACK(0x40000, 0x3ff00)
PRERAM_CBMEM_CONSOLE(0x80000, 8K)
FMAP_CACHE(0x82000, 2K)
+ CBFS_MCACHE(0x82800, 8K)
RAMSTAGE(0x100000, 16M)
}
diff --git a/src/mainboard/emulation/qemu-riscv/memlayout.ld b/src/mainboard/emulation/qemu-riscv/memlayout.ld
index e53df38..7eb0f00 100644
--- a/src/mainboard/emulation/qemu-riscv/memlayout.ld
+++ b/src/mainboard/emulation/qemu-riscv/memlayout.ld
@@ -38,6 +38,7 @@
#endif
PRERAM_CBMEM_CONSOLE(STAGES_START + 128K, 8K)
FMAP_CACHE(STAGES_START + 136K, 2K)
+ CBFS_MCACHE(STAGES_START + 138K, 8K)
RAMSTAGE(STAGES_START + 200K, 16M)
STACK(STAGES_START + 200K + 16M, 4K)
}
diff --git a/src/mainboard/emulation/spike-riscv/memlayout.ld b/src/mainboard/emulation/spike-riscv/memlayout.ld
index b6e4d9d..376b9b1 100644
--- a/src/mainboard/emulation/spike-riscv/memlayout.ld
+++ b/src/mainboard/emulation/spike-riscv/memlayout.ld
@@ -24,7 +24,8 @@
DRAM_START(START)
BOOTBLOCK(START, 64K)
STACK(START + 8M, 4K)
- FMAP_CACHE(START + 8M + 4K, 2K)
+ FMAP_CACHE(START + 12M, 2K)
+ CBFS_CACHE(START + 14M, 8K)
/* hole at (START + 8M + 6K, 58K) */
ROMSTAGE(START + 8M + 64K, 128K)
PRERAM_CBMEM_CONSOLE(START + 8M + 192k, 8K)
diff --git a/src/mainboard/google/octopus/Kconfig b/src/mainboard/google/octopus/Kconfig
index 3139716..8a33b5f 100644
--- a/src/mainboard/google/octopus/Kconfig
+++ b/src/mainboard/google/octopus/Kconfig
@@ -23,6 +23,7 @@
select MAINBOARD_HAS_TPM2
select GOOGLE_SMBIOS_MAINBOARD_VERSION
select NO_FMAP_CACHE
+ select NO_CBFS_MCACHE
if BOARD_GOOGLE_BASEBOARD_OCTOPUS
diff --git a/src/soc/cavium/cn81xx/include/soc/memlayout.ld b/src/soc/cavium/cn81xx/include/soc/memlayout.ld
index 1a0eb15..e78aa20 100644
--- a/src/soc/cavium/cn81xx/include/soc/memlayout.ld
+++ b/src/soc/cavium/cn81xx/include/soc/memlayout.ld
@@ -34,7 +34,8 @@
PRERAM_CBFS_CACHE(BOOTROM_OFFSET + 0x6000, 6K)
FMAP_CACHE(BOOTROM_OFFSET + 0x7800, 2K)
PRERAM_CBMEM_CONSOLE(BOOTROM_OFFSET + 0x8000, 8K)
- BOOTBLOCK(BOOTROM_OFFSET + 0x20000, 64K)
+ BOOTBLOCK(BOOTROM_OFFSET + 0x20000, 56K)
+ CBFS_MCACHE(BOOTROM_OFFSET + 0x2e000, 8K)
VBOOT2_WORK(BOOTROM_OFFSET + 0x30000, 12K)
VBOOT2_TPM_LOG(BOOTROM_OFFSET + 0x33000, 2K)
VERSTAGE(BOOTROM_OFFSET + 0x33800, 50K)
diff --git a/src/soc/mediatek/mt8173/include/soc/memlayout.ld b/src/soc/mediatek/mt8173/include/soc/memlayout.ld
index 2358c39..2d364b5 100644
--- a/src/soc/mediatek/mt8173/include/soc/memlayout.ld
+++ b/src/soc/mediatek/mt8173/include/soc/memlayout.ld
@@ -43,7 +43,8 @@
FMAP_CACHE(0x00103800, 2K)
PRERAM_CBMEM_CONSOLE(0x00104000, 12K)
WATCHDOG_TOMBSTONE(0x00107000, 4)
- PRERAM_CBFS_CACHE(0x00107004, 16K - 4)
+ PRERAM_CBFS_CACHE(0x00107004, 8K - 4)
+ CBFS_MCACHE(0x00109000, 8K)
TIMESTAMP(0x0010B000, 4K)
ROMSTAGE(0x0010C000, 92K)
STACK(0x00124000, 16K)
diff --git a/src/soc/mediatek/mt8183/include/soc/memlayout.ld b/src/soc/mediatek/mt8183/include/soc/memlayout.ld
index 996d2ec..0d20e31 100644
--- a/src/soc/mediatek/mt8183/include/soc/memlayout.ld
+++ b/src/soc/mediatek/mt8183/include/soc/memlayout.ld
@@ -43,7 +43,8 @@
SRAM_L2C_START(0x00200000)
OVERLAP_DECOMPRESSOR_VERSTAGE_ROMSTAGE(0x00201000, 188K)
- BOOTBLOCK(0x00230000, 64K)
+ BOOTBLOCK(0x00230000, 56K)
+ CBFS_MCACHE(0x0023e000, 8K)
DRAM_INIT_CODE(0x00240000, 208K)
PRERAM_CBFS_CACHE(0x00274000, 48K)
SRAM_L2C_END(0x00280000)
diff --git a/src/soc/nvidia/tegra124/include/soc/memlayout.ld b/src/soc/nvidia/tegra124/include/soc/memlayout.ld
index 7e2cc7a..a342f6a 100644
--- a/src/soc/nvidia/tegra124/include/soc/memlayout.ld
+++ b/src/soc/nvidia/tegra124/include/soc/memlayout.ld
@@ -29,7 +29,8 @@
TTB(0x40000000, 16K + 32)
PRERAM_CBMEM_CONSOLE(0x40004020, 6K - 32)
FMAP_CACHE(0x40005800, 2K)
- PRERAM_CBFS_CACHE(0x40006000, 14K)
+ CBFS_MCACHE(0x40006000, 8K)
+ PRERAM_CBFS_CACHE(0x40008000, 6K)
VBOOT2_WORK(0x40009800, 12K)
VBOOT2_TPM_LOG(0x4000D800, 2K)
STACK(0x4000E000, 8K)
diff --git a/src/soc/nvidia/tegra210/include/soc/memlayout.ld b/src/soc/nvidia/tegra210/include/soc/memlayout.ld
index b7268d1..44f0153 100644
--- a/src/soc/nvidia/tegra210/include/soc/memlayout.ld
+++ b/src/soc/nvidia/tegra210/include/soc/memlayout.ld
@@ -30,7 +30,8 @@
SRAM_START(0x40000000)
PRERAM_CBMEM_CONSOLE(0x40000000, 2K)
FMAP_CACHE(0x40000800, 2K)
- PRERAM_CBFS_CACHE(0x40001000, 28K)
+ PRERAM_CBFS_CACHE(0x40001000, 20K)
+ CBFS_MCACHE(0x40006000, 8K)
VBOOT2_WORK(0x40008000, 12K)
VBOOT2_TPM_LOG(0x4000B000, 2K)
#if ENV_ARM64
diff --git a/src/soc/qualcomm/ipq40xx/include/soc/memlayout.ld b/src/soc/qualcomm/ipq40xx/include/soc/memlayout.ld
index 6ff1018..76685cf 100644
--- a/src/soc/qualcomm/ipq40xx/include/soc/memlayout.ld
+++ b/src/soc/qualcomm/ipq40xx/include/soc/memlayout.ld
@@ -34,7 +34,8 @@
/* This includes bootblock image, can be reused after bootblock starts */
/* UBER_SBL(0x0A0C0000, 48K) */
- PRERAM_CBFS_CACHE(0x0A0C0000, 92K)
+ PRERAM_CBFS_CACHE(0x0A0C0000, 84K)
+ CBFS_MCACHE(0x0A0ED800, 8K)
FMAP_CACHE(0x0A0EF800, 2K)
TTB(0x0A0F0000, 16K)
diff --git a/src/soc/qualcomm/ipq806x/include/soc/memlayout.ld b/src/soc/qualcomm/ipq806x/include/soc/memlayout.ld
index 595d939..6e309c0 100644
--- a/src/soc/qualcomm/ipq806x/include/soc/memlayout.ld
+++ b/src/soc/qualcomm/ipq806x/include/soc/memlayout.ld
@@ -38,7 +38,8 @@
QCA_SHARED_RAM(2A03F000, 4K)
*/
STACK(0x2A040000, 16K)
- PRERAM_CBFS_CACHE(0x2A044000, 91K)
+ PRERAM_CBFS_CACHE(0x2A044000, 83K)
+ CBFS_MCACHE(0x2A059000, 8K)
FMAP_CACHE(0x2A05B000, 2K)
TTB_SUBTABLES(0x2A05B800, 2K)
TTB(0x2A05C000, 16K)
diff --git a/src/soc/qualcomm/qcs405/include/soc/memlayout.ld b/src/soc/qualcomm/qcs405/include/soc/memlayout.ld
index dd013b5..9d92949 100644
--- a/src/soc/qualcomm/qcs405/include/soc/memlayout.ld
+++ b/src/soc/qualcomm/qcs405/include/soc/memlayout.ld
@@ -38,7 +38,8 @@
STACK(0x8C4B000, 16K)
TIMESTAMP(0x8C4F000, 1K)
PRERAM_CBMEM_CONSOLE(0x8C4F400, 32K)
- PRERAM_CBFS_CACHE(0x8C57400, 70K)
+ PRERAM_CBFS_CACHE(0x8C57400, 62K)
+ CBFS_MCACHE(0x8C66C00, 8K)
FMAP_CACHE(0x8C68C00, 2K)
REGION(bsram_unused, 0x8C69400, 0xA1C00, 0x100)
BSRAM_END(0x8D80000)
diff --git a/src/soc/qualcomm/sc7180/include/soc/memlayout.ld b/src/soc/qualcomm/sc7180/include/soc/memlayout.ld
index 7323119..838fda3 100644
--- a/src/soc/qualcomm/sc7180/include/soc/memlayout.ld
+++ b/src/soc/qualcomm/sc7180/include/soc/memlayout.ld
@@ -52,6 +52,7 @@
REGION(qclib_serial_log, 0x14852000, 4K, 4K)
REGION(ddr_information, 0x14853000, 1K, 1K)
FMAP_CACHE(0x14853400, 2K)
+ CBFS_MCACHE(0x14853C00, 8K)
REGION(dcb, 0x14870000, 16K, 4K)
REGION(pmic, 0x14874000, 44K, 4K)
REGION(limits_cfg, 0x1487F000, 4K, 4K)
diff --git a/src/soc/qualcomm/sdm845/include/soc/memlayout.ld b/src/soc/qualcomm/sdm845/include/soc/memlayout.ld
index c3a3b4c..5ea3e96 100644
--- a/src/soc/qualcomm/sdm845/include/soc/memlayout.ld
+++ b/src/soc/qualcomm/sdm845/include/soc/memlayout.ld
@@ -58,7 +58,8 @@
PRERAM_CBMEM_CONSOLE(0x14836400, 32K)
PRERAM_CBFS_CACHE(0x1483E400, 70K)
FMAP_CACHE(0x1484FC00, 2K)
- REGION(bsram_unused, 0x14850400, 0x9DB00, 0x100)
+ CBFS_MCACHE(0x1485400, 8K)
+ REGION(bsram_unused, 0x14852400, 0x9BB00, 0x100)
REGION(ddr_information, 0x148EDF00, 256, 256)
REGION(limits_cfg, 0x148EE000, 4K, 4K)
REGION(qclib_serial_log, 0x148EF000, 4K, 4K)
diff --git a/src/soc/rockchip/rk3288/Kconfig b/src/soc/rockchip/rk3288/Kconfig
index 6a44ccd..e36a8e8 100644
--- a/src/soc/rockchip/rk3288/Kconfig
+++ b/src/soc/rockchip/rk3288/Kconfig
@@ -30,6 +30,7 @@
select HAVE_LINEAR_FRAMEBUFFER
select NO_BOOTBLOCK_CONSOLE
select NO_FMAP_CACHE
+ select NO_CBFS_MCACHE
if SOC_ROCKCHIP_RK3288
diff --git a/src/soc/rockchip/rk3399/include/soc/memlayout.ld b/src/soc/rockchip/rk3399/include/soc/memlayout.ld
index 4e46e2d..2c7be29 100644
--- a/src/soc/rockchip/rk3399/include/soc/memlayout.ld
+++ b/src/soc/rockchip/rk3399/include/soc/memlayout.ld
@@ -37,11 +37,12 @@
FMAP_CACHE(0xFF8C1400, 2K)
TIMESTAMP(0xFF8C1C00, 1K)
/* 0xFF8C2004 is the entry point address the masked ROM will jump to. */
- OVERLAP_DECOMPRESSOR_VERSTAGE_ROMSTAGE(0xFF8C2004, 88K - 4)
- BOOTBLOCK(0xFF8D8000, 40K)
+ OVERLAP_DECOMPRESSOR_VERSTAGE_ROMSTAGE(0xFF8C2004, 84K - 4)
+ BOOTBLOCK(0xFF8D7000, 40K)
#endif
- VBOOT2_WORK(0XFF8E2000, 12K)
- TTB(0xFF8E5000, 24K)
+ CBFS_MCACHE(0xFF8E1000, 8K)
+ VBOOT2_WORK(0XFF8E3000, 12K)
+ TTB(0xFF8E6000, 20K)
PRERAM_CBMEM_CONSOLE(0xFF8EB000, 8K)
STACK(0xFF8ED000, 12K)
SRAM_END(0xFF8F0000)
diff --git a/src/soc/samsung/exynos5250/include/soc/memlayout.ld b/src/soc/samsung/exynos5250/include/soc/memlayout.ld
index 7e052f0..e97fcb0 100644
--- a/src/soc/samsung/exynos5250/include/soc/memlayout.ld
+++ b/src/soc/samsung/exynos5250/include/soc/memlayout.ld
@@ -31,7 +31,8 @@
ROMSTAGE(0x2030000, 128K)
/* 32K hole */
TTB(0x2058000, 16K)
- PRERAM_CBFS_CACHE(0x205C000, 76K)
+ PRERAM_CBFS_CACHE(0x205C000, 68K)
+ CBFS_MCACHE(0x206D000, 8K)
FMAP_CACHE(0x206F000, 2K)
VBOOT2_TPM_LOG(0x206F800, 2K)
VBOOT2_WORK(0x2070000, 12K)
diff --git a/src/soc/samsung/exynos5420/include/soc/memlayout.ld b/src/soc/samsung/exynos5420/include/soc/memlayout.ld
index ff781d2..e2e51c0 100644
--- a/src/soc/samsung/exynos5420/include/soc/memlayout.ld
+++ b/src/soc/samsung/exynos5420/include/soc/memlayout.ld
@@ -32,7 +32,8 @@
ROMSTAGE(0x2030000, 128K)
/* 32K hole */
TTB(0x2058000, 16K)
- PRERAM_CBFS_CACHE(0x205C000, 74K)
+ PRERAM_CBFS_CACHE(0x205C000, 66K)
+ CBFS_MCACHE(0x206C800, 8K)
FMAP_CACHE(0x206E800, 2K)
STACK(0x206F000, 16K)
/* 1K hole for weird kernel-shared CPU/SMP state structure that doesn't
diff --git a/src/soc/sifive/fu540/include/soc/memlayout.ld b/src/soc/sifive/fu540/include/soc/memlayout.ld
index 46c559c..cc4f900 100644
--- a/src/soc/sifive/fu540/include/soc/memlayout.ld
+++ b/src/soc/sifive/fu540/include/soc/memlayout.ld
@@ -26,7 +26,8 @@
L2LIM_START(FU540_L2LIM)
BOOTBLOCK(FU540_L2LIM, 64K)
CAR_STACK(FU540_L2LIM + 64K, 20K)
- PRERAM_CBMEM_CONSOLE(FU540_L2LIM + 84K, 8K)
+ PRERAM_CBMEM_CONSOLE(FU540_L2LIM + 76K, 8K)
+ CBFS_MCACHE(FU540_L2LIM + 84K, 8K)
FMAP_CACHE(FU540_L2LIM + 92K, 2K)
ROMSTAGE(FU540_L2LIM + 128K, 128K)
PRERAM_CBFS_CACHE(FU540_L2LIM + 256K, 128K)
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