Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35439 )
Change subject: sb/intel/ibexpeak: Add CIR initialization ......................................................................
sb/intel/ibexpeak: Add CIR initialization
This properly the chipset initialization registers.
The information is taken from the EDS and from the thinkpad x201 vendor BIOS disassembly.
Change-Id: I21c2beaf70da27dbe6a56e2612df2c257c05fc62 Signed-off-by: Arthur Heymans arthur@aheymans.xyz --- M src/mainboard/lenovo/x201/romstage.c M src/mainboard/packardbell/ms2290/romstage.c M src/southbridge/intel/ibexpeak/Makefile.inc A src/southbridge/intel/ibexpeak/early_cir.c M src/southbridge/intel/ibexpeak/pch.h 5 files changed, 112 insertions(+), 34 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/39/35439/1
diff --git a/src/mainboard/lenovo/x201/romstage.c b/src/mainboard/lenovo/x201/romstage.c index 3a06a8c..9d98637 100644 --- a/src/mainboard/lenovo/x201/romstage.c +++ b/src/mainboard/lenovo/x201/romstage.c @@ -66,21 +66,6 @@ southbridge_configure_default_intmap();
static const u32 rcba_dump3[] = { - /* 3310 */ 0x02060100, 0x0000000f, 0x01020000, 0x80000000, - /* 3320 */ 0x00000000, 0x04000000, 0x00000000, 0x00000000, - /* 3330 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, - /* 3340 */ 0x000fffff, 0x00000000, 0x00000000, 0x00000000, - /* 3350 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, - /* 3360 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, - /* 3370 */ 0x00000000, 0x00000000, 0x7f8fdfff, 0x00000000, - /* 3380 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, - /* 3390 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, - /* 33a0 */ 0x00003900, 0x00000000, 0x00000000, 0x00000000, - /* 33b0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, - /* 33c0 */ 0x00010000, 0x00000000, 0x00000000, 0x0001004b, - /* 33d0 */ 0x06000008, 0x00010000, 0x00000000, 0x00000000, - /* 33e0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, - /* 33f0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, /* 3400 */ 0x0000001c, 0x00000080, 0x00000000, 0x00000000, /* 3410 */ 0x00000c61, 0x00000000, 0x16e41fe1, 0xbf4f001f, /* 3420 */ 0x00000000, 0x00060010, 0x0000001d, 0x00000000, @@ -135,8 +120,8 @@ }; unsigned i; for (i = 0; i < sizeof(rcba_dump3) / 4; i++) { - RCBA32(4 * i + 0x3310) = rcba_dump3[i]; - (void)RCBA32(4 * i + 0x3310); + RCBA32(4 * i + 0x3400) = rcba_dump3[i]; + (void)RCBA32(4 * i + 0x3400); } }
@@ -186,6 +171,8 @@
setup_pch_gpios(&mainboard_gpio_map);
+ pch_setup_cir(NEHALEM_MOBILE); +
/* This should probably go away. Until now it is required * and mainboard specific diff --git a/src/mainboard/packardbell/ms2290/romstage.c b/src/mainboard/packardbell/ms2290/romstage.c index 5a4a9f1..a426d89 100644 --- a/src/mainboard/packardbell/ms2290/romstage.c +++ b/src/mainboard/packardbell/ms2290/romstage.c @@ -61,21 +61,6 @@ southbridge_configure_default_intmap();
static const u32 rcba_dump3[] = { - /* 3310 */ 0x02060100, 0x0000000f, 0x01020000, 0x80000000, - /* 3320 */ 0x00000000, 0x04000000, 0x00000000, 0x00000000, - /* 3330 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, - /* 3340 */ 0x000fffff, 0x00000000, 0x00000000, 0x00000000, - /* 3350 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, - /* 3360 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, - /* 3370 */ 0x00000000, 0x00000000, 0x7f8fdfff, 0x00000000, - /* 3380 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, - /* 3390 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, - /* 33a0 */ 0x00003900, 0x00000000, 0x00000000, 0x00000000, - /* 33b0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, - /* 33c0 */ 0x00010000, 0x00000000, 0x00000000, 0x0001004b, - /* 33d0 */ 0x06000008, 0x00010000, 0x00000000, 0x00000000, - /* 33e0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, - /* 33f0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, /* 3400 */ 0x0000001c, 0x00000080, 0x00000000, 0x00000000, /* 3410 */ 0x00000c61, 0x00000000, 0x16fc1fe1, 0xbf4f001f, /* 3420 */ 0x00000000, 0x00060010, 0x0000001d, 0x00000000, @@ -131,8 +116,8 @@ unsigned i;
for (i = 0; i < sizeof(rcba_dump3) / 4; i++) { - RCBA32(4 * i + 0x3310) = rcba_dump3[i]; - (void)RCBA32(4 * i + 0x3310); + RCBA32(4 * i + 0x3400) = rcba_dump3[i]; + (void)RCBA32(4 * i + 0x3400); } }
@@ -181,6 +166,8 @@
setup_pch_gpios(&mainboard_gpio_map);
+ pch_setup_cir(NEHALEM_MOBILE); + /* This should probably go away. Until now it is required * and mainboard specific */ diff --git a/src/southbridge/intel/ibexpeak/Makefile.inc b/src/southbridge/intel/ibexpeak/Makefile.inc index 83d083f..97565d6 100644 --- a/src/southbridge/intel/ibexpeak/Makefile.inc +++ b/src/southbridge/intel/ibexpeak/Makefile.inc @@ -42,5 +42,6 @@ romstage-y +=../bd82x6x/me_status.c romstage-y += early_thermal.c romstage-y += ../bd82x6x/early_rcba.c +romstage-y += early_cir.c
endif diff --git a/src/southbridge/intel/ibexpeak/early_cir.c b/src/southbridge/intel/ibexpeak/early_cir.c new file mode 100644 index 0000000..5628bc5 --- /dev/null +++ b/src/southbridge/intel/ibexpeak/early_cir.c @@ -0,0 +1,83 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <console/console.h> +#include <cpu/cpu.h> +#include <device/pci_ops.h> +#include <device/pci_def.h> +#include <northbridge/intel/nehalem/nehalem.h> +#include "pch.h" + +/* This set up magic Chipset Initialization Registers */ + +void pch_setup_cir(int chipset_type) +{ + printk(BIOS_DEBUG, "Setting up Chipset Initialization registers\n"); + + uint16_t lpc_id = pci_read_config16(PCH_LPC_DEV, PCI_DEVICE_ID); + struct cpuinfo_x86 c; + + RCBA32(CIR7) = 0xf; + + switch (lpc_id) { + case 0x3b01: + case 0x3b03: + case 0x3b05: + case 0x3b07: + case 0x3b09: + case 0x3b0b: + case 0x3b0d: + case 0x3b0f: + RCBA32_AND_OR(CIR6, 0xff7ffff, 0x600000); + break; + } + + if (chipset_type == NEHALEM_DESKTOP) + pci_or_config32(PCH_LPC_DEV, GEN_PMCON_1, 1 << 3); + + pci_write_config8(PCH_LPC_DEV, CIR4, 0x45); + + RCBA32(CIR8) = 0x4000000; + pci_write_config32(PCH_LPC_DEV, PMIR, 0xc0000300); + RCBA32(0x3318) = 0x1020000; /* undocumented */ + get_fms(&c, cpuid_eax(1)); + if (c.x86_model == 0x1e) { + /* Lynnfield/Clarksfield */ + RCBA32(CIR13) = 0xfffff; + RCBA32(CIR14) = 0x61080; + RCBA32(CIR16) = 0x7f8fdf80; + RCBA32(CIR18) = 0; /* Does not match EDS */ + RCBA32(CIR19) = 0x20002; + RCBA32(CIR20) = 0x44b00; + RCBA32(CIR21) = 0x6002000; + /* Program this register after all registers in the + * 3330-33D3 range and D31:F0:A9h are already programmed + */ + RCBA32(CIR22) = 0x20000; + + } else if (c.x86_model == 0x1f || c.x86_model == 0x25) { + /* Auburndale/Havendale + Arrandale/Clarkdale */ + RCBA32(CIR10) = 0xfffff; + RCBA32(CIR15) = 0x7f8fdfff; + RCBA32(CIR17) = 0x3900; + RCBA32(CIR19) = 0x10000; + RCBA32(CIR20) = 0x1004b; + RCBA32(CIR21) = 0x6000008; + /* Program this register after all registers in the + * 3330-33D3 range and D31:F0:A9h are already programmed + */ + RCBA32(CIR22) = 0x10000; + } else { + die("unsupported CPU!\n"); + } +} diff --git a/src/southbridge/intel/ibexpeak/pch.h b/src/southbridge/intel/ibexpeak/pch.h index ee0f9ad..bc194ac 100644 --- a/src/southbridge/intel/ibexpeak/pch.h +++ b/src/southbridge/intel/ibexpeak/pch.h @@ -67,6 +67,7 @@
void early_thermal_init(void); void southbridge_configure_default_intmap(void); +void pch_setup_cir(int chipset_type);
#ifndef __ROMCC__ #include <device/device.h> @@ -104,6 +105,9 @@ #define ETR3_CWORWRE (1 << 18) #define ETR3_CF9GR (1 << 20)
+#define CIR4 0xa9 +#define PMIR 0xac + /* GEN_PMCON_3 bits */ #define RTC_BATTERY_DEAD (1 << 2) #define RTC_POWER_FAILED (1 << 1) @@ -352,6 +356,22 @@ #define SOFT_RESET_CTRL 0x38f4 #define SOFT_RESET_DATA 0x38f8
+#define CIR6 0x2024 +#define CIR7 0x3314 +#define CIR8 0x3324 +#define CIR9 0x3330 +#define CIR10 0x3340 +#define CIR13 0x3350 +#define CIR14 0x3368 +#define CIR15 0x3378 +#define CIR16 0x3388 +#define CIR17 0x33a0 +#define CIR18 0x33a8 +#define CIR19 0x33c0 +#define CIR20 0x33cc +#define CIR21 0x33d0 +#define CIR22 0x33d4 + #define DIR_ROUTE(x,a,b,c,d) \ RCBA32(x) = (((d) << DIR_IDR) | ((c) << DIR_ICR) | \ ((b) << DIR_IBR) | ((a) << DIR_IAR))
Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35439 )
Change subject: sb/intel/ibexpeak: Add CIR initialization ......................................................................
Patch Set 1: Code-Review-2
Seems to have boot problems. Need to investigate...
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35439 )
Change subject: sb/intel/ibexpeak: Add CIR initialization ......................................................................
Patch Set 1: Code-Review+1
(2 comments)
https://review.coreboot.org/c/coreboot/+/35439/1/src/southbridge/intel/ibexp... File src/southbridge/intel/ibexpeak/early_cir.c:
https://review.coreboot.org/c/coreboot/+/35439/1/src/southbridge/intel/ibexp... PS1, Line 21: set sets
https://review.coreboot.org/c/coreboot/+/35439/1/src/southbridge/intel/ibexp... PS1, Line 81: CPU CPU for southbridge code? Ah, it refers to the CPU this is paired with
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35439 )
Change subject: sb/intel/ibexpeak: Add CIR initialization ......................................................................
Patch Set 1:
Patch Set 1: Code-Review-2
Seems to have boot problems. Need to investigate...
Suggestion: printk() between every assignment :D
Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35439 )
Change subject: sb/intel/ibexpeak: Add CIR initialization ......................................................................
Patch Set 1:
Patch Set 1:
Patch Set 1: Code-Review-2
Seems to have boot problems. Need to investigate...
Suggestion: printk() between every assignment :D
It does not hang here, but somewhere in ramstage or in the payload. Sometimes it does boot but resume from s3 does not work.
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35439 )
Change subject: sb/intel/ibexpeak: Add CIR initialization ......................................................................
Patch Set 1: -Code-Review
(19 comments)
Here's some suggestions pulled out of intel magic, hope they help
https://review.coreboot.org/c/coreboot/+/35439/1/src/mainboard/lenovo/x201/r... File src/mainboard/lenovo/x201/romstage.c:
https://review.coreboot.org/c/coreboot/+/35439/1/src/mainboard/lenovo/x201/r... PS1, Line 69: 0x02060100 PRSTS, written as 0x3310 in lpc.c; my system has the same value. Not sure what the lpc code does with it, but it doesn't look like it's going to end like this
https://review.coreboot.org/c/coreboot/+/35439/1/src/southbridge/intel/ibexp... File src/southbridge/intel/ibexpeak/early_cir.c:
https://review.coreboot.org/c/coreboot/+/35439/1/src/southbridge/intel/ibexp... PS1, Line 30: CIR7 According to intel magic: Bitfield [3:0] should be 0xf
Unchecked fields: Value for [31:9] is 0x0 Value for [8:7] is 0x0 Value for [6:4] is 0x0
Should be fine.
https://review.coreboot.org/c/coreboot/+/35439/1/src/southbridge/intel/ibexp... PS1, Line 37: 0x3b09 My LPC device ID
https://review.coreboot.org/c/coreboot/+/35439/1/src/southbridge/intel/ibexp... PS1, Line 41: CIR6 According to intel magic: Bitfield [23:21] should be 0x3 Bitfield [7] should be 0x0
Unchecked fields: Value for [31:24] is 0x13 Value for [20:8] is 0x830 Value for [6:0] is 0x40
https://review.coreboot.org/c/coreboot/+/35439/1/src/southbridge/intel/ibexp... PS1, Line 48: pci_write_config8(PCH_LPC_DEV, CIR4, 0x45); OK
https://review.coreboot.org/c/coreboot/+/35439/1/src/southbridge/intel/ibexp... PS1, Line 50: RCBA32(CIR8) = 0x4000000; OK
https://review.coreboot.org/c/coreboot/+/35439/1/src/southbridge/intel/ibexp... PS1, Line 51: PMIR According to intel magic: Bitfield [31:30] should be 0x3 (for production machines) Bitfield [29:21] should be 0x0 Bitfield [20] should be 0x0 Bitfield [19:0] should be 0x00300
Side note: Bitfield [31:30] is related to the Management Engine. Its default value of 0x0 is used in debug environments.
https://review.coreboot.org/c/coreboot/+/35439/1/src/southbridge/intel/ibexp... PS1, Line 52: RCBA32(0x3318) = 0x1020000; /* undocumented */ According to intel magic, the value is correct
https://review.coreboot.org/c/coreboot/+/35439/1/src/southbridge/intel/ibexp... PS1, Line 58: 0x7f8fdf80 Intel magic suggests 0x7F8F9F80 instead
https://review.coreboot.org/c/coreboot/+/35439/1/src/southbridge/intel/ibexp... PS1, Line 59: /* Does not match EDS */ I don't think anybody tested Lynnfield/Clarksfield hardware. I would use the EDS value.
Is it me, or does this look similar to CIR17 but for another kind of CPU?
https://review.coreboot.org/c/coreboot/+/35439/1/src/southbridge/intel/ibexp... PS1, Line 62: 0x6002000 Intel magic suggests 0x2000 instead
https://review.coreboot.org/c/coreboot/+/35439/1/src/southbridge/intel/ibexp... PS1, Line 68: c.x86_model == 0x25 My CPU model (i3-370M)
https://review.coreboot.org/c/coreboot/+/35439/1/src/southbridge/intel/ibexp... PS1, Line 70: RCBA32(CIR10) = 0xfffff; According to intel magic: CIR10 Field 1 — R/W. BIOS must program this field to 00000000h for Lynnfield/Clarksfield-based systems and 000FFF80h for Havendale/Auburndale-based systems.
My system doesn't seem to program any value here (default 0x0)
https://review.coreboot.org/c/coreboot/+/35439/1/src/southbridge/intel/ibexp... PS1, Line 71: RCBA32(CIR15) = 0x7f8fdfff; Intel magic suggests 0x7F8F9FFF instead
https://review.coreboot.org/c/coreboot/+/35439/1/src/southbridge/intel/ibexp... PS1, Line 72: RCBA32(CIR17) = 0x3900; Intel magic suggests 0x2900 instead, but my system has 0x3900
https://review.coreboot.org/c/coreboot/+/35439/1/src/southbridge/intel/ibexp... PS1, Line 73: RCBA32(CIR19) = 0x10000; Intel magic suggests 0x10001 instead, but my system has 0x10000
https://review.coreboot.org/c/coreboot/+/35439/1/src/southbridge/intel/ibexp... PS1, Line 74: RCBA32(CIR20) = 0x1004b; OK
https://review.coreboot.org/c/coreboot/+/35439/1/src/southbridge/intel/ibexp... PS1, Line 75: RCBA32(CIR21) = 0x6000008; Intel magic says this value on my system is correct, but other intel magic suggests 0x0000008
https://review.coreboot.org/c/coreboot/+/35439/1/src/southbridge/intel/ibexp... PS1, Line 79: RCBA32(CIR22) = 0x10000; OK
Hello Alexander Couzens, Patrick Rudolph, Angel Pons, build bot (Jenkins), Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/35439
to look at the new patch set (#2).
Change subject: sb/intel/ibexpeak: Add CIR initialization ......................................................................
sb/intel/ibexpeak: Add CIR initialization
This properly the chipset initialization registers.
The information is taken from the EDS and from the thinkpad x201 vendor BIOS disassembly and from an HP UEFI.
TESTED on Thinkpad X201: still boots fine.
Change-Id: I21c2beaf70da27dbe6a56e2612df2c257c05fc62 Signed-off-by: Arthur Heymans arthur@aheymans.xyz --- M src/mainboard/lenovo/x201/romstage.c M src/mainboard/packardbell/ms2290/romstage.c M src/southbridge/intel/ibexpeak/Makefile.inc A src/southbridge/intel/ibexpeak/early_cir.c M src/southbridge/intel/ibexpeak/pch.h 5 files changed, 121 insertions(+), 34 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/39/35439/2
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35439 )
Change subject: sb/intel/ibexpeak: Add CIR initialization ......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/c/coreboot/+/35439/2/src/southbridge/intel/ibexp... File src/southbridge/intel/ibexpeak/early_cir.c:
https://review.coreboot.org/c/coreboot/+/35439/2/src/southbridge/intel/ibexp... PS2, Line 54: RCBA32_OR(0x3310,0x31); space required after that ',' (ctx:VxV)
Hello Alexander Couzens, Patrick Rudolph, Angel Pons, build bot (Jenkins), Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/35439
to look at the new patch set (#3).
Change subject: sb/intel/ibexpeak: Add CIR initialization ......................................................................
sb/intel/ibexpeak: Add CIR initialization
This properly the chipset initialization registers.
The information is taken from the EDS and from the thinkpad x201 vendor BIOS disassembly and from an HP UEFI.
TESTED on Thinkpad X201: still boots fine.
Change-Id: I21c2beaf70da27dbe6a56e2612df2c257c05fc62 Signed-off-by: Arthur Heymans arthur@aheymans.xyz --- M src/mainboard/lenovo/x201/romstage.c M src/mainboard/packardbell/ms2290/romstage.c M src/southbridge/intel/ibexpeak/Makefile.inc A src/southbridge/intel/ibexpeak/early_cir.c M src/southbridge/intel/ibexpeak/pch.h 5 files changed, 121 insertions(+), 34 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/39/35439/3
Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35439 )
Change subject: sb/intel/ibexpeak: Add CIR initialization ......................................................................
Patch Set 3: Code-Review-1
Still seems to inconsistently hang during GPU init...
Hello Alexander Couzens, Patrick Rudolph, Angel Pons, build bot (Jenkins), Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/35439
to look at the new patch set (#4).
Change subject: sb/intel/ibexpeak: Add CIR initialization ......................................................................
sb/intel/ibexpeak: Add CIR initialization
This properly the chipset initialization registers.
The information is taken from the EDS and from the thinkpad x201 vendor BIOS disassembly and from an HP UEFI.
TESTED on Thinkpad X201. Seems stable at booting, rebooting and resume from S3.
Change-Id: I21c2beaf70da27dbe6a56e2612df2c257c05fc62 Signed-off-by: Arthur Heymans arthur@aheymans.xyz --- M src/mainboard/lenovo/x201/romstage.c M src/mainboard/packardbell/ms2290/romstage.c M src/southbridge/intel/ibexpeak/Makefile.inc A src/southbridge/intel/ibexpeak/early_cir.c M src/southbridge/intel/ibexpeak/pch.h 5 files changed, 121 insertions(+), 34 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/39/35439/4
Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35439 )
Change subject: sb/intel/ibexpeak: Add CIR initialization ......................................................................
Patch Set 4:
(7 comments)
Nice stuff.
https://review.coreboot.org/c/coreboot/+/35439/4//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/35439/4//COMMIT_MSG@9 PS4, Line 9: This properly the chipset initialization registers. Missing verb: sets?
https://review.coreboot.org/c/coreboot/+/35439/4//COMMIT_MSG@15 PS4, Line 15: from S3. Can you please summarize what changed, or what the benefits are?
https://review.coreboot.org/c/coreboot/+/35439/4/src/southbridge/intel/ibexp... File src/southbridge/intel/ibexpeak/early_cir.c:
https://review.coreboot.org/c/coreboot/+/35439/4/src/southbridge/intel/ibexp... PS4, Line 21: set sets
https://review.coreboot.org/c/coreboot/+/35439/4/src/southbridge/intel/ibexp... PS4, Line 25: registers Registers? Also add (CIR) to the line?
https://review.coreboot.org/c/coreboot/+/35439/4/src/southbridge/intel/ibexp... PS4, Line 56: if (chipset_type == NEHALEM_DESKTOP) Add a comment with a datasheet section reference?
https://review.coreboot.org/c/coreboot/+/35439/4/src/southbridge/intel/ibexp... PS4, Line 85: die("unsupported CPU!\n"); Print out the model?
https://review.coreboot.org/c/coreboot/+/35439/4/src/southbridge/intel/ibexp... PS4, Line 90: */ Please use one of the recommended comment styles.
Hello Alexander Couzens, Patrick Rudolph, Angel Pons, build bot (Jenkins), Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/35439
to look at the new patch set (#5).
Change subject: sb/intel/ibexpeak: Add CIR initialization ......................................................................
sb/intel/ibexpeak: Add CIR initialization
This properly the chipset initialization registers.
The information is taken from the EDS and from the thinkpad x201 vendor BIOS disassembly and from an HP UEFI.
TESTED on Thinkpad X201. Seems stable at booting, rebooting and resume from S3.
Change-Id: I21c2beaf70da27dbe6a56e2612df2c257c05fc62 Signed-off-by: Arthur Heymans arthur@aheymans.xyz --- M src/mainboard/lenovo/x201/romstage.c M src/mainboard/packardbell/ms2290/romstage.c M src/southbridge/intel/ibexpeak/Makefile.inc A src/southbridge/intel/ibexpeak/early_cir.c M src/southbridge/intel/ibexpeak/pch.h 5 files changed, 121 insertions(+), 34 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/39/35439/5
Hello Alexander Couzens, Patrick Rudolph, Angel Pons, build bot (Jenkins), Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/35439
to look at the new patch set (#6).
Change subject: sb/intel/ibexpeak: Add CIR initialization ......................................................................
sb/intel/ibexpeak: Add CIR initialization
This properly the chipset initialization registers.
The information is taken from the EDS and from the thinkpad x201 vendor BIOS disassembly and from an HP UEFI.
TESTED on Thinkpad X201. Seems stable at booting, rebooting and resume from S3.
Change-Id: I21c2beaf70da27dbe6a56e2612df2c257c05fc62 Signed-off-by: Arthur Heymans arthur@aheymans.xyz --- M src/mainboard/lenovo/x201/romstage.c M src/mainboard/packardbell/ms2290/romstage.c M src/southbridge/intel/ibexpeak/Makefile.inc A src/southbridge/intel/ibexpeak/early_cir.c M src/southbridge/intel/ibexpeak/pch.h 5 files changed, 120 insertions(+), 34 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/39/35439/6
Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35439 )
Change subject: sb/intel/ibexpeak: Add CIR initialization ......................................................................
Patch Set 6:
(10 comments)
https://review.coreboot.org/c/coreboot/+/35439/1/src/southbridge/intel/ibexp... File src/southbridge/intel/ibexpeak/early_cir.c:
https://review.coreboot.org/c/coreboot/+/35439/1/src/southbridge/intel/ibexp... PS1, Line 41: CIR6
According to intel magic: […]
Done, however lpc.c l320 does touch this too :/ It seems to work now.
https://review.coreboot.org/c/coreboot/+/35439/1/src/southbridge/intel/ibexp... PS1, Line 51: PMIR
According to intel magic: […]
Ack
https://review.coreboot.org/c/coreboot/+/35439/1/src/southbridge/intel/ibexp... PS1, Line 58: 0x7f8fdf80
Intel magic suggests 0x7F8F9F80 instead
That's the EDS value. I'll use that.
https://review.coreboot.org/c/coreboot/+/35439/1/src/southbridge/intel/ibexp... PS1, Line 59: /* Does not match EDS */
I don't think anybody tested Lynnfield/Clarksfield hardware. I would use the EDS value. […]
Ack
https://review.coreboot.org/c/coreboot/+/35439/1/src/southbridge/intel/ibexp... PS1, Line 62: 0x6002000
Intel magic suggests 0x2000 instead
Ack
https://review.coreboot.org/c/coreboot/+/35439/1/src/southbridge/intel/ibexp... PS1, Line 70: RCBA32(CIR10) = 0xfffff;
According to intel magic: […]
Ack
https://review.coreboot.org/c/coreboot/+/35439/1/src/southbridge/intel/ibexp... PS1, Line 71: RCBA32(CIR15) = 0x7f8fdfff;
Intel magic suggests 0x7F8F9FFF instead
Ack
https://review.coreboot.org/c/coreboot/+/35439/1/src/southbridge/intel/ibexp... PS1, Line 72: RCBA32(CIR17) = 0x3900;
Intel magic suggests 0x2900 instead, but my system has 0x3900
Ack
https://review.coreboot.org/c/coreboot/+/35439/1/src/southbridge/intel/ibexp... PS1, Line 73: RCBA32(CIR19) = 0x10000;
Intel magic suggests 0x10001 instead, but my system has 0x10000
Ack
https://review.coreboot.org/c/coreboot/+/35439/1/src/southbridge/intel/ibexp... PS1, Line 75: RCBA32(CIR21) = 0x6000008;
Intel magic says this value on my system is correct, but other intel magic suggests 0x0000008
Ack
Hello Alexander Couzens, Patrick Rudolph, Angel Pons, build bot (Jenkins), Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/35439
to look at the new patch set (#7).
Change subject: sb/intel/ibexpeak: Add CIR initialization ......................................................................
sb/intel/ibexpeak: Add CIR initialization
This properly the chipset initialization registers.
The information is taken from the EDS and from the thinkpad x201 vendor BIOS disassembly and from an HP UEFI.
TESTED on Thinkpad X201. Seems stable at booting, rebooting and resume from S3.
Change-Id: I21c2beaf70da27dbe6a56e2612df2c257c05fc62 Signed-off-by: Arthur Heymans arthur@aheymans.xyz --- M src/mainboard/lenovo/x201/romstage.c M src/mainboard/packardbell/ms2290/romstage.c M src/southbridge/intel/ibexpeak/Makefile.inc A src/southbridge/intel/ibexpeak/early_cir.c M src/southbridge/intel/ibexpeak/pch.h 5 files changed, 120 insertions(+), 34 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/39/35439/7
Hello Alexander Couzens, Patrick Rudolph, Angel Pons, build bot (Jenkins), Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/35439
to look at the new patch set (#8).
Change subject: sb/intel/ibexpeak: Add CIR initialization ......................................................................
sb/intel/ibexpeak: Add CIR initialization
This properly sets up the chipset initialization registers, instead of replaying an RCBA dump.
The information is taken from the EDS and from the thinkpad x201 vendor BIOS disassembly and from an HP UEFI.
TESTED on Thinkpad X201. Seems stable at booting, rebooting and resume from S3.
Change-Id: I21c2beaf70da27dbe6a56e2612df2c257c05fc62 Signed-off-by: Arthur Heymans arthur@aheymans.xyz --- M src/mainboard/lenovo/x201/romstage.c M src/mainboard/packardbell/ms2290/romstage.c M src/southbridge/intel/ibexpeak/Makefile.inc A src/southbridge/intel/ibexpeak/early_cir.c M src/southbridge/intel/ibexpeak/pch.h 5 files changed, 120 insertions(+), 34 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/39/35439/8
Patrick Georgi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35439 )
Change subject: sb/intel/ibexpeak: Add CIR initialization ......................................................................
Patch Set 8:
(8 comments)
https://review.coreboot.org/c/coreboot/+/35439/4//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/35439/4//COMMIT_MSG@9 PS4, Line 9: This properly the chipset initialization registers.
Missing verb: sets?
Done
https://review.coreboot.org/c/coreboot/+/35439/4//COMMIT_MSG@15 PS4, Line 15: from S3.
Can you please summarize what changed, or what the benefits are?
Done
https://review.coreboot.org/c/coreboot/+/35439/1/src/southbridge/intel/ibexp... File src/southbridge/intel/ibexpeak/early_cir.c:
https://review.coreboot.org/c/coreboot/+/35439/1/src/southbridge/intel/ibexp... PS1, Line 21: set
sets
Done
https://review.coreboot.org/c/coreboot/+/35439/4/src/southbridge/intel/ibexp... File src/southbridge/intel/ibexpeak/early_cir.c:
https://review.coreboot.org/c/coreboot/+/35439/4/src/southbridge/intel/ibexp... PS4, Line 21: set
sets
Done
https://review.coreboot.org/c/coreboot/+/35439/4/src/southbridge/intel/ibexp... PS4, Line 25: registers
Registers? Also add (CIR) to the line?
Done
https://review.coreboot.org/c/coreboot/+/35439/4/src/southbridge/intel/ibexp... PS4, Line 56: if (chipset_type == NEHALEM_DESKTOP)
Add a comment with a datasheet section reference?
Done
https://review.coreboot.org/c/coreboot/+/35439/4/src/southbridge/intel/ibexp... PS4, Line 85: die("unsupported CPU!\n");
Print out the model?
Done
https://review.coreboot.org/c/coreboot/+/35439/4/src/southbridge/intel/ibexp... PS4, Line 90: */
Please use one of the recommended comment styles.
Done
Patrick Georgi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35439 )
Change subject: sb/intel/ibexpeak: Add CIR initialization ......................................................................
Patch Set 8:
(1 comment)
https://review.coreboot.org/c/coreboot/+/35439/1/src/mainboard/lenovo/x201/r... File src/mainboard/lenovo/x201/romstage.c:
https://review.coreboot.org/c/coreboot/+/35439/1/src/mainboard/lenovo/x201/r... PS1, Line 69: 0x02060100
PRSTS, written as 0x3310 in lpc.c; my system has the same value. […]
since this is still open (and no change in the latest patch set): what do you mean by this and what is Arthur supposed to do? :-)
Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35439 )
Change subject: sb/intel/ibexpeak: Add CIR initialization ......................................................................
Patch Set 8:
(14 comments)
https://review.coreboot.org/c/coreboot/+/35439/4//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/35439/4//COMMIT_MSG@9 PS4, Line 9: This properly the chipset initialization registers.
Missing verb: sets?
Done
https://review.coreboot.org/c/coreboot/+/35439/4//COMMIT_MSG@15 PS4, Line 15: from S3.
Can you please summarize what changed, or what the benefits are?
Done
https://review.coreboot.org/c/coreboot/+/35439/1/src/mainboard/lenovo/x201/r... File src/mainboard/lenovo/x201/romstage.c:
https://review.coreboot.org/c/coreboot/+/35439/1/src/mainboard/lenovo/x201/r... PS1, Line 69: 0x02060100
since this is still open (and no change in the latest patch set): what do you mean by this and what is Arthur supposed to do? :-)
All the bits are read/ write to clear and clearing those is supposedly done in ramstage in pch_power_options().
https://review.coreboot.org/c/coreboot/+/35439/1/src/southbridge/intel/ibexp... File src/southbridge/intel/ibexpeak/early_cir.c:
https://review.coreboot.org/c/coreboot/+/35439/1/src/southbridge/intel/ibexp... PS1, Line 21: set
sets
Done
https://review.coreboot.org/c/coreboot/+/35439/1/src/southbridge/intel/ibexp... PS1, Line 30: CIR7
According to intel magic: […]
Done
https://review.coreboot.org/c/coreboot/+/35439/1/src/southbridge/intel/ibexp... PS1, Line 37: 0x3b09
My LPC device ID
Done
https://review.coreboot.org/c/coreboot/+/35439/1/src/southbridge/intel/ibexp... PS1, Line 41: CIR6
Done, however lpc.c l320 does touch this too :/ It seems to work now.
Done
https://review.coreboot.org/c/coreboot/+/35439/4/src/southbridge/intel/ibexp... File src/southbridge/intel/ibexpeak/early_cir.c:
https://review.coreboot.org/c/coreboot/+/35439/4/src/southbridge/intel/ibexp... PS4, Line 21: set
sets
Done
https://review.coreboot.org/c/coreboot/+/35439/4/src/southbridge/intel/ibexp... PS4, Line 25: registers
Registers? Also add (CIR) to the line?
Done
https://review.coreboot.org/c/coreboot/+/35439/4/src/southbridge/intel/ibexp... PS4, Line 56: if (chipset_type == NEHALEM_DESKTOP)
Add a comment with a datasheet section reference?
Done
https://review.coreboot.org/c/coreboot/+/35439/4/src/southbridge/intel/ibexp... PS4, Line 85: die("unsupported CPU!\n");
Print out the model?
Done
https://review.coreboot.org/c/coreboot/+/35439/4/src/southbridge/intel/ibexp... PS4, Line 90: */
Please use one of the recommended comment styles.
Done
https://review.coreboot.org/c/coreboot/+/35439/5/src/southbridge/intel/ibexp... File src/southbridge/intel/ibexpeak/early_cir.c:
https://review.coreboot.org/c/coreboot/+/35439/5/src/southbridge/intel/ibexp... PS5, Line 54: RCBA32_OR(0x3310,0x31);
space required after that ',' (ctx:VxV)
Done
https://review.coreboot.org/c/coreboot/+/35439/6/src/southbridge/intel/ibexp... File src/southbridge/intel/ibexpeak/early_cir.c:
https://review.coreboot.org/c/coreboot/+/35439/6/src/southbridge/intel/ibexp... PS6, Line 54: RCBA32_OR(0x3310,0x31);
space required after that ',' (ctx:VxV)
Done
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35439 )
Change subject: sb/intel/ibexpeak: Add CIR initialization ......................................................................
Patch Set 8:
(1 comment)
https://review.coreboot.org/c/coreboot/+/35439/1/src/mainboard/lenovo/x201/r... File src/mainboard/lenovo/x201/romstage.c:
https://review.coreboot.org/c/coreboot/+/35439/1/src/mainboard/lenovo/x201/r... PS1, Line 69: 0x02060100
since this is still open (and no change in the latest patch set): what do you mean by this and wha […]
I don't know what I meant with this comment. I probably felt like documenting all the registers in RCBA, but I gave up rather soon... Sorry for the noise.
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35439 )
Change subject: sb/intel/ibexpeak: Add CIR initialization ......................................................................
Patch Set 8: Code-Review+2
Looks great, thanks for doing this! (I loathe those RCBA register dumps)
Arthur Heymans has submitted this change. ( https://review.coreboot.org/c/coreboot/+/35439 )
Change subject: sb/intel/ibexpeak: Add CIR initialization ......................................................................
sb/intel/ibexpeak: Add CIR initialization
This properly sets up the chipset initialization registers, instead of replaying an RCBA dump.
The information is taken from the EDS and from the thinkpad x201 vendor BIOS disassembly and from an HP UEFI.
TESTED on Thinkpad X201. Seems stable at booting, rebooting and resume from S3.
Change-Id: I21c2beaf70da27dbe6a56e2612df2c257c05fc62 Signed-off-by: Arthur Heymans arthur@aheymans.xyz Reviewed-on: https://review.coreboot.org/c/coreboot/+/35439 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Angel Pons th3fanbus@gmail.com --- M src/mainboard/lenovo/x201/romstage.c M src/mainboard/packardbell/ms2290/romstage.c M src/southbridge/intel/ibexpeak/Makefile.inc A src/southbridge/intel/ibexpeak/early_cir.c M src/southbridge/intel/ibexpeak/pch.h 5 files changed, 120 insertions(+), 34 deletions(-)
Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, approved
diff --git a/src/mainboard/lenovo/x201/romstage.c b/src/mainboard/lenovo/x201/romstage.c index 3a06a8c..9d98637 100644 --- a/src/mainboard/lenovo/x201/romstage.c +++ b/src/mainboard/lenovo/x201/romstage.c @@ -66,21 +66,6 @@ southbridge_configure_default_intmap();
static const u32 rcba_dump3[] = { - /* 3310 */ 0x02060100, 0x0000000f, 0x01020000, 0x80000000, - /* 3320 */ 0x00000000, 0x04000000, 0x00000000, 0x00000000, - /* 3330 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, - /* 3340 */ 0x000fffff, 0x00000000, 0x00000000, 0x00000000, - /* 3350 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, - /* 3360 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, - /* 3370 */ 0x00000000, 0x00000000, 0x7f8fdfff, 0x00000000, - /* 3380 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, - /* 3390 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, - /* 33a0 */ 0x00003900, 0x00000000, 0x00000000, 0x00000000, - /* 33b0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, - /* 33c0 */ 0x00010000, 0x00000000, 0x00000000, 0x0001004b, - /* 33d0 */ 0x06000008, 0x00010000, 0x00000000, 0x00000000, - /* 33e0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, - /* 33f0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, /* 3400 */ 0x0000001c, 0x00000080, 0x00000000, 0x00000000, /* 3410 */ 0x00000c61, 0x00000000, 0x16e41fe1, 0xbf4f001f, /* 3420 */ 0x00000000, 0x00060010, 0x0000001d, 0x00000000, @@ -135,8 +120,8 @@ }; unsigned i; for (i = 0; i < sizeof(rcba_dump3) / 4; i++) { - RCBA32(4 * i + 0x3310) = rcba_dump3[i]; - (void)RCBA32(4 * i + 0x3310); + RCBA32(4 * i + 0x3400) = rcba_dump3[i]; + (void)RCBA32(4 * i + 0x3400); } }
@@ -186,6 +171,8 @@
setup_pch_gpios(&mainboard_gpio_map);
+ pch_setup_cir(NEHALEM_MOBILE); +
/* This should probably go away. Until now it is required * and mainboard specific diff --git a/src/mainboard/packardbell/ms2290/romstage.c b/src/mainboard/packardbell/ms2290/romstage.c index 5a4a9f1..a426d89 100644 --- a/src/mainboard/packardbell/ms2290/romstage.c +++ b/src/mainboard/packardbell/ms2290/romstage.c @@ -61,21 +61,6 @@ southbridge_configure_default_intmap();
static const u32 rcba_dump3[] = { - /* 3310 */ 0x02060100, 0x0000000f, 0x01020000, 0x80000000, - /* 3320 */ 0x00000000, 0x04000000, 0x00000000, 0x00000000, - /* 3330 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, - /* 3340 */ 0x000fffff, 0x00000000, 0x00000000, 0x00000000, - /* 3350 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, - /* 3360 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, - /* 3370 */ 0x00000000, 0x00000000, 0x7f8fdfff, 0x00000000, - /* 3380 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, - /* 3390 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, - /* 33a0 */ 0x00003900, 0x00000000, 0x00000000, 0x00000000, - /* 33b0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, - /* 33c0 */ 0x00010000, 0x00000000, 0x00000000, 0x0001004b, - /* 33d0 */ 0x06000008, 0x00010000, 0x00000000, 0x00000000, - /* 33e0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, - /* 33f0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, /* 3400 */ 0x0000001c, 0x00000080, 0x00000000, 0x00000000, /* 3410 */ 0x00000c61, 0x00000000, 0x16fc1fe1, 0xbf4f001f, /* 3420 */ 0x00000000, 0x00060010, 0x0000001d, 0x00000000, @@ -131,8 +116,8 @@ unsigned i;
for (i = 0; i < sizeof(rcba_dump3) / 4; i++) { - RCBA32(4 * i + 0x3310) = rcba_dump3[i]; - (void)RCBA32(4 * i + 0x3310); + RCBA32(4 * i + 0x3400) = rcba_dump3[i]; + (void)RCBA32(4 * i + 0x3400); } }
@@ -181,6 +166,8 @@
setup_pch_gpios(&mainboard_gpio_map);
+ pch_setup_cir(NEHALEM_MOBILE); + /* This should probably go away. Until now it is required * and mainboard specific */ diff --git a/src/southbridge/intel/ibexpeak/Makefile.inc b/src/southbridge/intel/ibexpeak/Makefile.inc index 83d083f..97565d6 100644 --- a/src/southbridge/intel/ibexpeak/Makefile.inc +++ b/src/southbridge/intel/ibexpeak/Makefile.inc @@ -42,5 +42,6 @@ romstage-y +=../bd82x6x/me_status.c romstage-y += early_thermal.c romstage-y += ../bd82x6x/early_rcba.c +romstage-y += early_cir.c
endif diff --git a/src/southbridge/intel/ibexpeak/early_cir.c b/src/southbridge/intel/ibexpeak/early_cir.c new file mode 100644 index 0000000..0048235 --- /dev/null +++ b/src/southbridge/intel/ibexpeak/early_cir.c @@ -0,0 +1,92 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <console/console.h> +#include <cpu/cpu.h> +#include <device/pci_ops.h> +#include <device/pci_def.h> +#include <northbridge/intel/nehalem/nehalem.h> +#include "pch.h" + +/* This sets up magic Chipset Initialization Registers */ +void pch_setup_cir(int chipset_type) +{ + printk(BIOS_DEBUG, "Setting up Chipset Initialization Registers (CIR)\n"); + + uint16_t lpc_id = pci_read_config16(PCH_LPC_DEV, PCI_DEVICE_ID); + struct cpuinfo_x86 c; + uint32_t cir22; + + pci_or_config8(PCH_LPC_DEV, GEN_PMCON_3, 0xfb); + + RCBA32_OR(GCS, 0x40); /* FERR# MUX enable */ + + RCBA8(0x3430) |= 0xfc; + + RCBA32(CIR7) = 0xf; + + RCBA32(CIR9) = 0; + + switch (lpc_id) { + case 0x3b01: + case 0x3b03: + case 0x3b05: + case 0x3b07: + case 0x3b09: + case 0x3b0b: + case 0x3b0d: + case 0x3b0f: + RCBA32_AND_OR(CIR6, 0xff1fff7f, 0x600000); + break; + } + + RCBA32_OR(0x3310, 0x31); + + /* Intel 5 Series Chipset and Intel 3400 Series Chipset + External Design Specification (EDS) 13.8.1.1 */ + if (chipset_type == NEHALEM_DESKTOP) + pci_or_config32(PCH_LPC_DEV, GEN_PMCON_1, 1 << 3); + + pci_write_config8(PCH_LPC_DEV, CIR4, 0x45); + + RCBA32(CIR8) = 0x4000000; + pci_write_config32(PCH_LPC_DEV, PMIR, 0xc0000300); + RCBA32(0x3318) = 0x1020000; /* undocumented */ + get_fms(&c, cpuid_eax(1)); + if (c.x86_model == 0x1e) { + /* Lynnfield/Clarksfield */ + RCBA32(CIR13) = 0xfffff; + RCBA32(CIR14) = 0x61080; + RCBA32(CIR16) = 0x7f8f9f80; + RCBA32(CIR18) = 0x3900; + RCBA32(CIR19) = 0x20002; + RCBA32(CIR20) = 0x44b00; + RCBA32(CIR21) = 0x02000; + cir22 = 0x20000; + } else if (c.x86_model == 0x1f || c.x86_model == 0x25) { + /* Auburndale/Havendale + Arrandale/Clarkdale */ + RCBA32(CIR10) = 0xfff80; + RCBA32(CIR15) = 0x7f8f9fff; + RCBA32(CIR17) = 0x2900; + RCBA32(CIR19) = 0x10001; + RCBA32(CIR20) = 0x1004b; + RCBA32(CIR21) = 0x8; + cir22 = 0x10000; + } else { + die("unsupported CPU model: %x!\n", c.x86_model); + } + + /* EDS, 10.1.77: Program this register after all registers in the + 3330-33D3 range and D31:F0:A9h are already programmed */ + RCBA32(CIR22) = cir22; +} diff --git a/src/southbridge/intel/ibexpeak/pch.h b/src/southbridge/intel/ibexpeak/pch.h index f7b2929..f0e469a 100644 --- a/src/southbridge/intel/ibexpeak/pch.h +++ b/src/southbridge/intel/ibexpeak/pch.h @@ -67,6 +67,7 @@
void early_thermal_init(void); void southbridge_configure_default_intmap(void); +void pch_setup_cir(int chipset_type);
#ifndef __ROMCC__ #include <device/device.h> @@ -100,6 +101,9 @@ #define ETR3_CWORWRE (1 << 18) #define ETR3_CF9GR (1 << 20)
+#define CIR4 0xa9 +#define PMIR 0xac + /* GEN_PMCON_3 bits */ #define RTC_BATTERY_DEAD (1 << 2) #define RTC_POWER_FAILED (1 << 1) @@ -349,6 +353,21 @@ #define SOFT_RESET_DATA 0x38f8
#define PRSTS 0x3310 +#define CIR6 0x2024 +#define CIR7 0x3314 +#define CIR8 0x3324 +#define CIR9 0x3330 +#define CIR10 0x3340 +#define CIR13 0x3350 +#define CIR14 0x3368 +#define CIR15 0x3378 +#define CIR16 0x3388 +#define CIR17 0x33a0 +#define CIR18 0x33a8 +#define CIR19 0x33c0 +#define CIR20 0x33cc +#define CIR21 0x33d0 +#define CIR22 0x33d4
#define DIR_ROUTE(x,a,b,c,d) \ RCBA32(x) = (((d) << DIR_IDR) | ((c) << DIR_ICR) | \
-
Angel Pons (Code Review) -
Arthur Heymans (Code Review)
-
build bot (Jenkins) (Code Review)
-
Patrick Georgi (Code Review)
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Paul Menzel (Code Review)