14 comments:
Patch Set #4, Line 9: This properly the chipset initialization registers.
Missing verb: sets?
Done
Patch Set #4, Line 15: from S3.
Can you please summarize what changed, or what the benefits are?
Done
File src/mainboard/lenovo/x201/romstage.c:
Patch Set #1, Line 69: 0x02060100
since this is still open (and no change in the latest patch set): what do you mean by this and what is Arthur supposed to do? :-)
All the bits are read/ write to clear and clearing those is supposedly done in ramstage in pch_power_options().
File src/southbridge/intel/ibexpeak/early_cir.c:
sets
Done
According to intel magic: […]
Done
Patch Set #1, Line 37: 0x3b09
My LPC device ID
Done
Done, however lpc.c l320 does touch this too :/ It seems to work now.
Done
File src/southbridge/intel/ibexpeak/early_cir.c:
sets
Done
Patch Set #4, Line 25: registers
Registers? Also add (CIR) to the line?
Done
Patch Set #4, Line 56: if (chipset_type == NEHALEM_DESKTOP)
Add a comment with a datasheet section reference?
Done
Patch Set #4, Line 85: die("unsupported CPU!\n");
Print out the model?
Done
Please use one of the recommended comment styles.
Done
File src/southbridge/intel/ibexpeak/early_cir.c:
Patch Set #5, Line 54: RCBA32_OR(0x3310,0x31);
space required after that ',' (ctx:VxV)
Done
File src/southbridge/intel/ibexpeak/early_cir.c:
Patch Set #6, Line 54: RCBA32_OR(0x3310,0x31);
space required after that ',' (ctx:VxV)
Done
To view, visit change 35439. To unsubscribe, or for help writing mail filters, visit settings.