Change in coreboot[master]: soc/amd/picasso: Add controls for SMT and downcoring

[Marshall Dawson (Code Review)]

Marshall Dawson has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43299 )

Change subject: soc/amd/picasso: Add controls for SMT and downcoring
......................................................................

soc/amd/picasso: Add controls for SMT and downcoring

BUG=b:159198385
TEST=confirm both using Mandolin

Signed-off-by: Marshall Dawson 
Change-Id: I91654817608ab62e4104959b8876333911b90175
---
M src/soc/amd/picasso/chip.h
M src/soc/amd/picasso/romstage.c
2 files changed, 13 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/99/43299/1

diff --git a/src/soc/amd/picasso/chip.h b/src/soc/amd/picasso/chip.h
index 1dbe3d9..54e18af 100644
--- a/src/soc/amd/picasso/chip.h
+++ b/src/soc/amd/picasso/chip.h
@@ -38,6 +38,13 @@
    uint8_t	tx_res_tune;
 };

+enum downcore_modes {
+	DOWNCORE_AUTO = 0,
+	DOWNCORE_1 = 1, /* Run with single core */
+	DOWNCORE_2 = 3, /* Run with two cores */
+	DOWNCORE_3 = 4, /* Run with three cores */
+};
+
 struct soc_amd_picasso_config {
    struct soc_amd_common_config common_config;
    /*
@@ -91,6 +98,9 @@
    /* PROCHOT_L de-assertion Ramp Time */
    uint32_t prochot_l_deassertion_ramp_time;

+	uint8_t downcore_mode;
+	uint8_t smt_disable;
+
    /* Lower die temperature limit */
    uint32_t thermctl_limit;

diff --git a/src/soc/amd/picasso/romstage.c b/src/soc/amd/picasso/romstage.c
index 7d086fe..6acee50 100644
--- a/src/soc/amd/picasso/romstage.c
+++ b/src/soc/amd/picasso/romstage.c
@@ -51,6 +51,9 @@
    	mcfg->stapm_time_constant = config->stapm_time_constant;
    }

+	mcfg->ccx_down_core_mode = config->downcore_mode;
+	mcfg->ccx_disable_smt = config->smt_disable;
+
    mcfg->sustained_power_limit = config->sustained_power_limit;
    mcfg->prochot_l_deassertion_ramp_time = config->prochot_l_deassertion_ramp_time;
    mcfg->thermctl_limit = config->thermctl_limit;

[Furquan Shaikh (Code Review)]

Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43299 )

Change subject: soc/amd/picasso: Add controls for SMT and downcoring
......................................................................

Patch Set 1:

(2 comments)

https://review.coreboot.org/c/coreboot/+/43299/1/src/soc/amd/picasso/chip.h 
File src/soc/amd/picasso/chip.h:

https://review.coreboot.org/c/coreboot/+/43299/1/src/soc/amd/picasso/chip.h@... 
PS1, Line 101: downcore_mode
Add a comment that this uses values from enum downcore modes? Or probably just use:

enum {
    DOWNCORE_AUTO = 0,
    DOWNCORE_1 = 1, /* Run with single core */
    DOWNCORE_2 = 3, /* Run with two cores */
    DOWNCORE_3 = 4, /* Run with three cores */
} downcore_mode;

https://review.coreboot.org/c/coreboot/+/43299/1/src/soc/amd/picasso/chip.h@... 
PS1, Line 102: smt_disable
From the name, I am guessing this just takes 0/1?

[Marshall Dawson (Code Review)]

Hello build bot (Jenkins), Raul Rangel, Furquan Shaikh, Felix Held,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/43299

to look at the new patch set (#2).

Change subject: soc/amd/picasso: Add controls for SMT and downcoring
......................................................................

soc/amd/picasso: Add controls for SMT and downcoring

BUG=b:159198385
TEST=confirm both using Mandolin

Signed-off-by: Marshall Dawson 
Change-Id: I91654817608ab62e4104959b8876333911b90175
---
M src/soc/amd/picasso/chip.h
M src/soc/amd/picasso/romstage.c
2 files changed, 11 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/99/43299/2

[Marshall Dawson (Code Review)]

Hello build bot (Jenkins), Raul Rangel, Furquan Shaikh, Felix Held,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/43299

to look at the new patch set (#3).

Change subject: soc/amd/picasso: Add controls for SMT and downcoring
......................................................................

soc/amd/picasso: Add controls for SMT and downcoring

BUG=b:159198385
TEST=confirm both using Mandolin

Signed-off-by: Marshall Dawson 
Change-Id: I91654817608ab62e4104959b8876333911b90175
---
M src/soc/amd/picasso/chip.h
M src/soc/amd/picasso/romstage.c
2 files changed, 11 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/99/43299/3

[Marshall Dawson (Code Review)]

Marshall Dawson has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43299 )

Change subject: soc/amd/picasso: Add controls for SMT and downcoring
......................................................................

Patch Set 3:

(2 comments)

https://review.coreboot.org/c/coreboot/+/43299/1/src/soc/amd/picasso/chip.h 
File src/soc/amd/picasso/chip.h:

https://review.coreboot.org/c/coreboot/+/43299/1/src/soc/amd/picasso/chip.h@... 
PS1, Line 101: downcore_mode
> Add a comment that this uses values from enum downcore modes? Or probably just use: […]

Done

https://review.coreboot.org/c/coreboot/+/43299/1/src/soc/amd/picasso/chip.h@... 
PS1, Line 102: smt_disable
> From the name, I am guessing this just takes 0/1?

Done

[Felix Held (Code Review)]

Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43299 )

Change subject: soc/amd/picasso: Add controls for SMT and downcoring
......................................................................

Patch Set 3: Code-Review+2

(1 comment)

https://review.coreboot.org/c/coreboot/+/43299/1/src/soc/amd/picasso/chip.h 
File src/soc/amd/picasso/chip.h:

https://review.coreboot.org/c/coreboot/+/43299/1/src/soc/amd/picasso/chip.h@... 
PS1, Line 101: downcore_mode
> Add a comment that this uses values from enum downcore modes? Or probably just use: […]

Done

[Furquan Shaikh (Code Review)]

Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43299 )

Change subject: soc/amd/picasso: Add controls for SMT and downcoring
......................................................................

Patch Set 3: Code-Review+2

[Marshall Dawson (Code Review)]

Marshall Dawson has submitted this change. ( https://review.coreboot.org/c/coreboot/+/43299 )

Change subject: soc/amd/picasso: Add controls for SMT and downcoring
......................................................................

soc/amd/picasso: Add controls for SMT and downcoring

BUG=b:159198385
TEST=confirm both using Mandolin

Signed-off-by: Marshall Dawson 
Change-Id: I91654817608ab62e4104959b8876333911b90175
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43299
Reviewed-by: Felix Held 
Reviewed-by: Furquan Shaikh 
Tested-by: build bot (Jenkins) 
---
M src/soc/amd/picasso/chip.h
M src/soc/amd/picasso/romstage.c
2 files changed, 11 insertions(+), 0 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Felix Held: Looks good to me, approved
  Furquan Shaikh: Looks good to me, approved

diff --git a/src/soc/amd/picasso/chip.h b/src/soc/amd/picasso/chip.h
index 62272c0..b641379 100644
--- a/src/soc/amd/picasso/chip.h
+++ b/src/soc/amd/picasso/chip.h
@@ -93,6 +93,14 @@
    /* PROCHOT_L de-assertion Ramp Time */
    uint32_t prochot_l_deassertion_ramp_time;

+	enum {
+		DOWNCORE_AUTO = 0,
+		DOWNCORE_1 = 1, /* Run with single core */
+		DOWNCORE_2 = 3, /* Run with two cores */
+		DOWNCORE_3 = 4, /* Run with three cores */
+	} downcore_mode;
+	uint8_t smt_disable; /* 1=disable SMT, 0=enable SMT */
+
    /* Lower die temperature limit */
    uint32_t thermctl_limit;

diff --git a/src/soc/amd/picasso/romstage.c b/src/soc/amd/picasso/romstage.c
index 372c6b5..e7b4b3d 100644
--- a/src/soc/amd/picasso/romstage.c
+++ b/src/soc/amd/picasso/romstage.c
@@ -43,6 +43,9 @@
    	mcfg->stapm_time_constant = config->stapm_time_constant;
    }

+	mcfg->ccx_down_core_mode = config->downcore_mode;
+	mcfg->ccx_disable_smt = config->smt_disable;
+
    mcfg->sustained_power_limit = config->sustained_power_limit;
    mcfg->prochot_l_deassertion_ramp_time = config->prochot_l_deassertion_ramp_time;
    mcfg->thermctl_limit = config->thermctl_limit;