Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48486 )
Change subject: soc/amd/picasso/reset: remove leftover PCI includes ......................................................................
soc/amd/picasso/reset: remove leftover PCI includes
On Stoneyridge some PCI registers were accessed, but on Picasso this is no longer the case.
Change-Id: Ifbf65f9724a14d4847af98930759c865453775b4 Signed-off-by: Felix Held felix-coreboot@felixheld.de --- M src/soc/amd/picasso/reset.c 1 file changed, 0 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/86/48486/1
diff --git a/src/soc/amd/picasso/reset.c b/src/soc/amd/picasso/reset.c index 7a0074c..dea166a 100644 --- a/src/soc/amd/picasso/reset.c +++ b/src/soc/amd/picasso/reset.c @@ -3,9 +3,7 @@ #include <arch/io.h> #include <console/console.h> #include <reset.h> -#include <soc/pci_devs.h> #include <soc/reset.h> -#include <device/pci_ops.h> #include <soc/southbridge.h> #include <amdblocks/acpimmio.h> #include <amdblocks/reset.h>
Hello build bot (Jenkins), Jason Glenesk, Marshall Dawson,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/48486
to look at the new patch set (#3).
Change subject: soc/amd/picasso/reset: remove leftover PCI includes ......................................................................
soc/amd/picasso/reset: remove leftover PCI includes
On Stoneyridge some PCI registers were accessed in this compilation unit, but on Picasso this is no longer the case.
Change-Id: Ifbf65f9724a14d4847af98930759c865453775b4 Signed-off-by: Felix Held felix-coreboot@felixheld.de --- M src/soc/amd/picasso/reset.c 1 file changed, 0 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/86/48486/3
Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48486 )
Change subject: soc/amd/picasso/reset: remove leftover PCI includes ......................................................................
Patch Set 3: Code-Review+2
Marshall Dawson has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48486 )
Change subject: soc/amd/picasso/reset: remove leftover PCI includes ......................................................................
Patch Set 3: Code-Review+2
Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/48486 )
Change subject: soc/amd/picasso/reset: remove leftover PCI includes ......................................................................
soc/amd/picasso/reset: remove leftover PCI includes
On Stoneyridge some PCI registers were accessed in this compilation unit, but on Picasso this is no longer the case.
Change-Id: Ifbf65f9724a14d4847af98930759c865453775b4 Signed-off-by: Felix Held felix-coreboot@felixheld.de Reviewed-on: https://review.coreboot.org/c/coreboot/+/48486 Reviewed-by: Arthur Heymans arthur@aheymans.xyz Reviewed-by: Marshall Dawson marshalldawson3rd@gmail.com Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/soc/amd/picasso/reset.c 1 file changed, 0 insertions(+), 2 deletions(-)
Approvals: build bot (Jenkins): Verified Marshall Dawson: Looks good to me, approved Arthur Heymans: Looks good to me, approved
diff --git a/src/soc/amd/picasso/reset.c b/src/soc/amd/picasso/reset.c index 7a0074c..dea166a 100644 --- a/src/soc/amd/picasso/reset.c +++ b/src/soc/amd/picasso/reset.c @@ -3,9 +3,7 @@ #include <arch/io.h> #include <console/console.h> #include <reset.h> -#include <soc/pci_devs.h> #include <soc/reset.h> -#include <device/pci_ops.h> #include <soc/southbridge.h> #include <amdblocks/acpimmio.h> #include <amdblocks/reset.h>
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Arthur Heymans (Code Review) -
Felix Held (Code Review)
-
Marshall Dawson (Code Review)