Felix Held uploaded patch set #3 to this change.

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soc/amd/picasso/reset: remove leftover PCI includes

On Stoneyridge some PCI registers were accessed in this compilation
unit, but on Picasso this is no longer the case.

Change-Id: Ifbf65f9724a14d4847af98930759c865453775b4
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
---
M src/soc/amd/picasso/reset.c
1 file changed, 0 insertions(+), 2 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/86/48486/3

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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: Ifbf65f9724a14d4847af98930759c865453775b4
Gerrit-Change-Number: 48486
Gerrit-PatchSet: 3
Gerrit-Owner: Felix Held <felix-coreboot@felixheld.de>
Gerrit-Reviewer: Jason Glenesk <jason.glenesk@gmail.com>
Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd@gmail.com>
Gerrit-Reviewer: build bot (Jenkins) <no-reply@coreboot.org>
Gerrit-MessageType: newpatchset