coreboot-gerrit April 2025

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[S] Change in coreboot[main]: util/lint: Add lint file for gofmt
by Maximilian Brune (Code Review) 08 Apr '25

08 Apr '25

Maximilian Brune has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/87211?usp=email ) Change subject: util/lint: Add lint file for gofmt ...................................................................... util/lint: Add lint file for gofmt Add a linter file to check the formatting of our go files. For now only intelp2m utiliy is checked. Signed-off-by: Maximilian Brune <maximilian.brune(a)9elements.com> Change-Id: I9c75fc0bf20a2625ddae43b0472a6586ae78f213 --- A util/lint/lint-stable-031-gofmt 1 file changed, 33 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/11/87211/1 diff --git a/util/lint/lint-stable-031-gofmt b/util/lint/lint-stable-031-gofmt new file mode 100755 index 0000000..f22d39a --- /dev/null +++ b/util/lint/lint-stable-031-gofmt @@ -0,0 +1,33 @@ +#!/usr/bin/env sh +# +# SPDX-License-Identifier: GPL-2.0-only + +# DESCR: Run gofmt on util/intelp2m + +LINTDIR="$( + cd -- "$(dirname "$0")" > /dev/null 2>&1 || return + pwd -P +)" + +# shellcheck source=helper_functions.sh +. "${LINTDIR}/helper_functions.sh" + +# Until we require this by default, we need a list of opted-in directories +# If the script isn't looking at a git repository, just exit +if [ "${IN_GIT_TREE}" -eq 0 ]; then + exit 0 +fi + +files_to_check=$(${GIT} log HEAD~..HEAD --format= --name-only util/intelp2m | grep "\.go$") + +# nothing to do +if [ -z "$files_to_check" ]; then + exit 0 +fi + +diff_files=$(gofmt -l $files_to_check) +if [ "$diff_files" != "" ]; then + echo "Coding style mismatch. Run \"gofmt -w $files_to_check\" before pushing changes" + exit 1 +fi +exit 0 -- To view, visit https://review.coreboot.org/c/coreboot/+/87211?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I9c75fc0bf20a2625ddae43b0472a6586ae78f213 Gerrit-Change-Number: 87211 Gerrit-PatchSet: 1 Gerrit-Owner: Maximilian Brune <maximilian.brune(a)9elements.com>

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[XS] Change in coreboot[main]: mb/google/fatcat/var/felino: Use GPP_E03 for EC_SYNC_IRQ
by Tongtong Pan (Code Review) 08 Apr '25

08 Apr '25

Tongtong Pan has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/87210?usp=email ) Change subject: mb/google/fatcat/var/felino: Use GPP_E03 for EC_SYNC_IRQ ...................................................................... mb/google/fatcat/var/felino: Use GPP_E03 for EC_SYNC_IRQ Use GPP_E03 as the EC sync interrupt and provide this value to the embedded controller to be exported to the OS. BUG=b:403383143 Test=emerge-fatcat coreboot and Confirm the log: cros_ec_lpcs GOOG0004:00: Chrome EC device registered Change-Id: If7d120fcf2de8dbbbc399d2ead4e294d11ea8a14 Signed-off-by: Tongtong Pan <pantongtong(a)huaqin.corp-partner.google.com> --- M src/mainboard/google/fatcat/variants/baseboard/fatcat/include/baseboard/gpio.h M src/mainboard/google/fatcat/variants/felino/gpio.c 2 files changed, 3 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/10/87210/1 diff --git a/src/mainboard/google/fatcat/variants/baseboard/fatcat/include/baseboard/gpio.h b/src/mainboard/google/fatcat/variants/baseboard/fatcat/include/baseboard/gpio.h index dc4ce13..a5772a4 100644 --- a/src/mainboard/google/fatcat/variants/baseboard/fatcat/include/baseboard/gpio.h +++ b/src/mainboard/google/fatcat/variants/baseboard/fatcat/include/baseboard/gpio.h @@ -26,8 +26,8 @@ /* Used to gate SoC's SLP_S0# signal */ #define GPIO_SLP_S0_GATE GPP_F23 #elif CONFIG(BOARD_GOOGLE_FELINO) - #define EC_SYNC_IRQ 0 /* TODO */ - #define GPIO_PCH_WP 0 /* TODO */ + #define EC_SYNC_IRQ GPP_E03_IRQ + #define GPIO_PCH_WP 0 /* Used to gate SoC's SLP_S0# signal */ #define GPIO_SLP_S0_GATE GPP_D03 #endif diff --git a/src/mainboard/google/fatcat/variants/felino/gpio.c b/src/mainboard/google/fatcat/variants/felino/gpio.c index 3b2a693..f5f9852 100644 --- a/src/mainboard/google/fatcat/variants/felino/gpio.c +++ b/src/mainboard/google/fatcat/variants/felino/gpio.c @@ -207,7 +207,7 @@ /* GPP_E02: NC */ PAD_NC(GPP_E02, NONE), /* GPP_E03: NC */ - PAD_NC(GPP_E03, NONE), + PAD_CFG_GPI_APIC(GPP_E03, NONE, PLTRST, LEVEL, INVERT), /* GPP_E05: NC */ PAD_NC(GPP_E05, NONE), /* GPP_E06: GPP_E06 */ -- To view, visit https://review.coreboot.org/c/coreboot/+/87210?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If7d120fcf2de8dbbbc399d2ead4e294d11ea8a14 Gerrit-Change-Number: 87210 Gerrit-PatchSet: 1 Gerrit-Owner: Tongtong Pan <pantongtong(a)huaqin.corp-partner.google.com>

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[L] Change in coreboot[main]: superio/fintek: Add support for f81966d
by Maxim Polyakov (Code Review) 08 Apr '25

08 Apr '25

Attention is currently required from: Felix Singer, Frans Hendriks, Harrie Paijmans. Maxim Polyakov has posted comments on this change by Harrie Paijmans. ( https://review.coreboot.org/c/coreboot/+/87198?usp=email ) Change subject: superio/fintek: Add support for f81966d ...................................................................... Patch Set 2: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/87198/comment/2619ded6_5b62fe59?us… : PS2, Line 16: TEST Have you checked your updated configuration using util/superiotool? Do your values match the dump? File src/superio/fintek/f81966d/f81966d_hwm.c: https://review.coreboot.org/c/coreboot/+/87198/comment/b68c5867_22b15ba4?us… : PS2, Line 29: pnp_write_index Why don't you use pnp_write_hwm5_index() here? Maybe I'm wrong, but shouldn't we take into account the HWM offset +5, as superiotool does https://github.com/coreboot/coreboot/blob/main/util/superiotool/fintek.c#L8… ? -- To view, visit https://review.coreboot.org/c/coreboot/+/87198?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ibe3987b6e15eb07b92d7f5a7de2bd511de85e2f7 Gerrit-Change-Number: 87198 Gerrit-PatchSet: 2 Gerrit-Owner: Harrie Paijmans <hpaijmans(a)eltan.com> Gerrit-Reviewer: Erik van den Bogaert <ebogaert(a)eltan.com> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Attention: Harrie Paijmans <hpaijmans(a)eltan.com> Gerrit-Comment-Date: Tue, 08 Apr 2025 12:13:34 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[M] Change in coreboot[main]: mb/asus/p8z77-v: Attempt to correctly route PCIe lanes
by Keith Hui (Code Review) 08 Apr '25

08 Apr '25

Attention is currently required from: Angel Pons, Bill XIE, Nicholas Chin. Keith Hui has posted comments on this change by Keith Hui. ( https://review.coreboot.org/c/coreboot/+/85413?usp=email ) Change subject: mb/asus/p8z77-v: Attempt to correctly route PCIe lanes ...................................................................... Patch Set 7: (1 comment) File src/mainboard/asus/p8x7x-series/variants/p8z77-v/early_init.c: https://review.coreboot.org/c/coreboot/+/85413/comment/a2303b3d_ac45f391?us… : PS7, Line 104: 0x40 > > So the values we need are: 0x70, 0x40, 0x20. […] My understanding so far: 0x70: x4 or Setup[0x820] == 1 (This is confirmed; you can use it to verify the read, see below) 0x40: ASM1061 or Setup[0x820] == 0 0x20: PCIEX1_2 or Setup[0x820] == 2 Setup is an EFI variable, and I need a name for these values. So I need another test from you: 1. Go back to vendor BIOS. 2. Check that the EFI variables are mounted: ``` # mount ... efivarfs on /sys/firmware/efi/efivars type efivarfs (rw,... ``` The file we need is Setup-ec87d643-*. If I read my disassembly right, it should be 2141 +/- 5 bytes. 3. Set the PCIEX16_3 bandwidth option to each possible option and check back here to give these values a name. I'm not sure if the UEFI GetVariable call strips the 4 bytes of attributes in front from the data, but they are there if you read through efivarfs. If the values don't make sense, try offset 0x824 or cut 4 bytes from the head instead. In the meantime, get a(nother) backup SPI flash chip. The next patch set I upload will be the whole thing, including the part that reflashes the IFD. You should have a known good coreboot build on hand and be ready to recover from a botched flash. -- To view, visit https://review.coreboot.org/c/coreboot/+/85413?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If41197a1f817a48c209d25fc1ae461ec97ccf16c Gerrit-Change-Number: 85413 Gerrit-PatchSet: 7 Gerrit-Owner: Keith Hui <buurin(a)gmail.com> Gerrit-Reviewer: Bill XIE <persmule(a)hardenedlinux.org> Gerrit-Reviewer: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Bill XIE <persmule(a)hardenedlinux.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Comment-Date: Tue, 08 Apr 2025 12:03:17 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Bill XIE <persmule(a)hardenedlinux.org> Comment-In-Reply-To: Keith Hui <buurin(a)gmail.com>

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[XS] Change in coreboot[main]: soc/mediatek/mt8189: Reserve DRAM buffers for HW TX TRACKING
by Yidi Lin (Code Review) 08 Apr '25

08 Apr '25

Attention is currently required from: Hung-Te Lin, Vince Liu, Yu-Ping Wu. Yidi Lin has posted comments on this change by Vince Liu. ( https://review.coreboot.org/c/coreboot/+/87039?usp=email ) Change subject: soc/mediatek/mt8189: Reserve DRAM buffers for HW TX TRACKING ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/87039?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I2ecfe42dc9f1882163d03f50cf9b5ff8e98c2972 Gerrit-Change-Number: 87039 Gerrit-PatchSet: 2 Gerrit-Owner: Vince Liu <vince-wl.liu(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Vince Liu <vince-wl.liu(a)mediatek.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Tue, 08 Apr 2025 11:34:16 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[XS] Change in coreboot[main]: mb/google/skywalker: Add DRAM calibration init entry
by Yidi Lin (Code Review) 08 Apr '25

08 Apr '25

Attention is currently required from: Hung-Te Lin, Vince Liu, Yu-Ping Wu. Yidi Lin has posted comments on this change by Vince Liu. ( https://review.coreboot.org/c/coreboot/+/87038?usp=email ) Change subject: mb/google/skywalker: Add DRAM calibration init entry ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/87038?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iabdcabefc77a262c548019e801daf5b269eaa97a Gerrit-Change-Number: 87038 Gerrit-PatchSet: 2 Gerrit-Owner: Vince Liu <vince-wl.liu(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Vince Liu <vince-wl.liu(a)mediatek.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Tue, 08 Apr 2025 11:33:31 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[M] Change in coreboot[main]: soc/mediatek/mt8189: Add DRAM calibration support
by Yidi Lin (Code Review) 08 Apr '25

08 Apr '25

Attention is currently required from: Hung-Te Lin, Vince Liu, Yu-Ping Wu. Yidi Lin has posted comments on this change by Vince Liu. ( https://review.coreboot.org/c/coreboot/+/87037?usp=email ) Change subject: soc/mediatek/mt8189: Add DRAM calibration support ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/87037?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ia6f6e5afc1f4a2e919243bda0799712cd7b4d01f Gerrit-Change-Number: 87037 Gerrit-PatchSet: 2 Gerrit-Owner: Vince Liu <vince-wl.liu(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Vince Liu <vince-wl.liu(a)mediatek.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Tue, 08 Apr 2025 11:33:16 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[S] Change in coreboot[main]: soc/mediatek/common: Move DRAMC function declarations to common header
by Yidi Lin (Code Review) 08 Apr '25

08 Apr '25

Attention is currently required from: Hung-Te Lin, Vince Liu, Xi Chen, Yu-Ping Wu. Yidi Lin has posted comments on this change by Vince Liu. ( https://review.coreboot.org/c/coreboot/+/87209?usp=email ) Change subject: soc/mediatek/common: Move DRAMC function declarations to common header ...................................................................... Patch Set 1: Code-Review+2 (1 comment) Patchset: PS1: > This patch should be moved before CB:87036. sorry, please ignore this comment. -- To view, visit https://review.coreboot.org/c/coreboot/+/87209?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iab24f07b4c02da22779ea1c76f3237c144d92b98 Gerrit-Change-Number: 87209 Gerrit-PatchSet: 1 Gerrit-Owner: Vince Liu <vince-wl.liu(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Xi Chen <xixi.chen(a)mediatek.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Xi Chen <xixi.chen(a)mediatek.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Vince Liu <vince-wl.liu(a)mediatek.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Tue, 08 Apr 2025 11:32:52 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Yidi Lin <yidilin(a)google.com>

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[S] Change in coreboot[main]: soc/mediatek/common: Move DRAMC function declarations to common header
by Yidi Lin (Code Review) 08 Apr '25

08 Apr '25

Attention is currently required from: Hung-Te Lin, Vince Liu, Xi Chen, Yu-Ping Wu. Yidi Lin has posted comments on this change by Vince Liu. ( https://review.coreboot.org/c/coreboot/+/87209?usp=email ) Change subject: soc/mediatek/common: Move DRAMC function declarations to common header ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: This patch should be moved before CB:87036. -- To view, visit https://review.coreboot.org/c/coreboot/+/87209?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iab24f07b4c02da22779ea1c76f3237c144d92b98 Gerrit-Change-Number: 87209 Gerrit-PatchSet: 1 Gerrit-Owner: Vince Liu <vince-wl.liu(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Xi Chen <xixi.chen(a)mediatek.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Xi Chen <xixi.chen(a)mediatek.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Vince Liu <vince-wl.liu(a)mediatek.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Tue, 08 Apr 2025 11:30:59 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[S] Change in coreboot[main]: soc/mediatek/mt8196: Move TX TRACKING from MT8196 to common folder
by Yidi Lin (Code Review) 08 Apr '25

08 Apr '25

Attention is currently required from: Hung-Te Lin, Vince Liu, Yu-Ping Wu. Yidi Lin has posted comments on this change by Vince Liu. ( https://review.coreboot.org/c/coreboot/+/87036?usp=email ) Change subject: soc/mediatek/mt8196: Move TX TRACKING from MT8196 to common folder ...................................................................... Patch Set 2: Code-Review+2 (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/87036/comment/9d0baeb5_5c672929?us… : PS2, Line 13: directory. Can it move to above line ? -- To view, visit https://review.coreboot.org/c/coreboot/+/87036?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I3fdd9d2f7ab1bbdcc097510556929da2134f7d95 Gerrit-Change-Number: 87036 Gerrit-PatchSet: 2 Gerrit-Owner: Vince Liu <vince-wl.liu(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Vince Liu <vince-wl.liu(a)mediatek.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Tue, 08 Apr 2025 11:28:52 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes

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coreboot-gerrit April 2025