coreboot-gerrit April 2025

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[S] Change in coreboot[main]: cpu/x86: Conditionally invalidate caches based on self-snooping support
by Kapil Porwal (Code Review) 08 Apr '25

08 Apr '25

Attention is currently required from: Paul Menzel, Subrata Banik. Kapil Porwal has posted comments on this change by Subrata Banik. ( https://review.coreboot.org/c/coreboot/+/87182?usp=email ) Change subject: cpu/x86: Conditionally invalidate caches based on self-snooping support ...................................................................... Patch Set 5: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/87182?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If32439752d0ceaa03b1d81873ea0bc562092e9d5 Gerrit-Change-Number: 87182 Gerrit-PatchSet: 5 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Tue, 08 Apr 2025 10:04:29 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[M] Change in coreboot[main]: Documentation/util/intelp2m: Add info for developers
by Maxim Polyakov (Code Review) 08 Apr '25

08 Apr '25

Attention is currently required from: Maximilian Brune. Maxim Polyakov has posted comments on this change by Maxim Polyakov. ( https://review.coreboot.org/c/coreboot/+/85791?usp=email ) Change subject: Documentation/util/intelp2m: Add info for developers ...................................................................... Patch Set 4: (1 comment) File Documentation/util/intelp2m/index.md: https://review.coreboot.org/c/coreboot/+/85791/comment/0275a2a7_f9f4f33a?us… : PS4, Line 275: It depends on the changes: the `major` is incremented if a new platform is added, `minor` - if > I don't think that makes much sense. The versions should be about compatibility. […] So, to clarify, you're suggesting the following rule: keep `{major}.{minor}-{last commit in the intelp2m directory}-{?dirty}` unchanged, but `major` - changes to the command line (add or update option), `minor` - new platform or a new feature aren't you? -- To view, visit https://review.coreboot.org/c/coreboot/+/85791?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I9cc886e607c1aba92b94e06419d45d9581371065 Gerrit-Change-Number: 85791 Gerrit-PatchSet: 4 Gerrit-Owner: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Attention: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Comment-Date: Tue, 08 Apr 2025 08:56:40 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Maximilian Brune <maximilian.brune(a)9elements.com>

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[S] Change in coreboot[main]: mb/google/fatcat/var/felino: Add ALC712 codec to devicetree
by Subrata Banik (Code Review) 08 Apr '25

08 Apr '25

Attention is currently required from: Kapil Porwal, Mac Chiang, Paul Menzel, Pranava Y N, Tongtong Pan, Varun Upadhyay, Weimin Wu. Subrata Banik has posted comments on this change by Weimin Wu. ( https://review.coreboot.org/c/coreboot/+/85572?usp=email ) Change subject: mb/google/fatcat/var/felino: Add ALC712 codec to devicetree ...................................................................... Patch Set 7: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/85572?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ic5c38462cd1ab39d4aebc324d5151cb4337051df Gerrit-Change-Number: 85572 Gerrit-PatchSet: 7 Gerrit-Owner: Weimin Wu <wuweimin(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Mac Chiang <mac.chiang(a)intel.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tongtong Pan <pantongtong(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Varun Upadhyay <varun.upadhyay(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Mac Chiang <mac.chiang(a)intel.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Varun Upadhyay <varun.upadhyay(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Weimin Wu <wuweimin(a)huaqin.corp-partner.google.com> Gerrit-Attention: Tongtong Pan <pantongtong(a)huaqin.corp-partner.google.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com> Gerrit-Comment-Date: Tue, 08 Apr 2025 08:38:33 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[L] Change in coreboot[main]: superio/fintek: Add support for f81966d
by Maxim Polyakov (Code Review) 08 Apr '25

08 Apr '25

Attention is currently required from: Felix Singer, Harrie Paijmans. Maxim Polyakov has posted comments on this change by Harrie Paijmans. ( https://review.coreboot.org/c/coreboot/+/87198?usp=email ) The change is no longer submittable: All-Comments-Resolved is unsatisfied now. Change subject: superio/fintek: Add support for f81966d ...................................................................... Patch Set 1: Code-Review+1 (5 comments) File src/superio/fintek/f81966d/f81966d_gpio.c: https://review.coreboot.org/c/coreboot/+/87198/comment/475cd05a_bf5fb533?us… : PS1, Line 14: */ space before */ https://review.coreboot.org/c/coreboot/+/87198/comment/73e245af_b06b8d84?us… : PS1, Line 15: setreg set_reg to match the сode style https://review.coreboot.org/c/coreboot/+/87198/comment/14f23a6d_84e9973c?us… : PS1, Line 25: selectbank select_bank https://review.coreboot.org/c/coreboot/+/87198/comment/7727e60f_163f3d11?us… : PS1, Line 58: selectbank Do we really have to set a bank for each setreg()? Maybe we should do this when we switch between banks? File src/superio/fintek/f81966d/superio.c: https://review.coreboot.org/c/coreboot/+/87198/comment/e16ffceb_8e406693?us… : PS1, Line 58: Some of the 0x7f8 values may need to be corrected Mark it as `TODO: ...`? -- To view, visit https://review.coreboot.org/c/coreboot/+/87198?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ibe3987b6e15eb07b92d7f5a7de2bd511de85e2f7 Gerrit-Change-Number: 87198 Gerrit-PatchSet: 1 Gerrit-Owner: Harrie Paijmans <hpaijmans(a)eltan.com> Gerrit-Reviewer: Erik van den Bogaert <ebogaert(a)eltan.com> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Harrie Paijmans <hpaijmans(a)eltan.com> Gerrit-Comment-Date: Tue, 08 Apr 2025 08:36:56 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes

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[XS] Change in coreboot[main]: mb/starlabs/starbook/kbl: Re-add the GPE configuration
by Sean Rhodes (Code Review) 08 Apr '25

08 Apr '25

Sean Rhodes has submitted this change. ( https://review.coreboot.org/c/coreboot/+/87200?usp=email ) Change subject: mb/starlabs/starbook/kbl: Re-add the GPE configuration ...................................................................... mb/starlabs/starbook/kbl: Re-add the GPE configuration These were previously removed, but doing so, slowed down the brightness keys to approx. 3 seconds. Re-add them to make them instant. Change-Id: I1256b57192d2f8987bb476cbcc7fd7e81f314d6d Signed-off-by: Sean Rhodes <sean(a)starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/87200 Reviewed-by: Matt DeVillier <matt.devillier(a)gmail.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/starlabs/starbook/variants/kbl/devicetree.cb 1 file changed, 5 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Matt DeVillier: Looks good to me, approved diff --git a/src/mainboard/starlabs/starbook/variants/kbl/devicetree.cb b/src/mainboard/starlabs/starbook/variants/kbl/devicetree.cb index dd53a01..a9ac9c1 100644 --- a/src/mainboard/starlabs/starbook/variants/kbl/devicetree.cb +++ b/src/mainboard/starlabs/starbook/variants/kbl/devicetree.cb @@ -32,6 +32,11 @@ register "PmConfigSlpSusMinAssert" = "3" # 1s register "PmConfigSlpAMinAssert" = "3" # 98ms + # GPE configuration + register "gpe0_dw0" = "GPP_B" + register "gpe0_dw1" = "GPP_C" + register "gpe0_dw2" = "GPP_E" + # Enable the correct decode ranges on the LPC bus. register "lpc_ioe" = "LPC_IOE_EC_4E_4F | LPC_IOE_KBC_60_64 | -- To view, visit https://review.coreboot.org/c/coreboot/+/87200?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I1256b57192d2f8987bb476cbcc7fd7e81f314d6d Gerrit-Change-Number: 87200 Gerrit-PatchSet: 2 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[XS] Change in coreboot[main]: mb/starlabs/starbook/cml: Re-add the GPE configuration
by Sean Rhodes (Code Review) 08 Apr '25

08 Apr '25

Sean Rhodes has submitted this change. ( https://review.coreboot.org/c/coreboot/+/87199?usp=email ) Change subject: mb/starlabs/starbook/cml: Re-add the GPE configuration ...................................................................... mb/starlabs/starbook/cml: Re-add the GPE configuration These were previously removed, but doing so, slowed down the brightness keys to approx. 3 seconds. Re-add them to make them instant. Change-Id: I3af197cd995bd947c6e72bf5593fc966c85c3e3a Signed-off-by: Sean Rhodes <sean(a)starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/87199 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M src/mainboard/starlabs/starbook/variants/cml/devicetree.cb 1 file changed, 5 insertions(+), 0 deletions(-) Approvals: Matt DeVillier: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/mainboard/starlabs/starbook/variants/cml/devicetree.cb b/src/mainboard/starlabs/starbook/variants/cml/devicetree.cb index d502b2a..7a659ce 100644 --- a/src/mainboard/starlabs/starbook/variants/cml/devicetree.cb +++ b/src/mainboard/starlabs/starbook/variants/cml/devicetree.cb @@ -34,6 +34,11 @@ register "PchPmSlpSusMinAssert" = "3" # 1s register "PchPmSlpAMinAssert" = "3" # 98ms + # GPE configuration + register "gpe0_dw0" = "PMC_GPP_B" + register "gpe0_dw1" = "PMC_GPP_C" + register "gpe0_dw2" = "PMC_GPP_E" + # PCIe Clock register "PcieClkSrcClkReq[0]" = "PCIE_CLK_NOTUSED" register "PcieClkSrcClkReq[2]" = "PCIE_CLK_NOTUSED" -- To view, visit https://review.coreboot.org/c/coreboot/+/87199?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I3af197cd995bd947c6e72bf5593fc966c85c3e3a Gerrit-Change-Number: 87199 Gerrit-PatchSet: 3 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[S] Change in coreboot[main]: mb/google/fatcat/var/fatcat: Implement barrel jack presence check
by Subrata Banik (Code Review) 08 Apr '25

08 Apr '25

Attention is currently required from: Jayvik Desai, Kapil Porwal, Pranava Y N. Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/87207?usp=email ) Change subject: mb/google/fatcat/var/fatcat: Implement barrel jack presence check ...................................................................... mb/google/fatcat/var/fatcat: Implement barrel jack presence check Uses fw_config to check if barrel jack PSU is configured. If `PSU_BJ` is selected, checks hardware presence via `google_chromeec_is_barrel_charger_present()`. Allows 'fatcat' to adapt based on configured power source. Includes: - Adds `variant.c` to ramstage build in `Makefile.mk`. - Adds `PSU` field (`PSU_USBC`: 0, `PSU_BJ`: 1) to `overridetree.cb`. - Includes `ec.h` in `variant.c`. TEST=Boot time savings ~62ms on google/fatcat with PSU=0 (USB-C). Change-Id: I68507034cfbf4caa8e5c2ac9c7bebf758a5a5439 Signed-off-by: Subrata Banik <subratabanik(a)google.com> --- M src/mainboard/google/fatcat/variants/fatcat/Makefile.mk M src/mainboard/google/fatcat/variants/fatcat/overridetree.cb M src/mainboard/google/fatcat/variants/fatcat/variant.c 3 files changed, 14 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/07/87207/1 diff --git a/src/mainboard/google/fatcat/variants/fatcat/Makefile.mk b/src/mainboard/google/fatcat/variants/fatcat/Makefile.mk index b9f1fd1..3fdd464 100644 --- a/src/mainboard/google/fatcat/variants/fatcat/Makefile.mk +++ b/src/mainboard/google/fatcat/variants/fatcat/Makefile.mk @@ -6,4 +6,5 @@ romstage-$(CONFIG_FW_CONFIG) += fw_config.c ramstage-y += gpio.c romstage-$(CONFIG_FW_CONFIG) += variant.c +ramstage-$(CONFIG_FW_CONFIG) += variant.c ramstage-$(CONFIG_FW_CONFIG) += fw_config.c diff --git a/src/mainboard/google/fatcat/variants/fatcat/overridetree.cb b/src/mainboard/google/fatcat/variants/fatcat/overridetree.cb index c6a63c3..e154ffc 100644 --- a/src/mainboard/google/fatcat/variants/fatcat/overridetree.cb +++ b/src/mainboard/google/fatcat/variants/fatcat/overridetree.cb @@ -67,6 +67,10 @@ option ISH_DISABLE 0 option ISH_ENABLE 1 end + field PSU 25 + option PSU_USBC 0 + option PSU_BJ 1 + end end chip soc/intel/pantherlake diff --git a/src/mainboard/google/fatcat/variants/fatcat/variant.c b/src/mainboard/google/fatcat/variants/fatcat/variant.c index 5ba7683..3e0ee54 100644 --- a/src/mainboard/google/fatcat/variants/fatcat/variant.c +++ b/src/mainboard/google/fatcat/variants/fatcat/variant.c @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <baseboard/variants.h> +#include <ec/google/chromeec/ec.h> #include <fsp/api.h> #include <fw_config.h> #include <sar.h> @@ -84,3 +85,11 @@ m_cfg->PchHdaSdiEnable[1] = false; } } + +bool variant_is_barrel_charger_present(void) +{ + if (fw_config_probe(FW_CONFIG(PSU, PSU_BJ))) + return google_chromeec_is_barrel_charger_present(); + else + return false; +} -- To view, visit https://review.coreboot.org/c/coreboot/+/87207?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I68507034cfbf4caa8e5c2ac9c7bebf758a5a5439 Gerrit-Change-Number: 87207 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com>

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[S] Change in coreboot[main]: mb/google/fatcat: Introduce variant-specific barrel jack presence check
by Subrata Banik (Code Review) 08 Apr '25

08 Apr '25

Attention is currently required from: Jayvik Desai, Kapil Porwal, Pranava Y N. Hello Jayvik Desai, Kapil Porwal, Pranava Y N, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/87183?usp=email to look at the new patch set (#7). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: mb/google/fatcat: Introduce variant-specific barrel jack presence check ...................................................................... mb/google/fatcat: Introduce variant-specific barrel jack presence check This commit introduces a weak function `variant_is_barrel_charger_present()` to allow individual Fatcat variants to specify if they support power-on via a barrel jack. The default implementation of this function returns `false`, reflecting the fact that most Chromebook devices within the Fatcat family primarily use USB-C for power. The `baseboard_devtree_update()` function is updated to use this variant-specific check instead of directly calling `google_chromeec_is_barrel_charger_present()` and checking the board model. This allows for more flexibility in handling barrel jack presence across different Fatcat variants. This change enables specific variants that do support barrel jack power to override the weak function and return `true`, allowing the system to behave accordingly (e.g., skipping power optimization when booting with a barrel charger). TEST=Able to build and boot google/fatcat. Change-Id: I613417be5a59790b8a5e6055957a2f518f4c42df Signed-off-by: Subrata Banik <subratabanik(a)google.com> --- M src/mainboard/google/fatcat/variants/baseboard/fatcat/ramstage.c M src/mainboard/google/fatcat/variants/baseboard/include/baseboard/variants.h 2 files changed, 14 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/83/87183/7 -- To view, visit https://review.coreboot.org/c/coreboot/+/87183?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I613417be5a59790b8a5e6055957a2f518f4c42df Gerrit-Change-Number: 87183 Gerrit-PatchSet: 7 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com>

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[XS] Change in coreboot[main]: {commonlib, lib}: Add timestamp for early chip initialization
by Subrata Banik (Code Review) 08 Apr '25

08 Apr '25

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/87152?usp=email ) Change subject: {commonlib, lib}: Add timestamp for early chip initialization ...................................................................... {commonlib, lib}: Add timestamp for early chip initialization This commit introduces a new timestamp `TS_DEVICE_INIT_CHIPS` to specifically mark the start of the `dev_initialize_chips()` function. Previously, the `TS_DEVICE_ENUMERATE` timestamp was incorrectly associated with the `bs_dev_init_chips` function. This patch corrects this by: - Adding the `TS_DEVICE_INIT_CHIPS` enum and name definition. - Updating `bs_dev_init_chips` in `src/lib/hardwaremain.c` to use `TS_DEVICE_INIT_CHIPS`. - Moving the `TS_DEVICE_ENUMERATE` timestamp addition to the `bs_dev_enumerate` function where device enumeration actually begins. This change provides a more accurate and meaningful timestamp for the early chipset initialization phase. TEST=Able to build and boot google/fatcat. ``` 971:loading FSP-S 836,277 (10,658) 17:starting LZ4 decompress (ignore for x86) 847,297 (11,019) 18:finished LZ4 decompress (ignore for x86) 847,376 (79) 30:early chipset initialization 854,579 (7,203) 17:starting LZ4 decompress (ignore for x86) 863,483 (8,903) 18:finished LZ4 decompress (ignore for x86) 863,490 (6) 17:starting LZ4 decompress (ignore for x86) 875,196 (11,705) 18:finished LZ4 decompress (ignore for x86) 875,237 (41) 954:calling FspSiliconInit 875,344 (107) 955:returning from FspSiliconInit 942,740 (67,396) 962:calling FspMultiPhaseSiInit 942,744 (4) 963:returning from FspMultiPhaseSiInit 1,081,355 (138,610) 31:device enumeration 1,081,708 (352) 40:device configuration 1,085,721 (4,013) 50:device enable 1,091,517 (5,795) ``` Change-Id: Ib6860901c6b1528ec5098fc93240c6e65777642b Signed-off-by: Subrata Banik <subratabanik(a)google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/87152 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub(a)google.com> Reviewed-by: Julius Werner <jwerner(a)chromium.org> Reviewed-by: Wonkyu Kim <wonkyu.kim(a)intel.com> Reviewed-by: Kapil Porwal <kapilporwal(a)google.com> Reviewed-by: Jayvik Desai <jayvik(a)google.com> --- M src/commonlib/include/commonlib/timestamp_serialized.h M src/lib/hardwaremain.c 2 files changed, 6 insertions(+), 2 deletions(-) Approvals: Karthik Ramasubramanian: Looks good to me, approved build bot (Jenkins): Verified Kapil Porwal: Looks good to me, approved Julius Werner: Looks good to me, approved Wonkyu Kim: Looks good to me, but someone else must approve Jayvik Desai: Looks good to me, approved diff --git a/src/commonlib/include/commonlib/timestamp_serialized.h b/src/commonlib/include/commonlib/timestamp_serialized.h index f60e040..6bcbabc 100644 --- a/src/commonlib/include/commonlib/timestamp_serialized.h +++ b/src/commonlib/include/commonlib/timestamp_serialized.h @@ -37,7 +37,8 @@ TS_ULZMA_END = 16, TS_ULZ4F_START = 17, TS_ULZ4F_END = 18, - TS_DEVICE_ENUMERATE = 30, + TS_DEVICE_INIT_CHIPS = 30, + TS_DEVICE_ENUMERATE = 31, TS_DEVICE_CONFIGURE = 40, TS_DEVICE_ENABLE = 50, TS_DEVICE_INITIALIZE = 60, @@ -218,6 +219,7 @@ TS_NAME_DEF(TS_ULZMA_END, 0, "finished LZMA decompress (ignore for x86)"), TS_NAME_DEF(TS_ULZ4F_START, TS_ULZ4F_END, "starting LZ4 decompress (ignore for x86)"), TS_NAME_DEF(TS_ULZ4F_END, 0, "finished LZ4 decompress (ignore for x86)"), + TS_NAME_DEF(TS_DEVICE_INIT_CHIPS, TS_DEVICE_ENUMERATE, "early chipset initialization"), TS_NAME_DEF(TS_DEVICE_ENUMERATE, TS_DEVICE_CONFIGURE, "device enumeration"), TS_NAME_DEF(TS_DEVICE_CONFIGURE, TS_DEVICE_ENABLE, "device configuration"), TS_NAME_DEF(TS_DEVICE_ENABLE, TS_DEVICE_INITIALIZE, "device enable"), diff --git a/src/lib/hardwaremain.c b/src/lib/hardwaremain.c index fda6c62..7e5d848 100644 --- a/src/lib/hardwaremain.c +++ b/src/lib/hardwaremain.c @@ -93,7 +93,7 @@ static boot_state_t bs_dev_init_chips(void *arg) { - timestamp_add_now(TS_DEVICE_ENUMERATE); + timestamp_add_now(TS_DEVICE_INIT_CHIPS); /* Initialize chips early, they might disable unused devices. */ dev_initialize_chips(); @@ -103,6 +103,8 @@ static boot_state_t bs_dev_enumerate(void *arg) { + timestamp_add_now(TS_DEVICE_ENUMERATE); + /* Find the devices we don't have hard coded knowledge about. */ dev_enumerate(); -- To view, visit https://review.coreboot.org/c/coreboot/+/87152?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ib6860901c6b1528ec5098fc93240c6e65777642b Gerrit-Change-Number: 87152 Gerrit-PatchSet: 6 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[S] Change in coreboot[main]: mb/var/uldrenite: Configure descriptor for either MBVR or FIVR
by John Su (Code Review) 08 Apr '25

08 Apr '25

Attention is currently required from: Ben Kao, Dtrain Hsu, Eric Lai, Intel coreboot Reviewers, Jamie Chen, Jayvik Desai, Jérémy Compostella, Nick Vaccaro, Subrata Banik. John Su has posted comments on this change by John Su. ( https://review.coreboot.org/c/coreboot/+/87033?usp=email ) Change subject: mb/var/uldrenite: Configure descriptor for either MBVR or FIVR ...................................................................... Patch Set 12: (1 comment) Patchset: PS11: > I assume your issue is that https://review.coreboot. […] Done. Thank you for the reminder. I was too fixated on the current failure. -- To view, visit https://review.coreboot.org/c/coreboot/+/87033?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I337574c8c55889ceb49b9f33625feadb48bd8890 Gerrit-Change-Number: 87033 Gerrit-PatchSet: 12 Gerrit-Owner: John Su <john_su(a)compal.corp-partner.google.com> Gerrit-Reviewer: Ben Kao <ben.kao(a)intel.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Jamie Chen <jamie.chen(a)intel.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-CC: Jamie Chen <jamie_chen(a)compal.corp-partner.google.com> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Attention: Jamie Chen <jamie.chen(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Ben Kao <ben.kao(a)intel.com> Gerrit-Comment-Date: Tue, 08 Apr 2025 06:26:45 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: John Su <john_su(a)compal.corp-partner.google.com> Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Jérémy Compostella <jeremy.compostella(a)intel.com>

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