coreboot-gerrit April 2025

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[S] Change in coreboot[main]: soc/amd/common/cpu/noncar: Add SMBIOS helper
by Naresh Solanki (Code Review) 08 Apr '25

08 Apr '25

Attention is currently required from: Felix Held. Hello Felix Held, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/87123?usp=email to look at the new patch set (#5). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: soc/amd/common/cpu/noncar: Add SMBIOS helper ...................................................................... soc/amd/common/cpu/noncar: Add SMBIOS helper Some SoC like Glinda, 1. It has multiple L3 caches block, each identified by a unique cache UID. Each core is associated with a specific L3 cache, which can be determined based on the CPU core ID. 2. Each CPU core have slightly different CPU boost frequency. For L3 cache info in DMI table type 7, the default implementation (x86_get_cpu_cache_info) retrieves cache information only for the current core and assumes that the same L3 cache is shared across all cores. To accurately determine the total L3 cache size: 1. Retrieves L3 cache information for each CPU core. 2. Identifies the unique cache ID associated with each core. 3. Aggregates cache sizes for all unique cache IDs to compute the total L3 cache size, ensuring correct summation even when L3 cache blocks have different sizes. Additionally to get core max boost frequency, 1. Determine max boost frequency among all cores & update smbios_cpu_get_max_speed_mhz such that it return max of all cores. TEST=Build for Glinda SoC & check output of `dmidecode -t 7` & `dmidecode -t 4`. Verify DMI Type7 table to report L3 cache size as 24MB (16 + 8) & Also verify DMI Type4 'Max Speed: 5408 MHz' which is maximum boost clock frequency. Change-Id: I2569a9c744f7f41e4df692626e77a178184b7e0e Signed-off-by: Naresh Solanki <naresh.solanki(a)9elements.com> --- M src/soc/amd/common/block/cpu/noncar/cpu.c 1 file changed, 49 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/87123/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/87123?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I2569a9c744f7f41e4df692626e77a178184b7e0e Gerrit-Change-Number: 87123 Gerrit-PatchSet: 5 Gerrit-Owner: Naresh Solanki <naresh.solanki(a)9elements.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de>

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[S] Change in coreboot[main]: soc/amd/common/cpu/noncar: Compute core info
by Naresh Solanki (Code Review) 08 Apr '25

08 Apr '25

Attention is currently required from: Angel Pons, Felix Held, Fred Reitberger, Jason Glenesk, Marvin Drees, Matt DeVillier, Naresh Solanki. Hello Angel Pons, Felix Held, Fred Reitberger, Jason Glenesk, Marvin Drees, Matt DeVillier, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/85640?usp=email to look at the new patch set (#14). The following approvals got outdated and were removed: Code-Review+2 by Felix Held, Code-Review-1 by Naresh Solanki, Verified+1 by build bot (Jenkins) The change is no longer submittable: Code-Review and Verified are unsatisfied now. Change subject: soc/amd/common/cpu/noncar: Compute core info ...................................................................... soc/amd/common/cpu/noncar: Compute core info In some SoC like Glinda, have 1. Different CPU cores have slightly different max boost frequency, 2. Multiple L3 cache blocks of different size identified by unique ID. Add helper function, 1. get_max_boost_frequency() to compute max boost frequenncy. 2. ap_stash_core_info() to update core_info struct with max boost frequency & all L3 cache block uniq ID & its size. To accurately determine the total L3 cache size: 1. Retrieves L3 cache information for each CPU core. 2. Identifies the unique cache ID associated with each core. 3. Aggregates cache sizes for all unique cache IDs to compute the total L3 cache size, ensuring correct summation even when L3 cache blocks have different sizes. TEST=Build for Glinda SoC, with L3 cache = 16MB + 8MB. Ran command 'dmidecode -t 7' & verified L3 cache is 24MB. Change-Id: I46947e8ac62c903036a81642e03201e353c3dac6 Signed-off-by: Naresh Solanki <naresh.solanki(a)9elements.com> --- M src/soc/amd/common/block/cpu/noncar/cpu.c M src/soc/amd/common/block/include/amdblocks/cpu.h 2 files changed, 39 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/85640/14 -- To view, visit https://review.coreboot.org/c/coreboot/+/85640?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I46947e8ac62c903036a81642e03201e353c3dac6 Gerrit-Change-Number: 85640 Gerrit-PatchSet: 14 Gerrit-Owner: Naresh Solanki <naresh.solanki(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marvin Drees <marvin.drees(a)9elements.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Naresh Solanki <naresh.solanki(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-CC: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Marvin Drees <marvin.drees(a)9elements.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Attention: Naresh Solanki <naresh.solanki(a)9elements.com>

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[S] Change in coreboot[main]: soc/amd/common/cpu/noncar: Compute core info
by Naresh Solanki (Code Review) 08 Apr '25

08 Apr '25

Attention is currently required from: Angel Pons, Fred Reitberger, Jason Glenesk, Marvin Drees, Matt DeVillier. Naresh Solanki has posted comments on this change by Naresh Solanki. ( https://review.coreboot.org/c/coreboot/+/85640?usp=email ) Change subject: soc/amd/common/cpu/noncar: Compute core info ...................................................................... Patch Set 13: Code-Review-1 -- To view, visit https://review.coreboot.org/c/coreboot/+/85640?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I46947e8ac62c903036a81642e03201e353c3dac6 Gerrit-Change-Number: 85640 Gerrit-PatchSet: 13 Gerrit-Owner: Naresh Solanki <naresh.solanki(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marvin Drees <marvin.drees(a)9elements.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Naresh Solanki <naresh.solanki(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-CC: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Marvin Drees <marvin.drees(a)9elements.com> Gerrit-Comment-Date: Tue, 08 Apr 2025 20:31:05 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[L] Change in coreboot[main]: Documentation: Add information about the site-local directory
by Maximilian Brune (Code Review) 08 Apr '25

08 Apr '25

Attention is currently required from: Martin L Roth. Maximilian Brune has posted comments on this change by Martin L Roth. ( https://review.coreboot.org/c/coreboot/+/87185?usp=email ) The change is no longer submittable: All-Comments-Resolved is unsatisfied now. Change subject: Documentation: Add information about the site-local directory ...................................................................... Patch Set 2: (1 comment) File Documentation/getting_started/site-local.md: https://review.coreboot.org/c/coreboot/+/87185/comment/a5bd75b8_aa5da05e?us… : PS2, Line 165: One of the most powerful use cases for `site-local` is developing a new : SoC implementation out-of-tree before it's ready to be made public. : This allows you to: : I don't really understand this use case. Even with the points below I don't understand why someone wouldn't just create the new SOC inside the standard SOC directory. When you create a new SOC, you will never have any conflicts with upstream, because the directory doesn't exist upstream. The other scenario: Assuming the directory already exists upstream and you want to update some things in that SOC and don't want them to be public yet. I still don't understand why these changes would be in the site-local folder, because at some point you will need to rebase onto upstream and rebasing the site-local folder is much harder then just rebasing your patches on top of that SOC. The only use case I can imagine (and that I have myself) is putting files/patches into the site-local folder for which I know that they are NEVER going to go upstream, because they are just some weird hacks, debug things or binary blobs. I am not suggesting that this is the only "useful" use case, but before making suggestions to other users I would like to make clear why it is useful to do so and the points below just don't really give me this impression (or at least I don't understand them). -- To view, visit https://review.coreboot.org/c/coreboot/+/87185?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ida176aa460be7673bad219f958f741dd68a8aa62 Gerrit-Change-Number: 87185 Gerrit-PatchSet: 2 Gerrit-Owner: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Comment-Date: Tue, 08 Apr 2025 19:28:39 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[XS] Change in coreboot[main]: src/soc/amd/cezzane: Rename PSP_AB_RECOVERY setting
by Ana Carolina Cabral (Code Review) 08 Apr '25

08 Apr '25

Attention is currently required from: Felix Held, Fred Reitberger, Jason Glenesk, Julius Werner, Matt DeVillier, Zheng Bao. Ana Carolina Cabral has uploaded a new patch set (#9) to the change originally created by Bao Zheng. ( https://review.coreboot.org/c/coreboot/+/85646?usp=email ) The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: src/soc/amd/cezzane: Rename PSP_AB_RECOVERY setting ...................................................................... src/soc/amd/cezzane: Rename PSP_AB_RECOVERY setting Fix PSP_AB_RECOVERY config name that was causing the boad to hang at 00000000. Change-Id: Iaf092c4f7005f30ac12f5fffffa60c7c9f8f2ccb Signed-off-by: Zheng Bao <fishbaozi(a)gmail.com> --- M src/soc/amd/cezanne/Kconfig M src/soc/amd/cezanne/Makefile.mk 2 files changed, 2 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/46/85646/9 -- To view, visit https://review.coreboot.org/c/coreboot/+/85646?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iaf092c4f7005f30ac12f5fffffa60c7c9f8f2ccb Gerrit-Change-Number: 85646 Gerrit-PatchSet: 9 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Zheng Bao Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Zheng Bao Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de>

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[S] Change in coreboot[main]: doc/internals/devicetree_language: multiple segment groups supported
by Maximilian Brune (Code Review) 08 Apr '25

08 Apr '25

Maximilian Brune has submitted this change. ( https://review.coreboot.org/c/coreboot/+/87206?usp=email ) Change subject: doc/internals/devicetree_language: multiple segment groups supported ...................................................................... doc/internals/devicetree_language: multiple segment groups supported coreboot supports more than just one PCI segment group by having more than one domain in the devicetree, so update the PCI device description. Change-Id: I9911b5e43732dd32638d540fcec6ca57b34d4fbc Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/87206 Reviewed-by: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Reviewed-by: Matt DeVillier <matt.devillier(a)gmail.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Maximilian Brune <maximilian.brune(a)9elements.com> --- M Documentation/internals/devicetree_language.md 1 file changed, 5 insertions(+), 5 deletions(-) Approvals: Matt DeVillier: Looks good to me, approved Felix Singer: Looks good to me, approved build bot (Jenkins): Verified Maximilian Brune: Looks good to me, approved diff --git a/Documentation/internals/devicetree_language.md b/Documentation/internals/devicetree_language.md index ab1b646..43a2233 100644 --- a/Documentation/internals/devicetree_language.md +++ b/Documentation/internals/devicetree_language.md @@ -973,11 +973,11 @@ Resources for all PCI devices are assigned automatically, or must be assigned in code if they're non-standard. -Currently, only a single segment is supported, but there is work to make -multiple different segments supported, each with a bus 0. Because the -bus is not specified, It's assumed that all pci devices that are not -behind a pci bridge device are on bus 0. If there are additional pci -busses in a chip, they can be added behind their bridge device. +Only a single segment group is supported per domain, but there can be multiple +domains to support the case of multiple segment groups, each with a bus 0. +Because the bus is not specified, It's assumed that all pci devices that are +not behind a pci bridge device are on bus 0. If there are additional pci busses +in a chip, they can be added behind their bridge device. Examples: -- To view, visit https://review.coreboot.org/c/coreboot/+/87206?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I9911b5e43732dd32638d540fcec6ca57b34d4fbc Gerrit-Change-Number: 87206 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[XS] Change in coreboot[main]: doc/internals/devicetree_language: describe I2C identifier
by Maximilian Brune (Code Review) 08 Apr '25

08 Apr '25

Maximilian Brune has submitted this change. ( https://review.coreboot.org/c/coreboot/+/87205?usp=email ) Change subject: doc/internals/devicetree_language: describe I2C identifier ...................................................................... doc/internals/devicetree_language: describe I2C identifier Even when the identifier of an I2C device doesn't have a '0x' prefix, it's still interpreted as a hexadecimal number. Change-Id: I0e5a7e39ac56e25499493a16eefa49e4f8d79337 Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/87205 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier(a)gmail.com> Reviewed-by: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Reviewed-by: Maximilian Brune <maximilian.brune(a)9elements.com> --- M Documentation/internals/devicetree_language.md 1 file changed, 2 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Maximilian Brune: Looks good to me, approved Matt DeVillier: Looks good to me, approved Felix Singer: Looks good to me, approved diff --git a/Documentation/internals/devicetree_language.md b/Documentation/internals/devicetree_language.md index d189844..ab1b646 100644 --- a/Documentation/internals/devicetree_language.md +++ b/Documentation/internals/devicetree_language.md @@ -690,6 +690,8 @@ * Introduced in: Initial sconfig implementation, pre coreboot 4.0 * Usage: `device I2c <identifier> [alias <alias ID>] <status modifier> ... end` +The identifier is the device's address encoded as hexadecimal number. + Example: ```text -- To view, visit https://review.coreboot.org/c/coreboot/+/87205?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I0e5a7e39ac56e25499493a16eefa49e4f8d79337 Gerrit-Change-Number: 87205 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[XS] Change in coreboot[main]: doc/internals/devicetree_language: eSPI doesn't support legacy DRQ
by Maximilian Brune (Code Review) 08 Apr '25

08 Apr '25

Maximilian Brune has submitted this change. ( https://review.coreboot.org/c/coreboot/+/87204?usp=email ) Change subject: doc/internals/devicetree_language: eSPI doesn't support legacy DRQ ...................................................................... doc/internals/devicetree_language: eSPI doesn't support legacy DRQ In contracts to the ISA and LPC bus, eSPI doesn't support legacy ISA-style DMA any more, so don't list eSPI as interface in the 'drq' chapter. The Intel document #841685 "Enhanced Serial Peripheral Interface (eSPI) Interface Base Specification (for Client and Server Platforms)" revision 1.6 says this about the eSPI interface: "However, 8237 DMA and Firmware Hub (FWH) are not supported over this interface." Change-Id: I69d4b09688699dfc984a42671abfe3804d30ade9 Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/87204 Reviewed-by: Matt DeVillier <matt.devillier(a)gmail.com> Reviewed-by: Maximilian Brune <maximilian.brune(a)9elements.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> --- M Documentation/internals/devicetree_language.md 1 file changed, 1 insertion(+), 1 deletion(-) Approvals: Felix Singer: Looks good to me, approved build bot (Jenkins): Verified Matt DeVillier: Looks good to me, approved Maximilian Brune: Looks good to me, approved diff --git a/Documentation/internals/devicetree_language.md b/Documentation/internals/devicetree_language.md index 0609559..d189844 100644 --- a/Documentation/internals/devicetree_language.md +++ b/Documentation/internals/devicetree_language.md @@ -444,7 +444,7 @@ * Usage: `drq 0x<register #> = <drq line>` Drq is used to configure a legacy DMA Request line register for a device -on a legacy bus - ISA/LPC/eSPI. +on a legacy bus - ISA/LPC. The drq configuration is only allowed inside a pnp block. -- To view, visit https://review.coreboot.org/c/coreboot/+/87204?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I69d4b09688699dfc984a42671abfe3804d30ade9 Gerrit-Change-Number: 87204 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[S] Change in coreboot[main]: doc/contributing/git_commit_messages: fix line length
by Maximilian Brune (Code Review) 08 Apr '25

08 Apr '25

Maximilian Brune has submitted this change. ( https://review.coreboot.org/c/coreboot/+/87203?usp=email ) Change subject: doc/contributing/git_commit_messages: fix line length ...................................................................... doc/contributing/git_commit_messages: fix line length The line length limit in the commit messages is 72 characters, not 75, so fix the value in the documentation. The 72 characters also matches what checkpatch checks for. Change-Id: I2ec0fbd78fd0b054eae7bf9d6bd30580f47deb8f Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/87203 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Maximilian Brune <maximilian.brune(a)9elements.com> Reviewed-by: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Reviewed-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M Documentation/contributing/git_commit_messages.md 1 file changed, 5 insertions(+), 5 deletions(-) Approvals: build bot (Jenkins): Verified Felix Singer: Looks good to me, approved Maximilian Brune: Looks good to me, approved Matt DeVillier: Looks good to me, approved diff --git a/Documentation/contributing/git_commit_messages.md b/Documentation/contributing/git_commit_messages.md index 4addf4c..a007b2a 100644 --- a/Documentation/contributing/git_commit_messages.md +++ b/Documentation/contributing/git_commit_messages.md @@ -13,14 +13,14 @@ ## Line length - The subject line should be <= 65 characters, with an absolute maximum - of 75 characters -- Prose in the commit message should be <= 75 characters -- If reflowing prose to 75 characters can reduce the length of the + of 72 characters +- Prose in the commit message should be <= 72 characters +- If reflowing prose to 72 characters can reduce the length of the commit message by 2 or more lines, please reflow it. Using the entire - 75 characters on a line when reasonable is recommended, but not + 72 characters on a line when reasonable is recommended, but not required. - Non-prose text in the body in the commit message does not need to be - wrapped at 75 characters. Examples: URLs, compiler output, or poetry. + wrapped at 72 characters. Examples: URLs, compiler output, or poetry. ## Both Subject & body -- To view, visit https://review.coreboot.org/c/coreboot/+/87203?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I2ec0fbd78fd0b054eae7bf9d6bd30580f47deb8f Gerrit-Change-Number: 87203 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[XS] Change in coreboot[main]: doc/internals/devicetree_language: eSPI doesn't support legacy DRQ
by Maximilian Brune (Code Review) 08 Apr '25

08 Apr '25

Attention is currently required from: Felix Held. Maximilian Brune has posted comments on this change by Felix Held. ( https://review.coreboot.org/c/coreboot/+/87204?usp=email ) Change subject: doc/internals/devicetree_language: eSPI doesn't support legacy DRQ ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/87204?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I69d4b09688699dfc984a42671abfe3804d30ade9 Gerrit-Change-Number: 87204 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Tue, 08 Apr 2025 19:06:22 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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