coreboot-gerrit April 2025

coreboot-gerrit@coreboot.org

1 participants
3140 discussions

[S] Change in coreboot[main]: doc/internals/devicetree_language: multiple segment groups supported
by Maximilian Brune (Code Review) 08 Apr '25

08 Apr '25

Attention is currently required from: Felix Held. Maximilian Brune has posted comments on this change by Felix Held. ( https://review.coreboot.org/c/coreboot/+/87206?usp=email ) Change subject: doc/internals/devicetree_language: multiple segment groups supported ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/87206?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I9911b5e43732dd32638d540fcec6ca57b34d4fbc Gerrit-Change-Number: 87206 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Tue, 08 Apr 2025 18:59:06 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

1 0

[XS] Change in coreboot[main]: soc/intel/cmn/cpu: Refactor USE_INTEL_FSP_MP_INIT enablement logic
by Jérémy Compostella (Code Review) 08 Apr '25

08 Apr '25

Attention is currently required from: Intel coreboot Reviewers, Subrata Banik. Jérémy Compostella has posted comments on this change by Subrata Banik. ( https://review.coreboot.org/c/coreboot/+/87161?usp=email ) Change subject: soc/intel/cmn/cpu: Refactor USE_INTEL_FSP_MP_INIT enablement logic ...................................................................... Patch Set 5: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/87161?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I9ecc7b50ed6a6b13c4ccde0a49f50a40b606a848 Gerrit-Change-Number: 87161 Gerrit-PatchSet: 5 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Comment-Date: Tue, 08 Apr 2025 18:58:29 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

1 0

[XS] Change in coreboot[main]: doc/internals/devicetree_language: describe I2C identifier
by Maximilian Brune (Code Review) 08 Apr '25

08 Apr '25

Attention is currently required from: Felix Held. Maximilian Brune has posted comments on this change by Felix Held. ( https://review.coreboot.org/c/coreboot/+/87205?usp=email ) Change subject: doc/internals/devicetree_language: describe I2C identifier ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/87205?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I0e5a7e39ac56e25499493a16eefa49e4f8d79337 Gerrit-Change-Number: 87205 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Tue, 08 Apr 2025 18:58:28 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

1 0

[S] Change in coreboot[main]: doc/contributing/git_commit_messages: fix line length
by Maximilian Brune (Code Review) 08 Apr '25

08 Apr '25

Attention is currently required from: Felix Held. Maximilian Brune has posted comments on this change by Felix Held. ( https://review.coreboot.org/c/coreboot/+/87203?usp=email ) Change subject: doc/contributing/git_commit_messages: fix line length ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/87203?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I2ec0fbd78fd0b054eae7bf9d6bd30580f47deb8f Gerrit-Change-Number: 87203 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Tue, 08 Apr 2025 18:56:44 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

1 0

[L] Change in coreboot[main]: doc/arch/x86: Add MP-Init documentation
by Maximilian Brune (Code Review) 08 Apr '25

08 Apr '25

Attention is currently required from: Angel Pons, Benjamin Doron, Felix Held, Felix Singer, Martin Roth, Patrick Rudolph. Maximilian Brune has posted comments on this change by Maximilian Brune. ( https://review.coreboot.org/c/coreboot/+/86772?usp=email ) Change subject: doc/arch/x86: Add MP-Init documentation ...................................................................... Patch Set 5: This change is ready for review. -- To view, visit https://review.coreboot.org/c/coreboot/+/86772?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I1d16d608981d83438999321b30c2921a526f307e Gerrit-Change-Number: 86772 Gerrit-PatchSet: 5 Gerrit-Owner: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Tue, 08 Apr 2025 18:48:01 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No

1 0

[M] Change in coreboot[main]: src/soc/amd/* : Move CPU init in common code
by Naresh Solanki (Code Review) 08 Apr '25

08 Apr '25

Naresh Solanki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/87214?usp=email ) Change subject: src/soc/amd/* : Move CPU init in common code ...................................................................... src/soc/amd/* : Move CPU init in common code AMD SoC from family 17h share common cpu init code. Move those to common/block/cpu/noncar/cpu.c TEST=Build for glinda SoC & check for boot. Change-Id: If53455f359302f368f7c979defa2c1088c5c2f16 Signed-off-by: Naresh Solanki <naresh.solanki(a)9elements.com> --- M src/soc/amd/cezanne/cpu.c M src/soc/amd/common/block/cpu/noncar/cpu.c M src/soc/amd/common/block/include/amdblocks/cpu.h M src/soc/amd/genoa_poc/cpu.c M src/soc/amd/glinda/cpu.c M src/soc/amd/mendocino/cpu.c M src/soc/amd/phoenix/cpu.c 7 files changed, 19 insertions(+), 45 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/14/87214/1 diff --git a/src/soc/amd/cezanne/cpu.c b/src/soc/amd/cezanne/cpu.c index 4f39aef..70aa191 100644 --- a/src/soc/amd/cezanne/cpu.c +++ b/src/soc/amd/cezanne/cpu.c @@ -10,16 +10,8 @@ _Static_assert(CONFIG_MAX_CPUS == 16, "Do not override MAX_CPUS. To reduce the number of " "available cores, use the downcore_mode and disable_smt devicetree settings instead."); -static void zen_2_3_init(struct device *dev) -{ - check_mca(); - set_cstate_io_addr(); - - amd_apply_microcode_patch(); -} - static struct device_operations cpu_dev_ops = { - .init = zen_2_3_init, + .init = amd_cpu_init, }; static struct cpu_device_id cpu_table[] = { diff --git a/src/soc/amd/common/block/cpu/noncar/cpu.c b/src/soc/amd/common/block/cpu/noncar/cpu.c index e67d669..c97e2f4 100644 --- a/src/soc/amd/common/block/cpu/noncar/cpu.c +++ b/src/soc/amd/common/block/cpu/noncar/cpu.c @@ -1,10 +1,12 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <amdblocks/cpu.h> +#include <amdblocks/mca.h> #include <arch/cpuid.h> #include <cpu/cpu.h> #include <cpu/x86/msr.h> #include <cpu/amd/cpuid.h> +#include <cpu/amd/microcode.h> #include <cpu/amd/msr.h> #include <cpu/amd/mtrr.h> #include <smbios.h> @@ -100,3 +102,14 @@ return (cpuid_ebx(CPUID_EBX_MEM_ENCRYPT) & CPUID_EBX_MEM_ENCRYPT_ADDR_BITS_MASK) >> CPUID_EBX_MEM_ENCRYPT_ADDR_BITS_SHIFT; } + +void amd_cpu_init(struct device *dev) +{ + if (CONFIG(SOC_AMD_COMMON_BLOCK_MCA_COMMON)) + check_mca(); + + set_cstate_io_addr(); + + if (CONFIG(SOC_AMD_COMMON_BLOCK_UCODE)) + amd_apply_microcode_patch(); +} diff --git a/src/soc/amd/common/block/include/amdblocks/cpu.h b/src/soc/amd/common/block/include/amdblocks/cpu.h index 4aa225b..ce0b2da 100644 --- a/src/soc/amd/common/block/include/amdblocks/cpu.h +++ b/src/soc/amd/common/block/include/amdblocks/cpu.h @@ -22,5 +22,6 @@ uint32_t get_pstate_core_freq(union pstate_msr pstate_reg); uint32_t get_pstate_core_uvolts(union pstate_msr pstate_reg); const acpi_cstate_t *get_cstate_config_data(size_t *size); +void amd_cpu_init(struct device *dev); #endif /* AMD_BLOCK_CPU_H */ diff --git a/src/soc/amd/genoa_poc/cpu.c b/src/soc/amd/genoa_poc/cpu.c index 241bec2..89e7ef6 100644 --- a/src/soc/amd/genoa_poc/cpu.c +++ b/src/soc/amd/genoa_poc/cpu.c @@ -7,16 +7,8 @@ #include <device/device.h> #include <soc/cpu.h> -static void model_19_init(struct device *dev) -{ - check_mca(); - set_cstate_io_addr(); - - amd_apply_microcode_patch(); -} - static struct device_operations cpu_dev_ops = { - .init = model_19_init, + .init = amd_cpu_init, }; static struct cpu_device_id cpu_table[] = { diff --git a/src/soc/amd/glinda/cpu.c b/src/soc/amd/glinda/cpu.c index a716127..2b49c41 100644 --- a/src/soc/amd/glinda/cpu.c +++ b/src/soc/amd/glinda/cpu.c @@ -12,16 +12,8 @@ _Static_assert(CONFIG_MAX_CPUS == 24, "Do not override MAX_CPUS. To reduce the number of " "available cores, use the downcore_mode and disable_smt devicetree settings instead."); -static void zen_2_3_init(struct device *dev) -{ - check_mca(); - set_cstate_io_addr(); - - amd_apply_microcode_patch(); -} - static struct device_operations cpu_dev_ops = { - .init = zen_2_3_init, + .init = amd_cpu_init, }; static struct cpu_device_id cpu_table[] = { diff --git a/src/soc/amd/mendocino/cpu.c b/src/soc/amd/mendocino/cpu.c index 842b04f..14e1b23 100644 --- a/src/soc/amd/mendocino/cpu.c +++ b/src/soc/amd/mendocino/cpu.c @@ -10,16 +10,8 @@ _Static_assert(CONFIG_MAX_CPUS == 8, "Do not override MAX_CPUS. To reduce the number of " "available cores, use the downcore_mode and disable_smt devicetree settings instead."); -static void zen_2_3_init(struct device *dev) -{ - check_mca(); - set_cstate_io_addr(); - - amd_apply_microcode_patch(); -} - static struct device_operations cpu_dev_ops = { - .init = zen_2_3_init, + .init = amd_cpu_init, }; static struct cpu_device_id cpu_table[] = { diff --git a/src/soc/amd/phoenix/cpu.c b/src/soc/amd/phoenix/cpu.c index 05dac9a..1e05413 100644 --- a/src/soc/amd/phoenix/cpu.c +++ b/src/soc/amd/phoenix/cpu.c @@ -12,16 +12,8 @@ _Static_assert(CONFIG_MAX_CPUS == 16, "Do not override MAX_CPUS. To reduce the number of " "available cores, use the downcore_mode and disable_smt devicetree settings instead."); -static void zen_2_3_init(struct device *dev) -{ - check_mca(); - set_cstate_io_addr(); - - amd_apply_microcode_patch(); -} - static struct device_operations cpu_dev_ops = { - .init = zen_2_3_init, + .init = amd_cpu_init, }; static struct cpu_device_id cpu_table[] = { -- To view, visit https://review.coreboot.org/c/coreboot/+/87214?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If53455f359302f368f7c979defa2c1088c5c2f16 Gerrit-Change-Number: 87214 Gerrit-PatchSet: 1 Gerrit-Owner: Naresh Solanki <naresh.solanki(a)9elements.com>

1 0

[XS] Change in coreboot[main]: cpu/x86/smm: Add support for exception handling
by Jérémy Compostella (Code Review) 08 Apr '25

08 Apr '25

Attention is currently required from: Patrick Rudolph, Shuo Liu. Jérémy Compostella has posted comments on this change by Patrick Rudolph. ( https://review.coreboot.org/c/coreboot/+/87208?usp=email ) Change subject: cpu/x86/smm: Add support for exception handling ...................................................................... Patch Set 1: (6 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/87208/comment/d2a38010_3cd64278?us… : PS1, Line 9: expception typoe https://review.coreboot.org/c/coreboot/+/87208/comment/9a95b184_46c1f7a5?us… : PS1, Line 10: it is https://review.coreboot.org/c/coreboot/+/87208/comment/ba69f4af_02cf1aa1?us… : PS1, Line 10: Allows This allows https://review.coreboot.org/c/coreboot/+/87208/comment/820c1a38_acd4b174?us… : PS1, Line 10: to narrow down for narrowing down https://review.coreboot.org/c/coreboot/+/87208/comment/a40fd7c1_9266e138?us… : PS1, Line 11: tripple triple https://review.coreboot.org/c/coreboot/+/87208/comment/b9de4e93_41f5d43d?us… : PS1, Line 11: faulting fault -- To view, visit https://review.coreboot.org/c/coreboot/+/87208?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I2ccaf8d23d508d773ce56912983884ad6832ede6 Gerrit-Change-Number: 87208 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Comment-Date: Tue, 08 Apr 2025 17:50:40 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

1 0

[XS] Change in coreboot[main]: soc/intel/meteorlake: Add missing minimum D-state for SMBUS
by Kapil Porwal (Code Review) 08 Apr '25

08 Apr '25

Attention is currently required from: Dinesh Gehlot, Eran Mitrani, Intel coreboot Reviewers, Jakub "Kuba" Czapiga, Jérémy Compostella, Sean Rhodes, Tarun. Kapil Porwal has posted comments on this change by Sean Rhodes. ( https://review.coreboot.org/c/coreboot/+/86605?usp=email ) Change subject: soc/intel/meteorlake: Add missing minimum D-state for SMBUS ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/86605?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I73f84c09bece297194813202f17666741ad33d3a Gerrit-Change-Number: 86605 Gerrit-PatchSet: 3 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Jakub "Kuba" Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Attention: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Jakub "Kuba" Czapiga <czapiga(a)google.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Tarun <tstuli(a)gmail.com> Gerrit-Comment-Date: Tue, 08 Apr 2025 16:59:02 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

1 0

[S] Change in coreboot[main]: mb/var/uldrenite: Configure descriptor for either MBVR or FIVR
by Jérémy Compostella (Code Review) 08 Apr '25

08 Apr '25

Jérémy Compostella has submitted this change. ( https://review.coreboot.org/c/coreboot/+/87033?usp=email ) ( 10 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: mb/var/uldrenite: Configure descriptor for either MBVR or FIVR ...................................................................... mb/var/uldrenite: Configure descriptor for either MBVR or FIVR Since we need to support both MBVR (MotherBoard Voltage Regulator) and FIVR (Fully Integrated Voltage Regulator) in this phase, the FIT setting is initially set to FIVR. This causes MBVR boards to have two voltage sources, potentially triggering OVP and leading to reboots during the boot process. The current build's main source is MBVR, so we want to use fw_config to dynamically adjust MFIT and MBVR with the current phase devices to ensure consistency in client devices settings. Refer to Intel#822618 and set PMC Descriptor Record 7, bit 30 (VCCANA VR Location) accordingly. And then CONFIGURE_DESCRIPTOR is a temporary workaround for the current phase. In the next phase, we will choose a specific setting for implementation. If there are any concerns, we use the board ID to restrict it. BUG=b:404126972 TEST=boot to ChromeOS Change-Id: I337574c8c55889ceb49b9f33625feadb48bd8890 Signed-off-by: John Su <john_su(a)compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/87033 Reviewed-by: Jérémy Compostella <jeremy.compostella(a)intel.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal(a)google.com> Reviewed-by: Dinesh Gehlot <digehlot(a)google.com> --- M src/mainboard/google/brya/Kconfig M src/mainboard/google/brya/variants/uldrenite/Makefile.mk M src/mainboard/google/brya/variants/uldrenite/variant.c 3 files changed, 31 insertions(+), 0 deletions(-) Approvals: Jérémy Compostella: Looks good to me, but someone else must approve Dinesh Gehlot: Looks good to me, but someone else must approve Kapil Porwal: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/mainboard/google/brya/Kconfig b/src/mainboard/google/brya/Kconfig index 8886901..5331f0e 100644 --- a/src/mainboard/google/brya/Kconfig +++ b/src/mainboard/google/brya/Kconfig @@ -669,6 +669,7 @@ select INTEL_GMA_HAVE_VBT config BOARD_GOOGLE_ULDRENITE + select ALDERLAKE_CONFIGURE_DESCRIPTOR select BOARD_GOOGLE_BASEBOARD_TRULO select CHROMEOS_WIFI_SAR if CHROMEOS select DRIVERS_WWAN_FM350GL diff --git a/src/mainboard/google/brya/variants/uldrenite/Makefile.mk b/src/mainboard/google/brya/variants/uldrenite/Makefile.mk index c31fa30..0f152af 100644 --- a/src/mainboard/google/brya/variants/uldrenite/Makefile.mk +++ b/src/mainboard/google/brya/variants/uldrenite/Makefile.mk @@ -1,6 +1,7 @@ ## SPDX-License-Identifier: GPL-2.0-only bootblock-y += gpio.c +bootblock-y += variant.c romstage-y += gpio.c romstage-y += memory.c ramstage-y += gpio.c diff --git a/src/mainboard/google/brya/variants/uldrenite/variant.c b/src/mainboard/google/brya/variants/uldrenite/variant.c index 4217996..cbaf20b 100644 --- a/src/mainboard/google/brya/variants/uldrenite/variant.c +++ b/src/mainboard/google/brya/variants/uldrenite/variant.c @@ -2,10 +2,12 @@ #include <baseboard/gpio.h> #include <baseboard/variants.h> +#include <boardid.h> #include <console/console.h> #include <delay.h> #include <fw_config.h> #include <sar.h> +#include <soc/bootblock.h> const char *get_wifi_sar_cbfs_filename(void) { @@ -75,3 +77,30 @@ printk(BIOS_INFO, "Configured External FIVR\n"); } } + +void variant_update_descriptor(void) +{ + uint32_t board_version = board_id(); + + /* b/404126972: Only this phase has M/B with both FIVR and MBVR. */ + if (board_version != 1) + return; + + /* VccanaVrLocation = "VCCANA is CPU FIVR" */ + struct descriptor_byte fivr_bytes[] = { + { 0xc33, 0x32 } + }; + + /* VccanaVrLocation = "VCCANA is Platform VR" */ + struct descriptor_byte mbvr_bytes[] = { + { 0xc33, 0x72 } + }; + + if (fw_config_probe(FW_CONFIG(EXT_VR, EXT_VR_PRESENT))) { + printk(BIOS_INFO, "Configuring descriptor for MBVR\n"); + configure_descriptor(mbvr_bytes, ARRAY_SIZE(mbvr_bytes)); + } else { + printk(BIOS_INFO, "Configuring descriptor for FIVR\n"); + configure_descriptor(fivr_bytes, ARRAY_SIZE(fivr_bytes)); + } +} -- To view, visit https://review.coreboot.org/c/coreboot/+/87033?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I337574c8c55889ceb49b9f33625feadb48bd8890 Gerrit-Change-Number: 87033 Gerrit-PatchSet: 13 Gerrit-Owner: John Su <john_su(a)compal.corp-partner.google.com> Gerrit-Reviewer: Ben Kao <ben.kao(a)intel.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Jamie Chen <jamie.chen(a)intel.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-CC: Jamie Chen <jamie_chen(a)compal.corp-partner.google.com>

1 0

[XS] Change in coreboot[main]: soc/intel/alderlake: Fix incompatible pointer-to-integer conversion
by Jérémy Compostella (Code Review) 08 Apr '25

08 Apr '25

Jérémy Compostella has submitted this change. ( https://review.coreboot.org/c/coreboot/+/87091?usp=email ) Change subject: soc/intel/alderlake: Fix incompatible pointer-to-integer conversion ...................................................................... soc/intel/alderlake: Fix incompatible pointer-to-integer conversion Call update_descriptor, but the builder detected an incompatible pointer to integer conversion error, so upload CL to fix. BUG=b:404126972 TEST=boot to ChromeOS Change-Id: I1f8f19c6bb4636729ffe7be836c21db9a68d63d0 Signed-off-by: John Su <john_su(a)compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/87091 Reviewed-by: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal(a)google.com> Reviewed-by: Jayvik Desai <jayvik(a)google.com> Reviewed-by: Jérémy Compostella <jeremy.compostella(a)intel.com> --- M src/soc/intel/alderlake/bootblock/update_descriptor.c 1 file changed, 2 insertions(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Kapil Porwal: Looks good to me, approved Jayvik Desai: Looks good to me, but someone else must approve Dtrain Hsu: Looks good to me, approved Jérémy Compostella: Looks good to me, but someone else must approve diff --git a/src/soc/intel/alderlake/bootblock/update_descriptor.c b/src/soc/intel/alderlake/bootblock/update_descriptor.c index 42c4ee2..ee94894 100644 --- a/src/soc/intel/alderlake/bootblock/update_descriptor.c +++ b/src/soc/intel/alderlake/bootblock/update_descriptor.c @@ -23,13 +23,13 @@ static bool is_descriptor_writeable(uint8_t *desc) { /* Check flash has valid signature */ - if (read32p(desc + FLASH_SIGN_OFFSET) != FLASH_VAL_SIGN) { + if (read32p((uintptr_t)(desc + FLASH_SIGN_OFFSET)) != FLASH_VAL_SIGN) { printk(BIOS_ERR, "Flash Descriptor is not valid\n"); return false; } /* Check host has write access to the Descriptor Region */ - if (!((read32p(desc + FLMSTR1) >> FLMSTR_WR_SHIFT_V2) & BIT(0))) { + if (!((read32p((uintptr_t)(desc + FLMSTR1)) >> FLMSTR_WR_SHIFT_V2) & BIT(0))) { printk(BIOS_ERR, "Host doesn't have write access to Descriptor Region\n"); return false; } -- To view, visit https://review.coreboot.org/c/coreboot/+/87091?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I1f8f19c6bb4636729ffe7be836c21db9a68d63d0 Gerrit-Change-Number: 87091 Gerrit-PatchSet: 6 Gerrit-Owner: John Su <john_su(a)compal.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jamie Chen <jamie_chen(a)compal.corp-partner.google.com> Gerrit-CC: Van Chen <van_chen(a)compal.corp-partner.google.com>

1 0

Jump to page:

2025

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit April 2025