coreboot-gerrit April 2025

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[XS] Change in coreboot[main]: mb/starlabs/starbook/tgl: Change SSD Enable GPIO to PLTRST
by Matt DeVillier (Code Review) 08 Apr '25

08 Apr '25

Attention is currently required from: Sean Rhodes. Matt DeVillier has posted comments on this change by Sean Rhodes. ( https://review.coreboot.org/c/coreboot/+/87213?usp=email ) Change subject: mb/starlabs/starbook/tgl: Change SSD Enable GPIO to PLTRST ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/87213?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If4a406af13005ba4532091d0c5c75f5198e04ff4 Gerrit-Change-Number: 87213 Gerrit-PatchSet: 2 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Comment-Date: Tue, 08 Apr 2025 16:17:02 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[XS] Change in coreboot[main]: mb/starlabs/starbook/tgl: Change SSD Enable GPIO to PLTRST
by Sean Rhodes (Code Review) 08 Apr '25

08 Apr '25

Attention is currently required from: Matt DeVillier. Hello Matt DeVillier, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/87213?usp=email to look at the new patch set (#2). Change subject: mb/starlabs/starbook/tgl: Change SSD Enable GPIO to PLTRST ...................................................................... mb/starlabs/starbook/tgl: Change SSD Enable GPIO to PLTRST Change the SSD Enable GPIO to PLTRST, as having it configure to DEEP, renders the SSD inaccessible on S3 exit as it conflicts with the RTD3 driver. Change-Id: If4a406af13005ba4532091d0c5c75f5198e04ff4 Signed-off-by: Sean Rhodes <sean(a)starlabs.systems> --- M src/mainboard/starlabs/starbook/variants/tgl/gpio.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/13/87213/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/87213?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If4a406af13005ba4532091d0c5c75f5198e04ff4 Gerrit-Change-Number: 87213 Gerrit-PatchSet: 2 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com>

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[XS] Change in coreboot[main]: mb/starlabs/starbook/tgl: Change SSD Enable GPIO to PLTRST
by Sean Rhodes (Code Review) 08 Apr '25

08 Apr '25

Sean Rhodes has posted comments on this change by Sean Rhodes. ( https://review.coreboot.org/c/coreboot/+/87213?usp=email ) Change subject: mb/starlabs/starbook/tgl: Change SSD Enable GPIO to PLTRST ...................................................................... Set Ready For Review -- To view, visit https://review.coreboot.org/c/coreboot/+/87213?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If4a406af13005ba4532091d0c5c75f5198e04ff4 Gerrit-Change-Number: 87213 Gerrit-PatchSet: 1 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Comment-Date: Tue, 08 Apr 2025 16:02:02 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No

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[S] Change in coreboot[main]: mb/google/fatcat/var/fatcat: Implement barrel jack presence check
by YH Lin (Code Review) 08 Apr '25

08 Apr '25

Attention is currently required from: Jayvik Desai, Kapil Porwal, Pranava Y N, Subrata Banik, Wonkyu Kim. YH Lin has posted comments on this change by Subrata Banik. ( https://review.coreboot.org/c/coreboot/+/87207?usp=email ) Change subject: mb/google/fatcat/var/fatcat: Implement barrel jack presence check ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/87207?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I68507034cfbf4caa8e5c2ac9c7bebf758a5a5439 Gerrit-Change-Number: 87207 Gerrit-PatchSet: 2 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: YH Lin <yueherngl(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com> Gerrit-Comment-Date: Tue, 08 Apr 2025 15:56:34 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[S] Change in coreboot[main]: payloads/external/iPXE/: Allow building EFI target
by Martin L Roth (Code Review) 08 Apr '25

08 Apr '25

Attention is currently required from: Filip Lewiński, Krystian Hebel, Maciej Pijanowski, Michał Kopeć, Michał Żygowski, Paul Menzel. Martin L Roth has posted comments on this change by Filip Lewiński. ( https://review.coreboot.org/c/coreboot/+/83385?usp=email ) Change subject: payloads/external/iPXE/: Allow building EFI target ...................................................................... Patch Set 4: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/83385?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I7f247a59a65aeb18a67475d4d543f519af88aeb9 Gerrit-Change-Number: 83385 Gerrit-PatchSet: 4 Gerrit-Owner: Filip Lewiński <filip.lewinski(a)3mdeb.com> Gerrit-Reviewer: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-Reviewer: Maciej Pijanowski <maciej.pijanowski(a)3mdeb.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-CC: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Maciej Pijanowski <maciej.pijanowski(a)3mdeb.com> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Filip Lewiński <filip.lewinski(a)3mdeb.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Attention: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-Comment-Date: Tue, 08 Apr 2025 15:16:54 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[S] Change in coreboot[main]: payloads/external/iPXE/: Allow building EFI target
by Martin L Roth (Code Review) 08 Apr '25

08 Apr '25

Attention is currently required from: Filip Lewiński, Krystian Hebel, Maciej Pijanowski, Michał Kopeć, Michał Żygowski, Paul Menzel. Martin L Roth has posted comments on this change by Filip Lewiński. ( https://review.coreboot.org/c/coreboot/+/83385?usp=email ) Change subject: payloads/external/iPXE/: Allow building EFI target ...................................................................... Patch Set 4: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/83385/comment/3dcc0568_a1a54cd0?us… : PS4, Line 8: Maybe add what you put into the Kconfig help here? -- To view, visit https://review.coreboot.org/c/coreboot/+/83385?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I7f247a59a65aeb18a67475d4d543f519af88aeb9 Gerrit-Change-Number: 83385 Gerrit-PatchSet: 4 Gerrit-Owner: Filip Lewiński <filip.lewinski(a)3mdeb.com> Gerrit-Reviewer: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-Reviewer: Maciej Pijanowski <maciej.pijanowski(a)3mdeb.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-CC: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Maciej Pijanowski <maciej.pijanowski(a)3mdeb.com> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Filip Lewiński <filip.lewinski(a)3mdeb.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Attention: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-Comment-Date: Tue, 08 Apr 2025 15:16:48 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[S] Change in coreboot[main]: util/lint: Add lint file for gofmt
by Martin L Roth (Code Review) 08 Apr '25

08 Apr '25

Attention is currently required from: Maximilian Brune. Martin L Roth has posted comments on this change by Maximilian Brune. ( https://review.coreboot.org/c/coreboot/+/87211?usp=email ) Change subject: util/lint: Add lint file for gofmt ...................................................................... Patch Set 2: (1 comment) File util/lint/lint-stable-031-gofmt: https://review.coreboot.org/c/coreboot/+/87211/comment/707cd7a4_f8ba515d?us… : PS2, Line 21: log HEAD~..HEAD --format= --name-only `git ls-files util/intelp2m`? -- To view, visit https://review.coreboot.org/c/coreboot/+/87211?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I9c75fc0bf20a2625ddae43b0472a6586ae78f213 Gerrit-Change-Number: 87211 Gerrit-PatchSet: 2 Gerrit-Owner: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Comment-Date: Tue, 08 Apr 2025 15:12:09 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[XS] Change in coreboot[main]: mb/google/fatcat/var/felino: Use GPP_E03 for EC_SYNC_IRQ
by Subrata Banik (Code Review) 08 Apr '25

08 Apr '25

Attention is currently required from: Jayvik Desai, Kapil Porwal, Pranava Y N, Tongtong Pan, Weimin Wu. Subrata Banik has posted comments on this change by Tongtong Pan. ( https://review.coreboot.org/c/coreboot/+/87210?usp=email ) Change subject: mb/google/fatcat/var/felino: Use GPP_E03 for EC_SYNC_IRQ ...................................................................... Patch Set 1: (1 comment) File src/mainboard/google/fatcat/variants/felino/gpio.c: https://review.coreboot.org/c/coreboot/+/87210/comment/df0da4c3_e233d5bc?us… : PS1, Line 209: NC EC_SYNC_IRQ -- To view, visit https://review.coreboot.org/c/coreboot/+/87210?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If7d120fcf2de8dbbbc399d2ead4e294d11ea8a14 Gerrit-Change-Number: 87210 Gerrit-PatchSet: 1 Gerrit-Owner: Tongtong Pan <pantongtong(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Weimin Wu <wuweimin(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Dolan Liu <liuyong5(a)huaqin.corp-partner.google.com> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Weimin Wu <wuweimin(a)huaqin.corp-partner.google.com> Gerrit-Attention: Tongtong Pan <pantongtong(a)huaqin.corp-partner.google.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com> Gerrit-Comment-Date: Tue, 08 Apr 2025 14:46:47 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[M] Change in coreboot[main]: Documentation/util/intelp2m: Add info for developers
by Maximilian Brune (Code Review) 08 Apr '25

08 Apr '25

Attention is currently required from: Maxim Polyakov. Maximilian Brune has posted comments on this change by Maxim Polyakov. ( https://review.coreboot.org/c/coreboot/+/85791?usp=email ) Change subject: Documentation/util/intelp2m: Add info for developers ...................................................................... Patch Set 4: (1 comment) File Documentation/util/intelp2m/index.md: https://review.coreboot.org/c/coreboot/+/85791/comment/62b38b22_1a8089e7?us… : PS4, Line 275: It depends on the changes: the `major` is incremented if a new platform is added, `minor` - if > So, to clarify, you're suggesting the following rule: […] I honestly don't think we need a major/minor version for a tooling such as this one. We also don't have one for our other utilities, but I am fine either way. In any case the changes that I am suggesting are the following: `major` - incompatible API changes (e.g. remove or update a command line option) `minor` - new platform, new feature or adding a new command line option -- To view, visit https://review.coreboot.org/c/coreboot/+/85791?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I9cc886e607c1aba92b94e06419d45d9581371065 Gerrit-Change-Number: 85791 Gerrit-PatchSet: 4 Gerrit-Owner: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Attention: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-Comment-Date: Tue, 08 Apr 2025 13:19:44 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Maxim Polyakov <max.senia.poliak(a)gmail.com> Comment-In-Reply-To: Maximilian Brune <maximilian.brune(a)9elements.com>

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[M] Change in coreboot[main]: mb/google/nissa/var/telith: Support x32 memory configuration
by Kun Liu (Code Review) 08 Apr '25

08 Apr '25

Kun Liu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/87212?usp=email ) Change subject: mb/google/nissa/var/telith: Support x32 memory configuration ...................................................................... mb/google/nissa/var/telith: Support x32 memory configuration Use GPP_E19 level to determine whether x32 memory configuration is supported. BUG=b:405303038 TEST=emerge-nissa coreboot chromeos-bootimage Change-Id: I969fea2aba858f76870c1a31ad4bd884ec9b6ff3 Signed-off-by: Kun Liu <liukun11(a)huaqin.corp-partner.google.com> --- M src/mainboard/google/brya/Kconfig M src/mainboard/google/brya/variants/telith/Makefile.mk M src/mainboard/google/brya/variants/telith/gpio.c A src/mainboard/google/brya/variants/telith/memory.c 4 files changed, 133 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/12/87212/1 diff --git a/src/mainboard/google/brya/Kconfig b/src/mainboard/google/brya/Kconfig index 8886901..05c9a92 100644 --- a/src/mainboard/google/brya/Kconfig +++ b/src/mainboard/google/brya/Kconfig @@ -631,6 +631,7 @@ select DRIVERS_INTEL_MIPI_CAMERA select MAINBOARD_HAS_GOOGLE_STRAUSS_KEYBOARD select SOC_INTEL_TWINLAKE + select ENFORCE_MEM_CHANNEL_DISABLE config BOARD_GOOGLE_TEREID select BOARD_GOOGLE_BASEBOARD_NISSA diff --git a/src/mainboard/google/brya/variants/telith/Makefile.mk b/src/mainboard/google/brya/variants/telith/Makefile.mk index e7ef021..b67f308 100644 --- a/src/mainboard/google/brya/variants/telith/Makefile.mk +++ b/src/mainboard/google/brya/variants/telith/Makefile.mk @@ -1,6 +1,7 @@ # SPDX-License-Identifier: GPL-2.0-only bootblock-y += gpio.c +romstage-y += memory.c romstage-y += gpio.c ramstage-y += gpio.c diff --git a/src/mainboard/google/brya/variants/telith/gpio.c b/src/mainboard/google/brya/variants/telith/gpio.c index 0043111..75f7617 100644 --- a/src/mainboard/google/brya/variants/telith/gpio.c +++ b/src/mainboard/google/brya/variants/telith/gpio.c @@ -69,6 +69,9 @@ /* R7 : DMIC_DATA_1A ==> NC */ PAD_NC_LOCK(GPP_R7, NONE, LOCK_CONFIG), + /* E19 : DDP1_CTRLDATA ==> GPP_E19_STRAP */ + PAD_CFG_GPI_LOCK(GPP_E19, DN_20K, LOCK_CONFIG), + /* Configure the virtual CNVi Bluetooth I2S GPIO pads */ /* BT_I2S_BCLK */ PAD_CFG_NF(GPP_VGPIO_30, NONE, DEEP, NF3), @@ -112,6 +115,8 @@ PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2), /* H11 : UART0_TXD ==> UART_SOC_TX_DBG_RX */ PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2), + /* E19 : DDP1_CTRLDATA ==> GPP_E19_STRAP */ + PAD_CFG_GPI_LOCK(GPP_E19, DN_20K, LOCK_CONFIG), }; const struct pad_config *variant_gpio_override_table(size_t *num) diff --git a/src/mainboard/google/brya/variants/telith/memory.c b/src/mainboard/google/brya/variants/telith/memory.c new file mode 100644 index 0000000..7ac66b4 --- /dev/null +++ b/src/mainboard/google/brya/variants/telith/memory.c @@ -0,0 +1,126 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <baseboard/gpio.h> +#include <baseboard/variants.h> +#include <gpio.h> +#include <soc/romstage.h> + +static const struct mb_cfg variant_memcfg = { + .type = MEM_TYPE_LP5X, + + .rcomp = { + /* Baseboard uses only 100ohm Rcomp resistors */ + .resistor = 100, + }, + + /* DQ byte map */ + .lpx_dq_map = { + .ddr0 = { + .dq0 = { 12, 9, 10, 11, 14, 13, 8, 15 }, + .dq1 = { 3, 1, 2, 0, 4, 7, 5, 6 }, + }, + .ddr1 = { + .dq0 = { 3, 1, 2, 0, 4, 7, 5, 6 }, + .dq1 = { 13, 9, 8, 11, 10, 14, 15, 12 }, + }, + .ddr2 = { + .dq0 = { 2, 1, 3, 0, 4, 6, 5, 7 }, + .dq1 = { 8, 9, 10, 11, 13, 14, 12, 15 }, + }, + .ddr3 = { + .dq0 = { 3, 0, 1, 2, 5, 6, 4, 7 }, + .dq1 = { 13, 9, 11, 8, 14, 15, 10, 12 }, + }, + .ddr4 = { + .dq0 = { 12, 9, 10, 11, 14, 13, 8, 15 }, + .dq1 = { 3, 1, 2, 0, 4, 7, 5, 6 }, + }, + .ddr5 = { + .dq0 = { 3, 1, 2, 0, 4, 7, 5, 6 }, + .dq1 = { 13, 9, 8, 11, 10, 14, 15, 12 }, + }, + .ddr6 = { + .dq0 = { 2, 1, 3, 0, 4, 6, 5, 7 }, + .dq1 = { 8, 9, 10, 11, 13, 14, 12, 15 }, + }, + .ddr7 = { + .dq0 = { 3, 0, 1, 2, 5, 6, 4, 7 }, + .dq1 = { 13, 9, 11, 8, 14, 15, 10, 12 }, + }, + }, + + /* DQS CPU<>DRAM map */ + .lpx_dqs_map = { + .ddr0 = { .dqs0 = 1, .dqs1 = 0 }, + .ddr1 = { .dqs0 = 0, .dqs1 = 1 }, + .ddr2 = { .dqs0 = 0, .dqs1 = 1 }, + .ddr3 = { .dqs0 = 0, .dqs1 = 1 }, + .ddr4 = { .dqs0 = 1, .dqs1 = 0 }, + .ddr5 = { .dqs0 = 0, .dqs1 = 1 }, + .ddr6 = { .dqs0 = 0, .dqs1 = 1 }, + .ddr7 = { .dqs0 = 0, .dqs1 = 1 }, + }, + + .lp5x_config = { + .ccc_config = 0xff, + }, + + .ect = 1, /* Early Command Training */ + + .UserBd = BOARD_TYPE_MOBILE, +}; + +const struct mb_cfg *variant_memory_params(void) +{ + return &variant_memcfg; +} + +int variant_memory_sku(void) +{ + /* + * Memory configuration board straps + * GPIO_MEM_CONFIG_0 GPP_E1 + * GPIO_MEM_CONFIG_1 GPP_E2 + * GPIO_MEM_CONFIG_2 GPP_E3 + */ + gpio_t spd_gpios[] = { + GPP_E1, + GPP_E2, + GPP_E3, + }; + + return gpio_base2_value(spd_gpios, ARRAY_SIZE(spd_gpios)); +} + +bool variant_is_half_populated(void) +{ + /* + * Ideally half_populated is used in platforms with multiple channels to + * enable only one half of the channel. Alder Lake N has single channel, + * and it would require for new structures to be defined in meminit block + * driver for LPx memory configurations. In order to avoid adding new + * structures, set half_populated to true. This has the same effect as + * having single channel with 64-bit width. + */ + return true; +} + +void variant_get_spd_info(struct mem_spd *spd_info) +{ + spd_info->topo = MEM_TOPO_MEMORY_DOWN; + spd_info->cbfs_index = variant_memory_sku(); +} + +uint8_t mb_get_channel_disable_mask(void) +{ + /* + * GPP_E19 High -> One RAM Chip + * GPP_E19 Low -> Two RAM Chip + */ + if (gpio_get(GPP_E19)) { + /* Disable all other channels except first two on each controller */ + return (BIT(2) | BIT(3)); + } + + return 0; +} -- To view, visit https://review.coreboot.org/c/coreboot/+/87212?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I969fea2aba858f76870c1a31ad4bd884ec9b6ff3 Gerrit-Change-Number: 87212 Gerrit-PatchSet: 1 Gerrit-Owner: Kun Liu <liukun11(a)huaqin.corp-partner.google.com>

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coreboot-gerrit April 2025