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Change subject: mb/google/rauru: Support the panel with a load switch control
......................................................................
Patch Set 1: Code-Review+1
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/86282/comment/682c6945_dbf0e86b?us… :
PS1, Line 7: Support the panel with a load switch control
:
: The Rauru follower device goes `load switch` path to ensure the
: discharge timing meets the panel power-off sequence. Refactor panel.c to
: support this hardware change.
Mention OLED once?
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Change subject: mb/google/fatcat/var/francka: Modify USB-A phy configuration
......................................................................
Patch Set 2:
(3 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/86285/comment/96f5d7fd_4c7c6ced?us… :
PS2, Line 7: Modify USB-A phy configuration
Please be more specific. No idea if my terminology is correct:
> Decrease trace length of USB-A phy to short
https://review.coreboot.org/c/coreboot/+/86285/comment/24078869_caae9d74?us… :
PS2, Line 9: the USB PHY settings need to be modified
Please be more specific, and also mention the source for this. Were the schematics incorrect?
https://review.coreboot.org/c/coreboot/+/86285/comment/b86e7cad_3a6c9d90?us… :
PS2, Line 9: To resolve the issue of not being able to boot from USB on Francka
Any error in the logs?
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Hello Jayvik Desai, Kapil Porwal, Pranava Y N, Subrata Banik,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/86285?usp=email
to look at the new patch set (#2).
Change subject: mb/google/fatcat/var/francka: Modify USB-A phy configuration
......................................................................
mb/google/fatcat/var/francka: Modify USB-A phy configuration
To resolve the issue of not being able to boot from USB on Francka, the USB PHY settings need to be modified.
BUG=b:394206896
TEST=Build and test Type-A port function works fine
Change-Id: I140b8a2047768d3aeb0d5919aad998bd9dcd099f
Signed-off-by: Amanda Huang <amanda_hwang(a)compal.corp-partner.google.com>
---
M src/mainboard/google/fatcat/variants/francka/overridetree.cb
1 file changed, 2 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/85/86285/2
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Amanda Hwang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/86285?usp=email )
Change subject: mb/google/fatcat/var/francka: Modify USB-A phy configuration
......................................................................
mb/google/fatcat/var/francka: Modify USB-A phy configuration
To resolve the issue of not being able to boot from USB on Francka, the USB
PHY settings need to be modified.
BUG=b:394206896
TEST=Build and test Type-A port function works fine
Change-Id: I140b8a2047768d3aeb0d5919aad998bd9dcd099f
Signed-off-by: Amanda Huang <amanda_hwang(a)compal.corp-partner.google.com>
---
M src/mainboard/google/fatcat/variants/francka/overridetree.cb
1 file changed, 2 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/85/86285/1
diff --git a/src/mainboard/google/fatcat/variants/francka/overridetree.cb b/src/mainboard/google/fatcat/variants/francka/overridetree.cb
index 9d2dd2f..dc76b85 100644
--- a/src/mainboard/google/fatcat/variants/francka/overridetree.cb
+++ b/src/mainboard/google/fatcat/variants/francka/overridetree.cb
@@ -28,9 +28,9 @@
register "max_dram_speed_mts" = "7467"
- register "usb2_ports[1]" = "USB2_PORT_MID(OC0)" # Type-A Port A0
+ register "usb2_ports[1]" = "USB2_PORT_SHORT(OC0)" # Type-A Port A0
register "usb2_ports[3]" = "USB2_PORT_TYPE_C(OC_SKIP)" # USB2_C0
- register "usb2_ports[4]" = "USB2_PORT_MID(OC0)" # Type-A Port A1
+ register "usb2_ports[4]" = "USB2_PORT_SHORT(OC0)" # Type-A Port A1
register "usb2_ports[5]" = "USB2_PORT_TYPE_C(OC_SKIP)" # USB2_C1
register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)" # USB HUB (USB2 Camera)
register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # CNVi BT or discrete BT
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Attention is currently required from: Julius Werner, Lean Sheng Tan.
Benjamin Doron has posted comments on this change by Benjamin Doron. ( https://review.coreboot.org/c/coreboot/+/85643?usp=email )
Change subject: commonlib/device_tree.c: Add a function that reads FDT ints
......................................................................
Patch Set 7:
(3 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/85643/comment/7dbecf08_378dcda8?us… :
PS5, Line 13: /
> typo
Done
File src/commonlib/device_tree.c:
https://review.coreboot.org/c/coreboot/+/85643/comment/a964e00c_8b4d8d58?us… :
PS5, Line 266: printk(BIOS_ERR, "FDT integer property of size %u @%p doesn't match expected cell count %u\n", prop->size, prop->data, cells);
> Should at least drop the arguments after the format string into a continuation line.
Done
File src/commonlib/device_tree.c:
https://review.coreboot.org/c/coreboot/+/85643/comment/1b0e6277_05d06b7a?us… :
PS6, Line 267: printk(BIOS_DEBUG, "FDT integer property of size %u @%p is %u cells\n", prop->size, prop->data, cells);
> I don't think we'll want to print this every time, it's just gonna be spam.
True, it's a very low-level detail about the FDT and also useful for debugging this code. I'll drop it.
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Hello Julius Werner, Lean Sheng Tan, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/85643?usp=email
to look at the new patch set (#7).
The following approvals got outdated and were removed:
Verified+1 by build bot (Jenkins)
Change subject: commonlib/device_tree.c: Add a function that reads FDT ints
......................................................................
commonlib/device_tree.c: Add a function that reads FDT ints
Follow the recommendation at
https://review.coreboot.org/c/coreboot/+/84796/comment/21f615a2_99a41147/
and implement support for reading integer properties generically, using
their size to determine how much to read. This will be used for reading
`load`, `entry` and perhaps others.
Change-Id: I02d27eb5e23dfbfc1404d209ee8d60968e22bb80
Signed-off-by: Benjamin Doron <benjamin.doron(a)9elements.com>
---
M src/commonlib/device_tree.c
M src/commonlib/include/commonlib/device_tree.h
2 files changed, 22 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/43/85643/7
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Matt DeVillier has submitted this change. ( https://review.coreboot.org/c/coreboot/+/86257?usp=email )
Change subject: soc/intel/{adl,tgl}: Set IOM ACPI device to hidden/on
......................................................................
soc/intel/{adl,tgl}: Set IOM ACPI device to hidden/on
This prevents Windows from displaying the IOM device in Device Manager
as an unknown device with no driver available, and brings Alderlake
and Tigerlake in line with Meteorlake and Pantherlake.
TEST=build/boot Win11 on starlabs/starlite_adl, verify IOM device
not shown as unknown device in Device Manager.
Change-Id: Ib31018173126737b36a6e0d822eba2ebc9c42306
Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86257
Reviewed-by: Jérémy Compostella <jeremy.compostella(a)intel.com>
Reviewed-by: Sean Rhodes <sean(a)starlabs.systems>
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
---
M src/soc/intel/alderlake/acpi/tcss.asl
M src/soc/intel/tigerlake/acpi/tcss.asl
2 files changed, 4 insertions(+), 2 deletions(-)
Approvals:
Jérémy Compostella: Looks good to me, approved
Sean Rhodes: Looks good to me, approved
build bot (Jenkins): Verified
diff --git a/src/soc/intel/alderlake/acpi/tcss.asl b/src/soc/intel/alderlake/acpi/tcss.asl
index 6f8edda..2d09c64 100644
--- a/src/soc/intel/alderlake/acpi/tcss.asl
+++ b/src/soc/intel/alderlake/acpi/tcss.asl
@@ -331,7 +331,8 @@
Name (_CRS, ResourceTemplate () {
Memory32Fixed (ReadWrite, IOM_BASE_ADDRESS, IOM_BASE_SIZE)
})
- Name (_STA, 0xF)
+ /* ACPI_STATUS_DEVICE_HIDDEN_ON */
+ Name (_STA, 0xB)
}
/*
diff --git a/src/soc/intel/tigerlake/acpi/tcss.asl b/src/soc/intel/tigerlake/acpi/tcss.asl
index 588ed5e..f02a4a3 100644
--- a/src/soc/intel/tigerlake/acpi/tcss.asl
+++ b/src/soc/intel/tigerlake/acpi/tcss.asl
@@ -331,7 +331,8 @@
Name (_CRS, ResourceTemplate () {
Memory32Fixed (ReadWrite, IOM_BASE_ADDRESS, IOM_BASE_SIZE)
})
- Name (_STA, 0xF)
+ /* ACPI_STATUS_DEVICE_HIDDEN_ON */
+ Name (_STA, 0xB)
}
/*
--
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Matt DeVillier has submitted this change. ( https://review.coreboot.org/c/coreboot/+/86256?usp=email )
Change subject: soc/intel/{adl,tgl}: Set PMC ACPI device to hidden/on
......................................................................
soc/intel/{adl,tgl}: Set PMC ACPI device to hidden/on
This prevents Windows from displaying the PMC device in Device Manager
as an unknown device with no driver available, and brings Alderlake
and Tigerlake in line with Meteorlake and Pantherlake.
TEST=build/boot Win11 on starlabs/starlite_adl, verify PMC device
not shown as unknown device in Device Manager.
Change-Id: I4bd62d113455fab7fcb272d85f70e6a185e53b74
Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86256
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
Reviewed-by: Jérémy Compostella <jeremy.compostella(a)intel.com>
Reviewed-by: Sean Rhodes <sean(a)starlabs.systems>
---
M src/soc/intel/alderlake/pmc.c
M src/soc/intel/tigerlake/pmc.c
2 files changed, 2 insertions(+), 2 deletions(-)
Approvals:
Sean Rhodes: Looks good to me, approved
build bot (Jenkins): Verified
Jérémy Compostella: Looks good to me, approved
diff --git a/src/soc/intel/alderlake/pmc.c b/src/soc/intel/alderlake/pmc.c
index 8930a06..58c9fa8 100644
--- a/src/soc/intel/alderlake/pmc.c
+++ b/src/soc/intel/alderlake/pmc.c
@@ -108,7 +108,7 @@
acpigen_write_name_string("_HID", PMC_HID);
acpigen_write_name_string("_DDN", "Intel(R) Alder Lake IPC Controller");
- acpigen_write_STA(ACPI_STATUS_DEVICE_ALL_ON);
+ acpigen_write_STA(ACPI_STATUS_DEVICE_HIDDEN_ON);
/*
* Part of the PCH's reserved 32 MB MMIO range (0xFC800000 - 0xFE7FFFFF).
diff --git a/src/soc/intel/tigerlake/pmc.c b/src/soc/intel/tigerlake/pmc.c
index 8912cb3..8846c94 100644
--- a/src/soc/intel/tigerlake/pmc.c
+++ b/src/soc/intel/tigerlake/pmc.c
@@ -107,7 +107,7 @@
acpigen_write_name_string("_HID", PMC_HID);
acpigen_write_name_string("_DDN", "Intel(R) Tiger Lake IPC Controller");
- acpigen_write_STA(ACPI_STATUS_DEVICE_ALL_ON);
+ acpigen_write_STA(ACPI_STATUS_DEVICE_HIDDEN_ON);
/*
* Part of the PCH's reserved 32 MB MMIO range (0xFC800000 - 0xFE7FFFFF).
--
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