coreboot-gerrit February 2025

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[M] Change in coreboot[main]: CFR: add dependencies based on specific option values
by Angel Pons (Code Review) 06 Feb '25

06 Feb '25

Attention is currently required from: Filip Brozovic. Angel Pons has posted comments on this change by Filip Brozovic. ( https://review.coreboot.org/c/coreboot/+/85987?usp=email ) Change subject: CFR: add dependencies based on specific option values ...................................................................... Patch Set 4: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/85987?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iaf7965551490969052eb27c207fa524470d4dd6a Gerrit-Change-Number: 85987 Gerrit-PatchSet: 4 Gerrit-Owner: Filip Brozovic <fbrozovic(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Filip Brozovic <fbrozovic(a)gmail.com> Gerrit-Comment-Date: Thu, 06 Feb 2025 12:05:57 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[XS] Change in coreboot[main]: CFR: Add version field to root struct
by Angel Pons (Code Review) 06 Feb '25

06 Feb '25

Attention is currently required from: Filip Brozovic, Sean Rhodes. Angel Pons has posted comments on this change by Filip Brozovic. ( https://review.coreboot.org/c/coreboot/+/86080?usp=email ) Change subject: CFR: Add version field to root struct ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/86080?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ifcb950f1bdedc0ab925f3841befb7e7001c0f7f4 Gerrit-Change-Number: 86080 Gerrit-PatchSet: 2 Gerrit-Owner: Filip Brozovic <fbrozovic(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Attention: Filip Brozovic <fbrozovic(a)gmail.com> Gerrit-Comment-Date: Thu, 06 Feb 2025 12:04:15 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[S] Change in coreboot[main]: soc/intel/pantherlake: Add support for VMD device
by Ronak Kanabar (Code Review) 06 Feb '25

06 Feb '25

Attention is currently required from: Intel coreboot Reviewers, Jayvik Desai, Kapil Porwal, Pranava Y N, Subrata Banik. Ronak Kanabar has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/86301?usp=email ) Change subject: soc/intel/pantherlake: Add support for VMD device ...................................................................... soc/intel/pantherlake: Add support for VMD device This commit adds support for the VMD in the Pantherlake SoC. Changes include: - Add VMD to the `min_pci_sleep_states` array in `acpi.c` - Update `chipset.cb` to include the VMD device' - Introduce a new function `fill_fsps_vmd_params` - Define the VMD device and function numbers in `pci_devs.h`. Change-Id: Ie391196e7b4537d1146ac30177a0ba472a1bfb43 Signed-off-by: Ronak Kanabar <ronak.kanabar(a)intel.com> --- M src/soc/intel/pantherlake/acpi.c M src/soc/intel/pantherlake/chipset.cb M src/soc/intel/pantherlake/fsp_params.c M src/soc/intel/pantherlake/include/soc/pci_devs.h 4 files changed, 14 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/01/86301/1 diff --git a/src/soc/intel/pantherlake/acpi.c b/src/soc/intel/pantherlake/acpi.c index 5df3ef9..1c965f4 100644 --- a/src/soc/intel/pantherlake/acpi.c +++ b/src/soc/intel/pantherlake/acpi.c @@ -193,6 +193,7 @@ { PCI_DEVFN_TCSS_XDCI, ACPI_DEVICE_SLEEP_D3 }, { SA_DEVFN_TCSS_DMA0, ACPI_DEVICE_SLEEP_D3 }, { SA_DEVFN_TCSS_DMA1, ACPI_DEVICE_SLEEP_D3 }, + { PCI_DEVFN_VMD, ACPI_DEVICE_SLEEP_D3 }, { PCI_DEVFN_THC0, ACPI_DEVICE_SLEEP_D3 }, { PCI_DEVFN_THC1, ACPI_DEVICE_SLEEP_D3 }, { PCH_DEVFN_XHCI, ACPI_DEVICE_SLEEP_D3 }, diff --git a/src/soc/intel/pantherlake/chipset.cb b/src/soc/intel/pantherlake/chipset.cb index 0f7967b..0c57a7d 100644 --- a/src/soc/intel/pantherlake/chipset.cb +++ b/src/soc/intel/pantherlake/chipset.cb @@ -86,6 +86,7 @@ device pci 0d.1 alias tcss_xdci off end device pci 0d.2 alias tcss_dma0 off end device pci 0d.3 alias tcss_dma1 off end + device pci 0e.0 alias vmd off end device pci 10.0 alias thc0 off end device pci 10.1 alias thc1 off end device pci 12.0 alias ish off end diff --git a/src/soc/intel/pantherlake/fsp_params.c b/src/soc/intel/pantherlake/fsp_params.c index a78059d..169d8c5 100644 --- a/src/soc/intel/pantherlake/fsp_params.c +++ b/src/soc/intel/pantherlake/fsp_params.c @@ -560,6 +560,13 @@ s_cfg->CnviBtInterface = is_devfn_enabled(PCI_DEVFN_CNVI_BT) ? 2 : 1; } +static void fill_fsps_vmd_params(FSP_S_CONFIG *s_cfg, + const struct soc_intel_pantherlake_config *config) +{ + /* VMD */ + s_cfg->VmdEnable = is_devfn_enabled(PCI_DEVFN_VMD); +} + static void fill_fsps_pmcpd_params(FSP_S_CONFIG *s_cfg, const struct soc_intel_pantherlake_config *config) { @@ -710,6 +717,7 @@ fill_fsps_pci_ssid_params, fill_fsps_lan_params, fill_fsps_cnvi_params, + fill_fsps_vmd_params, fill_fsps_pmcpd_params, fill_fsps_thc_params, fill_fsps_8254_params, diff --git a/src/soc/intel/pantherlake/include/soc/pci_devs.h b/src/soc/intel/pantherlake/include/soc/pci_devs.h index 5c74b6d..a69f482 100644 --- a/src/soc/intel/pantherlake/include/soc/pci_devs.h +++ b/src/soc/intel/pantherlake/include/soc/pci_devs.h @@ -79,6 +79,10 @@ #define PCI_DEV_TCSS_DMA0 _PCI_DEV(TCSS, 2) #define PCI_DEV_TCSS_DMA1 _PCI_DEV(TCSS, 3) +#define PCI_DEV_SLOT_VMD 0x0e +#define PCI_DEVFN_VMD _PCI_DEVFN(VMD, 0) +#define PCI_DEV_VMD _PCI_DEV(VMD, 0) + #define PCI_DEV_SLOT_THC 0x10 #define PCI_DEVFN_THC0 _PCI_DEVFN(THC, 0) #define PCI_DEVFN_THC1 _PCI_DEVFN(THC, 1) -- To view, visit https://review.coreboot.org/c/coreboot/+/86301?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ie391196e7b4537d1146ac30177a0ba472a1bfb43 Gerrit-Change-Number: 86301 Gerrit-PatchSet: 1 Gerrit-Owner: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com>

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[XS] Change in coreboot[main]: mb/google/nissa/var/gothrax: Add 2 Hynix parts to RAM ID table
by Subrata Banik (Code Review) 06 Feb '25

06 Feb '25

Attention is currently required from: Dinesh Gehlot, Eric Lai, Jayvik Desai, Kapil Porwal, Nick Vaccaro, Yunlong Jia. Subrata Banik has posted comments on this change by Yunlong Jia. ( https://review.coreboot.org/c/coreboot/+/86296?usp=email ) Change subject: mb/google/nissa/var/gothrax: Add 2 Hynix parts to RAM ID table ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/86296?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I9945ef9f8b9f5de8aedc34e4bc41c29a702be819 Gerrit-Change-Number: 86296 Gerrit-PatchSet: 1 Gerrit-Owner: Yunlong Jia <yunlong.jia(a)ecs.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Yunlong Jia <yunlong.jia(a)ecs.corp-partner.google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Comment-Date: Thu, 06 Feb 2025 10:59:01 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[S] Change in coreboot[main]: soc/amd/common/block/graphics: Support non VGA IGDs
by Patrick Rudolph (Code Review) 06 Feb '25

06 Feb '25

Attention is currently required from: Felix Held, Fred Reitberger, Jason Glenesk, Matt DeVillier. Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/86300?usp=email ) Change subject: soc/amd/common/block/graphics: Support non VGA IGDs ...................................................................... soc/amd/common/block/graphics: Support non VGA IGDs On glinda the IGD is no longer VGA compatible, thus use the D-segment over C-segment for the VBIOS location. Introduce a new Kconfig and select it where necessary to keep existing behaviour on older SoC while fixing FSP GOP init on glinda. Change-Id: I6ab28aab74f3169d45d7d852a37ddfcfc75b7c88 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/soc/amd/cezanne/Kconfig M src/soc/amd/common/block/graphics/Kconfig M src/soc/amd/common/block/graphics/graphics.c M src/soc/amd/mendocino/Kconfig M src/soc/amd/phoenix/Kconfig M src/soc/amd/picasso/Kconfig M src/soc/amd/stoneyridge/Kconfig 7 files changed, 16 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/00/86300/1 diff --git a/src/soc/amd/cezanne/Kconfig b/src/soc/amd/cezanne/Kconfig index 7b97ce7..e8705a4 100644 --- a/src/soc/amd/cezanne/Kconfig +++ b/src/soc/amd/cezanne/Kconfig @@ -46,6 +46,7 @@ select SOC_AMD_COMMON_BLOCK_EMMC select SOC_AMD_COMMON_BLOCK_GPP_CLK select SOC_AMD_COMMON_BLOCK_GRAPHICS + select SOC_AMD_COMMON_BLOCK_GRAPHICS_VGA select SOC_AMD_COMMON_BLOCK_HAS_ESPI select SOC_AMD_COMMON_BLOCK_I2C select SOC_AMD_COMMON_BLOCK_I2C_PAD_CTRL diff --git a/src/soc/amd/common/block/graphics/Kconfig b/src/soc/amd/common/block/graphics/Kconfig index 3b2eaed..7b9f57b 100644 --- a/src/soc/amd/common/block/graphics/Kconfig +++ b/src/soc/amd/common/block/graphics/Kconfig @@ -35,3 +35,10 @@ help Select this option to provide Audio CoProcessor ACPI device for pre-Ryzen APUs for use by custom Windows drivers. + +config SOC_AMD_COMMON_BLOCK_GRAPHICS_VGA + bool + depends on SOC_AMD_COMMON_BLOCK_GRAPHICS + help + Select this option when the IGD is VGA compatible. On newer platforms the IGD + advertises itself as a Display device, but not VGA Display controller. diff --git a/src/soc/amd/common/block/graphics/graphics.c b/src/soc/amd/common/block/graphics/graphics.c index 264cf0f..63fe4b1 100644 --- a/src/soc/amd/common/block/graphics/graphics.c +++ b/src/soc/amd/common/block/graphics/graphics.c @@ -151,7 +151,10 @@ if (!CONFIG(RUN_FSP_GOP)) return NULL; - return (void *)(uintptr_t)PCI_VGA_RAM_IMAGE_START; + if (CONFIG(SOC_AMD_COMMON_BLOCK_GRAPHICS_VGA)) + return (void *)(uintptr_t)PCI_VGA_RAM_IMAGE_START; + + return (void *)(uintptr_t)PCI_RAM_IMAGE_START; } static void graphics_set_resources(struct device *const dev) diff --git a/src/soc/amd/mendocino/Kconfig b/src/soc/amd/mendocino/Kconfig index ee6c968..3fdb20f 100644 --- a/src/soc/amd/mendocino/Kconfig +++ b/src/soc/amd/mendocino/Kconfig @@ -50,6 +50,7 @@ select SOC_AMD_COMMON_BLOCK_ESPI_EXTENDED_DECODE_RANGES select SOC_AMD_COMMON_BLOCK_GPP_CLK select SOC_AMD_COMMON_BLOCK_GRAPHICS + select SOC_AMD_COMMON_BLOCK_GRAPHICS_VGA select SOC_AMD_COMMON_BLOCK_HAS_ESPI select SOC_AMD_COMMON_BLOCK_HAS_ESPI_ALERT_ENABLE select SOC_AMD_COMMON_BLOCK_I2C diff --git a/src/soc/amd/phoenix/Kconfig b/src/soc/amd/phoenix/Kconfig index b15c12d..261cf3a 100644 --- a/src/soc/amd/phoenix/Kconfig +++ b/src/soc/amd/phoenix/Kconfig @@ -45,6 +45,7 @@ select SOC_AMD_COMMON_BLOCK_ESPI_EXTENDED_DECODE_RANGES select SOC_AMD_COMMON_BLOCK_GPP_CLK select SOC_AMD_COMMON_BLOCK_GRAPHICS # TODO: Check if this is still correct + select SOC_AMD_COMMON_BLOCK_GRAPHICS_VGA select SOC_AMD_COMMON_BLOCK_HAS_ESPI select SOC_AMD_COMMON_BLOCK_HAS_ESPI_ALERT_ENABLE select SOC_AMD_COMMON_BLOCK_I2C diff --git a/src/soc/amd/picasso/Kconfig b/src/soc/amd/picasso/Kconfig index f450e29..0b61284 100644 --- a/src/soc/amd/picasso/Kconfig +++ b/src/soc/amd/picasso/Kconfig @@ -41,6 +41,7 @@ select SOC_AMD_COMMON_BLOCK_EMMC_SKIP_POWEROFF select SOC_AMD_COMMON_BLOCK_GPP_CLK select SOC_AMD_COMMON_BLOCK_GRAPHICS + select SOC_AMD_COMMON_BLOCK_GRAPHICS_VGA select SOC_AMD_COMMON_BLOCK_HAS_ESPI select SOC_AMD_COMMON_BLOCK_HDA select SOC_AMD_COMMON_BLOCK_I2C diff --git a/src/soc/amd/stoneyridge/Kconfig b/src/soc/amd/stoneyridge/Kconfig index 47de102..cd08f58 100644 --- a/src/soc/amd/stoneyridge/Kconfig +++ b/src/soc/amd/stoneyridge/Kconfig @@ -27,6 +27,7 @@ select SOC_AMD_COMMON_BLOCK_CAR select SOC_AMD_COMMON_BLOCK_CPUFREQ_FAM15H_16H select SOC_AMD_COMMON_BLOCK_GRAPHICS + select SOC_AMD_COMMON_BLOCK_GRAPHICS_VGA select SOC_AMD_COMMON_BLOCK_HDA select SOC_AMD_COMMON_BLOCK_I2C select SOC_AMD_COMMON_BLOCK_IOMMU -- To view, visit https://review.coreboot.org/c/coreboot/+/86300?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I6ab28aab74f3169d45d7d852a37ddfcfc75b7c88 Gerrit-Change-Number: 86300 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de>

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[M] Change in coreboot[main]: soc/amd/common/block/graphics: Use vbt_get()
by Patrick Rudolph (Code Review) 06 Feb '25

06 Feb '25

Attention is currently required from: Andrey Petrov, Felix Held, Fred Reitberger, Intel coreboot Reviewers, Jason Glenesk, Matt DeVillier, Ronak Kanabar. Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/86299?usp=email ) Change subject: soc/amd/common/block/graphics: Use vbt_get() ...................................................................... soc/amd/common/block/graphics: Use vbt_get() Implement vbt_get() on AMD and return the VBIOS location. This allows to drop the hardcoded addresses used in various places and return an address in DRAM that is reserved for FSP use. Change-Id: I92d76fc4df88fbce792b9d7c912c6799617704a0 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/drivers/intel/fsp2_0/silicon_init.c M src/soc/amd/cezanne/fsp_s_params.c M src/soc/amd/common/block/graphics/graphics.c A src/soc/amd/common/block/include/amdblocks/vbt.h M src/soc/amd/glinda/fsp_s_params.c M src/soc/amd/mendocino/fsp_s_params.c M src/soc/amd/phoenix/fsp_s_params.c M src/soc/amd/picasso/fsp_s_params.c 8 files changed, 44 insertions(+), 19 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/99/86299/1 diff --git a/src/drivers/intel/fsp2_0/silicon_init.c b/src/drivers/intel/fsp2_0/silicon_init.c index 1caf00f..fdac9f5 100644 --- a/src/drivers/intel/fsp2_0/silicon_init.c +++ b/src/drivers/intel/fsp2_0/silicon_init.c @@ -14,7 +14,12 @@ #include <mrc_cache.h> #include <program_loading.h> #include <soc/intel/common/reset.h> +#if CONFIG(SOC_AMD_COMMON) +#include <amdblocks/vbt.h> +#endif +#if CONFIG(SOC_INTEL_COMMON) #include <soc/intel/common/vbt.h> +#endif #include <stage_cache.h> #include <string.h> #include <timestamp.h> diff --git a/src/soc/amd/cezanne/fsp_s_params.c b/src/soc/amd/cezanne/fsp_s_params.c index b9770f3..391461e 100644 --- a/src/soc/amd/cezanne/fsp_s_params.c +++ b/src/soc/amd/cezanne/fsp_s_params.c @@ -2,6 +2,7 @@ #include <acpi/acpi.h> #include <amdblocks/apob_cache.h> +#include <amdblocks/vbt.h> #include <device/pci.h> #include <fsp/api.h> #include <program_loading.h> @@ -13,7 +14,7 @@ * part of FSP GOP init. We can delay loading of the VBIOS until * before FSP notify AFTER_PCI_ENUM. */ - scfg->vbios_buffer = CONFIG(RUN_FSP_GOP) ? PCI_VGA_RAM_IMAGE_START : 0; + scfg->vbios_buffer = (uintptr_t)vbt_get(); } void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) diff --git a/src/soc/amd/common/block/graphics/graphics.c b/src/soc/amd/common/block/graphics/graphics.c index 77420ae..264cf0f 100644 --- a/src/soc/amd/common/block/graphics/graphics.c +++ b/src/soc/amd/common/block/graphics/graphics.c @@ -4,6 +4,7 @@ #include <acpi/acpigen.h> #include <amdblocks/graphics.h> #include <amdblocks/vbios_cache.h> +#include <amdblocks/vbt.h> #include <boot/coreboot_tables.h> #include <bootmode.h> #include <bootstate.h> @@ -12,7 +13,6 @@ #include <device/pci.h> #include <fmap.h> #include <security/vboot/vbios_cache_hash_tpm.h> -#include <soc/intel/common/vbt.h> #include <timestamp.h> static bool vbios_loaded_from_cache = false; @@ -146,18 +146,12 @@ return "IGFX"; } -/* - * On AMD platforms the VBT is called ATOMBIOS and is always part of the - * VGA Option ROM. As part of the FSP GOP init the ATOMBIOS tables are - * updated in place. Thus the VBIOS must be loaded into RAM before FSP GOP - * runs. The address of the VBIOS must be passed to FSP-S using UPDs, but - * loading of the VBIOS can be delayed until before FSP AFTER_PCI_ENUM - * notify is called. FSP expects a pointer to the PCI option rom instead - * a pointer to the ATOMBIOS table directly. - */ void *vbt_get(void) { - return NULL; + if (!CONFIG(RUN_FSP_GOP)) + return NULL; + + return (void *)(uintptr_t)PCI_VGA_RAM_IMAGE_START; } static void graphics_set_resources(struct device *const dev) @@ -259,12 +253,12 @@ } /* copy from PCI_VGA_RAM_IMAGE_START to rdev */ - if (rdev_writeat(&rw_vbios_cache, (void *)PCI_VGA_RAM_IMAGE_START, 0, + if (rdev_writeat(&rw_vbios_cache, vbt_get(), 0, VBIOS_CACHE_FMAP_SIZE) != VBIOS_CACHE_FMAP_SIZE) printk(BIOS_ERR, "Failed to save vbios data to flash; rdev_writeat() failed.\n"); /* copy modified vbios data from PCI_VGA_RAM_IMAGE_START to buffer before hashing */ - memcpy(vbios_data, (void *)PCI_VGA_RAM_IMAGE_START, VBIOS_CACHE_FMAP_SIZE); + memcpy(vbios_data, vbt_get(), VBIOS_CACHE_FMAP_SIZE); /* save data hash to TPM NVRAM for validation on subsequent boots */ vbios_cache_update_hash(vbios_data, VBIOS_CACHE_FMAP_SIZE); @@ -280,7 +274,7 @@ void vbios_load_from_cache(void) { /* copy cached vbios data from buffer to PCI_VGA_RAM_IMAGE_START */ - memcpy((void *)PCI_VGA_RAM_IMAGE_START, vbios_data, VBIOS_CACHE_FMAP_SIZE); + memcpy(vbt_get(), vbios_data, VBIOS_CACHE_FMAP_SIZE); /* mark cache as used so we know not to write it later */ vbios_loaded_from_cache = true; diff --git a/src/soc/amd/common/block/include/amdblocks/vbt.h b/src/soc/amd/common/block/include/amdblocks/vbt.h new file mode 100644 index 0000000..38ed8f3 --- /dev/null +++ b/src/soc/amd/common/block/include/amdblocks/vbt.h @@ -0,0 +1,21 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _AMD_BLOCK_VBT_H_ +#define _AMD_BLOCK_VBT_H_ + +/* + * On AMD platforms the VBT is called ATOMBIOS and is always part of the + * VGA Option ROM. As part of the FSP GOP init the ATOMBIOS tables are + * updated in place. Thus the VBIOS must be loaded into RAM before FSP GOP + * runs. The address of the VBIOS must be passed to FSP-S using UPDs, but + * loading of the VBIOS can be delayed until before FSP AFTER_PCI_ENUM + * notify is called. FSP expects a pointer to the PCI option rom instead + * a pointer to the ATOMBIOS table directly. + * + * Returns a pointer to the VGA Option ROM in DRAM after checking + * prerequisites for Pre OS Graphics initialization. When returning + * non NULL the Option ROM might not be loaded at this address yet, + * but is guaranted to be present at end of BS_DEV_RESOURCES phase. + */ +void *vbt_get(void); +#endif diff --git a/src/soc/amd/glinda/fsp_s_params.c b/src/soc/amd/glinda/fsp_s_params.c index e037957..980eea8 100644 --- a/src/soc/amd/glinda/fsp_s_params.c +++ b/src/soc/amd/glinda/fsp_s_params.c @@ -4,6 +4,7 @@ #include <acpi/acpi.h> #include <amdblocks/apob_cache.h> +#include <amdblocks/vbt.h> #include <device/pci.h> #include <fsp/api.h> #include <program_loading.h> @@ -15,7 +16,7 @@ * part of FSP GOP init. We can delay loading of the VBIOS until * before FSP notify AFTER_PCI_ENUM. */ - scfg->vbios_buffer = CONFIG(RUN_FSP_GOP) ? PCI_VGA_RAM_IMAGE_START : 0; + scfg->vbios_buffer = (uintptr_t)vbt_get(); } void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) diff --git a/src/soc/amd/mendocino/fsp_s_params.c b/src/soc/amd/mendocino/fsp_s_params.c index 5c37334..5393eba 100644 --- a/src/soc/amd/mendocino/fsp_s_params.c +++ b/src/soc/amd/mendocino/fsp_s_params.c @@ -5,6 +5,7 @@ #include <acpi/acpi.h> #include <amdblocks/apob_cache.h> #include <amdblocks/vbios_cache.h> +#include <amdblocks/vbt.h> #include <bootmode.h> #include <bootsplash.h> #include <console/console.h> @@ -26,7 +27,7 @@ * before FSP notify AFTER_PCI_ENUM. */ printk(BIOS_SPEW, "%s: not using VBIOS cache; running GOP driver.\n", __func__); - scfg->vbios_buffer = CONFIG(RUN_FSP_GOP) ? PCI_VGA_RAM_IMAGE_START : 0; + scfg->vbios_buffer = (uintptr_t)vbt_get(); } void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) diff --git a/src/soc/amd/phoenix/fsp_s_params.c b/src/soc/amd/phoenix/fsp_s_params.c index 883cde0..9ce09f8 100644 --- a/src/soc/amd/phoenix/fsp_s_params.c +++ b/src/soc/amd/phoenix/fsp_s_params.c @@ -4,6 +4,7 @@ #include <acpi/acpi.h> #include <amdblocks/apob_cache.h> +#include <amdblocks/vbt.h> #include <device/pci.h> #include <fsp/api.h> #include <program_loading.h> @@ -15,7 +16,7 @@ * part of FSP GOP init. We can delay loading of the VBIOS until * before FSP notify AFTER_PCI_ENUM. */ - scfg->vbios_buffer = CONFIG(RUN_FSP_GOP) ? PCI_VGA_RAM_IMAGE_START : 0; + scfg->vbios_buffer = (uintptr_t)vbt_get(); } void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) diff --git a/src/soc/amd/picasso/fsp_s_params.c b/src/soc/amd/picasso/fsp_s_params.c index d4cfa27..fd6f817 100644 --- a/src/soc/amd/picasso/fsp_s_params.c +++ b/src/soc/amd/picasso/fsp_s_params.c @@ -2,6 +2,7 @@ #include <assert.h> #include <amdblocks/ioapic.h> +#include <amdblocks/vbt.h> #include <device/pci.h> #include <soc/iomap.h> #include <soc/pci_devs.h> @@ -190,7 +191,7 @@ * part of FSP GOP init. We can delay loading of the VBIOS until * before FSP notify AFTER_PCI_ENUM. */ - scfg->vbios_buffer_addr = CONFIG(RUN_FSP_GOP) ? PCI_VGA_RAM_IMAGE_START : 0; + scfg->vbios_buffer_addr = (uintptr_t)vbt_get(); } void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) -- To view, visit https://review.coreboot.org/c/coreboot/+/86299?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I92d76fc4df88fbce792b9d7c912c6799617704a0 Gerrit-Change-Number: 86299 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de>

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[S] Change in coreboot[main]: soc/amd: Document VBIOS handling
by Patrick Rudolph (Code Review) 06 Feb '25

06 Feb '25

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/86298?usp=email ) Change subject: soc/amd: Document VBIOS handling ...................................................................... soc/amd: Document VBIOS handling The code flow isn't that obvious in the beginning. You pass an address of the VBIOS to FSP, but don't load any VBIOS until BS_DEV_RESOURCES phase. Add comments to document what is done and when. This will help to improve the code in the next step. Change-Id: I643bc9088306d99cc0fbb79648809e16b068fb33 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/soc/amd/cezanne/fsp_s_params.c M src/soc/amd/common/block/graphics/graphics.c M src/soc/amd/glinda/fsp_s_params.c M src/soc/amd/mendocino/fsp_s_params.c M src/soc/amd/phoenix/fsp_s_params.c M src/soc/amd/picasso/fsp_s_params.c 6 files changed, 38 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/86298/1 diff --git a/src/soc/amd/cezanne/fsp_s_params.c b/src/soc/amd/cezanne/fsp_s_params.c index 60f3942..b9770f3 100644 --- a/src/soc/amd/cezanne/fsp_s_params.c +++ b/src/soc/amd/cezanne/fsp_s_params.c @@ -8,6 +8,11 @@ static void fsp_assign_vbios_upds(FSP_S_CONFIG *scfg) { + /* + * The VBIOS contains the ATOMBIOS tables that will be modified as + * part of FSP GOP init. We can delay loading of the VBIOS until + * before FSP notify AFTER_PCI_ENUM. + */ scfg->vbios_buffer = CONFIG(RUN_FSP_GOP) ? PCI_VGA_RAM_IMAGE_START : 0; } diff --git a/src/soc/amd/common/block/graphics/graphics.c b/src/soc/amd/common/block/graphics/graphics.c index ea7308a..77420ae 100644 --- a/src/soc/amd/common/block/graphics/graphics.c +++ b/src/soc/amd/common/block/graphics/graphics.c @@ -147,9 +147,13 @@ } /* - * Even though AMD does not need VBT we still need to implement the - * vbt_get() function to not break the build with GOP driver enabled - * (see fsps_return_value_handler() in fsp2_0/silicon_init.c + * On AMD platforms the VBT is called ATOMBIOS and is always part of the + * VGA Option ROM. As part of the FSP GOP init the ATOMBIOS tables are + * updated in place. Thus the VBIOS must be loaded into RAM before FSP GOP + * runs. The address of the VBIOS must be passed to FSP-S using UPDs, but + * loading of the VBIOS can be delayed until before FSP AFTER_PCI_ENUM + * notify is called. FSP expects a pointer to the PCI option rom instead + * a pointer to the ATOMBIOS table directly. */ void *vbt_get(void) { @@ -165,6 +169,7 @@ if (!CONFIG(RUN_FSP_GOP)) return; + /* Load the VBIOS before FSP AFTER_PCI_ENUM notify is called. */ timestamp_add_now(TS_OPROM_INITIALIZE); if (CONFIG(USE_SELECTIVE_GOP_INIT) && vbios_cache_is_valid() && !display_init_required()) { @@ -172,6 +177,11 @@ timestamp_add_now(TS_OPROM_COPY_END); return; } + + /* + * VBIOS cache was not used, so load it from CBFS and let FSP GOP + * initialize the ATOMBIOS tables. + */ rom = pci_rom_probe(dev); if (rom == NULL) { printk(BIOS_ERR, "%s: Unable to find ROM for %s\n", diff --git a/src/soc/amd/glinda/fsp_s_params.c b/src/soc/amd/glinda/fsp_s_params.c index 597f7a9..e037957 100644 --- a/src/soc/amd/glinda/fsp_s_params.c +++ b/src/soc/amd/glinda/fsp_s_params.c @@ -10,6 +10,11 @@ static void fsp_assign_vbios_upds(FSP_S_CONFIG *scfg) { + /* + * The VBIOS contains the ATOMBIOS tables that will be modified as + * part of FSP GOP init. We can delay loading of the VBIOS until + * before FSP notify AFTER_PCI_ENUM. + */ scfg->vbios_buffer = CONFIG(RUN_FSP_GOP) ? PCI_VGA_RAM_IMAGE_START : 0; } diff --git a/src/soc/amd/mendocino/fsp_s_params.c b/src/soc/amd/mendocino/fsp_s_params.c index 50923e9..5c37334 100644 --- a/src/soc/amd/mendocino/fsp_s_params.c +++ b/src/soc/amd/mendocino/fsp_s_params.c @@ -20,6 +20,11 @@ printk(BIOS_SPEW, "%s: using VBIOS cache; skipping GOP driver.\n", __func__); return; } + /* + * The VBIOS contains the ATOMBIOS tables that will be modified as + * part of FSP GOP init. We can delay loading of the VBIOS until + * before FSP notify AFTER_PCI_ENUM. + */ printk(BIOS_SPEW, "%s: not using VBIOS cache; running GOP driver.\n", __func__); scfg->vbios_buffer = CONFIG(RUN_FSP_GOP) ? PCI_VGA_RAM_IMAGE_START : 0; } diff --git a/src/soc/amd/phoenix/fsp_s_params.c b/src/soc/amd/phoenix/fsp_s_params.c index 46c8e76..883cde0 100644 --- a/src/soc/amd/phoenix/fsp_s_params.c +++ b/src/soc/amd/phoenix/fsp_s_params.c @@ -10,6 +10,11 @@ static void fsp_assign_vbios_upds(FSP_S_CONFIG *scfg) { + /* + * The VBIOS contains the ATOMBIOS tables that will be modified as + * part of FSP GOP init. We can delay loading of the VBIOS until + * before FSP notify AFTER_PCI_ENUM. + */ scfg->vbios_buffer = CONFIG(RUN_FSP_GOP) ? PCI_VGA_RAM_IMAGE_START : 0; } diff --git a/src/soc/amd/picasso/fsp_s_params.c b/src/soc/amd/picasso/fsp_s_params.c index 9f491d6..d4cfa27 100644 --- a/src/soc/amd/picasso/fsp_s_params.c +++ b/src/soc/amd/picasso/fsp_s_params.c @@ -185,6 +185,11 @@ static void fsp_assign_vbios_upds(FSP_S_CONFIG *scfg) { + /* + * The VBIOS contains the ATOMBIOS tables that will be modified as + * part of FSP GOP init. We can delay loading of the VBIOS until + * before FSP notify AFTER_PCI_ENUM. + */ scfg->vbios_buffer_addr = CONFIG(RUN_FSP_GOP) ? PCI_VGA_RAM_IMAGE_START : 0; } -- To view, visit https://review.coreboot.org/c/coreboot/+/86298?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I643bc9088306d99cc0fbb79648809e16b068fb33 Gerrit-Change-Number: 86298 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com>

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[XS] Change in coreboot[main]: mb/google/nissa/var/gothrax: Add 2 Hynix parts to RAM ID table
by Yunlong Jia (Code Review) 06 Feb '25

06 Feb '25

Yunlong Jia has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/86296?usp=email ) Change subject: mb/google/nissa/var/gothrax: Add 2 Hynix parts to RAM ID table ...................................................................... mb/google/nissa/var/gothrax: Add 2 Hynix parts to RAM ID table Add the support RAM parts for gothrax. Here is the ram part number list: DRAM Part Name ID to assign MT62F512M32D2DR-031 WT:B 0 (0000) H58G56AK6BX069 1 (0001) K3LKBKB0BM-MGCP 2 (0010) H9JCNNNBK3MLYR-N6E 0 (0000) H9JCNNNCP3MLYR-N6E 3 (0011) BUG=b:394756067 BRANCH=None TEST=emerge-nissa coreboot Change-Id: I9945ef9f8b9f5de8aedc34e4bc41c29a702be819 Signed-off-by: Yunlong Jia <yunlong.jia(a)ecs.corp-partner.google.com> --- M src/mainboard/google/brya/variants/gothrax/memory/Makefile.mk M src/mainboard/google/brya/variants/gothrax/memory/dram_id.generated.txt M src/mainboard/google/brya/variants/gothrax/memory/mem_parts_used.txt 3 files changed, 6 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/96/86296/1 diff --git a/src/mainboard/google/brya/variants/gothrax/memory/Makefile.mk b/src/mainboard/google/brya/variants/gothrax/memory/Makefile.mk index d3c1f68..96e2023 100644 --- a/src/mainboard/google/brya/variants/gothrax/memory/Makefile.mk +++ b/src/mainboard/google/brya/variants/gothrax/memory/Makefile.mk @@ -4,6 +4,7 @@ # ./util/spd_tools/bin/part_id_gen ADL lp5 src/mainboard/google/brya/variants/gothrax/memory src/mainboard/google/brya/variants/gothrax/memory/mem_parts_used.txt SPD_SOURCES = -SPD_SOURCES += spd/lp5/set-0/spd-1.hex # ID = 0(0b0000) Parts = MT62F512M32D2DR-031 WT:B +SPD_SOURCES += spd/lp5/set-0/spd-1.hex # ID = 0(0b0000) Parts = MT62F512M32D2DR-031 WT:B, H9JCNNNBK3MLYR-N6E SPD_SOURCES += spd/lp5/set-0/spd-3.hex # ID = 1(0b0001) Parts = H58G56AK6BX069 SPD_SOURCES += spd/lp5/set-0/spd-3.hex # ID = 2(0b0010) Parts = K3LKBKB0BM-MGCP +SPD_SOURCES += spd/lp5/set-0/spd-2.hex # ID = 3(0b0011) Parts = H9JCNNNCP3MLYR-N6E diff --git a/src/mainboard/google/brya/variants/gothrax/memory/dram_id.generated.txt b/src/mainboard/google/brya/variants/gothrax/memory/dram_id.generated.txt index 7db6e24..ee10ecf 100644 --- a/src/mainboard/google/brya/variants/gothrax/memory/dram_id.generated.txt +++ b/src/mainboard/google/brya/variants/gothrax/memory/dram_id.generated.txt @@ -7,3 +7,5 @@ MT62F512M32D2DR-031 WT:B 0 (0000) H58G56AK6BX069 1 (0001) K3LKBKB0BM-MGCP 2 (0010) +H9JCNNNBK3MLYR-N6E 0 (0000) +H9JCNNNCP3MLYR-N6E 3 (0011) diff --git a/src/mainboard/google/brya/variants/gothrax/memory/mem_parts_used.txt b/src/mainboard/google/brya/variants/gothrax/memory/mem_parts_used.txt index f38995e..5d05034 100644 --- a/src/mainboard/google/brya/variants/gothrax/memory/mem_parts_used.txt +++ b/src/mainboard/google/brya/variants/gothrax/memory/mem_parts_used.txt @@ -13,3 +13,5 @@ MT62F512M32D2DR-031 WT:B, H58G56AK6BX069,*1 K3LKBKB0BM-MGCP, +H9JCNNNBK3MLYR-N6E, +H9JCNNNCP3MLYR-N6E, -- To view, visit https://review.coreboot.org/c/coreboot/+/86296?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I9945ef9f8b9f5de8aedc34e4bc41c29a702be819 Gerrit-Change-Number: 86296 Gerrit-PatchSet: 1 Gerrit-Owner: Yunlong Jia <yunlong.jia(a)ecs.corp-partner.google.com>

1 0

[XS] Change in coreboot[main]: mb/google/trulo/var/uldrenite: Add WIFI SAR table
by Jayvik Desai (Code Review) 06 Feb '25

06 Feb '25

Attention is currently required from: Dinesh Gehlot, Eric Lai, Jamie Chen, Kapil Porwal, Nick Vaccaro. Jayvik Desai has posted comments on this change by Jamie Chen. ( https://review.coreboot.org/c/coreboot/+/86291?usp=email ) Change subject: mb/google/trulo/var/uldrenite: Add WIFI SAR table ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/86291?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ieb7f7ba54aaa6bdf1a19e59e57eb46cfafd655fe Gerrit-Change-Number: 86291 Gerrit-PatchSet: 3 Gerrit-Owner: Jamie Chen <jamie_chen(a)compal.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Frank Wu <frank_wu(a)compal.corp-partner.google.com> Gerrit-CC: John Su <john_su(a)compal.corp-partner.google.com> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Jamie Chen <jamie_chen(a)compal.corp-partner.google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Comment-Date: Thu, 06 Feb 2025 10:09:14 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

1 0

[XS] Change in blobs[main]: soc/mediatek/mt8196: Update SSPM firmware to v4.0
by Yu-Ping Wu (Code Review) 06 Feb '25

06 Feb '25

Attention is currently required from: Jarried Lin, Kenji Yu. Yu-Ping Wu has posted comments on this change by Kenji Yu. ( https://review.coreboot.org/c/blobs/+/86293?usp=email ) Change subject: soc/mediatek/mt8196: Update SSPM firmware to v4.0 ...................................................................... Patch Set 3: Code-Review+2 Verified+1 -- To view, visit https://review.coreboot.org/c/blobs/+/86293?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: blobs Gerrit-Branch: main Gerrit-Change-Id: Ic717aba8ec18c55659cb3197c19984718646bfec Gerrit-Change-Number: 86293 Gerrit-PatchSet: 3 Gerrit-Owner: Kenji Yu <kenji.yu(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Kenji Yu <kenji.yu(a)mediatek.corp-partner.google.com> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Comment-Date: Thu, 06 Feb 2025 09:53:29 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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