coreboot-gerrit February 2025

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[S] Change in coreboot[main]: tree: remove duplicated includes
by Angel Pons (Code Review) 08 Feb '25

08 Feb '25

Attention is currently required from: Elyes Haouas, Felix Held, Fred Reitberger, Hung-Te Lin, Intel coreboot Reviewers, Jason Glenesk, Jayvik Desai, Jeff Daly, Kapil Porwal, Martin L Roth, Matt DeVillier, Pranava Y N, Sean Rhodes, Subrata Banik, Vanessa Eusebio, Varshit Pandya, Yidi Lin, Yu-Ping Wu. Angel Pons has posted comments on this change by Elyes Haouas. ( https://review.coreboot.org/c/coreboot/+/86330?usp=email ) Change subject: tree: remove duplicated includes ...................................................................... Patch Set 1: Code-Review+1 (3 comments) File src/commonlib/device_tree.c: https://review.coreboot.org/c/coreboot/+/86330/comment/78646f24_4173aba5?us… : PS1, Line 13: #include <stdio.h> You should remove this one instead File src/mainboard/amd/crater/port_descriptors_renoir.c: https://review.coreboot.org/c/coreboot/+/86330/comment/17ecb375_450b839d?us… : PS1, Line 11: #include <stdint.h> Technically not duplicated, but provided by <types.h> I would prefer to handle these separately from literal duplicates File src/soc/mediatek/mt8196/mminfra.c: https://review.coreboot.org/c/coreboot/+/86330/comment/123c6172_485bc0f1?us… : PS1, Line 8: #include <stddef.h> Same here -- To view, visit https://review.coreboot.org/c/coreboot/+/86330?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iaf10e1b9fb8ce51605a75ec0a92ee33924c42aa6 Gerrit-Change-Number: 86330 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Jeff Daly <jeffd(a)silicom-usa.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Reviewer: Varshit Pandya <pandyavarshit(a)gmail.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Jeff Daly <jeffd(a)silicom-usa.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-Attention: Varshit Pandya <pandyavarshit(a)gmail.com> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Sat, 08 Feb 2025 09:55:03 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes

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[S] Change in coreboot[main]: tree: remove duplicated includes
by Elyes Haouas (Code Review) 08 Feb '25

08 Feb '25

Elyes Haouas has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/86330?usp=email ) Change subject: tree: remove duplicated includes ...................................................................... tree: remove duplicated includes Change-Id: Iaf10e1b9fb8ce51605a75ec0a92ee33924c42aa6 Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> --- M src/commonlib/device_tree.c M src/mainboard/amd/crater/port_descriptors_renoir.c M src/mainboard/emulation/qemu-sbsa/mainboard.c M src/mainboard/google/dedede/variants/baseboard/ramstage.c M src/northbridge/intel/haswell/broadwell_mrc/raminit.c M src/soc/amd/genoa_poc/chip.c M src/soc/amd/genoa_poc/config.c M src/soc/amd/picasso/acpi.c M src/soc/intel/apollolake/cpu.c M src/soc/intel/denverton_ns/include/soc/pci_devs.h M src/soc/intel/pantherlake/bootblock/report_platform.c M src/soc/mediatek/mt8196/mminfra.c M util/superiotool/superiotool.h 13 files changed, 1 insertion(+), 18 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/30/86330/1 diff --git a/src/commonlib/device_tree.c b/src/commonlib/device_tree.c index 4d72fb0..ce2dde2 100644 --- a/src/commonlib/device_tree.c +++ b/src/commonlib/device_tree.c @@ -13,7 +13,6 @@ #include <stdio.h> #define printk(level, ...) printf(__VA_ARGS__) #endif -#include <stdio.h> #include <string.h> #include <stddef.h> #include <stdlib.h> diff --git a/src/mainboard/amd/crater/port_descriptors_renoir.c b/src/mainboard/amd/crater/port_descriptors_renoir.c index bcddf1e..b8b0ffa 100644 --- a/src/mainboard/amd/crater/port_descriptors_renoir.c +++ b/src/mainboard/amd/crater/port_descriptors_renoir.c @@ -8,7 +8,6 @@ #include <soc/pci_devs.h> #include <console/console.h> #include <ec/acpi/ec.h> -#include <stdint.h> #define ECRAM_MACID_OFFSET 0x54 #define MACID_LEN 12 diff --git a/src/mainboard/emulation/qemu-sbsa/mainboard.c b/src/mainboard/emulation/qemu-sbsa/mainboard.c index 9d64b73..55e4c67 100644 --- a/src/mainboard/emulation/qemu-sbsa/mainboard.c +++ b/src/mainboard/emulation/qemu-sbsa/mainboard.c @@ -7,8 +7,6 @@ #include <cbfs.h> #include <device/device.h> #include <commonlib/device_tree.h> -#include <bootmem.h> -#include <arch/mmu.h> #include <mainboard/addressmap.h> #include <stdint.h> #include <symbols.h> diff --git a/src/mainboard/google/dedede/variants/baseboard/ramstage.c b/src/mainboard/google/dedede/variants/baseboard/ramstage.c index f5a8f98..6833b70 100644 --- a/src/mainboard/google/dedede/variants/baseboard/ramstage.c +++ b/src/mainboard/google/dedede/variants/baseboard/ramstage.c @@ -6,7 +6,6 @@ #include <drivers/usb/acpi/chip.h> #include <fw_config.h> #include <gpio.h> -#include <soc/pci_devs.h> #include <ec/google/chromeec/ec.h> #include <device/pci_ops.h> #include <intelblocks/power_limit.h> diff --git a/src/northbridge/intel/haswell/broadwell_mrc/raminit.c b/src/northbridge/intel/haswell/broadwell_mrc/raminit.c index beae496..5b2427b 100644 --- a/src/northbridge/intel/haswell/broadwell_mrc/raminit.c +++ b/src/northbridge/intel/haswell/broadwell_mrc/raminit.c @@ -14,7 +14,6 @@ #include <device/device.h> #include <device/pci_def.h> #include <device/pci_ops.h> -#include <device/dram/ddr3.h> #include <northbridge/intel/haswell/chip.h> #include <northbridge/intel/haswell/haswell.h> #include <northbridge/intel/haswell/raminit.h> diff --git a/src/soc/amd/genoa_poc/chip.c b/src/soc/amd/genoa_poc/chip.c index 98a995f..c76b716 100644 --- a/src/soc/amd/genoa_poc/chip.c +++ b/src/soc/amd/genoa_poc/chip.c @@ -5,7 +5,6 @@ #include <device/device.h> #include <drivers/amd/opensil/opensil.h> #include <soc/southbridge.h> -#include <soc/southbridge.h> static void soc_init(void *chip_info) { diff --git a/src/soc/amd/genoa_poc/config.c b/src/soc/amd/genoa_poc/config.c index eab1ae4..600ace6 100644 --- a/src/soc/amd/genoa_poc/config.c +++ b/src/soc/amd/genoa_poc/config.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <device/device.h> #include <amdblocks/chip.h> #include <device/device.h> #include <static.h> diff --git a/src/soc/amd/picasso/acpi.c b/src/soc/amd/picasso/acpi.c index b95db5d..d07b38c 100644 --- a/src/soc/amd/picasso/acpi.c +++ b/src/soc/amd/picasso/acpi.c @@ -19,7 +19,6 @@ #include <amdblocks/chip.h> #include <amdblocks/cpu.h> #include <amdblocks/ioapic.h> -#include <device/device.h> #include <soc/pci_devs.h> #include <soc/southbridge.h> #include "chip.h" diff --git a/src/soc/intel/apollolake/cpu.c b/src/soc/intel/apollolake/cpu.c index b8bf391..fb95009 100644 --- a/src/soc/intel/apollolake/cpu.c +++ b/src/soc/intel/apollolake/cpu.c @@ -13,7 +13,6 @@ #include <cpu/x86/mtrr.h> #include <cpu/x86/smm.h> #include <cpu/intel/em64t100_save_state.h> -#include <cpu/intel/microcode.h> #include <cpu/intel/smm_reloc.h> #include <device/device.h> #include <device/pci.h> diff --git a/src/soc/intel/denverton_ns/include/soc/pci_devs.h b/src/soc/intel/denverton_ns/include/soc/pci_devs.h index f62ea2b..5ad39cc 100644 --- a/src/soc/intel/denverton_ns/include/soc/pci_devs.h +++ b/src/soc/intel/denverton_ns/include/soc/pci_devs.h @@ -22,7 +22,6 @@ #if defined(__SIMPLE_DEVICE__) #define SA_DEV_ROOT PCI_DEV(0, SA_DEV_SLOT_ROOT, 0) #else -#include <device/device.h> #define SA_DEV_ROOT pcidev_path_on_root(PCI_DEVFN(SA_DEV_SLOT_ROOT, 0)) #endif #define SA_DEV 0x0 diff --git a/src/soc/intel/pantherlake/bootblock/report_platform.c b/src/soc/intel/pantherlake/bootblock/report_platform.c index aa8b030..28ec747 100644 --- a/src/soc/intel/pantherlake/bootblock/report_platform.c +++ b/src/soc/intel/pantherlake/bootblock/report_platform.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <device/pci_ops.h> #include <console/console.h> #include <cpu/cpu.h> #include <cpu/intel/cpu_ids.h> diff --git a/src/soc/mediatek/mt8196/mminfra.c b/src/soc/mediatek/mt8196/mminfra.c index c5eadf3..4a2e09d 100644 --- a/src/soc/mediatek/mt8196/mminfra.c +++ b/src/soc/mediatek/mt8196/mminfra.c @@ -5,7 +5,6 @@ #include <soc/addressmap.h> #include <soc/mminfra.h> #include <soc/spm_mtcmos.h> -#include <stddef.h> #include <string.h> #include <timer.h> #include <types.h> diff --git a/util/superiotool/superiotool.h b/util/superiotool/superiotool.h index ef2bfd6..1d41e12 100644 --- a/util/superiotool/superiotool.h +++ b/util/superiotool/superiotool.h @@ -9,6 +9,7 @@ #include <string.h> #include <getopt.h> #include <commonlib/bsd/helpers.h> +#include <sys/types.h> #if defined(__linux__) #include <sys/io.h> #endif @@ -25,11 +26,7 @@ # endif #endif -#include <sys/types.h> -#include <stdint.h> - #if defined(__FreeBSD__) -#include <sys/types.h> #include <machine/cpufunc.h> #define OUTB(x, y) do { u_int tmp = (y); outb(tmp, (x)); } while (0) #define OUTW(x, y) do { u_int tmp = (y); outw(tmp, (x)); } while (0) @@ -47,7 +44,6 @@ #endif #if defined(__NetBSD__) && (defined(__i386__) || defined(__x86_64__)) -#include <sys/types.h> #include <machine/sysarch.h> #if defined(__i386__) #define iopl i386_iopl -- To view, visit https://review.coreboot.org/c/coreboot/+/86330?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iaf10e1b9fb8ce51605a75ec0a92ee33924c42aa6 Gerrit-Change-Number: 86330 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr>

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[XS] Change in coreboot[main]: acpi/acpi.h: Use boolean
by Elyes Haouas (Code Review) 08 Feb '25

08 Feb '25

Attention is currently required from: Felix Singer. Hello Felix Singer, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/84858?usp=email to look at the new patch set (#6). Change subject: acpi/acpi.h: Use boolean ...................................................................... acpi/acpi.h: Use boolean permanent_smi_handler and acpi_s3_resume_allowed returns boolean, so use boolean instead of int. Change-Id: I8f390bf3b472519dc41db7daa57b16458961139e Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> --- M src/include/acpi/acpi.h 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/58/84858/6 -- To view, visit https://review.coreboot.org/c/coreboot/+/84858?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I8f390bf3b472519dc41db7daa57b16458961139e Gerrit-Change-Number: 84858 Gerrit-PatchSet: 6 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de>

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[M] Change in coreboot[main]: fatcat: Add 64M fmd file
by Dolan Liu (Code Review) 08 Feb '25

08 Feb '25

Dolan Liu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/86328?usp=email ) Change subject: fatcat: Add 64M fmd file ...................................................................... fatcat: Add 64M fmd file add 64MiB size rom support on fatcat only add size to 64M and no others flashmap change Change-Id: I7df35f89c7a42e92bba66a292722ef7a3374c4fd --- M src/mainboard/google/fatcat/Kconfig A src/mainboard/google/fatcat/chromeos-64M.fmd 2 files changed, 54 insertions(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/28/86328/1 diff --git a/src/mainboard/google/fatcat/Kconfig b/src/mainboard/google/fatcat/Kconfig index e82081d..a67ea3b 100644 --- a/src/mainboard/google/fatcat/Kconfig +++ b/src/mainboard/google/fatcat/Kconfig @@ -3,16 +3,14 @@ config BOARD_GOOGLE_FATCAT_COMMON def_bool n select BOARD_ROMSIZE_KB_32768 - select DRIVERS_GFX_GENERIC select DRIVERS_I2C_GENERIC select DRIVERS_I2C_HID - select DRIVERS_INTEL_DPTF select DRIVERS_INTEL_MIPI_CAMERA select DRIVERS_INTEL_PMC select DRIVERS_INTEL_SOUNDWIRE select DRIVERS_WWAN_FM350GL select DRIVERS_AUDIO_SOF - select DRIVERS_SOUNDWIRE_ALC_BASE_7XX + select DRIVERS_SOUNDWIRE_ALC722 select DRIVERS_SPI_ACPI select DUMP_SMBIOS_TYPE17 select EC_ACPI @@ -33,7 +31,6 @@ select MAINBOARD_HAS_TPM2 select MB_COMPRESS_RAMSTAGE_LZ4 select PMC_IPC_ACPI_INTERFACE - select SOC_INTEL_COMMON_BLOCK_VARIANT_POWER_LIMIT select SOC_INTEL_CSE_LITE_SYNC_BY_PAYLOAD select SOC_INTEL_CSE_SEND_EOP_BY_PAYLOAD select SOC_INTEL_PANTHERLAKE_U_H @@ -44,7 +41,6 @@ select BOARD_GOOGLE_FATCAT_COMMON select CHROMEOS_WIFI_SAR if CHROMEOS select DRIVERS_INTEL_ISH - select DRIVER_INTEL_ISH_HAS_MAIN_FW select DRIVERS_INTEL_USB4_RETIMER select HAVE_SLP_S0_GATE select MAINBOARD_HAS_CHROMEOS @@ -58,7 +54,6 @@ config BOARD_GOOGLE_MODEL_FATCAT def_bool n select BOARD_GOOGLE_BASEBOARD_FATCAT - select DRIVERS_GENERIC_BAYHUB_LV2 select DRIVERS_GENERIC_MAX98357A config BOARD_GOOGLE_FATCAT @@ -118,7 +113,10 @@ hex default 0x03 if BOARD_GOOGLE_MODEL_FATCAT default 0x01 if BOARD_GOOGLE_FRANCKA - default 0x01 if BOARD_GOOGLE_FELINO + +config FMDFILE + default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/chromeos-debug-fsp.fmd" if CHROMEOS && BUILDING_WITH_DEBUG_FSP + default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/chromeos.fmd" if CHROMEOS config HAVE_SLP_S0_GATE def_bool n diff --git a/src/mainboard/google/fatcat/chromeos-64M.fmd b/src/mainboard/google/fatcat/chromeos-64M.fmd new file mode 100644 index 0000000..1e43dad --- /dev/null +++ b/src/mainboard/google/fatcat/chromeos-64M.fmd @@ -0,0 +1,49 @@ +FLASH 64M { + SI_ALL 8M { + SI_DESC 16K + SI_ME + } + SI_BIOS 24M { + RW_SECTION_A 8M { + VBLOCK_A 8K + FW_MAIN_A(CBFS) + RW_FWID_A 64 + } + # This section starts at the 16M boundary in SPI flash. + # PTL does not support a region crossing this boundary, + # because the SPI flash is memory-mapped into two non- + # contiguous windows. + RW_SECTION_B 8M { + VBLOCK_B 8K + FW_MAIN_B(CBFS) + RW_FWID_B 64 + } + RW_MISC 1M { + UNIFIED_MRC_CACHE(PRESERVE) 128K { + RECOVERY_MRC_CACHE 64K + RW_MRC_CACHE 64K + } + RW_ELOG(PRESERVE) 16K + RW_SHARED 16K { + SHARED_DATA 8K + VBLOCK_DEV 8K + } + RW_VPD(PRESERVE) 8K + RW_NVRAM(PRESERVE) 24K + } + RW_LEGACY(CBFS) 1M + RW_UNUSED 2M + # Make WP_RO region align with SPI vendor + # memory protected range specification. + WP_RO 4M { + RO_VPD(PRESERVE) 16K + RO_GSCVD 8K + RO_SECTION { + FMAP 2K + RO_FRID 64 + GBB@4K 12K + COREBOOT(CBFS) + } + } + } +} -- To view, visit https://review.coreboot.org/c/coreboot/+/86328?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I7df35f89c7a42e92bba66a292722ef7a3374c4fd Gerrit-Change-Number: 86328 Gerrit-PatchSet: 1 Gerrit-Owner: Dolan Liu <liuyong5(a)huaqin.corp-partner.google.com>

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[XS] Change in coreboot[main]: include/smp/node: Drop unused is_smp_boot
by Elyes Haouas (Code Review) 08 Feb '25

08 Feb '25

Elyes Haouas has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/86327?usp=email ) Change subject: include/smp/node: Drop unused is_smp_boot ...................................................................... include/smp/node: Drop unused is_smp_boot Change-Id: I831d405c58817da64eb241f432a3eb8a096dbe1b Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> --- M src/include/smp/node.h 1 file changed, 0 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/27/86327/1 diff --git a/src/include/smp/node.h b/src/include/smp/node.h index 8f3d14f..78db124 100644 --- a/src/include/smp/node.h +++ b/src/include/smp/node.h @@ -9,9 +9,4 @@ #define boot_cpu(x) 1 #endif -static inline int is_smp_boot(void) -{ - return CONFIG(SMP) && CONFIG_MAX_CPUS > 1; -} - #endif /* _SMP_NODE_H_ */ -- To view, visit https://review.coreboot.org/c/coreboot/+/86327?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I831d405c58817da64eb241f432a3eb8a096dbe1b Gerrit-Change-Number: 86327 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr>

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[XS] Change in coreboot[main]: cpu/intel/haswell: Use boolean for haswell_is_ult
by Elyes Haouas (Code Review) 08 Feb '25

08 Feb '25

Elyes Haouas has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/86326?usp=email ) Change subject: cpu/intel/haswell: Use boolean for haswell_is_ult ...................................................................... cpu/intel/haswell: Use boolean for haswell_is_ult Change-Id: I319fd385231c0195793781722c563477816b93cd Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> --- M src/cpu/intel/haswell/haswell.h 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/26/86326/1 diff --git a/src/cpu/intel/haswell/haswell.h b/src/cpu/intel/haswell/haswell.h index 5697d0f..a991299 100644 --- a/src/cpu/intel/haswell/haswell.h +++ b/src/cpu/intel/haswell/haswell.h @@ -181,7 +181,7 @@ return cpuid_eax(1) & 0xf; } -static inline int haswell_is_ult(void) +static inline bool haswell_is_ult(void) { return CONFIG(INTEL_LYNXPOINT_LP); } -- To view, visit https://review.coreboot.org/c/coreboot/+/86326?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I319fd385231c0195793781722c563477816b93cd Gerrit-Change-Number: 86326 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr>

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[XS] Change in coreboot[main]: device/Kconfig: Make option to allocate above 4G appear in Kconfig
by Angel Pons (Code Review) 08 Feb '25

08 Feb '25

Attention is currently required from: Alicja Michalska, Arthur Heymans, David Hendricks, Felix Held. Angel Pons has posted comments on this change by Alicja Michalska. ( https://review.coreboot.org/c/coreboot/+/86131?usp=email ) Change subject: device/Kconfig: Make option to allocate above 4G appear in Kconfig ...................................................................... Patch Set 5: (2 comments) File src/device/Kconfig: https://review.coreboot.org/c/coreboot/+/86131/comment/ad0f37a0_0ffef044?us… : PS4, Line 1015: default y > Gotcha, reverted :) Done https://review.coreboot.org/c/coreboot/+/86131/comment/69c97765_98c68be0?us… : PS4, Line 1014: default n > ```suggestion […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/86131?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ia17b3312016409d8fd6bcce4321481a7b7e35ce5 Gerrit-Change-Number: 86131 Gerrit-PatchSet: 5 Gerrit-Owner: Alicja Michalska <ahplka19(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Attention: Alicja Michalska <ahplka19(a)gmail.com> Gerrit-Attention: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Sat, 08 Feb 2025 08:38:23 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Alicja Michalska <ahplka19(a)gmail.com> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Comment-In-Reply-To: Felix Held <felix-coreboot(a)felixheld.de>

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[XS] Change in coreboot[main]: mb/erying/tgl: Drop specifying which timers to use
by Angel Pons (Code Review) 08 Feb '25

08 Feb '25

Attention is currently required from: Alicja Michalska, Jérémy Compostella, Matt DeVillier. Angel Pons has posted comments on this change by Alicja Michalska. ( https://review.coreboot.org/c/coreboot/+/86093?usp=email ) Change subject: mb/erying/tgl: Drop specifying which timers to use ...................................................................... Patch Set 5: Code-Review+2 (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/86093/comment/37839a29_9c26c52b?us… : PS5, Line 10: If we build coreboot with both timers =N, system enters s0ix state (although it doesn't cut the power to the platform) and can be woken up by pressing the key on the keyboard. Please wrap lines at 72 characters -- To view, visit https://review.coreboot.org/c/coreboot/+/86093?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If6e0ac1d289447c292a49111251d321c951078e2 Gerrit-Change-Number: 86093 Gerrit-PatchSet: 5 Gerrit-Owner: Alicja Michalska <ahplka19(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Attention: Alicja Michalska <ahplka19(a)gmail.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Comment-Date: Sat, 08 Feb 2025 08:37:07 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes

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[XS] Change in coreboot[main]: acpi/acpi.h: Use boolean for permanent_smi_handler()
by Elyes Haouas (Code Review) 08 Feb '25

08 Feb '25

Attention is currently required from: Felix Singer. Elyes Haouas has posted comments on this change by Elyes Haouas. ( https://review.coreboot.org/c/coreboot/+/84858?usp=email ) Change subject: acpi/acpi.h: Use boolean for permanent_smi_handler() ...................................................................... Patch Set 4: (2 comments) File src/include/acpi/acpi.h: https://review.coreboot.org/c/coreboot/+/84858/comment/5eaf47ee_1167f529?us… : PS3, Line 1976: static inline int acpi_s3_resume_allowed(void) > This too? Acknowledged https://review.coreboot.org/c/coreboot/+/84858/comment/97c25f91_a810dd3e?us… : PS3, Line 1981: static inline int acpi_is_wakeup_s3(void) > This too? this one, needs some work -- To view, visit https://review.coreboot.org/c/coreboot/+/84858?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I8f390bf3b472519dc41db7daa57b16458961139e Gerrit-Change-Number: 84858 Gerrit-PatchSet: 4 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Comment-Date: Sat, 08 Feb 2025 08:23:38 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Felix Singer <service+coreboot-gerrit(a)felixsinger.de>

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[XS] Change in coreboot[main]: soc/mediatek/common: Measure mtk_fsp_load_and_run() execution time
by Yu-Ping Wu (Code Review) 08 Feb '25

08 Feb '25

Attention is currently required from: Hung-Te Lin, Yidi Lin. Yu-Ping Wu has posted comments on this change by Yidi Lin. ( https://review.coreboot.org/c/coreboot/+/86325?usp=email ) Change subject: soc/mediatek/common: Measure mtk_fsp_load_and_run() execution time ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/86325?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I61706952bef4590c5bfd09707a08a4f1a25fbda2 Gerrit-Change-Number: 86325 Gerrit-PatchSet: 1 Gerrit-Owner: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-Comment-Date: Sat, 08 Feb 2025 07:56:33 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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