Sean Rhodes has submitted this change. ( https://review.coreboot.org/c/coreboot/+/86310?usp=email )
Change subject: mb/starlabs/starbook/mtl: Change the user board type
......................................................................
mb/starlabs/starbook/mtl: Change the user board type
Change the board type to ULX as seen in the AMI CRB. This fixes
failed memory training for certain memory modules.
Change-Id: I951387fcfc0be8fb931b4c5ac0b5f022e057b371
Signed-off-by: Sean Rhodes <sean(a)starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86310
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier(a)gmail.com>
---
M src/mainboard/starlabs/starbook/variants/mtl/romstage.c
1 file changed, 1 insertion(+), 1 deletion(-)
Approvals:
build bot (Jenkins): Verified
Matt DeVillier: Looks good to me, approved
diff --git a/src/mainboard/starlabs/starbook/variants/mtl/romstage.c b/src/mainboard/starlabs/starbook/variants/mtl/romstage.c
index d938bad..7d9b9ae 100644
--- a/src/mainboard/starlabs/starbook/variants/mtl/romstage.c
+++ b/src/mainboard/starlabs/starbook/variants/mtl/romstage.c
@@ -10,7 +10,7 @@
const struct mb_cfg mem_config = {
.type = MEM_TYPE_DDR5,
.ect = true,
- .UserBd = BOARD_TYPE_MOBILE,
+ .UserBd = BOARD_TYPE_ULT_ULX,
.ddr_config = {
.dq_pins_interleaved = false,
},
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Gerrit-Change-Id: I951387fcfc0be8fb931b4c5ac0b5f022e057b371
Gerrit-Change-Number: 86310
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Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems>
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Sean Rhodes has submitted this change. ( https://review.coreboot.org/c/coreboot/+/86317?usp=email )
Change subject: ec/starlabs/merlin: Remove unused name objects
......................................................................
ec/starlabs/merlin: Remove unused name objects
These are not referenced anywhere, so remove them.
Change-Id: Ieb66099dcb9e13b26e6a7a752584537c060c8c18
Signed-off-by: Sean Rhodes <sean(a)starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86317
Reviewed-by: Matt DeVillier <matt.devillier(a)gmail.com>
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
---
M src/ec/starlabs/merlin/acpi/ec.asl
1 file changed, 0 insertions(+), 24 deletions(-)
Approvals:
build bot (Jenkins): Verified
Matt DeVillier: Looks good to me, approved
diff --git a/src/ec/starlabs/merlin/acpi/ec.asl b/src/ec/starlabs/merlin/acpi/ec.asl
index 8fa16c5..3560484 100644
--- a/src/ec/starlabs/merlin/acpi/ec.asl
+++ b/src/ec/starlabs/merlin/acpi/ec.asl
@@ -11,30 +11,6 @@
Name (_GPE, CONFIG_EC_GPE_SCI)
Name (ECAV, 0x00)
Name (ECTK, 0x01)
- Name (B2ST, 0x00)
- Name (CFAN, 0x00)
- Name (CMDR, 0x00)
- Name (DOCK, 0x00)
- Name (PLMX, 0x00)
- Name (PECH, 0x00)
- Name (PECL, 0x00)
- Name (PENV, 0x00)
- Name (PINV, 0x00)
- Name (PPSH, 0x00)
- Name (PPSL, 0x00)
- Name (PSTP, 0x00)
- Name (RPWR, 0x00)
- Name (VPWR, 0x00)
- Name (WTMS, 0x00)
- Name (AWT2, 0x00)
- Name (AWT1, 0x00)
- Name (AWT0, 0x00)
- Name (DLED, 0x00)
- Name (SPT2, 0x00)
- Name (PB10, 0x00)
- Name (IWCW, 0x00)
- Name (IWCR, 0x00)
- Name (PVOL, 0x00)
Mutex (ECMT, 0x00)
Name (BFFR, ResourceTemplate()
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Yidi Lin has posted comments on this change by Jarried Lin. ( https://review.coreboot.org/c/coreboot/+/86311?usp=email )
Change subject: mb/google/rauru: Deassert PCIe PERST# earlier in romstage
......................................................................
Patch Set 3:
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/86311/comment/5cc9857d_8a539b47?us… :
PS3, Line 10: This change helps to optimize
: the initialization sequence and reduce overall boot time.
> Please document the measured numbers. Now as a Gerrit comment for posterity.
Not necessary. It does the same trick like CB:84118. And currently, there is no variant equipped with NVMe storage.
https://review.coreboot.org/c/coreboot/+/86311/comment/27aec03c_54f447d3?us… :
PS3, Line 14: TEST=Build pass
> Obviously you did more tests. Please do not accept such boiler plate TEST= lines in the future.
It is enough. See above comment.
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Change subject: mb/google/rauru: Deassert PCIe PERST# earlier in romstage
......................................................................
Patch Set 3:
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/86311/comment/a1726196_e0e62e44?us… :
PS3, Line 10: This change helps to optimize
: the initialization sequence and reduce overall boot time.
Please document the measured numbers. Now as a Gerrit comment for posterity.
https://review.coreboot.org/c/coreboot/+/86311/comment/45b874ba_c30d576f?us… :
PS3, Line 14: TEST=Build pass
Obviously you did more tests. Please do not accept such boiler plate TEST= lines in the future.
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Hello Alexander Couzens, Angel Pons, Felix Held, Intel coreboot Reviewers, Julius Werner, Matt DeVillier, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/86331?usp=email
to look at the new patch set (#4).
Change subject: tree: Use boolean for s3resume
......................................................................
tree: Use boolean for s3resume
Change-Id: I3e23134f879fcaf817cf62b641e9b59563eb643b
Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr>
---
M src/arch/arm64/include/arch/acpi.h
M src/drivers/amd/agesa/mtrr_fixme.c
M src/drivers/tpm/tpm.c
M src/include/acpi/acpi.h
M src/include/cbmem.h
M src/include/romstage_handoff.h
M src/include/stage_cache.h
M src/lib/bootblock.c
M src/lib/imd_cbmem.c
M src/lib/romstage_handoff.c
M src/mainboard/dell/snb_ivb_workstations/romstage.c
M src/mainboard/emulation/qemu-i440fx/romstage.c
M src/mainboard/emulation/qemu-q35/romstage.c
M src/mainboard/google/auron/ec.c
M src/mainboard/google/auron/variants/gandof/variant.c
M src/mainboard/google/auron/variants/lulu/variant.c
M src/mainboard/google/auron/variants/samus/variant.c
M src/mainboard/google/link/early_init.c
M src/mainboard/google/slippy/ec.c
M src/mainboard/google/stout/early_init.c
M src/mainboard/kontron/ktqm77/early_init.c
M src/mainboard/lenovo/t420/early_init.c
M src/mainboard/lenovo/t420s/early_init.c
M src/mainboard/lenovo/t430/early_init.c
M src/mainboard/lenovo/t430s/variants/t430s/romstage.c
M src/mainboard/lenovo/t520/early_init.c
M src/mainboard/lenovo/t530/early_init.c
M src/mainboard/supermicro/x9scl/early_init.c
M src/northbridge/amd/agesa/agesa_helper.h
M src/northbridge/amd/agesa/state_machine.h
M src/northbridge/intel/e7505/romstage.c
M src/northbridge/intel/gm45/gm45.h
M src/northbridge/intel/gm45/raminit.c
M src/northbridge/intel/gm45/raminit_read_write_training.c
M src/northbridge/intel/gm45/romstage.c
M src/northbridge/intel/haswell/broadwell_mrc/raminit.c
M src/northbridge/intel/haswell/haswell_mrc/raminit.c
M src/northbridge/intel/haswell/native_raminit/raminit_native.c
M src/northbridge/intel/haswell/raminit.h
M src/northbridge/intel/haswell/romstage.c
M src/northbridge/intel/i440bx/raminit.c
M src/northbridge/intel/i440bx/raminit.h
M src/northbridge/intel/i945/early_init.c
M src/northbridge/intel/i945/i945.h
M src/northbridge/intel/i945/romstage.c
M src/northbridge/intel/ironlake/quickpath.c
M src/northbridge/intel/ironlake/raminit.c
M src/northbridge/intel/ironlake/raminit.h
M src/northbridge/intel/ironlake/romstage.c
M src/northbridge/intel/pineview/romstage.c
M src/northbridge/intel/sandybridge/raminit.c
M src/northbridge/intel/sandybridge/raminit_common.h
M src/northbridge/intel/sandybridge/raminit_mrc.c
M src/northbridge/intel/sandybridge/raminit_native.c
M src/northbridge/intel/sandybridge/romstage.c
M src/northbridge/intel/sandybridge/sandybridge.h
M src/northbridge/intel/x4x/raminit.c
M src/northbridge/via/cx700/romstage.c
M src/security/intel/txt/ramstage.c
M src/soc/amd/stoneyridge/romstage.c
M src/soc/intel/baytrail/romstage/raminit.c
M src/soc/intel/baytrail/romstage/romstage.c
M src/soc/intel/broadwell/include/soc/romstage.h
M src/soc/intel/broadwell/raminit.c
M src/soc/intel/broadwell/romstage.c
M src/southbridge/intel/lynxpoint/early_pch_native.c
M src/southbridge/intel/lynxpoint/pch.h
67 files changed, 102 insertions(+), 94 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/86331/4
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Change subject: mb/google/fatcat/var/francka: Decrease trace length of USB-A phy to short
......................................................................
Patch Set 4:
(3 comments)
Patchset:
PS4:
Please do not refer to non-public issues.
Commit Message:
https://review.coreboot.org/c/coreboot/+/86285/comment/6a88dcb0_08fb529c?us… :
PS2, Line 9: To resolve the issue of not being able to boot from USB on Francka
> Refer to issue ID 394206896.
I am denied access. Please mention it here.
https://review.coreboot.org/c/coreboot/+/86285/comment/83dd7c06_38b23572?us… :
PS2, Line 9: the USB PHY settings need to be modified
> Refer to issue ID 394206896.
Please update it here.
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Change subject: mb/starlabs/starbook/mtl: Correct DIMM Speed Size
......................................................................
Patch Set 2:
(1 comment)
File src/mainboard/starlabs/starbook/Kconfig:
https://review.coreboot.org/c/coreboot/+/86306/comment/131db901_a0f102ee?us… :
PS2, Line 141: SPD
In the commit message you talk about speed. How is it related?
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Change subject: mb/starlabs/starbook/mtl: Add rcomp configuration
......................................................................
Patch Set 3:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/86307/comment/ffa5c80a_97b1963c?us… :
PS3, Line 10: for certain memory modules
For posterity, it’d be great if you listed the modules you experienced this with.
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