coreboot-gerrit February 2025

coreboot-gerrit@coreboot.org

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[M] Change in coreboot[main]: drivers/asmedia: Add code to enable AHCI for ASM1061
by Paul Menzel (Code Review) 09 Feb '25

09 Feb '25

Attention is currently required from: Nicholas Chin. Paul Menzel has posted comments on this change by Nicholas Chin. ( https://review.coreboot.org/c/coreboot/+/85816?usp=email ) Change subject: drivers/asmedia: Add code to enable AHCI for ASM1061 ...................................................................... Patch Set 6: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/85816/comment/832933ce_42535663?us… : PS6, Line 23: Tested on the ASUS Maximus VI Gene. For posterity (in Gerrit), it’d be great if you pasted the new log line. File src/drivers/asmedia/asm1061.c: https://review.coreboot.org/c/coreboot/+/85816/comment/de53fc49_1bb947f4?us… : PS6, Line 47: .devices = pci_device_ids, Ic49dc56263cafce3cfe40bb3ed7036fa25300f9f (drivers/asmedia/asm1061: Align = only with tabs and not spaces) [1] [1]: https://review.coreboot.org/c/coreboot/+/86335 -- To view, visit https://review.coreboot.org/c/coreboot/+/85816?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I7a1470894261c7d14fadccdcade968f87f78fe23 Gerrit-Change-Number: 85816 Gerrit-PatchSet: 6 Gerrit-Owner: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Jan Philipp Groß <jeangrande(a)mailbox.org> Gerrit-Reviewer: Riku Viitanen <riku.viitanen(a)protonmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Comment-Date: Sun, 09 Feb 2025 06:56:58 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[XS] Change in coreboot[main]: drivers/asmedia/asm1061: Align = only with tabs and not spaces
by Paul Menzel (Code Review) 09 Feb '25

09 Feb '25

Paul Menzel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/86335?usp=email ) Change subject: drivers/asmedia/asm1061: Align = only with tabs and not spaces ...................................................................... drivers/asmedia/asm1061: Align = only with tabs and not spaces The `.devices` line only had once space before the =, as the tab boundary is directly after the s of devices. The lines above had once space after the last tab, so the equal sign is closer to the left side. As the whole file aligns the equal sign, replace the space by a tab, and do *not* go the route of not aligning the equal signs. Change-Id: Ic49dc56263cafce3cfe40bb3ed7036fa25300f9f Signed-off-by: Paul Menzel <pmenzel(a)molgen.mpg.de> --- M src/drivers/asmedia/asm1061.c 1 file changed, 3 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/35/86335/1 diff --git a/src/drivers/asmedia/asm1061.c b/src/drivers/asmedia/asm1061.c index 6d2edaa..29d2704 100644 --- a/src/drivers/asmedia/asm1061.c +++ b/src/drivers/asmedia/asm1061.c @@ -42,7 +42,7 @@ }; static const struct pci_driver asmedia_asm1061 __pci_driver = { - .ops = &asm1061_ops, - .vendor = 0x1b21, - .devices = pci_device_ids, + .ops = &asm1061_ops, + .vendor = 0x1b21, + .devices = pci_device_ids, }; -- To view, visit https://review.coreboot.org/c/coreboot/+/86335?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ic49dc56263cafce3cfe40bb3ed7036fa25300f9f Gerrit-Change-Number: 86335 Gerrit-PatchSet: 1 Gerrit-Owner: Paul Menzel <paulepanter(a)mailbox.org>

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[L] Change in coreboot[main]: mb/lenovo: Add ThinkCentre M900 (Skylake/LGA 1151)
by Nicholas Chin (Code Review) 09 Feb '25

09 Feb '25

Attention is currently required from: Alexander Couzens, Felix Singer, Paul Menzel. Nicholas Chin has posted comments on this change by Nicholas Chin. ( https://review.coreboot.org/c/coreboot/+/74187?usp=email ) Change subject: mb/lenovo: Add ThinkCentre M900 (Skylake/LGA 1151) ...................................................................... Patch Set 3: (18 comments) File src/mainboard/lenovo/m900/Kconfig: https://review.coreboot.org/c/coreboot/+/74187/comment/67dc7d46_1c69cbbd?us… : PS2, Line 1: if BOARD_LENOVO_M900 > ```suggestion […] Done https://review.coreboot.org/c/coreboot/+/74187/comment/62f8cb45_d7166ca2?us… : PS2, Line 5: select BOARD_ROMSIZE_KB_16384 : select HAVE_ACPI_RESUME : select HAVE_ACPI_TABLES : select HAVE_OPTION_TABLE : select HAVE_CMOS_DEFAULT : select INTEL_GMA_HAVE_VBT : select INTEL_INT15 : select SOC_INTEL_SKYLAKE : select SKYLAKE_SOC_PCH_H : select SUPERIO_NUVOTON_COMMON_PRE_RAM : select MAINBOARD_HAS_LIBGFXINIT > ``` […] Done https://review.coreboot.org/c/coreboot/+/74187/comment/0cc32fdf_63133bf5?us… : PS2, Line 27: hex > Remove Done File src/mainboard/lenovo/m900/Kconfig.name: https://review.coreboot.org/c/coreboot/+/74187/comment/5fc684c0_850b13ba?us… : PS2, Line 1: config BOARD_LENOVO_M900 > ```suggestion […] Done File src/mainboard/lenovo/m900/Makefile.inc: PS2: > Rebase and rename to Makefile. […] Done File src/mainboard/lenovo/m900/devicetree.cb: PS2: > Use chipset. […] Done PS2: > A lot of the configuration here is probably wrong, as it's mostly unchanged from the H110M Done https://review.coreboot.org/c/coreboot/+/74187/comment/994d82f7_dc118db3?us… : PS2, Line 21: r > Move that under iGPU Done https://review.coreboot.org/c/coreboot/+/74187/comment/5a33c8a8_abf3c4cf?us… : PS2, Line 53: register "usb2_ports[0]" = "USB2_PORT_MID(OC0)" : register "usb2_ports[1]" = "USB2_PORT_MID(OC0)" : register "usb2_ports[2]" = "USB2_PORT_MID(OC4)" : register "usb2_ports[3]" = "USB2_PORT_MID(OC4)" : register "usb2_ports[4]" = "USB2_PORT_MID(OC2)" : register "usb2_ports[5]" = "USB2_PORT_MID(OC2)" : register "usb2_ports[6]" = "USB2_PORT_MID(OC0)" : register "usb2_ports[7]" = "USB2_PORT_MID(OC0)" : register "usb2_ports[8]" = "USB2_PORT_MID(OC0)" : register "usb2_ports[9]" = "USB2_PORT_MID(OC0)" : register "usb2_ports[10]" = "USB2_PORT_MID(OC1)" : register "usb2_ports[11]" = "USB2_PORT_MID(OC1)" : register "usb2_ports[12]" = "USB2_PORT_MID(OC_SKIP)" : register "usb2_ports[13]" = "USB2_PORT_MID(OC_SKIP)" > ```suggestion […] Done https://review.coreboot.org/c/coreboot/+/74187/comment/d883324f_fc31e2ef?us… : PS2, Line 68: register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)" : register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC0)" : register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC3)" : register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC3)" : register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC1)" : register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC1)" : register "usb3_ports[6]" = "USB3_PORT_DEFAULT(OC_SKIP)" : register "usb3_ports[7]" = "USB3_PORT_DEFAULT(OC_SKIP)" : register "usb3_ports[8]" = "USB3_PORT_DEFAULT(OC_SKIP)" : > ```suggestion […] Done https://review.coreboot.org/c/coreboot/+/74187/comment/1fa43789_f268fd59?us… : PS2, Line 97: register "SataPortsEnable" = "{ \ : [0] = 1, \ : [1] = 1, \ : [2] = 1, \ : [3] = 1, \ : }" > The backslashes for line continuation are not needed […] Done https://review.coreboot.org/c/coreboot/+/74187/comment/49fcf8de_245cc7b7?us… : PS2, Line 155: # Set LPC Serial IRQ mode > Seems superfluous too Done https://review.coreboot.org/c/coreboot/+/74187/comment/b9198c81_bba00b02?us… : PS2, Line 157: > Remove superfluous lines Done https://review.coreboot.org/c/coreboot/+/74187/comment/9c1f582d_59ac6a57?us… : PS2, Line 159: # LPC Interface > It's already in line 150 Done File src/mainboard/lenovo/m900/gpio.h: PS2: > Look into regenerating this, as it doesn't look like the typical gpio.h format in other boards. […] Done File src/mainboard/lenovo/m900/hda_verb.c: https://review.coreboot.org/c/coreboot/+/74187/comment/3a71d365_164ac3af?us… : PS2, Line 13: 0x411111f0 > ```suggestion […] Done https://review.coreboot.org/c/coreboot/+/74187/comment/b42c4026_89c710d7?us… : PS2, Line 18: 0x411111f0 > ```suggestion […] Done https://review.coreboot.org/c/coreboot/+/74187/comment/c606ee40_8175777e?us… : PS2, Line 20: 0x411111f0 > ```suggestion […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/74187?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I4e70c9f42c19f130a00170b32ae74b61f0483a22 Gerrit-Change-Number: 74187 Gerrit-PatchSet: 3 Gerrit-Owner: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Comment-Date: Sun, 09 Feb 2025 06:17:39 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Comment-In-Reply-To: Nicholas Chin <nic.c3.14(a)gmail.com>

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[L] Change in coreboot[main]: mb/lenovo: Add ThinkCentre M900 (Skylake/LGA 1151)
by Nicholas Chin (Code Review) 09 Feb '25

09 Feb '25

Attention is currently required from: Alexander Couzens, Nicholas Chin, Paul Menzel. Hello Alexander Couzens, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/74187?usp=email to look at the new patch set (#3). Change subject: mb/lenovo: Add ThinkCentre M900 (Skylake/LGA 1151) ...................................................................... mb/lenovo: Add ThinkCentre M900 (Skylake/LGA 1151) The mainboard is marked IQ1X0MS, though it is also known as the MS-7988. The Small Form Factor version was used for this port, though the Mini Tower seems to use the exact same board. Other systems such as the ThinkCentre M800, ThinkStation P310, ThinkStation P320, and IdeaCentre 700-25ISH appear to use the same PCB with different configurations of components. All the code in this port was originally copied from the Asrock H110M and then modified to match the actual configuration of the M900. The VBT was extracted using `intelvbttool -l -v data.vbt` while running version FWKTBFA of the vendor firmware. Working: - Boots to Linux with SeaBIOS 1.16.3 - Boots to Linux with EDK2 (MrChromebox uefipayload_202408) - Display Ports - VGA port - PCIe slots - Console over serial port - Front and rear USB 3.0 ports and internal USB2.0 headers - Front and rear audio jacks - Internal speaker - SATA ports 1-4 (5 and 6 are not populated on the M900) - Hardware monitoring via nct6683 kernel module - Gigabit Ethernet - S3 suspend/resume Unknown/untested: - M.2 E-key slot - Parallel port header - PS/2 Mouse/Keyboard via KB_MS1 header - TPM Change-Id: I4e70c9f42c19f130a00170b32ae74b61f0483a22 Signed-off-by: Nicholas Chin <nic.c3.14(a)gmail.com> --- A src/mainboard/lenovo/m900/Kconfig A src/mainboard/lenovo/m900/Kconfig.name A src/mainboard/lenovo/m900/Makefile.mk A src/mainboard/lenovo/m900/acpi/dptf.asl A src/mainboard/lenovo/m900/acpi/ec.asl A src/mainboard/lenovo/m900/acpi/mainboard.asl A src/mainboard/lenovo/m900/acpi/superio.asl A src/mainboard/lenovo/m900/board_info.txt A src/mainboard/lenovo/m900/bootblock.c A src/mainboard/lenovo/m900/cmos.default A src/mainboard/lenovo/m900/cmos.layout A src/mainboard/lenovo/m900/data.vbt A src/mainboard/lenovo/m900/devicetree.cb A src/mainboard/lenovo/m900/dsdt.asl A src/mainboard/lenovo/m900/gma-mainboard.ads A src/mainboard/lenovo/m900/gpio.h A src/mainboard/lenovo/m900/hda_verb.c A src/mainboard/lenovo/m900/mainboard.c A src/mainboard/lenovo/m900/ramstage.c A src/mainboard/lenovo/m900/romstage.c 20 files changed, 816 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/87/74187/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/74187?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I4e70c9f42c19f130a00170b32ae74b61f0483a22 Gerrit-Change-Number: 74187 Gerrit-PatchSet: 3 Gerrit-Owner: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Attention: Alexander Couzens <lynxis(a)fe80.eu>

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[M] Change in coreboot[main]: drivers/intel/fsp2_0: Add low battery indicator screen
by Subrata Banik (Code Review) 08 Feb '25

08 Feb '25

Attention is currently required from: Andrey Petrov, Intel coreboot Reviewers, Julius Werner, Jérémy Compostella, Karthik Ramasubramanian, Ronak Kanabar. Subrata Banik has posted comments on this change by Subrata Banik. ( https://review.coreboot.org/c/coreboot/+/86225?usp=email ) Change subject: drivers/intel/fsp2_0: Add low battery indicator screen ...................................................................... Patch Set 9: (2 comments) File src/drivers/intel/fsp2_0/Kconfig: https://review.coreboot.org/c/coreboot/+/86225/comment/2d7807d8_2384b2db?us… : PS8, Line 527: select BMP_LOGO > This should probably be a `depends on` instead? Acknowledged File src/vendorcode/google/chromeos/Makefile.mk: https://review.coreboot.org/c/coreboot/+/86225/comment/5be20275_f511815f?us… : PS8, Line 45: low_battery.bmp,CONFIG_PLATFORM_LOW_BATTERY_INDICATOR_LOGO_PATH)) > This should go either in `fsp2_0/Makefile.mk` or in `src/lib/Makefile.mk` (because `bmp_logo.c` is there... actually, it's quite weird that we don't have a rule adding a `logo.bmp` file when `HAVE_CUSTOM_BMP_LOGO` is false, that should probably go in there too). not sure if I understand the later one about not having a rule inside fsp2_0/makefile.mk ``` # Add logo to the cbfs image ifneq ($(CONFIG_HAVE_CUSTOM_BMP_LOGO),y) cbfs-files-$(CONFIG_BMP_LOGO) += logo.bmp logo.bmp-file := $(call strip_quotes,$(CONFIG_FSP2_0_LOGO_FILE_NAME)) logo.bmp-type := raw ifeq ($(CONFIG_BMP_LOGO_COMPRESS_LZMA),y) logo.bmp-compression := LZMA else ifeq ($(CONFIG_BMP_LOGO_COMPRESS_LZ4),y) logo.bmp-compression := LZ4 endif endif ``` -- To view, visit https://review.coreboot.org/c/coreboot/+/86225?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I711c53455639b449fe85903139bbc06cdab08d09 Gerrit-Change-Number: 86225 Gerrit-PatchSet: 9 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-CC: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Sun, 09 Feb 2025 03:29:05 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Julius Werner <jwerner(a)chromium.org>

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[M] Change in coreboot[main]: drivers/intel/fsp2_0: Add low battery indicator screen
by Subrata Banik (Code Review) 08 Feb '25

08 Feb '25

Attention is currently required from: Andrey Petrov, Intel coreboot Reviewers, Jérémy Compostella, Karthik Ramasubramanian, Ronak Kanabar, Subrata Banik. Hello Andrey Petrov, Intel coreboot Reviewers, Karthik Ramasubramanian, Ronak Kanabar, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/86225?usp=email to look at the new patch set (#9). The following approvals got outdated and were removed: Code-Review+2 by Karthik Ramasubramanian, Verified+1 by build bot (Jenkins) Change subject: drivers/intel/fsp2_0: Add low battery indicator screen ...................................................................... drivers/intel/fsp2_0: Add low battery indicator screen This commit adds low battery indicator bitmap into CBFS. This screen is displayed when the system detects a critically low battery condition. The screen displays a logo and can be configured with a custom path. An option to display an early low battery indicator in text mode is also included. This early indicator can defer the firmware update. This feature is controlled by the PLATFORM_HAS_LOW_BATTERY_INDICATOR Kconfig option. BUG=b:339673254 TEST=Able to see low-battery user notification in text mode before memory init. Verified low-battery boot event listed in the eventlog. Change-Id: I711c53455639b449fe85903139bbc06cdab08d09 Signed-off-by: Subrata Banik <subratabanik(a)google.com> --- M src/drivers/intel/fsp2_0/Kconfig M src/drivers/intel/fsp2_0/Makefile.mk 2 files changed, 56 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/25/86225/9 -- To view, visit https://review.coreboot.org/c/coreboot/+/86225?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I711c53455639b449fe85903139bbc06cdab08d09 Gerrit-Change-Number: 86225 Gerrit-PatchSet: 9 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-CC: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com>

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[M] Change in coreboot[main]: lib: Refactor ux_locales_get_text API
by Subrata Banik (Code Review) 08 Feb '25

08 Feb '25

Attention is currently required from: Dinesh Gehlot, Eran Mitrani, Intel coreboot Reviewers, Jakub "Kuba" Czapiga, Jayvik Desai, Julius Werner, Jérémy Compostella, Kapil Porwal, Nick Vaccaro, Tarun. Hello Dinesh Gehlot, Eran Mitrani, Intel coreboot Reviewers, Jakub "Kuba" Czapiga, Jayvik Desai, Julius Werner, Kapil Porwal, Nick Vaccaro, Tarun, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/86283?usp=email to look at the new patch set (#11). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: lib: Refactor ux_locales_get_text API ...................................................................... lib: Refactor ux_locales_get_text API This patch refactors the `ux_locales_get_text` API to handle fallback text (English) internally, rather than relying on the caller. It introduces message IDs for lookups, enabling the API to locate both the UX locale name and fallback text based on the ID. With this patch, `ux_locales_get_text` API locates UX locales message based on message ID. `ux_locales_get_text` retrieves fallback text message depending upon the message ID if UX locales is not available. This centralizes fallback handling and simplifies adding future messages without per-SoC duplication. BUG=b:339673254 TEST=Built and booted google/brox. Verified eSOL display. Change-Id: I4952802396265b9ee8d164d6e43a7f2b3599d6c0 Signed-off-by: Subrata Banik <subratabanik(a)google.com> --- M src/include/ux_locales.h M src/lib/ux_locales.c M src/soc/intel/alderlake/romstage/ux.c M src/soc/intel/meteorlake/romstage/fsp_params.c M tests/lib/ux_locales-test.c 5 files changed, 97 insertions(+), 74 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/83/86283/11 -- To view, visit https://review.coreboot.org/c/coreboot/+/86283?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I4952802396265b9ee8d164d6e43a7f2b3599d6c0 Gerrit-Change-Number: 86283 Gerrit-PatchSet: 11 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Jakub "Kuba" Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Jakub "Kuba" Czapiga <czapiga(a)google.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Tarun <tstuli(a)gmail.com>

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[S] Change in coreboot[main]: mb/starlabs/*: Use a safe configurations for DRAM Sleep GPIO
by Matt DeVillier (Code Review) 08 Feb '25

08 Feb '25

Attention is currently required from: Sean Rhodes. Matt DeVillier has posted comments on this change by Sean Rhodes. ( https://review.coreboot.org/c/coreboot/+/86332?usp=email ) Change subject: mb/starlabs/*: Use a safe configurations for DRAM Sleep GPIO ...................................................................... Patch Set 1: Code-Review+2 (1 comment) Patchset: PS1: Intel doc #759603 actually contains the GPIO NF list for ADL-N, and GPP_E8 has no native functions. So if using for SLP_DRAM_N, configuring as a GPO with value 1 is correct. -- To view, visit https://review.coreboot.org/c/coreboot/+/86332?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I49b8faa7f8712ad0ead22b7ccbfa6deca6046368 Gerrit-Change-Number: 86332 Gerrit-PatchSet: 1 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Comment-Date: Sun, 09 Feb 2025 00:34:20 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes

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[XS] Change in coreboot[main]: ec/starlabs/merlin: Drop unused reference to events.asl
by Matt DeVillier (Code Review) 08 Feb '25

08 Feb '25

Attention is currently required from: Sean Rhodes. Matt DeVillier has posted comments on this change by Matt DeVillier. ( https://review.coreboot.org/c/coreboot/+/86321?usp=email ) Change subject: ec/starlabs/merlin: Drop unused reference to events.asl ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: > It's needed for the !merlin ones: […] how are those in scope? -- To view, visit https://review.coreboot.org/c/coreboot/+/86321?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ifbb986378dd49c6a1d316a4922c46c46180497ee Gerrit-Change-Number: 86321 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Comment-Date: Sat, 08 Feb 2025 22:07:17 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Sean Rhodes <sean(a)starlabs.systems>

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[S] Change in coreboot[main]: mb/asus/p8h67-i_deluxe: Implement voltage settings
by Riku Viitanen (Code Review) 08 Feb '25

08 Feb '25

Riku Viitanen has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/86334?usp=email ) Change subject: mb/asus/p8h67-i_deluxe: Implement voltage settings ...................................................................... mb/asus/p8h67-i_deluxe: Implement voltage settings Add NCT3933U chips and channel mappings to devicetree. This board can set DRAM, PCH, and VCCIO voltages, plus CPU and iGPU offsets (relative to what is requested by CPU via SVID). Also enable automatic DRAM voltage setting from raminit. Tested with the following modules and a multimeter confirmed the voltages: - 2x HMT41GS6BFR8A-RD -> 1.35V - 2x HMT351S6CFR8C-PB -> 1.5V - HMT41GS6BFR8A-RD + M471B5273DH0-CH9 -> 1.5V Change-Id: Ief2f02b0c2c2f6ba010df2ab4e6ecaef19e50a99 Signed-off-by: Riku Viitanen <riku.viitanen(a)protonmail.com> --- M src/mainboard/asus/h61-series/Kconfig M src/mainboard/asus/h61-series/variants/p8h67-i_deluxe/overridetree.cb 2 files changed, 27 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/34/86334/1 diff --git a/src/mainboard/asus/h61-series/Kconfig b/src/mainboard/asus/h61-series/Kconfig index 4c4fd7e..b4b3bf3 100644 --- a/src/mainboard/asus/h61-series/Kconfig +++ b/src/mainboard/asus/h61-series/Kconfig @@ -63,6 +63,7 @@ config BOARD_ASUS_P8H67_I_DELUXE select BOARD_ASUS_H61_SERIES select BOARD_ROMSIZE_KB_4096 + select DRIVERS_I2C_NCT3933U_DRAM select HAVE_CMOS_DEFAULT select HAVE_OPTION_TABLE select NO_UART_ON_SUPERIO @@ -90,6 +91,12 @@ default "P8H61-M PRO CM6630" if BOARD_ASUS_P8H61_M_PRO_CM6630 default "P8H67-I DELUXE" if BOARD_ASUS_P8H67_I_DELUXE +config MAINBOARD_HW_MAXIMUM_DRAM_VOLTAGE + default 2135 if BOARD_ASUS_P8H67_I_DELUXE + +config MAINBOARD_HW_MINIMUM_DRAM_VOLTAGE + default 865 if BOARD_ASUS_P8H67_I_DELUXE + config OVERRIDE_DEVICETREE default "variants/\$(CONFIG_VARIANT_DIR)/overridetree.cb" diff --git a/src/mainboard/asus/h61-series/variants/p8h67-i_deluxe/overridetree.cb b/src/mainboard/asus/h61-series/variants/p8h67-i_deluxe/overridetree.cb index ef24784..13d595a7 100644 --- a/src/mainboard/asus/h61-series/variants/p8h67-i_deluxe/overridetree.cb +++ b/src/mainboard/asus/h61-series/variants/p8h67-i_deluxe/overridetree.cb @@ -92,6 +92,26 @@ register "sata_interface_speed_support" = "0x3" register "sata_port_map" = "0x1f" # 0-3: internal SATA, 4: eSATA end + device ref smbus on + device i2c 0x10 on + chip drivers/i2c/nct3933u + register "default_mv" = "{0, 0, 1050}" + register "step_uv" = "{0, 5000, 5000}" + device generic 1 off end # unknown + device generic 2 alias cpu_vcore_offset on end + device generic 3 alias vccio on end + end + end + device i2c 0x15 on + chip drivers/i2c/nct3933u + register "default_mv" = "{1500, 1050, 0}" + register "step_uv" = "{5000, 5000, 5000}" + device generic 1 alias v_dram on end + device generic 2 alias v_pch on end + device generic 3 alias igpu_vcore_offset on end + end + end + end end end end -- To view, visit https://review.coreboot.org/c/coreboot/+/86334?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ief2f02b0c2c2f6ba010df2ab4e6ecaef19e50a99 Gerrit-Change-Number: 86334 Gerrit-PatchSet: 1 Gerrit-Owner: Riku Viitanen <riku.viitanen(a)protonmail.com>

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