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Change subject: ec/starlabs/merlin: Drop unused reference to events.asl
......................................................................
Patch Set 1:
(1 comment)
Patchset:
PS1:
> `src/ec/starlabs/merlin/Makefile.mk`: […]
thx, not sure how I missed that
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Change subject: ec/starlabs/merlin: Drop unused reference to events.asl
......................................................................
Patch Set 1:
(1 comment)
Patchset:
PS1:
> how are those in scope?
`src/ec/starlabs/merlin/Makefile.mk`:
```
EC_VARIANT_DIR := $(call strip_quotes, $(CONFIG_EC_VARIANT_DIR))
CPPFLAGS_common += -I$(src)/ec/starlabs/merlin/variants/$(EC_VARIANT_DIR)
```
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Change subject: mb/lenovo: Add ThinkCentre M900 (Skylake/LGA 1151)
......................................................................
Patch Set 5:
(1 comment)
File src/mainboard/lenovo/m900/bootblock.c:
https://review.coreboot.org/c/coreboot/+/74187/comment/d7e445fd_3b09d203?us… :
PS4, Line 9: /* Change to NCT6687D_SP1 to use COM2 header */
> Should probably be a Kconfig
Would tying it to `CONFIG_UART_FOR_CONSOLE` make sense? I had experimented with that locally the other day. Another thing I tried is adding a configurable option in the mainboard Kconfig to select either COM1 or COM2. With that latter option `CONFIG_UART_FOR_CONSOLE` also needs to be set to match what the devicetree sets otherwise coreboot locks up in ramstage when configuring the I/O base addresses for the COM ports in the SuperIO. The former option would also probably lock up the console if index 2 or 3 is selected. One issue with tying it to `CONFIG_UART_FOR_CONSOLE` is that it isn't very obvious which physical port is being used.
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Change subject: mb/lenovo: Add ThinkCentre M900 (Skylake/LGA 1151)
......................................................................
Patch Set 5:
(8 comments)
File src/mainboard/lenovo/m900/Kconfig:
https://review.coreboot.org/c/coreboot/+/74187/comment/e112db4a_2106208b?us… :
PS4, Line 36: config PRERAM_CBMEM_CONSOLE_SIZE
: default 0xd00
> Why is the default value not suitable?
Copypasta from the H110. The console seems to be fine with the default value, so I'll remove the override here.
File src/mainboard/lenovo/m900/acpi/dptf.asl:
PS4:
> Was this tested?
No. Should I remove it?
File src/mainboard/lenovo/m900/cmos.layout:
https://review.coreboot.org/c/coreboot/+/74187/comment/a618cc07_a463d427?us… :
PS4, Line 24: 408 1 e 1 nmi
> Skylake doesn't implement this option, IIRC.
Done
https://review.coreboot.org/c/coreboot/+/74187/comment/4774e0e8_03839fc3?us… :
PS4, Line 28: ChromeOS
> Hmmmmm... […]
It seems like there is an intention to deprecate VBOOT_VBNV_CMOS (https://issuetracker.google.com/issues/235293589; you posted this link on my E6400 patch before). Seems like the code for it is still present though (`security/vboot/vbnv_cmos.c`), and Skylake also seems to select `VBOOT_VBNV_CMOS` and `VBOOT_VBNV_CMOS_BACKUP_TO_FLASH` in `soc/intel/skylake/Kconfig`.
File src/mainboard/lenovo/m900/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/74187/comment/bb0388c9_52797b3e?us… :
PS4, Line 38: register "SendVrMbxCmd" = "2"
> I'm pretty sure this is copy-pasta from a Chromebook that no one knows what it does. […]
Looks like it was added in commit 9a8b67d0af6a ("soc/intel/skylake: Enable another VR mailbox command for certain boards"). Seems like it has something to do with hangs during S0ix and the IVMP8 PS4 power state (can't find much information about that). I've removed it.
File src/mainboard/lenovo/m900/dsdt.asl:
https://review.coreboot.org/c/coreboot/+/74187/comment/46a958a8_d3d218cb?us… :
PS4, Line 25: /* Image processing unit */
: #include <soc/intel/skylake/acpi/ipu.asl>
> I am pretty sure IPU is not used on a desktop. I'm not even sure if it exists on PCH-H platforms.
Done. The IPU seems to be pci 14.3, which only seems to be on the mobile U/Y single chip platforms based on the datasheets.
File src/mainboard/lenovo/m900/ramstage.c:
https://review.coreboot.org/c/coreboot/+/74187/comment/33a97e66_a38e980a?us… :
PS4, Line 12: params->CdClock = 3;
> What does this do? Is this needed?
Seems like it corresponds to the Core Display Clock Frequency selection, based on a comment in `soc/intel/jasperlake/chip.h`. Nowhere else seems to expand the abbreviation. Anyway, according to the Kabylake FSP Integration guide it defaults to 3 so its probably safe to just remove.
File src/mainboard/lenovo/m900/romstage.c:
https://review.coreboot.org/c/coreboot/+/74187/comment/8cc4d842_7b3c6c56?us… :
PS4, Line 21: assert(sizeof(mem_cfg->RcompResistor) == sizeof(rcomp_resistors));
: assert(sizeof(mem_cfg->RcompTarget) == sizeof(rcomp_targets));
> nit: move just above corresponding memcpy()?
Done
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Hello Alexander Couzens, Jan Philipp Groß, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
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Verified+1 by build bot (Jenkins)
Change subject: mb/lenovo: Add ThinkCentre M900 (Skylake/LGA 1151)
......................................................................
mb/lenovo: Add ThinkCentre M900 (Skylake/LGA 1151)
The mainboard is marked IQ1X0MS, though it is also known as the MS-7988.
The Small Form Factor version was used for this port, though the Mini
Tower seems to use the exact same board. Other systems such as the
ThinkCentre M800, ThinkStation P310, ThinkStation P320, and IdeaCentre
700-25ISH appear to use the same PCB with different configurations of
components.
All the code in this port was originally copied from the Asrock H110M
and then modified to match the actual configuration of the M900. The VBT
was extracted using `intelvbttool -l -v data.vbt` while running version
FWKTBFA of the vendor firmware.
Working:
- Boots to Linux with SeaBIOS 1.16.3
- Boots to Linux with EDK2 (MrChromebox uefipayload_202408)
- Display Ports
- VGA port
- PCIe slots
- Console over serial port
- Front and rear USB 3.0 ports and internal USB2.0 headers
- Front and rear audio jacks
- Internal speaker
- SATA ports 1-4 (5 and 6 are not populated on the M900)
- Hardware monitoring via nct6683 kernel module
- Gigabit Ethernet
- S3 suspend/resume
Unknown/untested:
- M.2 E-key slot
- Parallel port header
- PS/2 Mouse/Keyboard via KB_MS1 header
- TPM
Change-Id: I4e70c9f42c19f130a00170b32ae74b61f0483a22
Signed-off-by: Nicholas Chin <nic.c3.14(a)gmail.com>
---
A src/mainboard/lenovo/m900/Kconfig
A src/mainboard/lenovo/m900/Kconfig.name
A src/mainboard/lenovo/m900/Makefile.mk
A src/mainboard/lenovo/m900/acpi/dptf.asl
A src/mainboard/lenovo/m900/acpi/ec.asl
A src/mainboard/lenovo/m900/acpi/mainboard.asl
A src/mainboard/lenovo/m900/acpi/superio.asl
A src/mainboard/lenovo/m900/board_info.txt
A src/mainboard/lenovo/m900/bootblock.c
A src/mainboard/lenovo/m900/cmos.default
A src/mainboard/lenovo/m900/cmos.layout
A src/mainboard/lenovo/m900/data.vbt
A src/mainboard/lenovo/m900/devicetree.cb
A src/mainboard/lenovo/m900/dsdt.asl
A src/mainboard/lenovo/m900/gma-mainboard.ads
A src/mainboard/lenovo/m900/gpio.h
A src/mainboard/lenovo/m900/hda_verb.c
A src/mainboard/lenovo/m900/mainboard.c
A src/mainboard/lenovo/m900/ramstage.c
A src/mainboard/lenovo/m900/romstage.c
20 files changed, 806 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/87/74187/5
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Change subject: mb/lenovo: Add ThinkCentre M900 (Skylake/LGA 1151)
......................................................................
Patch Set 4:
(10 comments)
File src/mainboard/lenovo/m900/Kconfig:
https://review.coreboot.org/c/coreboot/+/74187/comment/fe3851c4_23376c1b?us… :
PS4, Line 36: config PRERAM_CBMEM_CONSOLE_SIZE
: default 0xd00
Why is the default value not suitable?
File src/mainboard/lenovo/m900/acpi/dptf.asl:
PS4:
Was this tested?
File src/mainboard/lenovo/m900/bootblock.c:
https://review.coreboot.org/c/coreboot/+/74187/comment/cf7ac9e2_f5b643d4?us… :
PS4, Line 9: /* Change to NCT6687D_SP1 to use COM2 header */
Should probably be a Kconfig
File src/mainboard/lenovo/m900/cmos.layout:
https://review.coreboot.org/c/coreboot/+/74187/comment/672321c4_890e29fb?us… :
PS4, Line 24: 408 1 e 1 nmi
Skylake doesn't implement this option, IIRC.
https://review.coreboot.org/c/coreboot/+/74187/comment/af644bc0_1476c065?us… :
PS4, Line 28: ChromeOS
Hmmmmm... I think vboot doesn't use this CMOS field anymore?
File src/mainboard/lenovo/m900/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/74187/comment/6573803a_c3329e7f?us… :
PS4, Line 20: # SLP_S3 Minimum Assertion Width. Values 0: 60us, 1: 1ms, 2: 50ms, 3: 2s
For another patch: provide an enum in SoC code
https://review.coreboot.org/c/coreboot/+/74187/comment/720f0217_331ac8e0?us… :
PS4, Line 38: register "SendVrMbxCmd" = "2"
I'm pretty sure this is copy-pasta from a Chromebook that no one knows what it does. I've had no problems removing it on the HP 280 G2.
File src/mainboard/lenovo/m900/dsdt.asl:
https://review.coreboot.org/c/coreboot/+/74187/comment/f2ab0b6b_a669c7cc?us… :
PS4, Line 25: /* Image processing unit */
: #include <soc/intel/skylake/acpi/ipu.asl>
I am pretty sure IPU is not used on a desktop. I'm not even sure if it exists on PCH-H platforms.
File src/mainboard/lenovo/m900/ramstage.c:
https://review.coreboot.org/c/coreboot/+/74187/comment/8dbecf32_2c75c1e2?us… :
PS4, Line 12: params->CdClock = 3;
What does this do? Is this needed?
File src/mainboard/lenovo/m900/romstage.c:
https://review.coreboot.org/c/coreboot/+/74187/comment/eaa2cfe4_dac75737?us… :
PS4, Line 21: assert(sizeof(mem_cfg->RcompResistor) == sizeof(rcomp_resistors));
: assert(sizeof(mem_cfg->RcompTarget) == sizeof(rcomp_targets));
nit: move just above corresponding memcpy()?
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Change subject: mb/lenovo: Add ThinkCentre M900 (Skylake/LGA 1151)
......................................................................
Patch Set 4:
(2 comments)
File src/mainboard/lenovo/m900/acpi/dptf.asl:
https://review.coreboot.org/c/coreboot/+/74187/comment/6f4fbb27_22eee200?us… :
PS3, Line 14:
> Nit: drop blank line?
Done
File src/mainboard/lenovo/m900/gma-mainboard.ads:
https://review.coreboot.org/c/coreboot/+/74187/comment/68f794e9_23796990?us… :
PS3, Line 16: HDMI3,
> What's the output of `xrandr`? According to the images of the board that I've found, it does not fea […]
Correct, it doesn't have HDMI ports. However, the DisplayPorts are dual-mode (DP++), which means they can operate in HDMI mode using simple adapters.
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Hello Alexander Couzens, Jan Philipp Groß, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/74187?usp=email
to look at the new patch set (#4).
The following approvals got outdated and were removed:
Code-Review+1 by Jan Philipp Groß, Verified+1 by build bot (Jenkins)
Change subject: mb/lenovo: Add ThinkCentre M900 (Skylake/LGA 1151)
......................................................................
mb/lenovo: Add ThinkCentre M900 (Skylake/LGA 1151)
The mainboard is marked IQ1X0MS, though it is also known as the MS-7988.
The Small Form Factor version was used for this port, though the Mini
Tower seems to use the exact same board. Other systems such as the
ThinkCentre M800, ThinkStation P310, ThinkStation P320, and IdeaCentre
700-25ISH appear to use the same PCB with different configurations of
components.
All the code in this port was originally copied from the Asrock H110M
and then modified to match the actual configuration of the M900. The VBT
was extracted using `intelvbttool -l -v data.vbt` while running version
FWKTBFA of the vendor firmware.
Working:
- Boots to Linux with SeaBIOS 1.16.3
- Boots to Linux with EDK2 (MrChromebox uefipayload_202408)
- Display Ports
- VGA port
- PCIe slots
- Console over serial port
- Front and rear USB 3.0 ports and internal USB2.0 headers
- Front and rear audio jacks
- Internal speaker
- SATA ports 1-4 (5 and 6 are not populated on the M900)
- Hardware monitoring via nct6683 kernel module
- Gigabit Ethernet
- S3 suspend/resume
Unknown/untested:
- M.2 E-key slot
- Parallel port header
- PS/2 Mouse/Keyboard via KB_MS1 header
- TPM
Change-Id: I4e70c9f42c19f130a00170b32ae74b61f0483a22
Signed-off-by: Nicholas Chin <nic.c3.14(a)gmail.com>
---
A src/mainboard/lenovo/m900/Kconfig
A src/mainboard/lenovo/m900/Kconfig.name
A src/mainboard/lenovo/m900/Makefile.mk
A src/mainboard/lenovo/m900/acpi/dptf.asl
A src/mainboard/lenovo/m900/acpi/ec.asl
A src/mainboard/lenovo/m900/acpi/mainboard.asl
A src/mainboard/lenovo/m900/acpi/superio.asl
A src/mainboard/lenovo/m900/board_info.txt
A src/mainboard/lenovo/m900/bootblock.c
A src/mainboard/lenovo/m900/cmos.default
A src/mainboard/lenovo/m900/cmos.layout
A src/mainboard/lenovo/m900/data.vbt
A src/mainboard/lenovo/m900/devicetree.cb
A src/mainboard/lenovo/m900/dsdt.asl
A src/mainboard/lenovo/m900/gma-mainboard.ads
A src/mainboard/lenovo/m900/gpio.h
A src/mainboard/lenovo/m900/hda_verb.c
A src/mainboard/lenovo/m900/mainboard.c
A src/mainboard/lenovo/m900/ramstage.c
A src/mainboard/lenovo/m900/romstage.c
20 files changed, 815 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/87/74187/4
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Attention is currently required from: Intel coreboot Reviewers, Julius Werner, Karthik Ramasubramanian.
Hello Intel coreboot Reviewers, Julius Werner, Karthik Ramasubramanian, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/86336?usp=email
to look at the new patch set (#2).
The following approvals got outdated and were removed:
Verified+1 by build bot (Jenkins)
Change subject: soc/intel/cmn/pmc: Add support for early power off
......................................................................
soc/intel/cmn/pmc: Add support for early power off
This commit adds support for early power off on Intel platforms
alongwith existing PMC based implementation to support power off
at later stage (like ramsatge).
A new function, `platform_do_early_poweroff`, is added to the
pmclib to handle platform-specific early power off procedures.
This function is called before memory initialization (in romstage or
earlier).
A weak default implementation is provided which prints an error message
and halts the system if EC_GOOGLE_CHROMEEC Kconfig not present.
Otherwise call into `google_chromeec_do_early_poweroff` to power off
the platform.
BUG=b:339673254
TEST=Able to build and boot google/brox.
Change-Id: I39f516640b3f75ab4c6a09826922289c0533f79b
Signed-off-by: Subrata Banik <subratabanik(a)google.com>
---
M src/soc/intel/common/block/include/intelblocks/pmclib.h
M src/soc/intel/common/block/pmc/pmclib.c
2 files changed, 39 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/36/86336/2
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