coreboot-gerrit February 2025

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[XS] Change in coreboot[main]: ec/starlabs/merlin: Drop unused reference to events.asl
by Matt DeVillier (Code Review) 09 Feb '25

09 Feb '25

Attention is currently required from: Sean Rhodes. Matt DeVillier has posted comments on this change by Matt DeVillier. ( https://review.coreboot.org/c/coreboot/+/86321?usp=email ) Change subject: ec/starlabs/merlin: Drop unused reference to events.asl ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: > `src/ec/starlabs/merlin/Makefile.mk`: […] thx, not sure how I missed that -- To view, visit https://review.coreboot.org/c/coreboot/+/86321?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ifbb986378dd49c6a1d316a4922c46c46180497ee Gerrit-Change-Number: 86321 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Comment-Date: Sun, 09 Feb 2025 20:20:09 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Sean Rhodes <sean(a)starlabs.systems> Comment-In-Reply-To: Matt DeVillier <matt.devillier(a)gmail.com>

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[XS] Change in coreboot[main]: ec/starlabs/merlin: Drop unused reference to events.asl
by Sean Rhodes (Code Review) 09 Feb '25

09 Feb '25

Attention is currently required from: Matt DeVillier. Sean Rhodes has posted comments on this change by Matt DeVillier. ( https://review.coreboot.org/c/coreboot/+/86321?usp=email ) Change subject: ec/starlabs/merlin: Drop unused reference to events.asl ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: > how are those in scope? `src/ec/starlabs/merlin/Makefile.mk`: ``` EC_VARIANT_DIR := $(call strip_quotes, $(CONFIG_EC_VARIANT_DIR)) CPPFLAGS_common += -I$(src)/ec/starlabs/merlin/variants/$(EC_VARIANT_DIR) ``` -- To view, visit https://review.coreboot.org/c/coreboot/+/86321?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ifbb986378dd49c6a1d316a4922c46c46180497ee Gerrit-Change-Number: 86321 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Comment-Date: Sun, 09 Feb 2025 20:17:08 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Sean Rhodes <sean(a)starlabs.systems> Comment-In-Reply-To: Matt DeVillier <matt.devillier(a)gmail.com>

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[L] Change in coreboot[main]: mb/lenovo: Add ThinkCentre M900 (Skylake/LGA 1151)
by Nicholas Chin (Code Review) 09 Feb '25

09 Feb '25

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[L] Change in coreboot[main]: mb/lenovo: Add ThinkCentre M900 (Skylake/LGA 1151)
by Nicholas Chin (Code Review) 09 Feb '25

09 Feb '25

Attention is currently required from: Alexander Couzens, Angel Pons, Felix Singer, Jan Philipp Groß, Paul Menzel. Nicholas Chin has posted comments on this change by Nicholas Chin. ( https://review.coreboot.org/c/coreboot/+/74187?usp=email ) Change subject: mb/lenovo: Add ThinkCentre M900 (Skylake/LGA 1151) ...................................................................... Patch Set 5: (8 comments) File src/mainboard/lenovo/m900/Kconfig: https://review.coreboot.org/c/coreboot/+/74187/comment/e112db4a_2106208b?us… : PS4, Line 36: config PRERAM_CBMEM_CONSOLE_SIZE : default 0xd00 > Why is the default value not suitable? Copypasta from the H110. The console seems to be fine with the default value, so I'll remove the override here. File src/mainboard/lenovo/m900/acpi/dptf.asl: PS4: > Was this tested? No. Should I remove it? File src/mainboard/lenovo/m900/cmos.layout: https://review.coreboot.org/c/coreboot/+/74187/comment/a618cc07_a463d427?us… : PS4, Line 24: 408 1 e 1 nmi > Skylake doesn't implement this option, IIRC. Done https://review.coreboot.org/c/coreboot/+/74187/comment/4774e0e8_03839fc3?us… : PS4, Line 28: ChromeOS > Hmmmmm... […] It seems like there is an intention to deprecate VBOOT_VBNV_CMOS (https://issuetracker.google.com/issues/235293589; you posted this link on my E6400 patch before). Seems like the code for it is still present though (`security/vboot/vbnv_cmos.c`), and Skylake also seems to select `VBOOT_VBNV_CMOS` and `VBOOT_VBNV_CMOS_BACKUP_TO_FLASH` in `soc/intel/skylake/Kconfig`. File src/mainboard/lenovo/m900/devicetree.cb: https://review.coreboot.org/c/coreboot/+/74187/comment/bb0388c9_52797b3e?us… : PS4, Line 38: register "SendVrMbxCmd" = "2" > I'm pretty sure this is copy-pasta from a Chromebook that no one knows what it does. […] Looks like it was added in commit 9a8b67d0af6a ("soc/intel/skylake: Enable another VR mailbox command for certain boards"). Seems like it has something to do with hangs during S0ix and the IVMP8 PS4 power state (can't find much information about that). I've removed it. File src/mainboard/lenovo/m900/dsdt.asl: https://review.coreboot.org/c/coreboot/+/74187/comment/46a958a8_d3d218cb?us… : PS4, Line 25: /* Image processing unit */ : #include <soc/intel/skylake/acpi/ipu.asl> > I am pretty sure IPU is not used on a desktop. I'm not even sure if it exists on PCH-H platforms. Done. The IPU seems to be pci 14.3, which only seems to be on the mobile U/Y single chip platforms based on the datasheets. File src/mainboard/lenovo/m900/ramstage.c: https://review.coreboot.org/c/coreboot/+/74187/comment/33a97e66_a38e980a?us… : PS4, Line 12: params->CdClock = 3; > What does this do? Is this needed? Seems like it corresponds to the Core Display Clock Frequency selection, based on a comment in `soc/intel/jasperlake/chip.h`. Nowhere else seems to expand the abbreviation. Anyway, according to the Kabylake FSP Integration guide it defaults to 3 so its probably safe to just remove. File src/mainboard/lenovo/m900/romstage.c: https://review.coreboot.org/c/coreboot/+/74187/comment/8cc4d842_7b3c6c56?us… : PS4, Line 21: assert(sizeof(mem_cfg->RcompResistor) == sizeof(rcomp_resistors)); : assert(sizeof(mem_cfg->RcompTarget) == sizeof(rcomp_targets)); > nit: move just above corresponding memcpy()? Done -- To view, visit https://review.coreboot.org/c/coreboot/+/74187?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I4e70c9f42c19f130a00170b32ae74b61f0483a22 Gerrit-Change-Number: 74187 Gerrit-PatchSet: 5 Gerrit-Owner: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Jan Philipp Groß <jeangrande(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jan Philipp Groß <jeangrande(a)mailbox.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Comment-Date: Sun, 09 Feb 2025 18:39:36 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com>

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[L] Change in coreboot[main]: mb/lenovo: Add ThinkCentre M900 (Skylake/LGA 1151)
by Nicholas Chin (Code Review) 09 Feb '25

09 Feb '25

Attention is currently required from: Alexander Couzens, Felix Singer, Jan Philipp Groß, Nicholas Chin, Paul Menzel. Hello Alexander Couzens, Jan Philipp Groß, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/74187?usp=email to look at the new patch set (#5). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: mb/lenovo: Add ThinkCentre M900 (Skylake/LGA 1151) ...................................................................... mb/lenovo: Add ThinkCentre M900 (Skylake/LGA 1151) The mainboard is marked IQ1X0MS, though it is also known as the MS-7988. The Small Form Factor version was used for this port, though the Mini Tower seems to use the exact same board. Other systems such as the ThinkCentre M800, ThinkStation P310, ThinkStation P320, and IdeaCentre 700-25ISH appear to use the same PCB with different configurations of components. All the code in this port was originally copied from the Asrock H110M and then modified to match the actual configuration of the M900. The VBT was extracted using `intelvbttool -l -v data.vbt` while running version FWKTBFA of the vendor firmware. Working: - Boots to Linux with SeaBIOS 1.16.3 - Boots to Linux with EDK2 (MrChromebox uefipayload_202408) - Display Ports - VGA port - PCIe slots - Console over serial port - Front and rear USB 3.0 ports and internal USB2.0 headers - Front and rear audio jacks - Internal speaker - SATA ports 1-4 (5 and 6 are not populated on the M900) - Hardware monitoring via nct6683 kernel module - Gigabit Ethernet - S3 suspend/resume Unknown/untested: - M.2 E-key slot - Parallel port header - PS/2 Mouse/Keyboard via KB_MS1 header - TPM Change-Id: I4e70c9f42c19f130a00170b32ae74b61f0483a22 Signed-off-by: Nicholas Chin <nic.c3.14(a)gmail.com> --- A src/mainboard/lenovo/m900/Kconfig A src/mainboard/lenovo/m900/Kconfig.name A src/mainboard/lenovo/m900/Makefile.mk A src/mainboard/lenovo/m900/acpi/dptf.asl A src/mainboard/lenovo/m900/acpi/ec.asl A src/mainboard/lenovo/m900/acpi/mainboard.asl A src/mainboard/lenovo/m900/acpi/superio.asl A src/mainboard/lenovo/m900/board_info.txt A src/mainboard/lenovo/m900/bootblock.c A src/mainboard/lenovo/m900/cmos.default A src/mainboard/lenovo/m900/cmos.layout A src/mainboard/lenovo/m900/data.vbt A src/mainboard/lenovo/m900/devicetree.cb A src/mainboard/lenovo/m900/dsdt.asl A src/mainboard/lenovo/m900/gma-mainboard.ads A src/mainboard/lenovo/m900/gpio.h A src/mainboard/lenovo/m900/hda_verb.c A src/mainboard/lenovo/m900/mainboard.c A src/mainboard/lenovo/m900/ramstage.c A src/mainboard/lenovo/m900/romstage.c 20 files changed, 806 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/87/74187/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/74187?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I4e70c9f42c19f130a00170b32ae74b61f0483a22 Gerrit-Change-Number: 74187 Gerrit-PatchSet: 5 Gerrit-Owner: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Jan Philipp Groß <jeangrande(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jan Philipp Groß <jeangrande(a)mailbox.org> Gerrit-Attention: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Attention: Alexander Couzens <lynxis(a)fe80.eu>

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[L] Change in coreboot[main]: mb/lenovo: Add ThinkCentre M900 (Skylake/LGA 1151)
by Angel Pons (Code Review) 09 Feb '25

09 Feb '25

Attention is currently required from: Alexander Couzens, Felix Singer, Jan Philipp Groß, Nicholas Chin, Paul Menzel. Angel Pons has posted comments on this change by Nicholas Chin. ( https://review.coreboot.org/c/coreboot/+/74187?usp=email ) Change subject: mb/lenovo: Add ThinkCentre M900 (Skylake/LGA 1151) ...................................................................... Patch Set 4: (10 comments) File src/mainboard/lenovo/m900/Kconfig: https://review.coreboot.org/c/coreboot/+/74187/comment/fe3851c4_23376c1b?us… : PS4, Line 36: config PRERAM_CBMEM_CONSOLE_SIZE : default 0xd00 Why is the default value not suitable? File src/mainboard/lenovo/m900/acpi/dptf.asl: PS4: Was this tested? File src/mainboard/lenovo/m900/bootblock.c: https://review.coreboot.org/c/coreboot/+/74187/comment/cf7ac9e2_f5b643d4?us… : PS4, Line 9: /* Change to NCT6687D_SP1 to use COM2 header */ Should probably be a Kconfig File src/mainboard/lenovo/m900/cmos.layout: https://review.coreboot.org/c/coreboot/+/74187/comment/672321c4_890e29fb?us… : PS4, Line 24: 408 1 e 1 nmi Skylake doesn't implement this option, IIRC. https://review.coreboot.org/c/coreboot/+/74187/comment/af644bc0_1476c065?us… : PS4, Line 28: ChromeOS Hmmmmm... I think vboot doesn't use this CMOS field anymore? File src/mainboard/lenovo/m900/devicetree.cb: https://review.coreboot.org/c/coreboot/+/74187/comment/6573803a_c3329e7f?us… : PS4, Line 20: # SLP_S3 Minimum Assertion Width. Values 0: 60us, 1: 1ms, 2: 50ms, 3: 2s For another patch: provide an enum in SoC code https://review.coreboot.org/c/coreboot/+/74187/comment/720f0217_331ac8e0?us… : PS4, Line 38: register "SendVrMbxCmd" = "2" I'm pretty sure this is copy-pasta from a Chromebook that no one knows what it does. I've had no problems removing it on the HP 280 G2. File src/mainboard/lenovo/m900/dsdt.asl: https://review.coreboot.org/c/coreboot/+/74187/comment/f2ab0b6b_a669c7cc?us… : PS4, Line 25: /* Image processing unit */ : #include <soc/intel/skylake/acpi/ipu.asl> I am pretty sure IPU is not used on a desktop. I'm not even sure if it exists on PCH-H platforms. File src/mainboard/lenovo/m900/ramstage.c: https://review.coreboot.org/c/coreboot/+/74187/comment/8dbecf32_2c75c1e2?us… : PS4, Line 12: params->CdClock = 3; What does this do? Is this needed? File src/mainboard/lenovo/m900/romstage.c: https://review.coreboot.org/c/coreboot/+/74187/comment/eaa2cfe4_dac75737?us… : PS4, Line 21: assert(sizeof(mem_cfg->RcompResistor) == sizeof(rcomp_resistors)); : assert(sizeof(mem_cfg->RcompTarget) == sizeof(rcomp_targets)); nit: move just above corresponding memcpy()? -- To view, visit https://review.coreboot.org/c/coreboot/+/74187?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I4e70c9f42c19f130a00170b32ae74b61f0483a22 Gerrit-Change-Number: 74187 Gerrit-PatchSet: 4 Gerrit-Owner: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Jan Philipp Groß <jeangrande(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jan Philipp Groß <jeangrande(a)mailbox.org> Gerrit-Attention: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Attention: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Comment-Date: Sun, 09 Feb 2025 16:39:53 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[S] Change in coreboot[main]: mb/google/trulo/var/uldrenite: Add fw_config probe for USB-C ports
by John Su (Code Review) 09 Feb '25

09 Feb '25

John Su has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/86338?usp=email ) Change subject: mb/google/trulo/var/uldrenite: Add fw_config probe for USB-C ports ...................................................................... mb/google/trulo/var/uldrenite: Add fw_config probe for USB-C ports Use fw_config to probe USB-C ports. BUG=b:392040004 BRANCH=firmware-trulo-15217.771.B TEST=emerge-nissa coreboot chromeos-bootimage Change-Id: Ic0161e8b85c5a2afe6ec8473497d21a5737f4f70 Signed-off-by: John Su <john_su(a)compal.corp-partner.google.com> --- M src/mainboard/google/brya/variants/uldrenite/overridetree.cb 1 file changed, 10 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/38/86338/1 diff --git a/src/mainboard/google/brya/variants/uldrenite/overridetree.cb b/src/mainboard/google/brya/variants/uldrenite/overridetree.cb index 862968e..285db4a 100644 --- a/src/mainboard/google/brya/variants/uldrenite/overridetree.cb +++ b/src/mainboard/google/brya/variants/uldrenite/overridetree.cb @@ -7,6 +7,10 @@ option TOUCHSCREEN_UNKNOWN 0 option TOUCHSCREEN_NONE 1 end + field MB_TYPEC 7 7 + option MB_C_TWO 0 + option MB_C_ONE 1 + end end chip soc/intel/alderlake @@ -250,7 +254,9 @@ register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" register "use_custom_pld" = "true" register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, RIGHT, ACPI_PLD_GROUP(2, 1))" - device ref tcss_usb3_port2 on end + device ref tcss_usb3_port2 on + probe MB_TYPEC MB_C_TWO + end end end end @@ -270,7 +276,9 @@ register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" register "use_custom_pld" = "true" register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(2, 1))" - device ref usb2_port2 on end + device ref usb2_port2 on + probe MB_TYPEC MB_C_TWO + end end chip drivers/usb/acpi register "desc" = ""USB2 Type-A Port A0 (MLB)"" -- To view, visit https://review.coreboot.org/c/coreboot/+/86338?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ic0161e8b85c5a2afe6ec8473497d21a5737f4f70 Gerrit-Change-Number: 86338 Gerrit-PatchSet: 1 Gerrit-Owner: John Su <john_su(a)compal.corp-partner.google.com>

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[L] Change in coreboot[main]: mb/lenovo: Add ThinkCentre M900 (Skylake/LGA 1151)
by Nicholas Chin (Code Review) 09 Feb '25

09 Feb '25

Attention is currently required from: Alexander Couzens, Felix Singer, Jan Philipp Groß, Paul Menzel. Nicholas Chin has posted comments on this change by Nicholas Chin. ( https://review.coreboot.org/c/coreboot/+/74187?usp=email ) Change subject: mb/lenovo: Add ThinkCentre M900 (Skylake/LGA 1151) ...................................................................... Patch Set 4: (2 comments) File src/mainboard/lenovo/m900/acpi/dptf.asl: https://review.coreboot.org/c/coreboot/+/74187/comment/6f4fbb27_22eee200?us… : PS3, Line 14: > Nit: drop blank line? Done File src/mainboard/lenovo/m900/gma-mainboard.ads: https://review.coreboot.org/c/coreboot/+/74187/comment/68f794e9_23796990?us… : PS3, Line 16: HDMI3, > What's the output of `xrandr`? According to the images of the board that I've found, it does not fea […] Correct, it doesn't have HDMI ports. However, the DisplayPorts are dual-mode (DP++), which means they can operate in HDMI mode using simple adapters. -- To view, visit https://review.coreboot.org/c/coreboot/+/74187?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I4e70c9f42c19f130a00170b32ae74b61f0483a22 Gerrit-Change-Number: 74187 Gerrit-PatchSet: 4 Gerrit-Owner: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Jan Philipp Groß <jeangrande(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jan Philipp Groß <jeangrande(a)mailbox.org> Gerrit-Attention: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Comment-Date: Sun, 09 Feb 2025 15:26:02 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Jan Philipp Groß <jeangrande(a)mailbox.org>

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[L] Change in coreboot[main]: mb/lenovo: Add ThinkCentre M900 (Skylake/LGA 1151)
by Nicholas Chin (Code Review) 09 Feb '25

09 Feb '25

Attention is currently required from: Alexander Couzens, Felix Singer, Jan Philipp Groß, Nicholas Chin, Paul Menzel. Hello Alexander Couzens, Jan Philipp Groß, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/74187?usp=email to look at the new patch set (#4). The following approvals got outdated and were removed: Code-Review+1 by Jan Philipp Groß, Verified+1 by build bot (Jenkins) Change subject: mb/lenovo: Add ThinkCentre M900 (Skylake/LGA 1151) ...................................................................... mb/lenovo: Add ThinkCentre M900 (Skylake/LGA 1151) The mainboard is marked IQ1X0MS, though it is also known as the MS-7988. The Small Form Factor version was used for this port, though the Mini Tower seems to use the exact same board. Other systems such as the ThinkCentre M800, ThinkStation P310, ThinkStation P320, and IdeaCentre 700-25ISH appear to use the same PCB with different configurations of components. All the code in this port was originally copied from the Asrock H110M and then modified to match the actual configuration of the M900. The VBT was extracted using `intelvbttool -l -v data.vbt` while running version FWKTBFA of the vendor firmware. Working: - Boots to Linux with SeaBIOS 1.16.3 - Boots to Linux with EDK2 (MrChromebox uefipayload_202408) - Display Ports - VGA port - PCIe slots - Console over serial port - Front and rear USB 3.0 ports and internal USB2.0 headers - Front and rear audio jacks - Internal speaker - SATA ports 1-4 (5 and 6 are not populated on the M900) - Hardware monitoring via nct6683 kernel module - Gigabit Ethernet - S3 suspend/resume Unknown/untested: - M.2 E-key slot - Parallel port header - PS/2 Mouse/Keyboard via KB_MS1 header - TPM Change-Id: I4e70c9f42c19f130a00170b32ae74b61f0483a22 Signed-off-by: Nicholas Chin <nic.c3.14(a)gmail.com> --- A src/mainboard/lenovo/m900/Kconfig A src/mainboard/lenovo/m900/Kconfig.name A src/mainboard/lenovo/m900/Makefile.mk A src/mainboard/lenovo/m900/acpi/dptf.asl A src/mainboard/lenovo/m900/acpi/ec.asl A src/mainboard/lenovo/m900/acpi/mainboard.asl A src/mainboard/lenovo/m900/acpi/superio.asl A src/mainboard/lenovo/m900/board_info.txt A src/mainboard/lenovo/m900/bootblock.c A src/mainboard/lenovo/m900/cmos.default A src/mainboard/lenovo/m900/cmos.layout A src/mainboard/lenovo/m900/data.vbt A src/mainboard/lenovo/m900/devicetree.cb A src/mainboard/lenovo/m900/dsdt.asl A src/mainboard/lenovo/m900/gma-mainboard.ads A src/mainboard/lenovo/m900/gpio.h A src/mainboard/lenovo/m900/hda_verb.c A src/mainboard/lenovo/m900/mainboard.c A src/mainboard/lenovo/m900/ramstage.c A src/mainboard/lenovo/m900/romstage.c 20 files changed, 815 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/87/74187/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/74187?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I4e70c9f42c19f130a00170b32ae74b61f0483a22 Gerrit-Change-Number: 74187 Gerrit-PatchSet: 4 Gerrit-Owner: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Jan Philipp Groß <jeangrande(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jan Philipp Groß <jeangrande(a)mailbox.org> Gerrit-Attention: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Attention: Alexander Couzens <lynxis(a)fe80.eu>

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[S] Change in coreboot[main]: soc/intel/cmn/pmc: Add support for early power off
by Subrata Banik (Code Review) 09 Feb '25

09 Feb '25

Attention is currently required from: Intel coreboot Reviewers, Julius Werner, Karthik Ramasubramanian. Hello Intel coreboot Reviewers, Julius Werner, Karthik Ramasubramanian, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/86336?usp=email to look at the new patch set (#2). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: soc/intel/cmn/pmc: Add support for early power off ...................................................................... soc/intel/cmn/pmc: Add support for early power off This commit adds support for early power off on Intel platforms alongwith existing PMC based implementation to support power off at later stage (like ramsatge). A new function, `platform_do_early_poweroff`, is added to the pmclib to handle platform-specific early power off procedures. This function is called before memory initialization (in romstage or earlier). A weak default implementation is provided which prints an error message and halts the system if EC_GOOGLE_CHROMEEC Kconfig not present. Otherwise call into `google_chromeec_do_early_poweroff` to power off the platform. BUG=b:339673254 TEST=Able to build and boot google/brox. Change-Id: I39f516640b3f75ab4c6a09826922289c0533f79b Signed-off-by: Subrata Banik <subratabanik(a)google.com> --- M src/soc/intel/common/block/include/intelblocks/pmclib.h M src/soc/intel/common/block/pmc/pmclib.c 2 files changed, 39 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/36/86336/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/86336?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I39f516640b3f75ab4c6a09826922289c0533f79b Gerrit-Change-Number: 86336 Gerrit-PatchSet: 2 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com>

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coreboot-gerrit February 2025