coreboot-gerrit February 2025

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[XS] Change in coreboot[main]: mb/google/rauru: Deassert PCIe PERST# earlier in romstage
by Yidi Lin (Code Review) 08 Feb '25

08 Feb '25

Yidi Lin has submitted this change. ( https://review.coreboot.org/c/coreboot/+/86311?usp=email ) Change subject: mb/google/rauru: Deassert PCIe PERST# earlier in romstage ...................................................................... mb/google/rauru: Deassert PCIe PERST# earlier in romstage Reorder the PCIe reset before mtk_dram_init to overlap the de-assert time with the DRAM initialization process. This change helps to optimize the initialization sequence and reduce overall boot time. BRANCH=rauru TEST=Build pass BUG=b:391333055 Change-Id: I24b254ff3a3cbe6d9a60a8e6afea2c621e0a07e2 Signed-off-by: Jarried Lin <jarried.lin(a)mediatek.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/86311 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso(a)google.com> Reviewed-by: Yidi Lin <yidilin(a)google.com> --- M src/mainboard/google/rauru/romstage.c 1 file changed, 2 insertions(+), 3 deletions(-) Approvals: build bot (Jenkins): Verified Yu-Ping Wu: Looks good to me, approved Yidi Lin: Looks good to me, approved diff --git a/src/mainboard/google/rauru/romstage.c b/src/mainboard/google/rauru/romstage.c index 7860dfd..584af61 100644 --- a/src/mainboard/google/rauru/romstage.c +++ b/src/mainboard/google/rauru/romstage.c @@ -47,11 +47,10 @@ clk_buf_init(); if (CONFIG(RTC)) rtc_boot(); + if (CONFIG(PCI)) + mtk_pcie_deassert_perst(); mtk_dram_init(); modem_power_down(); dvfs_init(); thermal_init(); - - if (CONFIG(PCI)) - mtk_pcie_deassert_perst(); } -- To view, visit https://review.coreboot.org/c/coreboot/+/86311?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I24b254ff3a3cbe6d9a60a8e6afea2c621e0a07e2 Gerrit-Change-Number: 86311 Gerrit-PatchSet: 3 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[M] Change in coreboot[main]: lib: Refactor ux_locales_get_text API
by Subrata Banik (Code Review) 08 Feb '25

08 Feb '25

Attention is currently required from: Dinesh Gehlot, Eran Mitrani, Intel coreboot Reviewers, Jakub "Kuba" Czapiga, Jayvik Desai, Julius Werner, Jérémy Compostella, Kapil Porwal, Nick Vaccaro, Tarun. Subrata Banik has posted comments on this change by Subrata Banik. ( https://review.coreboot.org/c/coreboot/+/86283?usp=email ) Change subject: lib: Refactor ux_locales_get_text API ...................................................................... Patch Set 8: (1 comment) File src/lib/ux_locales.c: https://review.coreboot.org/c/coreboot/+/86283/comment/ece2ba4f_8f434a14?us… : PS8, Line 27: ux_locale_text_msg > nit: should probably call this `ux_locale_fallback_text` to clarify that it is only used when the ac […] Acknowledged -- To view, visit https://review.coreboot.org/c/coreboot/+/86283?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I4952802396265b9ee8d164d6e43a7f2b3599d6c0 Gerrit-Change-Number: 86283 Gerrit-PatchSet: 8 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Jakub "Kuba" Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Jakub "Kuba" Czapiga <czapiga(a)google.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Tarun <tstuli(a)gmail.com> Gerrit-Comment-Date: Sat, 08 Feb 2025 12:23:04 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Julius Werner <jwerner(a)chromium.org>

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[M] Change in coreboot[main]: lib: Refactor ux_locales_get_text API
by Subrata Banik (Code Review) 08 Feb '25

08 Feb '25

Attention is currently required from: Dinesh Gehlot, Eran Mitrani, Intel coreboot Reviewers, Jakub "Kuba" Czapiga, Jayvik Desai, Jérémy Compostella, Kapil Porwal, Nick Vaccaro, Subrata Banik, Tarun. Hello Dinesh Gehlot, Eran Mitrani, Intel coreboot Reviewers, Jakub "Kuba" Czapiga, Jayvik Desai, Julius Werner, Kapil Porwal, Nick Vaccaro, Tarun, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/86283?usp=email to look at the new patch set (#9). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: lib: Refactor ux_locales_get_text API ...................................................................... lib: Refactor ux_locales_get_text API This patch refactors the `ux_locales_get_text` API to handle fallback text (English) internally, rather than relying on the caller. It introduces message IDs for lookups, enabling the API to locate both the UX locale name and fallback text based on the ID. - ux_locales_get_text: Get UX locales message based on locales name. - ux_locales_get_text_by_id: Get UX locales message based on message ID. `ux_locales_get_text_by_id` retrieves fallback text message depending upon the message ID if UX locales is not available. `ux_locales_get_text` API now takes an additional argument as `fallback_text` if provided, otherwise return `NULL`. This centralizes fallback handling and simplifies adding future messages without per-SoC duplication. BUG=b:339673254 TEST=Built and booted google/brox. Verified eSOL display. Change-Id: I4952802396265b9ee8d164d6e43a7f2b3599d6c0 Signed-off-by: Subrata Banik <subratabanik(a)google.com> --- M src/include/ux_locales.h M src/lib/ux_locales.c M src/soc/intel/alderlake/romstage/ux.c M src/soc/intel/meteorlake/romstage/fsp_params.c M tests/lib/ux_locales-test.c 5 files changed, 53 insertions(+), 31 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/83/86283/9 -- To view, visit https://review.coreboot.org/c/coreboot/+/86283?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I4952802396265b9ee8d164d6e43a7f2b3599d6c0 Gerrit-Change-Number: 86283 Gerrit-PatchSet: 9 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Jakub "Kuba" Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Jakub "Kuba" Czapiga <czapiga(a)google.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Tarun <tstuli(a)gmail.com>

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[XS] Change in coreboot[main]: acpi/acpi.h: Use boolean
by Elyes Haouas (Code Review) 08 Feb '25

08 Feb '25

Attention is currently required from: Felix Singer. Elyes Haouas has posted comments on this change by Elyes Haouas. ( https://review.coreboot.org/c/coreboot/+/84858?usp=email ) Change subject: acpi/acpi.h: Use boolean ...................................................................... Patch Set 6: (1 comment) File src/include/acpi/acpi.h: https://review.coreboot.org/c/coreboot/+/84858/comment/4143d682_cfe247f2?us… : PS3, Line 1981: static inline int acpi_is_wakeup_s3(void) > this one, needs some work this needs to use boolean for s3resume .... please see https://review.coreboot.org/c/coreboot/+/86331 -- To view, visit https://review.coreboot.org/c/coreboot/+/84858?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I8f390bf3b472519dc41db7daa57b16458961139e Gerrit-Change-Number: 84858 Gerrit-PatchSet: 6 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Comment-Date: Sat, 08 Feb 2025 11:22:30 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Comment-In-Reply-To: Elyes Haouas <ehaouas(a)noos.fr>

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[M] Change in coreboot[main]: tree: Use boolean for s3resume
by Elyes Haouas (Code Review) 08 Feb '25

08 Feb '25

Elyes Haouas has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/86331?usp=email ) Change subject: tree: Use boolean for s3resume ...................................................................... tree: Use boolean for s3resume Change-Id: I3e23134f879fcaf817cf62b641e9b59563eb643b Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> --- M src/arch/arm64/include/arch/acpi.h M src/drivers/amd/agesa/mtrr_fixme.c M src/drivers/tpm/tpm.c M src/include/acpi/acpi.h M src/include/cbmem.h M src/include/romstage_handoff.h M src/include/stage_cache.h M src/lib/bootblock.c M src/lib/imd_cbmem.c M src/lib/romstage_handoff.c M src/mainboard/dell/snb_ivb_workstations/romstage.c M src/mainboard/emulation/qemu-i440fx/romstage.c M src/mainboard/emulation/qemu-q35/romstage.c M src/mainboard/google/auron/ec.c M src/mainboard/google/auron/variants/gandof/variant.c M src/mainboard/google/auron/variants/lulu/variant.c M src/mainboard/google/auron/variants/samus/variant.c M src/mainboard/google/link/early_init.c M src/mainboard/google/slippy/ec.c M src/mainboard/google/stout/early_init.c M src/mainboard/kontron/ktqm77/early_init.c M src/mainboard/lenovo/t420/early_init.c M src/mainboard/lenovo/t420s/early_init.c M src/mainboard/lenovo/t430/early_init.c M src/mainboard/lenovo/t430s/variants/t430s/romstage.c M src/mainboard/lenovo/t520/early_init.c M src/mainboard/lenovo/t530/early_init.c M src/mainboard/supermicro/x9scl/early_init.c M src/northbridge/amd/agesa/agesa_helper.h M src/northbridge/amd/agesa/state_machine.h M src/northbridge/intel/e7505/romstage.c M src/northbridge/intel/gm45/gm45.h M src/northbridge/intel/gm45/raminit.c M src/northbridge/intel/gm45/raminit_read_write_training.c M src/northbridge/intel/gm45/romstage.c M src/northbridge/intel/haswell/broadwell_mrc/raminit.c M src/northbridge/intel/haswell/haswell_mrc/raminit.c M src/northbridge/intel/haswell/native_raminit/raminit_native.c M src/northbridge/intel/haswell/raminit.h M src/northbridge/intel/haswell/romstage.c M src/northbridge/intel/i440bx/raminit.c M src/northbridge/intel/i440bx/raminit.h M src/northbridge/intel/i945/early_init.c M src/northbridge/intel/i945/i945.h M src/northbridge/intel/i945/romstage.c M src/northbridge/intel/ironlake/quickpath.c M src/northbridge/intel/ironlake/raminit.c M src/northbridge/intel/ironlake/raminit.h M src/northbridge/intel/ironlake/romstage.c M src/northbridge/intel/pineview/romstage.c M src/northbridge/intel/sandybridge/raminit.c M src/northbridge/intel/sandybridge/raminit_common.h M src/northbridge/intel/sandybridge/raminit_mrc.c M src/northbridge/intel/sandybridge/raminit_native.c M src/northbridge/intel/sandybridge/romstage.c M src/northbridge/intel/sandybridge/sandybridge.h M src/northbridge/intel/x4x/raminit.c M src/northbridge/via/cx700/romstage.c M src/security/intel/txt/ramstage.c M src/soc/amd/stoneyridge/romstage.c M src/soc/intel/baytrail/romstage/raminit.c M src/soc/intel/baytrail/romstage/romstage.c M src/soc/intel/broadwell/include/soc/romstage.h M src/soc/intel/broadwell/raminit.c M src/soc/intel/broadwell/romstage.c M src/southbridge/intel/lynxpoint/early_pch_native.c M src/southbridge/intel/lynxpoint/pch.h 67 files changed, 95 insertions(+), 92 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/86331/1 diff --git a/src/arch/arm64/include/arch/acpi.h b/src/arch/arm64/include/arch/acpi.h index 396cdfd..f5e615a 100644 --- a/src/arch/arm64/include/arch/acpi.h +++ b/src/arch/arm64/include/arch/acpi.h @@ -6,7 +6,7 @@ /* STUB */ static inline int acpi_is_wakeup(void) { return 0; } -static inline int acpi_is_wakeup_s3(void) { return 0; } +static inline bool acpi_is_wakeup_s3(void) { return 0; } static inline int acpi_is_wakeup_s4(void) { return 0; } #endif /* __ARCH_ACPI_H_ */ diff --git a/src/drivers/amd/agesa/mtrr_fixme.c b/src/drivers/amd/agesa/mtrr_fixme.c index 9db1fe5..5b1294e 100644 --- a/src/drivers/amd/agesa/mtrr_fixme.c +++ b/src/drivers/amd/agesa/mtrr_fixme.c @@ -33,7 +33,7 @@ wrmsr(MTRR_PHYS_MASK(i), msr); } -void fixup_cbmem_to_UC(int s3resume) +void fixup_cbmem_to_UC(bool s3resume) { if (s3resume) return; @@ -54,7 +54,7 @@ { msr_t base, mask; int i; - int s3resume = romstage_handoff_is_resume(); + bool s3resume = romstage_handoff_is_resume(); /* Replicate non-UC MTRRs as left behind by AGESA. */ diff --git a/src/drivers/tpm/tpm.c b/src/drivers/tpm/tpm.c index 3b582c8..f284146 100644 --- a/src/drivers/tpm/tpm.c +++ b/src/drivers/tpm/tpm.c @@ -6,7 +6,7 @@ static void init_tpm_dev(void *unused) { - int s3resume = acpi_is_wakeup_s3(); + bool s3resume = acpi_is_wakeup_s3(); tpm_setup(s3resume); } diff --git a/src/include/acpi/acpi.h b/src/include/acpi/acpi.h index 9c22499..8dc9c1c 100644 --- a/src/include/acpi/acpi.h +++ b/src/include/acpi/acpi.h @@ -1978,10 +1978,10 @@ return CONFIG(HAVE_ACPI_RESUME); } -static inline int acpi_is_wakeup_s3(void) +static inline bool acpi_is_wakeup_s3(void) { if (!acpi_s3_resume_allowed()) - return 0; + return flase; if (ENV_ROMSTAGE_OR_BEFORE) return (acpi_get_sleep_type() == ACPI_S3); diff --git a/src/include/cbmem.h b/src/include/cbmem.h index fd258cd..43b8ba4 100644 --- a/src/include/cbmem.h +++ b/src/include/cbmem.h @@ -86,7 +86,7 @@ /* Returns 0 if old cbmem was recovered. Recovery is only attempted if * s3resume is non-zero. */ -int cbmem_recovery(int s3resume); +int cbmem_recovery(bool s3resume); /* Add a cbmem entry of a given size and id. These return NULL on failure. The * add function performs a find first and do not check against the original * size. */ diff --git a/src/include/romstage_handoff.h b/src/include/romstage_handoff.h index d0e30b4..2136fc2 100644 --- a/src/include/romstage_handoff.h +++ b/src/include/romstage_handoff.h @@ -6,6 +6,6 @@ int romstage_handoff_init(int is_s3_resume); /* Return 1 if resuming or 0 if not. */ -int romstage_handoff_is_resume(void); +bool romstage_handoff_is_resume(void); #endif /* ROMSTAGE_HANDOFF_H */ diff --git a/src/include/stage_cache.h b/src/include/stage_cache.h index 1e46b5c..1a3811b 100644 --- a/src/include/stage_cache.h +++ b/src/include/stage_cache.h @@ -39,10 +39,10 @@ #endif -static inline int resume_from_stage_cache(void) +static inline bool resume_from_stage_cache(void) { if (CONFIG(NO_STAGE_CACHE)) - return 0; + return false; /* TBD: Replace this with acpi_is_wakeup_s3(). */ return romstage_handoff_is_resume(); diff --git a/src/lib/bootblock.c b/src/lib/bootblock.c index 5c202ba..21b5d1e 100644 --- a/src/lib/bootblock.c +++ b/src/lib/bootblock.c @@ -59,7 +59,7 @@ bootblock_mainboard_init(); if (CONFIG(TPM_MEASURED_BOOT_INIT_BOOTBLOCK)) { - int s3resume = acpi_is_wakeup_s3(); + bool s3resume = acpi_is_wakeup_s3(); tpm_setup(s3resume); } diff --git a/src/lib/imd_cbmem.c b/src/lib/imd_cbmem.c index 2fc54bf..234e761 100644 --- a/src/lib/imd_cbmem.c +++ b/src/lib/imd_cbmem.c @@ -121,7 +121,7 @@ return 0; } -int cbmem_recovery(int is_wakeup) +int cbmem_recovery(bool is_wakeup) { int rv = 0; if (!is_wakeup) diff --git a/src/lib/romstage_handoff.c b/src/lib/romstage_handoff.c index faa2bc9..7937fb7 100644 --- a/src/lib/romstage_handoff.c +++ b/src/lib/romstage_handoff.c @@ -53,7 +53,7 @@ return 0; } -int romstage_handoff_is_resume(void) +bool romstage_handoff_is_resume(void) { static int once, s3_resume; struct romstage_handoff *handoff; @@ -65,7 +65,7 @@ once = 1; handoff = cbmem_find(CBMEM_ID_ROMSTAGE_INFO); if (handoff == NULL) - return 0; + return false; s3_resume = handoff->s3_resume; if (s3_resume) diff --git a/src/mainboard/dell/snb_ivb_workstations/romstage.c b/src/mainboard/dell/snb_ivb_workstations/romstage.c index d2a6b11..54e1dd4 100644 --- a/src/mainboard/dell/snb_ivb_workstations/romstage.c +++ b/src/mainboard/dell/snb_ivb_workstations/romstage.c @@ -23,7 +23,7 @@ DIR_ROUTE(D20IR, PIRQA, PIRQB, PIRQC, PIRQD); } -void mainboard_early_init(int s3resume) +void mainboard_early_init(bool s3resume) { uint16_t ec_fw_version; diff --git a/src/mainboard/emulation/qemu-i440fx/romstage.c b/src/mainboard/emulation/qemu-i440fx/romstage.c index f1c9176..db2c12e 100644 --- a/src/mainboard/emulation/qemu-i440fx/romstage.c +++ b/src/mainboard/emulation/qemu-i440fx/romstage.c @@ -5,5 +5,5 @@ void mainboard_romstage_entry(void) { - cbmem_recovery(0); + cbmem_recovery(false); } diff --git a/src/mainboard/emulation/qemu-q35/romstage.c b/src/mainboard/emulation/qemu-q35/romstage.c index c64321f..fe5f7f9 100644 --- a/src/mainboard/emulation/qemu-q35/romstage.c +++ b/src/mainboard/emulation/qemu-q35/romstage.c @@ -29,5 +29,5 @@ printk(BIOS_WARNING, "%s: Unsupported TSEG size: 0x%x\n", __func__, CONFIG_SMM_TSEG_SIZE); } - cbmem_recovery(0); + cbmem_recovery(false); } diff --git a/src/mainboard/google/auron/ec.c b/src/mainboard/google/auron/ec.c index 2334cb61..09d0fe7 100644 --- a/src/mainboard/google/auron/ec.c +++ b/src/mainboard/google/auron/ec.c @@ -14,7 +14,7 @@ .s5_wake_events = MAINBOARD_EC_S5_WAKE_EVENTS, }; - int s3_wakeup = acpi_is_wakeup_s3(); + bool s3_wakeup = acpi_is_wakeup_s3(); printk(BIOS_DEBUG, "%s\n", __func__); post_code(0xf0); diff --git a/src/mainboard/google/auron/variants/gandof/variant.c b/src/mainboard/google/auron/variants/gandof/variant.c index b93e2c1..b26300a 100644 --- a/src/mainboard/google/auron/variants/gandof/variant.c +++ b/src/mainboard/google/auron/variants/gandof/variant.c @@ -24,7 +24,7 @@ return len; } -void mainboard_post_raminit(const int s3resume) +void mainboard_post_raminit(const bool s3resume) { if (!s3resume) google_chromeec_kbbacklight(75); diff --git a/src/mainboard/google/auron/variants/lulu/variant.c b/src/mainboard/google/auron/variants/lulu/variant.c index 8349acae..0d42d4f 100644 --- a/src/mainboard/google/auron/variants/lulu/variant.c +++ b/src/mainboard/google/auron/variants/lulu/variant.c @@ -34,7 +34,7 @@ return len; } -void mainboard_post_raminit(const int s3resume) +void mainboard_post_raminit(const bool s3resume) { if (!s3resume) google_chromeec_kbbacklight(75); diff --git a/src/mainboard/google/auron/variants/samus/variant.c b/src/mainboard/google/auron/variants/samus/variant.c index 441cefe..a51f0d4 100644 --- a/src/mainboard/google/auron/variants/samus/variant.c +++ b/src/mainboard/google/auron/variants/samus/variant.c @@ -21,7 +21,7 @@ return 0; } -void mainboard_post_raminit(const int s3resume) +void mainboard_post_raminit(const bool s3resume) { if (!s3resume) google_chromeec_kbbacklight(100); diff --git a/src/mainboard/google/link/early_init.c b/src/mainboard/google/link/early_init.c index 2d20ac0..d606022 100644 --- a/src/mainboard/google/link/early_init.c +++ b/src/mainboard/google/link/early_init.c @@ -71,7 +71,7 @@ spdi->spd_index = get_spd_index(); } -void mainboard_early_init(int s3resume) +void mainboard_early_init(bool s3resume) { if (!s3resume) { /* This is the fastest way to let users know diff --git a/src/mainboard/google/slippy/ec.c b/src/mainboard/google/slippy/ec.c index 2334cb61..09d0fe7 100644 --- a/src/mainboard/google/slippy/ec.c +++ b/src/mainboard/google/slippy/ec.c @@ -14,7 +14,7 @@ .s5_wake_events = MAINBOARD_EC_S5_WAKE_EVENTS, }; - int s3_wakeup = acpi_is_wakeup_s3(); + bool s3_wakeup = acpi_is_wakeup_s3(); printk(BIOS_DEBUG, "%s\n", __func__); post_code(0xf0); diff --git a/src/mainboard/google/stout/early_init.c b/src/mainboard/google/stout/early_init.c index 178d270..4b29c59 100644 --- a/src/mainboard/google/stout/early_init.c +++ b/src/mainboard/google/stout/early_init.c @@ -83,7 +83,7 @@ /* TODO: Confirm if nortbridge_fill_pei_data() gets .system_type right (should be 0) */ } -void mainboard_early_init(int s3resume) +void mainboard_early_init(bool s3resume) { /* Do ec reset as early as possible, but skip it on S3 resume */ if (!s3resume) { diff --git a/src/mainboard/kontron/ktqm77/early_init.c b/src/mainboard/kontron/ktqm77/early_init.c index 7a23765..1d2503a 100644 --- a/src/mainboard/kontron/ktqm77/early_init.c +++ b/src/mainboard/kontron/ktqm77/early_init.c @@ -54,7 +54,7 @@ { } -void mainboard_early_init(int s3resume) +void mainboard_early_init(bool s3resume) { /* Enable PEG10 (1x16) */ pci_write_config32(PCI_DEV(0, 0, 0), DEVEN, diff --git a/src/mainboard/lenovo/t420/early_init.c b/src/mainboard/lenovo/t420/early_init.c index 514e567..b14fea9 100644 --- a/src/mainboard/lenovo/t420/early_init.c +++ b/src/mainboard/lenovo/t420/early_init.c @@ -30,7 +30,7 @@ pci_write_config32(PCI_DEV(0, 0, 0), DEVEN, reg32); } -void mainboard_early_init(int s3resume) +void mainboard_early_init(bool s3resume) { hybrid_graphics_init(); } diff --git a/src/mainboard/lenovo/t420s/early_init.c b/src/mainboard/lenovo/t420s/early_init.c index 514e567..b14fea9 100644 --- a/src/mainboard/lenovo/t420s/early_init.c +++ b/src/mainboard/lenovo/t420s/early_init.c @@ -30,7 +30,7 @@ pci_write_config32(PCI_DEV(0, 0, 0), DEVEN, reg32); } -void mainboard_early_init(int s3resume) +void mainboard_early_init(bool s3resume) { hybrid_graphics_init(); } diff --git a/src/mainboard/lenovo/t430/early_init.c b/src/mainboard/lenovo/t430/early_init.c index ed1f59b..8306e0e 100644 --- a/src/mainboard/lenovo/t430/early_init.c +++ b/src/mainboard/lenovo/t430/early_init.c @@ -32,7 +32,7 @@ pci_write_config32(PCI_DEV(0, 0, 0), DEVEN, reg32); } -void mainboard_early_init(int s3resume) +void mainboard_early_init(bool s3resume) { hybrid_graphics_init(); } diff --git a/src/mainboard/lenovo/t430s/variants/t430s/romstage.c b/src/mainboard/lenovo/t430s/variants/t430s/romstage.c index b69c71d..211ec2d 100644 --- a/src/mainboard/lenovo/t430s/variants/t430s/romstage.c +++ b/src/mainboard/lenovo/t430s/variants/t430s/romstage.c @@ -7,7 +7,7 @@ #include <ec/lenovo/pmh7/pmh7.h> #include <types.h> -void mainboard_early_init(int s3resume) +void mainboard_early_init(bool s3resume) { u8 enable_peg = get_uint_option("enable_dual_graphics", 0); diff --git a/src/mainboard/lenovo/t520/early_init.c b/src/mainboard/lenovo/t520/early_init.c index 0b0a576..ba98ec7 100644 --- a/src/mainboard/lenovo/t520/early_init.c +++ b/src/mainboard/lenovo/t520/early_init.c @@ -34,7 +34,7 @@ pci_write_config32(PCI_DEV(0, 0, 0), DEVEN, reg32); } -void mainboard_early_init(int s3resume) +void mainboard_early_init(bool s3resume) { hybrid_graphics_init(); } diff --git a/src/mainboard/lenovo/t530/early_init.c b/src/mainboard/lenovo/t530/early_init.c index b6bfa5f..429ab28 100644 --- a/src/mainboard/lenovo/t530/early_init.c +++ b/src/mainboard/lenovo/t530/early_init.c @@ -33,7 +33,7 @@ pci_write_config32(PCI_DEV(0, 0, 0), DEVEN, reg32); } -void mainboard_early_init(int s3resume) +void mainboard_early_init(bool s3resume) { hybrid_graphics_init(); } diff --git a/src/mainboard/supermicro/x9scl/early_init.c b/src/mainboard/supermicro/x9scl/early_init.c index c284240..c8a3e6e 100644 --- a/src/mainboard/supermicro/x9scl/early_init.c +++ b/src/mainboard/supermicro/x9scl/early_init.c @@ -83,7 +83,7 @@ bmc_init(); } -void mainboard_early_init(int s3resume) +void mainboard_early_init(bool s3resume) { /* Disable IGD VGA decode, no GTT or GFX stolen */ pci_write_config16(PCI_DEV(0, 0, 0), GGC, 2); diff --git a/src/northbridge/amd/agesa/agesa_helper.h b/src/northbridge/amd/agesa/agesa_helper.h index e8a1323..d64c7f5 100644 --- a/src/northbridge/amd/agesa/agesa_helper.h +++ b/src/northbridge/amd/agesa/agesa_helper.h @@ -34,7 +34,7 @@ #define HIGH_MEMORY_SCRATCH 0x30000 -void fixup_cbmem_to_UC(int s3resume); +void fixup_cbmem_to_UC(bool s3resume); void restore_mtrr(void); void backup_mtrr(void); diff --git a/src/northbridge/amd/agesa/state_machine.h b/src/northbridge/amd/agesa/state_machine.h index 6c77d21..50f3b09 100644 --- a/src/northbridge/amd/agesa/state_machine.h +++ b/src/northbridge/amd/agesa/state_machine.h @@ -28,7 +28,7 @@ { AMD_CONFIG_PARAMS StdHeader; - int s3resume; + bool s3resume; }; void board_BeforeAgesa(struct sysinfo *cb); diff --git a/src/northbridge/intel/e7505/romstage.c b/src/northbridge/intel/e7505/romstage.c index d997ee1..77cdf9c 100644 --- a/src/northbridge/intel/e7505/romstage.c +++ b/src/northbridge/intel/e7505/romstage.c @@ -14,5 +14,5 @@ sdram_initialize(); - cbmem_recovery(0); + cbmem_recovery(false); } diff --git a/src/northbridge/intel/gm45/gm45.h b/src/northbridge/intel/gm45/gm45.h index 5d9ac56..f68bfde 100644 --- a/src/northbridge/intel/gm45/gm45.h +++ b/src/northbridge/intel/gm45/gm45.h @@ -410,7 +410,7 @@ void enter_raminit_or_reset(void); void get_gmch_info(sysinfo_t *); -void raminit(sysinfo_t *, int s3resume); +void raminit(sysinfo_t *, bool s3resume); void raminit_thermal(const sysinfo_t *); void setup_sdram_meminfo(const sysinfo_t *); void init_igd(const sysinfo_t *const); @@ -423,8 +423,8 @@ void raminit_rcomp_calibration(stepping_t stepping); void raminit_reset_readwrite_pointers(void); void raminit_receive_enable_calibration(int ddr_type, const timings_t *, const dimminfo_t *); -void raminit_write_training(const mem_clock_t, const dimminfo_t *, int s3resume); -void raminit_read_training(const dimminfo_t *, int s3resume); +void raminit_write_training(const mem_clock_t, const dimminfo_t *, bool s3resume); +void raminit_read_training(const dimminfo_t *, bool s3resume); void gm45_late_init(stepping_t); diff --git a/src/northbridge/intel/gm45/raminit.c b/src/northbridge/intel/gm45/raminit.c index b7e0139..def9e1e 100644 --- a/src/northbridge/intel/gm45/raminit.c +++ b/src/northbridge/intel/gm45/raminit.c @@ -2100,7 +2100,7 @@ mchbar_setbits32(0x15f0, 1 << 10); } -void raminit(sysinfo_t *const sysinfo, const int s3resume) +void raminit(sysinfo_t *const sysinfo, const bool s3resume) { const dimminfo_t *const dimms = sysinfo->dimms; const timings_t *const timings = &sysinfo->selected_timings; diff --git a/src/northbridge/intel/gm45/raminit_read_write_training.c b/src/northbridge/intel/gm45/raminit_read_write_training.c index d3571df..f2308ab 100644 --- a/src/northbridge/intel/gm45/raminit_read_write_training.c +++ b/src/northbridge/intel/gm45/raminit_read_write_training.c @@ -262,7 +262,7 @@ } } } -void raminit_read_training(const dimminfo_t *const dimms, const int s3resume) +void raminit_read_training(const dimminfo_t *const dimms, const bool s3resume) { if (!s3resume) { perform_read_training(dimms); @@ -633,7 +633,7 @@ } void raminit_write_training(const mem_clock_t ddr3clock, const dimminfo_t *const dimms, - const int s3resume) + const bool s3resume) { const int memclk1067 = ddr3clock == MEM_CLOCK_1067MT; diff --git a/src/northbridge/intel/gm45/romstage.c b/src/northbridge/intel/gm45/romstage.c index bc17618..b44bee7 100644 --- a/src/northbridge/intel/gm45/romstage.c +++ b/src/northbridge/intel/gm45/romstage.c @@ -33,7 +33,7 @@ void mainboard_romstage_entry(void) { sysinfo_t sysinfo; - int s3resume = 0; + bool s3resume = false; int cbmem_initted; u16 reg16; diff --git a/src/northbridge/intel/haswell/broadwell_mrc/raminit.c b/src/northbridge/intel/haswell/broadwell_mrc/raminit.c index beae496..39ee6a6 100644 --- a/src/northbridge/intel/haswell/broadwell_mrc/raminit.c +++ b/src/northbridge/intel/haswell/broadwell_mrc/raminit.c @@ -311,7 +311,7 @@ return oc_pin >= USB_OC_PIN_SKIP ? PEI_USB_OC_PIN_SKIP : oc_pin; } -static bool early_init_native(int s3resume) +static bool early_init_native(bool s3resume) { printk(BIOS_DEBUG, "Starting native platform initialisation\n"); @@ -327,7 +327,7 @@ return cpu_replaced; } -void perform_raminit(const int s3resume) +void perform_raminit(const bool s3resume) { const struct northbridge_intel_haswell_config *cfg = config_of_soc(); diff --git a/src/northbridge/intel/haswell/haswell_mrc/raminit.c b/src/northbridge/intel/haswell/haswell_mrc/raminit.c index 3d5e46c..1657320 100644 --- a/src/northbridge/intel/haswell/haswell_mrc/raminit.c +++ b/src/northbridge/intel/haswell/haswell_mrc/raminit.c @@ -340,7 +340,7 @@ return oc_pin >= USB_OC_PIN_SKIP ? PEI_USB_OC_PIN_SKIP : oc_pin; } -void perform_raminit(const int s3resume) +void perform_raminit(const bool s3resume) { const struct device *gbe = pcidev_on_root(0x19, 0); diff --git a/src/northbridge/intel/haswell/native_raminit/raminit_native.c b/src/northbridge/intel/haswell/native_raminit/raminit_native.c index 2fed93d..ae1490d 100644 --- a/src/northbridge/intel/haswell/native_raminit/raminit_native.c +++ b/src/northbridge/intel/haswell/native_raminit/raminit_native.c @@ -168,7 +168,7 @@ return bootmode; } -void perform_raminit(const int s3resume) +void perform_raminit(const bool s3resume) { /* * See, this function's name is a lie. There are more things to diff --git a/src/northbridge/intel/haswell/raminit.h b/src/northbridge/intel/haswell/raminit.h index 6c76739..3f13a03 100644 --- a/src/northbridge/intel/haswell/raminit.h +++ b/src/northbridge/intel/haswell/raminit.h @@ -17,6 +17,6 @@ void mb_get_spd_map(struct spd_info *spdi); void get_spd_info(struct spd_info *spdi, const struct northbridge_intel_haswell_config *cfg); -void perform_raminit(const int s3resume); +void perform_raminit(const bool s3resume); #endif /* NORTHBRIDGE_INTEL_HASWELL_RAMINIT_H */ diff --git a/src/northbridge/intel/haswell/romstage.c b/src/northbridge/intel/haswell/romstage.c index ce14915..85fe967c 100644 --- a/src/northbridge/intel/haswell/romstage.c +++ b/src/northbridge/intel/haswell/romstage.c @@ -27,7 +27,7 @@ haswell_early_initialization(); printk(BIOS_DEBUG, "Back from haswell_early_initialization()\n"); - const int s3resume = southbridge_detect_s3_resume(); + const bool s3resume = southbridge_detect_s3_resume(); elog_boot_notify(s3resume); diff --git a/src/northbridge/intel/i440bx/raminit.c b/src/northbridge/intel/i440bx/raminit.c index f82d54c..e940b8d 100644 --- a/src/northbridge/intel/i440bx/raminit.c +++ b/src/northbridge/intel/i440bx/raminit.c @@ -989,7 +989,7 @@ /* Implemented under mainboard. */ void __weak enable_spd(void) { } -void sdram_initialize(int s3resume) +void sdram_initialize(bool s3resume) { timestamp_add_now(TS_INITRAM_START); enable_spd(); diff --git a/src/northbridge/intel/i440bx/raminit.h b/src/northbridge/intel/i440bx/raminit.h index b35554f..fa74c13 100644 --- a/src/northbridge/intel/i440bx/raminit.h +++ b/src/northbridge/intel/i440bx/raminit.h @@ -13,7 +13,7 @@ #define DIMM3 0x53 void enable_spd(void); -void sdram_initialize(int s3resume); +void sdram_initialize(bool s3resume); /* Debug */ #if CONFIG(DEBUG_RAM_SETUP) diff --git a/src/northbridge/intel/i945/early_init.c b/src/northbridge/intel/i945/early_init.c index eea2028..ac36f08 100644 --- a/src/northbridge/intel/i945/early_init.c +++ b/src/northbridge/intel/i945/early_init.c @@ -793,16 +793,16 @@ RCBA32(0x2010) |= (1 << 10); } -static void i945_prepare_resume(int s3resume) +static void i945_prepare_resume(bool s3resume) { - int cbmem_was_initted; + bool cbmem_was_initted; cbmem_was_initted = !cbmem_recovery(s3resume); romstage_handoff_init(cbmem_was_initted && s3resume); } -void i945_late_initialization(int s3resume) +void i945_late_initialization(bool s3resume) { i945_setup_egress_port(); diff --git a/src/northbridge/intel/i945/i945.h b/src/northbridge/intel/i945/i945.h index 4818a73..a9f956a 100644 --- a/src/northbridge/intel/i945/i945.h +++ b/src/northbridge/intel/i945/i945.h @@ -323,7 +323,7 @@ int i945_silicon_revision(void); void i945_early_initialization(void); -void i945_late_initialization(int s3resume); +void i945_late_initialization(bool s3resume); /* debugging functions */ void print_pci_devices(void); diff --git a/src/northbridge/intel/i945/romstage.c b/src/northbridge/intel/i945/romstage.c index 61b9bcf..5607f78 100644 --- a/src/northbridge/intel/i945/romstage.c +++ b/src/northbridge/intel/i945/romstage.c @@ -26,7 +26,7 @@ void mainboard_romstage_entry(void) { - int s3resume = 0; + bool s3resume = false; u8 spd_map[4] = {}; mainboard_lpc_decode(); diff --git a/src/northbridge/intel/ironlake/quickpath.c b/src/northbridge/intel/ironlake/quickpath.c index aac852a..cbdd54b 100644 --- a/src/northbridge/intel/ironlake/quickpath.c +++ b/src/northbridge/intel/ironlake/quickpath.c @@ -353,7 +353,7 @@ } } -static void set_2dxx_series(struct raminfo *info, int s3resume) +static void set_2dxx_series(struct raminfo *info, bool s3resume) { set_2dx8_reg(info, 0x2d00, 0, 0x78, frequency_11(info) / 2, 1359, 1005, 0, 1); diff --git a/src/northbridge/intel/ironlake/raminit.c b/src/northbridge/intel/ironlake/raminit.c index b262097..f4f41e5 100644 --- a/src/northbridge/intel/ironlake/raminit.c +++ b/src/northbridge/intel/ironlake/raminit.c @@ -333,7 +333,7 @@ } static void -config_rank(struct raminfo *info, int s3resume, int channel, int slot, int rank) +config_rank(struct raminfo *info, bool s3resume, int channel, int slot, int rank) { int add; @@ -2856,7 +2856,7 @@ gav(inb(DEFAULT_GPIOBASE | 0xe)); // = 0xfdcaff6e } -void chipset_init(const int s3resume) +void chipset_init(const bool s3resume) { u8 x2ca8; u16 ggc; @@ -2915,12 +2915,12 @@ return val; } -void raminit(const int s3resume, const u8 *spd_addrmap) +void raminit(const bool s3resume, const u8 *spd_addrmap) { unsigned int channel, slot, lane, rank; struct raminfo info; u8 x2ca8; - int cbmem_wasnot_inited; + bool cbmem_wasnot_inited; x2ca8 = mchbar_read8(0x2ca8); diff --git a/src/northbridge/intel/ironlake/raminit.h b/src/northbridge/intel/ironlake/raminit.h index edfce51..377864a 100644 --- a/src/northbridge/intel/ironlake/raminit.h +++ b/src/northbridge/intel/ironlake/raminit.h @@ -92,7 +92,7 @@ return (info->clock_speed_index + 3) * 120; } -void chipset_init(const int s3resume); +void chipset_init(const bool s3resume); /* spd_addrmap is array of 4 elements: Channel 0 Slot 0 Channel 0 Slot 1 @@ -100,10 +100,10 @@ Channel 1 Slot 1 0 means "not present" */ -void raminit(const int s3resume, const u8 *spd_addrmap); +void raminit(const bool s3resume, const u8 *spd_addrmap); u16 get_max_timing(struct raminfo *info, int channel); void early_quickpath_init(struct raminfo *info, const u8 x2ca8); -void late_quickpath_init(struct raminfo *info, const int s3resume); +void late_quickpath_init(struct raminfo *info, const bool s3resume); #endif /* RAMINIT_H */ diff --git a/src/northbridge/intel/ironlake/romstage.c b/src/northbridge/intel/ironlake/romstage.c index 1e6bf67..aea1cc5 100644 --- a/src/northbridge/intel/ironlake/romstage.c +++ b/src/northbridge/intel/ironlake/romstage.c @@ -22,7 +22,7 @@ */ void mainboard_romstage_entry(void) { - int s3resume = 0; + bool s3resume = false; u8 spd_addrmap[4] = {}; /* TODO, make this configurable */ @@ -34,7 +34,7 @@ if (s3resume) { u8 reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xa2); if (!(reg8 & 0x20)) { - s3resume = 0; + s3resume = false; printk(BIOS_DEBUG, "Bad resume from S3 detected.\n"); } } diff --git a/src/northbridge/intel/pineview/romstage.c b/src/northbridge/intel/pineview/romstage.c index 03058ec..5755eaa 100644 --- a/src/northbridge/intel/pineview/romstage.c +++ b/src/northbridge/intel/pineview/romstage.c @@ -27,8 +27,9 @@ void mainboard_romstage_entry(void) { u8 spd_addrmap[4] = {}; - int boot_path, cbmem_was_initted; - int s3resume = 0; + int boot_path; + bool cbmem_was_initted; + bool s3resume = false; /* Do some early chipset init, necessary for RAM init to work */ i82801gx_early_init(); diff --git a/src/northbridge/intel/sandybridge/raminit.c b/src/northbridge/intel/sandybridge/raminit.c index 9ec8fb6f..06e63c4 100644 --- a/src/northbridge/intel/sandybridge/raminit.c +++ b/src/northbridge/intel/sandybridge/raminit.c @@ -336,9 +336,10 @@ ctrl->ecc_forced ? "yes" : "no"); } -static void init_dram_ddr3(int s3resume, const u32 cpuid) +static void init_dram_ddr3(bool s3resume, const u32 cpuid) { - int me_uma_size, cbmem_was_inited, fast_boot, err; + int me_uma_size, fast_boot, err; + bool cbmem_was_inited; ramctr_timing ctrl; spd_ddr3_raw_data spds[4]; size_t mrc_size = 0; @@ -519,7 +520,7 @@ setup_sdram_meminfo(&ctrl); } -void perform_raminit(int s3resume) +void perform_raminit(bool s3resume) { post_code(0x3a); init_dram_ddr3(s3resume, cpu_get_cpuid()); diff --git a/src/northbridge/intel/sandybridge/raminit_common.h b/src/northbridge/intel/sandybridge/raminit_common.h index ee7c525..202f67a 100644 --- a/src/northbridge/intel/sandybridge/raminit_common.h +++ b/src/northbridge/intel/sandybridge/raminit_common.h @@ -468,7 +468,7 @@ void set_normal_operation(ramctr_timing *ctrl); void final_registers(ramctr_timing *ctrl); void restore_timings(ramctr_timing *ctrl); -int try_init_dram_ddr3(ramctr_timing *ctrl, int fast_boot, int s3resume, int me_uma_size); +int try_init_dram_ddr3(ramctr_timing *ctrl, int fast_boot, bool s3resume, int me_uma_size); void channel_scrub(ramctr_timing *ctrl); bool get_host_ecc_cap(void); diff --git a/src/northbridge/intel/sandybridge/raminit_mrc.c b/src/northbridge/intel/sandybridge/raminit_mrc.c index b81716a..146ec24 100644 --- a/src/northbridge/intel/sandybridge/raminit_mrc.c +++ b/src/northbridge/intel/sandybridge/raminit_mrc.c @@ -340,7 +340,7 @@ static void setup_sdram_meminfo(struct pei_data *pei_data); -void perform_raminit(int s3resume) +void perform_raminit(bool s3resume) { const struct northbridge_intel_sandybridge_config *cfg = config_of_soc(); struct pei_data pei_data = { @@ -412,7 +412,7 @@ hexdump(mrc_var, sizeof(*mrc_var)); } - const int cbmem_was_initted = !cbmem_recovery(s3resume); + const bool cbmem_was_initted = !cbmem_recovery(s3resume); if (!s3resume) save_mrc_data(&pei_data); diff --git a/src/northbridge/intel/sandybridge/raminit_native.c b/src/northbridge/intel/sandybridge/raminit_native.c index ed11945..282058b 100644 --- a/src/northbridge/intel/sandybridge/raminit_native.c +++ b/src/northbridge/intel/sandybridge/raminit_native.c @@ -630,7 +630,7 @@ printram("done\n"); } -int try_init_dram_ddr3(ramctr_timing *ctrl, int fast_boot, int s3resume, int me_uma_size) +int try_init_dram_ddr3(ramctr_timing *ctrl, int fast_boot, bool s3resume, int me_uma_size) { int err; diff --git a/src/northbridge/intel/sandybridge/romstage.c b/src/northbridge/intel/sandybridge/romstage.c index 86569c1..0638072 100644 --- a/src/northbridge/intel/sandybridge/romstage.c +++ b/src/northbridge/intel/sandybridge/romstage.c @@ -16,7 +16,7 @@ #include <southbridge/intel/common/pmclib.h> #include <elog.h> -__weak void mainboard_early_init(int s3resume) +__weak void mainboard_early_init(bool s3resume) { } @@ -48,7 +48,7 @@ /* The romstage entry point for this platform is not mainboard-specific, hence the name */ void mainboard_romstage_entry(void) { - int s3resume = 0; + bool s3resume = false; if (mchbar_read16(SSKPD_HI) == 0xcafe) system_reset(); diff --git a/src/northbridge/intel/sandybridge/sandybridge.h b/src/northbridge/intel/sandybridge/sandybridge.h index 0eaa4ec..2b07c49 100644 --- a/src/northbridge/intel/sandybridge/sandybridge.h +++ b/src/northbridge/intel/sandybridge/sandybridge.h @@ -64,8 +64,8 @@ void early_init_dmi(void); /* mainboard_early_init: Optional callback, run after console init but before raminit. */ -void mainboard_early_init(int s3resume); -void perform_raminit(int s3resume); +void mainboard_early_init(bool s3resume); +void perform_raminit(bool s3resume); void report_memory_config(void); enum platform_type get_platform_type(void); diff --git a/src/northbridge/intel/x4x/raminit.c b/src/northbridge/intel/x4x/raminit.c index 3149074..6b0f358 100644 --- a/src/northbridge/intel/x4x/raminit.c +++ b/src/northbridge/intel/x4x/raminit.c @@ -561,7 +561,8 @@ { struct sysinfo s, *ctrl_cached; u8 reg8; - int fast_boot, cbmem_was_inited; + int fast_boot; + bool cbmem_was_inited; size_t mrc_size; timestamp_add_now(TS_INITRAM_START); @@ -640,7 +641,7 @@ printk(BIOS_DEBUG, "RAM initialization finished.\n"); - int s3resume = boot_path == BOOT_PATH_RESUME; + bool s3resume = boot_path == BOOT_PATH_RESUME; cbmem_was_inited = !cbmem_recovery(s3resume); if (!fast_boot) diff --git a/src/northbridge/via/cx700/romstage.c b/src/northbridge/via/cx700/romstage.c index d554b76..9294da8 100644 --- a/src/northbridge/via/cx700/romstage.c +++ b/src/northbridge/via/cx700/romstage.c @@ -57,7 +57,7 @@ sdram_enable(&config->dram_cfg); - cbmem_recovery(/* s3resume => */0); + cbmem_recovery(/* s3resume => */false); prepare_and_run_postcar(); } diff --git a/src/security/intel/txt/ramstage.c b/src/security/intel/txt/ramstage.c index 5c03da9..85606d4 100644 --- a/src/security/intel/txt/ramstage.c +++ b/src/security/intel/txt/ramstage.c @@ -173,7 +173,7 @@ log_ibb_measurements(); } - int s3resume = acpi_is_wakeup_s3(); + bool s3resume = acpi_is_wakeup_s3(); if (!s3resume && !CONFIG(INTEL_CBNT_SUPPORT)) { printk(BIOS_INFO, "TEE-TXT: Scheck...\n"); if (intel_txt_run_bios_acm(ACMINPUT_SCHECK) < 0) { diff --git a/src/soc/amd/stoneyridge/romstage.c b/src/soc/amd/stoneyridge/romstage.c index 900d1a6..8e2ebae 100644 --- a/src/soc/amd/stoneyridge/romstage.c +++ b/src/soc/amd/stoneyridge/romstage.c @@ -55,7 +55,7 @@ msr_t base, mask; msr_t mtrr_cap = rdmsr(MTRR_CAP_MSR); int vmtrrs = mtrr_cap.lo & MTRR_CAP_VCNT; - int s3_resume = acpi_is_wakeup_s3(); + bool s3_resume = acpi_is_wakeup_s3(); int i; soc_enable_psp_early(); diff --git a/src/soc/intel/baytrail/romstage/raminit.c b/src/soc/intel/baytrail/romstage/raminit.c index 6244072..82e98f7 100644 --- a/src/soc/intel/baytrail/romstage/raminit.c +++ b/src/soc/intel/baytrail/romstage/raminit.c @@ -129,7 +129,7 @@ mp->prev_sleep_state = prev_sleep_state; mp->rmt_enabled = CONFIG(MRC_RMT); - int s3resume = prev_sleep_state == ACPI_S3; + bool s3resume = prev_sleep_state == ACPI_S3; /* Default to 2GiB IO hole. */ if (!mp->io_hole_mb) @@ -182,7 +182,7 @@ ret = mrc_entry(mp); - int cbmem_was_initted = !cbmem_recovery(s3resume); + bool cbmem_was_initted = !cbmem_recovery(s3resume); if (s3resume && !cbmem_was_initted) { /* Failed S3 resume, reset to come up cleanly */ printk(BIOS_CRIT, "Failed to recover CBMEM in S3 resume.\n"); diff --git a/src/soc/intel/baytrail/romstage/romstage.c b/src/soc/intel/baytrail/romstage/romstage.c index 658da2c..572f03e 100644 --- a/src/soc/intel/baytrail/romstage/romstage.c +++ b/src/soc/intel/baytrail/romstage/romstage.c @@ -108,7 +108,7 @@ printk(BIOS_DEBUG, "prev_sleep_state = S%d\n", prev_sleep_state); - int s3resume = prev_sleep_state == ACPI_S3; + bool s3resume = prev_sleep_state == ACPI_S3; elog_boot_notify(s3resume); diff --git a/src/soc/intel/broadwell/include/soc/romstage.h b/src/soc/intel/broadwell/include/soc/romstage.h index d878e7a9..5b2e3b0 100644 --- a/src/soc/intel/broadwell/include/soc/romstage.h +++ b/src/soc/intel/broadwell/include/soc/romstage.h @@ -3,7 +3,7 @@ #ifndef _BROADWELL_ROMSTAGE_H_ #define _BROADWELL_ROMSTAGE_H_ -void mainboard_post_raminit(const int s3resume); +void mainboard_post_raminit(const bool s3resume); struct chipset_power_state; struct chipset_power_state *fill_power_state(void); diff --git a/src/soc/intel/broadwell/raminit.c b/src/soc/intel/broadwell/raminit.c index cacf8ecc..9dc7973 100644 --- a/src/soc/intel/broadwell/raminit.c +++ b/src/soc/intel/broadwell/raminit.c @@ -191,7 +191,7 @@ void perform_raminit(const struct chipset_power_state *const power_state) { - const int s3resume = power_state->prev_sleep_state == ACPI_S3; + const bool s3resume = power_state->prev_sleep_state == ACPI_S3; struct pei_data pei_data = { 0 }; @@ -232,7 +232,7 @@ timestamp_add_now(TS_INITRAM_END); - int cbmem_was_initted = !cbmem_recovery(s3resume); + bool cbmem_was_initted = !cbmem_recovery(s3resume); if (s3resume && !cbmem_was_initted) { /* Failed S3 resume, reset to come up cleanly */ printk(BIOS_CRIT, "Failed to recover CBMEM in S3 resume.\n"); diff --git a/src/soc/intel/broadwell/romstage.c b/src/soc/intel/broadwell/romstage.c index 5c172ed..4e2cb6a 100644 --- a/src/soc/intel/broadwell/romstage.c +++ b/src/soc/intel/broadwell/romstage.c @@ -12,7 +12,7 @@ #include <southbridge/intel/lynxpoint/lp_gpio.h> #include <stdint.h> -__weak void mainboard_post_raminit(const int s3resume) +__weak void mainboard_post_raminit(const bool s3resume) { } diff --git a/src/southbridge/intel/lynxpoint/early_pch_native.c b/src/southbridge/intel/lynxpoint/early_pch_native.c index d866182..452c8a5 100644 --- a/src/southbridge/intel/lynxpoint/early_pch_native.c +++ b/src/southbridge/intel/lynxpoint/early_pch_native.c @@ -83,7 +83,7 @@ pci_or_config8(PCH_SATA_DEV, SATA_PCS, sata_pcs); } -void early_pch_init_native(int s3resume) +void early_pch_init_native(bool s3resume) { const uint8_t pch_revision = pci_read_config8(PCH_LPC_DEV, PCI_REVISION_ID); diff --git a/src/southbridge/intel/lynxpoint/pch.h b/src/southbridge/intel/lynxpoint/pch.h index 07f4b9d..622c426 100644 --- a/src/southbridge/intel/lynxpoint/pch.h +++ b/src/southbridge/intel/lynxpoint/pch.h @@ -116,7 +116,7 @@ void pch_dmi_tc_vc_mapping(u32 vc0, u32 vc1, u32 vcp, u32 vcm); void early_usb_init(void); void early_thermal_init(void); -void early_pch_init_native(int s3resume); +void early_pch_init_native(bool s3resume); void usb_ehci_sleep_prepare(pci_devfn_t dev, u8 slp_typ); void usb_ehci_disable(pci_devfn_t dev); -- To view, visit https://review.coreboot.org/c/coreboot/+/86331?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I3e23134f879fcaf817cf62b641e9b59563eb643b Gerrit-Change-Number: 86331 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr>

1 0

[S] Change in coreboot[main]: tree: remove duplicated includes
by Elyes Haouas (Code Review) 08 Feb '25

08 Feb '25

Attention is currently required from: Elyes Haouas, Felix Held, Fred Reitberger, Hung-Te Lin, Intel coreboot Reviewers, Jason Glenesk, Jayvik Desai, Jeff Daly, Kapil Porwal, Martin L Roth, Matt DeVillier, Pranava Y N, Sean Rhodes, Subrata Banik, Vanessa Eusebio, Varshit Pandya, Yidi Lin, Yu-Ping Wu. Hello Angel Pons, Felix Held, Fred Reitberger, Hung-Te Lin, Intel coreboot Reviewers, Jason Glenesk, Jayvik Desai, Jeff Daly, Kapil Porwal, Martin L Roth, Matt DeVillier, Pranava Y N, Sean Rhodes, Subrata Banik, Vanessa Eusebio, Varshit Pandya, Yidi Lin, Yu-Ping Wu, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/86330?usp=email to look at the new patch set (#3). Change subject: tree: remove duplicated includes ...................................................................... tree: remove duplicated includes Also remove stdint and stddef when provided by <types.h> Change-Id: Iaf10e1b9fb8ce51605a75ec0a92ee33924c42aa6 Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> --- M src/commonlib/device_tree.c M src/mainboard/amd/crater/port_descriptors_renoir.c M src/mainboard/emulation/qemu-sbsa/mainboard.c M src/mainboard/google/dedede/variants/baseboard/ramstage.c M src/northbridge/intel/haswell/broadwell_mrc/raminit.c M src/soc/amd/genoa_poc/chip.c M src/soc/amd/genoa_poc/config.c M src/soc/amd/picasso/acpi.c M src/soc/intel/apollolake/cpu.c M src/soc/intel/denverton_ns/include/soc/pci_devs.h M src/soc/intel/pantherlake/bootblock/report_platform.c M src/soc/mediatek/mt8196/mminfra.c M util/superiotool/superiotool.h 13 files changed, 1 insertion(+), 18 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/30/86330/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/86330?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iaf10e1b9fb8ce51605a75ec0a92ee33924c42aa6 Gerrit-Change-Number: 86330 Gerrit-PatchSet: 3 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Jeff Daly <jeffd(a)silicom-usa.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Reviewer: Varshit Pandya <pandyavarshit(a)gmail.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Jeff Daly <jeffd(a)silicom-usa.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-Attention: Varshit Pandya <pandyavarshit(a)gmail.com> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de>

1 0

[S] Change in coreboot[main]: tree: remove duplicated includes
by Elyes Haouas (Code Review) 08 Feb '25

08 Feb '25

Attention is currently required from: Elyes Haouas, Felix Held, Fred Reitberger, Hung-Te Lin, Intel coreboot Reviewers, Jason Glenesk, Jayvik Desai, Jeff Daly, Kapil Porwal, Martin L Roth, Matt DeVillier, Pranava Y N, Sean Rhodes, Subrata Banik, Vanessa Eusebio, Varshit Pandya, Yidi Lin, Yu-Ping Wu. Hello Angel Pons, Felix Held, Fred Reitberger, Hung-Te Lin, Intel coreboot Reviewers, Jason Glenesk, Jayvik Desai, Jeff Daly, Kapil Porwal, Martin L Roth, Matt DeVillier, Pranava Y N, Sean Rhodes, Subrata Banik, Vanessa Eusebio, Varshit Pandya, Yidi Lin, Yu-Ping Wu, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/86330?usp=email to look at the new patch set (#2). Change subject: tree: remove duplicated includes ...................................................................... tree: remove duplicated includes Also remove stdint and stddef when it is provided by <types.h> Change-Id: Iaf10e1b9fb8ce51605a75ec0a92ee33924c42aa6 Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> --- M src/commonlib/device_tree.c M src/mainboard/amd/crater/port_descriptors_renoir.c M src/mainboard/emulation/qemu-sbsa/mainboard.c M src/mainboard/google/dedede/variants/baseboard/ramstage.c M src/northbridge/intel/haswell/broadwell_mrc/raminit.c M src/soc/amd/genoa_poc/chip.c M src/soc/amd/genoa_poc/config.c M src/soc/amd/picasso/acpi.c M src/soc/intel/apollolake/cpu.c M src/soc/intel/denverton_ns/include/soc/pci_devs.h M src/soc/intel/pantherlake/bootblock/report_platform.c M src/soc/mediatek/mt8196/mminfra.c M util/superiotool/superiotool.h 13 files changed, 1 insertion(+), 18 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/30/86330/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/86330?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iaf10e1b9fb8ce51605a75ec0a92ee33924c42aa6 Gerrit-Change-Number: 86330 Gerrit-PatchSet: 2 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Jeff Daly <jeffd(a)silicom-usa.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Reviewer: Varshit Pandya <pandyavarshit(a)gmail.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Jeff Daly <jeffd(a)silicom-usa.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-Attention: Varshit Pandya <pandyavarshit(a)gmail.com> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de>

1 0

[XS] Change in coreboot[main]: mainboard/google/fatcat: Set TCC offset
by Subrata Banik (Code Review) 08 Feb '25

08 Feb '25

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/86292?usp=email ) Change subject: mainboard/google/fatcat: Set TCC offset ...................................................................... mainboard/google/fatcat: Set TCC offset This commit sets the TCC offset for the Fatcat baseboard variant. A value of 10 was chosen, resulting in a TCC trip point of 100C (Tjmax of 110C - offset of 10C). This allows for thermal throttling to begin at a more appropriate temperature. Fatcat variants can override the TCC offset as per platform requirements between power and/or performance. TEST=Able to build and boot to CrOS. Change-Id: I2a57fd3b06378f4e62872ffeb116a65561100e33 Signed-off-by: Subrata Banik <subratabanik(a)google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/86292 Reviewed-by: Jamie Ryu <jamie.m.ryu(a)intel.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Dinesh Gehlot <digehlot(a)google.com> --- M src/mainboard/google/fatcat/variants/baseboard/fatcat/devicetree.cb 1 file changed, 3 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Jamie Ryu: Looks good to me, approved Dinesh Gehlot: Looks good to me, approved diff --git a/src/mainboard/google/fatcat/variants/baseboard/fatcat/devicetree.cb b/src/mainboard/google/fatcat/variants/baseboard/fatcat/devicetree.cb index c217a15..b09f9e3 100644 --- a/src/mainboard/google/fatcat/variants/baseboard/fatcat/devicetree.cb +++ b/src/mainboard/google/fatcat/variants/baseboard/fatcat/devicetree.cb @@ -51,6 +51,9 @@ # DPTF enable register "dptf_enable" = "true" + # Setting TCC of 100C = Tj max (110) - TCC_Offset (10) + register "tcc_offset" = "10" + # Disable C1 C-state auto-demotion register "disable_c1_state_auto_demotion" = "true" # Disable PKGC-state auto-demotion -- To view, visit https://review.coreboot.org/c/coreboot/+/86292?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I2a57fd3b06378f4e62872ffeb116a65561100e33 Gerrit-Change-Number: 86292 Gerrit-PatchSet: 2 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[L] Change in coreboot[main]: mb/google/nissa/var/dirks: Add initial override devicetree
by Subrata Banik (Code Review) 08 Feb '25

08 Feb '25

Attention is currently required from: Dinesh Gehlot, Ivy Jian, Jayvik Desai, Kapil Porwal, Nick Vaccaro. Subrata Banik has posted comments on this change by Ivy Jian. ( https://review.coreboot.org/c/coreboot/+/86250?usp=email ) The change is no longer submittable: All-Comments-Resolved is unsatisfied now. Change subject: mb/google/nissa/var/dirks: Add initial override devicetree ...................................................................... Patch Set 2: (1 comment) File src/mainboard/google/brya/variants/dirks/overridetree.cb: https://review.coreboot.org/c/coreboot/+/86250/comment/46987a6c_dfdd332b?us… : PS2, Line 264: use tab? -- To view, visit https://review.coreboot.org/c/coreboot/+/86250?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ic0b80e3121d94ede771ecc30cf0c66a67b9a41d0 Gerrit-Change-Number: 86250 Gerrit-PatchSet: 2 Gerrit-Owner: Ivy Jian <ivy.jian(a)quanta.corp-partner.google.com> Gerrit-Reviewer: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Ivy Jian <ivy.jian(a)quanta.corp-partner.google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Comment-Date: Sat, 08 Feb 2025 10:00:46 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[XS] Change in coreboot[main]: mb/google/nissa/var/pujjoniru: Update I2C_5 parameters
by Subrata Banik (Code Review) 08 Feb '25

08 Feb '25

Attention is currently required from: Dinesh Gehlot, Jayvik Desai, Kapil Porwal, Nick Vaccaro, Weimin Wu, hualin wei. Subrata Banik has posted comments on this change by hualin wei. ( https://review.coreboot.org/c/coreboot/+/86324?usp=email ) Change subject: mb/google/nissa/var/pujjoniru: Update I2C_5 parameters ...................................................................... Patch Set 5: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/86324?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I3c8c8d3b78236247ca7be810ac152085f615a6ef Gerrit-Change-Number: 86324 Gerrit-PatchSet: 5 Gerrit-Owner: hualin wei <weihualin(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Qinghong Zeng <zengqinghong(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Weimin Wu <wuweimin(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Cindy Lu <luyi8(a)huaqin.corp-partner.google.com> Gerrit-CC: Dolan Liu <liuyong5(a)huaqin.corp-partner.google.com> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: hualin wei <weihualin(a)huaqin.corp-partner.google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Weimin Wu <wuweimin(a)huaqin.corp-partner.google.com> Gerrit-Comment-Date: Sat, 08 Feb 2025 09:59:39 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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