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Change subject: mainboard/google/fatcat: Fix SMBIOS Processor upgrade info
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Patch Set 4:
(1 comment)
File src/mainboard/google/fatcat/Kconfig:
https://review.coreboot.org/c/coreboot/+/85960/comment/5b646433_df629956?us… :
PS3, Line 6:
> can you please keep the alphabetical order.
Done
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Hello Jayvik Desai, Jérémy Compostella, Kapil Porwal, Pranava Y N, Subrata Banik, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/85960?usp=email
to look at the new patch set (#4).
The following approvals got outdated and were removed:
Verified+1 by build bot (Jenkins)
Change subject: mainboard/google/fatcat: Fix SMBIOS Processor upgrade info
......................................................................
mainboard/google/fatcat: Fix SMBIOS Processor upgrade info
The current SMBIOS for fatcat is missing processor upgrade info,
This patch adds the missing value by enabling a kconfig flag.
Refer to SMBIOS spec sheet for documentation on cpu socket values:
https://web.archive.org/web/20221012222420/https://www.dmtf.org/sites/defau…
BUG=NONE
TEST=Boot and verified that SMBIOS processor upgrade value is correct.
Change-Id: Ica92d15e4a6123f928fceb77c7638e4c45d6dc7d
Signed-off-by: Zhixing Ma <zhixing.ma(a)intel.com>
---
M src/mainboard/google/fatcat/Kconfig
1 file changed, 1 insertion(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/60/85960/4
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Change subject: mainboard/google/fatcat: Fix SMBIOS Processor upgrade info
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Patch Set 3:
(1 comment)
File src/mainboard/google/fatcat/Kconfig:
https://review.coreboot.org/c/coreboot/+/85960/comment/84d04a88_d78a287b?us… :
PS3, Line 6:
can you please keep the alphabetical order.
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Change subject: mainboard/google/fatcat: Fix SMBIOS Processor upgrade info
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Patch Set 3:
(1 comment)
File src/mainboard/google/fatcat/Kconfig:
https://review.coreboot.org/c/coreboot/+/85960/comment/bebd93eb_cd7f1685?us… :
PS2, Line 40:
> need tab instead of space?
Done
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Change subject: mainboard/google/fatcat: Fix SMBIOS Processor upgrade info
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Change subject: soc/amd/mendocino/chipset_*: Enable gpp_bridge_[a/b/c] by default
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Change subject: soc/amd/glinda/chipset.cb: Enable gpp_bridge_[a/b/c] by default
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Patch Set 1:
(1 comment)
This change is ready for review.
Commit Message:
https://review.coreboot.org/c/coreboot/+/86270/comment/2c692279_04204a0d?us… :
PS1, Line 9: TODO
> Since FSP doesn't support disabling bridges and has no UPDs for that, they must be enabled in DT to […]
Thanks.
I will take that as commit-msg
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Change subject: mb/emulation/spike-riscv/uart.c: Update UART address
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Patch Set 2:
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https://review.coreboot.org/c/coreboot/+/85852/comment/f32db692_4d83b2ac?us… :
PS1, Line 9: Simualator
> Simulator
Done
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